2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg
=
86 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
87 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
90 static int debug
= -1; /* defaults above */
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly
= 128;
95 module_param(copybreak
, int, 0);
96 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
98 static int disable_msi
= 0;
99 module_param(disable_msi
, int, 0);
100 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
151 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
152 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
154 static void sky2_set_multicast(struct net_device
*dev
);
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
161 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
162 gma_write16(hw
, port
, GM_SMI_CTRL
,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
165 for (i
= 0; i
< PHY_RETRIES
; i
++) {
166 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
170 if (!(ctrl
& GM_SMI_CT_BUSY
))
176 dev_warn(&hw
->pdev
->dev
,"%s: phy write timeout\n", hw
->dev
[port
]->name
);
180 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
184 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
188 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
189 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
191 for (i
= 0; i
< PHY_RETRIES
; i
++) {
192 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
196 if (ctrl
& GM_SMI_CT_RD_VAL
) {
197 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
204 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
207 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
211 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
214 __gm_phy_read(hw
, port
, reg
, &v
);
219 static void sky2_power_on(struct sky2_hw
*hw
)
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw
, B0_POWER_CTRL
,
223 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
225 /* disable Core Clock Division, */
226 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
228 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
229 /* enable bits are inverted */
230 sky2_write8(hw
, B2_Y2_CLK_GATE
,
231 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
232 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
233 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
235 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
237 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
240 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
242 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg
&= P_ASPM_CONTROL_MSK
;
245 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
247 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
250 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
252 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg
= sky2_read32(hw
, B2_GP_IO
);
256 reg
|= GLB_GPIO_STAT_RACE_DIS
;
257 sky2_write32(hw
, B2_GP_IO
, reg
);
259 sky2_read32(hw
, B2_GP_IO
);
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_ON
);
266 static void sky2_power_aux(struct sky2_hw
*hw
)
268 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
269 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
271 /* enable bits are inverted */
272 sky2_write8(hw
, B2_Y2_CLK_GATE
,
273 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
274 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
275 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
279 pci_pme_capable(hw
->pdev
, PCI_D3cold
))
280 sky2_write8(hw
, B0_POWER_CTRL
,
281 (PC_VAUX_ENA
| PC_VCC_ENA
|
282 PC_VAUX_ON
| PC_VCC_OFF
));
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_OFF
);
288 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
295 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
296 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
297 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
298 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
300 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
301 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
302 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv
[] = {
308 [FC_TX
] = PHY_M_AN_ASP
,
309 [FC_RX
] = PHY_M_AN_PC
,
310 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv
[] = {
315 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
316 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
317 [FC_RX
] = PHY_M_P_SYM_MD_X
,
318 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable
[] = {
323 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
324 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
325 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
330 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
332 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
333 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
335 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
336 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
337 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
339 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
341 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
348 /* set master & slave downshift counter to 1x */
349 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
351 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
354 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
355 if (sky2_is_copper(hw
)) {
356 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
357 /* enable automatic crossover */
358 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
360 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
361 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
364 /* Enable Class A driver for FE+ A0 */
365 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
366 spec
|= PHY_M_FESC_SEL_CL_A
;
367 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
370 /* disable energy detect */
371 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
373 /* enable automatic crossover */
374 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
378 (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl
&= ~PHY_M_PC_DSC_MSK
;
381 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
388 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
391 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
395 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
399 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
400 ctrl
&= ~PHY_M_MAC_MD_MSK
;
401 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
402 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
404 if (hw
->pmd_type
== 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
410 ctrl
|= PHY_M_FIB_SIGD_POL
;
411 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
414 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
422 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) {
423 if (sky2_is_copper(hw
)) {
424 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
425 ct1000
|= PHY_M_1000C_AFD
;
426 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
427 ct1000
|= PHY_M_1000C_AHD
;
428 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
429 adv
|= PHY_M_AN_100_FD
;
430 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
431 adv
|= PHY_M_AN_100_HD
;
432 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
433 adv
|= PHY_M_AN_10_FD
;
434 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
435 adv
|= PHY_M_AN_10_HD
;
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
439 adv
|= PHY_M_AN_1000X_AFD
;
440 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
441 adv
|= PHY_M_AN_1000X_AHD
;
444 /* Restart Auto-negotiation */
445 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
447 /* forced speed/duplex settings */
448 ct1000
= PHY_M_1000C_MSE
;
450 /* Disable auto update for duplex flow control and duplex */
451 reg
|= GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_SPD_DIS
;
453 switch (sky2
->speed
) {
455 ctrl
|= PHY_CT_SP1000
;
456 reg
|= GM_GPCR_SPEED_1000
;
459 ctrl
|= PHY_CT_SP100
;
460 reg
|= GM_GPCR_SPEED_100
;
464 if (sky2
->duplex
== DUPLEX_FULL
) {
465 reg
|= GM_GPCR_DUP_FULL
;
466 ctrl
|= PHY_CT_DUP_MD
;
467 } else if (sky2
->speed
< SPEED_1000
)
468 sky2
->flow_mode
= FC_NONE
;
471 if (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
) {
472 if (sky2_is_copper(hw
))
473 adv
|= copper_fc_adv
[sky2
->flow_mode
];
475 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
477 reg
|= GM_GPCR_AU_FCT_DIS
;
478 reg
|= gm_fc_disable
[sky2
->flow_mode
];
480 /* Forward pause packets to GMAC? */
481 if (sky2
->flow_mode
& FC_RX
)
482 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
484 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
487 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
489 if (hw
->flags
& SKY2_HW_GIGABIT
)
490 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
492 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
493 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
495 /* Setup Phy LED's */
496 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
499 switch (hw
->chip_id
) {
500 case CHIP_ID_YUKON_FE
:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
504 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
506 /* delete ACT LED control bits */
507 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
508 /* change ACT LED control to blink mode */
509 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
510 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
513 case CHIP_ID_YUKON_FE_P
:
514 /* Enable Link Partner Next Page */
515 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
516 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
518 /* disable Energy Detect and enable scrambler */
519 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
520 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
527 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
530 case CHIP_ID_YUKON_XL
:
531 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
536 /* set LED Function Control register */
537 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
543 /* set Polarity Control register */
544 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
552 /* restore page register */
553 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
556 case CHIP_ID_YUKON_EC_U
:
557 case CHIP_ID_YUKON_EX
:
558 case CHIP_ID_YUKON_SUPR
:
559 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
564 /* set LED Function Control register */
565 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
573 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
574 /* restore page register */
575 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
582 /* turn off the Rx LED (LED_RX) */
583 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
586 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw
, port
, 0x18, 0xaa99);
592 gm_phy_write(hw
, port
, 0x17, 0x2011);
594 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw
, port
, 0x18, 0xa204);
597 gm_phy_write(hw
, port
, 0x17, 0x2002);
600 /* set page register to 0 */
601 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
602 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
603 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
606 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
607 } else if (hw
->chip_id
== CHIP_ID_YUKON_OPT
&& hw
->chip_rev
== 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00ff);
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw
, port
, 24, 0x2800);
613 gm_phy_write(hw
, port
, 23, 0x2001);
615 /* set page register back to 0 */
616 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
617 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
618 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
622 if (!(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) ||
623 sky2
->speed
== SPEED_100
) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
629 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
635 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
637 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
640 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
641 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
643 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
647 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
648 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
649 reg1
&= ~phy_power
[port
];
651 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
652 reg1
|= coma_mode
[port
];
654 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
655 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
656 sky2_pci_read32(hw
, PCI_DEV_REG1
);
658 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
659 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
660 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
661 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
664 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
669 /* release GPHY Control reset */
670 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
672 /* release GMAC reset */
673 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
675 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
679 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
680 /* allow GMII Power Down */
681 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
682 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
684 /* set page register back to 0 */
685 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
688 /* setup General Purpose Control Register */
689 gma_write16(hw
, port
, GM_GP_CTRL
,
690 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
|
691 GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_FCT_DIS
|
694 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
695 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
699 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
700 /* enable Power Down */
701 ctrl
|= PHY_M_PC_POW_D_ENA
;
702 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
704 /* set page register back to 0 */
705 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
712 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
713 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
714 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
715 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
716 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
719 /* Force a renegotiation */
720 static void sky2_phy_reinit(struct sky2_port
*sky2
)
722 spin_lock_bh(&sky2
->phy_lock
);
723 sky2_phy_init(sky2
->hw
, sky2
->port
);
724 spin_unlock_bh(&sky2
->phy_lock
);
727 /* Put device in state to listen for Wake On Lan */
728 static void sky2_wol_init(struct sky2_port
*sky2
)
730 struct sky2_hw
*hw
= sky2
->hw
;
731 unsigned port
= sky2
->port
;
732 enum flow_control save_mode
;
736 /* Bring hardware out of reset */
737 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
738 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
740 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
741 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
744 * sky2_reset will re-enable on resume
746 save_mode
= sky2
->flow_mode
;
747 ctrl
= sky2
->advertising
;
749 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
750 sky2
->flow_mode
= FC_NONE
;
752 spin_lock_bh(&sky2
->phy_lock
);
753 sky2_phy_power_up(hw
, port
);
754 sky2_phy_init(hw
, port
);
755 spin_unlock_bh(&sky2
->phy_lock
);
757 sky2
->flow_mode
= save_mode
;
758 sky2
->advertising
= ctrl
;
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw
, port
, GM_GP_CTRL
,
762 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
763 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
765 /* Set WOL address */
766 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
767 sky2
->netdev
->dev_addr
, ETH_ALEN
);
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
772 if (sky2
->wol
& WAKE_PHY
)
773 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
775 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
777 if (sky2
->wol
& WAKE_MAGIC
)
778 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
780 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;
782 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
783 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
785 /* Turn on legacy PCI-Express PME mode */
786 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
787 reg1
|= PCI_Y2_PME_LEGACY
;
788 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
791 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
795 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
797 struct net_device
*dev
= hw
->dev
[port
];
799 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
800 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
801 hw
->chip_id
>= CHIP_ID_YUKON_FE_P
) {
802 /* Yukon-Extreme B0 and further Extreme devices */
803 /* enable Store & Forward mode for TX */
805 if (dev
->mtu
<= ETH_DATA_LEN
)
806 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
807 TX_JUMBO_DIS
| TX_STFW_ENA
);
810 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
811 TX_JUMBO_ENA
| TX_STFW_ENA
);
813 if (dev
->mtu
<= ETH_DATA_LEN
)
814 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
816 /* set Tx GMAC FIFO Almost Empty Threshold */
817 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
818 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
820 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
822 /* Can't do offload because of lack of store/forward */
823 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_ALL_CSUM
);
828 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
830 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
834 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
836 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
837 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
839 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
841 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
842 /* WA DEV_472 -- looks like crossed wires on port 2 */
843 /* clear GMAC 1 Control reset */
844 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
846 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
847 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
848 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
849 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
850 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
853 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
855 /* Enable Transmit FIFO Underrun */
856 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
858 spin_lock_bh(&sky2
->phy_lock
);
859 sky2_phy_power_up(hw
, port
);
860 sky2_phy_init(hw
, port
);
861 spin_unlock_bh(&sky2
->phy_lock
);
864 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
865 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
867 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
868 gma_read16(hw
, port
, i
);
869 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
871 /* transmit control */
872 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
874 /* receive control reg: unicast + multicast + no FCS */
875 gma_write16(hw
, port
, GM_RX_CTRL
,
876 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
878 /* transmit flow control */
879 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
881 /* transmit parameter */
882 gma_write16(hw
, port
, GM_TX_PARAM
,
883 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
884 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
885 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
886 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
888 /* serial mode register */
889 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
890 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
892 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
893 reg
|= GM_SMOD_JUMBO_ENA
;
895 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
897 /* virtual address for data */
898 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
900 /* physical address: used for pause frames */
901 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
903 /* ignore counter overflows */
904 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
905 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
906 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
908 /* Configure Rx MAC FIFO */
909 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
910 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
911 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
912 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
913 rx_reg
|= GMF_RX_OVER_ON
;
915 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
917 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
918 /* Hardware errata - clear flush mask */
919 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
921 /* Flush Rx MAC FIFO on any flow control or error */
922 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
925 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
926 reg
= RX_GMF_FL_THR_DEF
+ 1;
927 /* Another magic mystery workaround from sk98lin */
928 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
929 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
931 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
933 /* Configure Tx MAC FIFO */
934 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
935 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
937 /* On chips without ram buffer, pause is controled by MAC level */
938 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
939 /* Pause threshold is scaled by 8 in bytes */
940 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
941 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
945 sky2_write16(hw
, SK_REG(port
, RX_GMF_UP_THR
), reg
);
946 sky2_write16(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768 / 8);
948 sky2_set_tx_stfwd(hw
, port
);
951 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
952 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
953 /* disable dynamic watermark */
954 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
955 reg
&= ~TX_DYN_WM_ENA
;
956 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
960 /* Assign Ram Buffer allocation to queue */
961 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
965 /* convert from K bytes to qwords used for hw register */
968 end
= start
+ space
- 1;
970 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
971 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
972 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
973 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
974 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
976 if (q
== Q_R1
|| q
== Q_R2
) {
977 u32 tp
= space
- space
/4;
979 /* On receive queue's set the thresholds
980 * give receiver priority when > 3/4 full
981 * send pause when down to 2K
983 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
984 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
987 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
988 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
990 /* Enable store & forward on Tx queue's because
991 * Tx FIFO is only 1K on Yukon
993 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
996 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
997 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
1000 /* Setup Bus Memory Interface */
1001 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
1003 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
1004 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
1005 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
1006 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
1009 /* Setup prefetch unit registers. This is the interface between
1010 * hardware and driver list elements
1012 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
1013 dma_addr_t addr
, u32 last
)
1015 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1016 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
1017 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), upper_32_bits(addr
));
1018 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), lower_32_bits(addr
));
1019 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
1020 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
1022 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
1025 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
, u16
*slot
)
1027 struct sky2_tx_le
*le
= sky2
->tx_le
+ *slot
;
1029 *slot
= RING_NEXT(*slot
, sky2
->tx_ring_size
);
1034 static void tx_init(struct sky2_port
*sky2
)
1036 struct sky2_tx_le
*le
;
1038 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1039 sky2
->tx_tcpsum
= 0;
1040 sky2
->tx_last_mss
= 0;
1042 le
= get_tx_le(sky2
, &sky2
->tx_prod
);
1044 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1045 sky2
->tx_last_upper
= 0;
1048 /* Update chip's next pointer */
1049 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1051 /* Make sure write' to descriptors are complete before we tell hardware */
1053 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1055 /* Synchronize I/O on since next processor may write to tail */
1060 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1062 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1063 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1068 /* Build description to hardware for one receive segment */
1069 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1070 dma_addr_t map
, unsigned len
)
1072 struct sky2_rx_le
*le
;
1074 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1075 le
= sky2_next_rx(sky2
);
1076 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1077 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1080 le
= sky2_next_rx(sky2
);
1081 le
->addr
= cpu_to_le32(lower_32_bits(map
));
1082 le
->length
= cpu_to_le16(len
);
1083 le
->opcode
= op
| HW_OWNER
;
1086 /* Build description to hardware for one possibly fragmented skb */
1087 static void sky2_rx_submit(struct sky2_port
*sky2
,
1088 const struct rx_ring_info
*re
)
1092 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1094 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1095 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1099 static int sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1102 struct sk_buff
*skb
= re
->skb
;
1105 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1106 if (pci_dma_mapping_error(pdev
, re
->data_addr
))
1109 pci_unmap_len_set(re
, data_size
, size
);
1111 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1112 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1114 re
->frag_addr
[i
] = pci_map_page(pdev
, frag
->page
,
1117 PCI_DMA_FROMDEVICE
);
1119 if (pci_dma_mapping_error(pdev
, re
->frag_addr
[i
]))
1120 goto map_page_error
;
1126 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1127 skb_shinfo(skb
)->frags
[i
].size
,
1128 PCI_DMA_FROMDEVICE
);
1131 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1132 PCI_DMA_FROMDEVICE
);
1135 if (net_ratelimit())
1136 dev_warn(&pdev
->dev
, "%s: rx mapping error\n",
1141 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1143 struct sk_buff
*skb
= re
->skb
;
1146 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1147 PCI_DMA_FROMDEVICE
);
1149 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1150 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1151 skb_shinfo(skb
)->frags
[i
].size
,
1152 PCI_DMA_FROMDEVICE
);
1155 /* Tell chip where to start receive checksum.
1156 * Actually has two checksums, but set both same to avoid possible byte
1159 static void rx_set_checksum(struct sky2_port
*sky2
)
1161 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1163 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1165 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1167 sky2_write32(sky2
->hw
,
1168 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1169 (sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
)
1170 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1174 * The RX Stop command will not work for Yukon-2 if the BMU does not
1175 * reach the end of packet and since we can't make sure that we have
1176 * incoming data, we must reset the BMU while it is not doing a DMA
1177 * transfer. Since it is possible that the RX path is still active,
1178 * the RX RAM buffer will be stopped first, so any possible incoming
1179 * data will not trigger a DMA. After the RAM buffer is stopped, the
1180 * BMU is polled until any DMA in progress is ended and only then it
1183 static void sky2_rx_stop(struct sky2_port
*sky2
)
1185 struct sky2_hw
*hw
= sky2
->hw
;
1186 unsigned rxq
= rxqaddr
[sky2
->port
];
1189 /* disable the RAM Buffer receive queue */
1190 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1192 for (i
= 0; i
< 0xffff; i
++)
1193 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1194 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1197 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1198 sky2
->netdev
->name
);
1200 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1202 /* reset the Rx prefetch unit */
1203 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1207 /* Clean out receive buffer area, assumes receiver hardware stopped */
1208 static void sky2_rx_clean(struct sky2_port
*sky2
)
1212 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1213 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1214 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1217 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1224 /* Basic MII support */
1225 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1227 struct mii_ioctl_data
*data
= if_mii(ifr
);
1228 struct sky2_port
*sky2
= netdev_priv(dev
);
1229 struct sky2_hw
*hw
= sky2
->hw
;
1230 int err
= -EOPNOTSUPP
;
1232 if (!netif_running(dev
))
1233 return -ENODEV
; /* Phy still in reset */
1237 data
->phy_id
= PHY_ADDR_MARV
;
1243 spin_lock_bh(&sky2
->phy_lock
);
1244 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1245 spin_unlock_bh(&sky2
->phy_lock
);
1247 data
->val_out
= val
;
1252 spin_lock_bh(&sky2
->phy_lock
);
1253 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1255 spin_unlock_bh(&sky2
->phy_lock
);
1261 #ifdef SKY2_VLAN_TAG_USED
1262 static void sky2_set_vlan_mode(struct sky2_hw
*hw
, u16 port
, bool onoff
)
1265 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1267 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1270 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1272 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1277 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1279 struct sky2_port
*sky2
= netdev_priv(dev
);
1280 struct sky2_hw
*hw
= sky2
->hw
;
1281 u16 port
= sky2
->port
;
1283 netif_tx_lock_bh(dev
);
1284 napi_disable(&hw
->napi
);
1287 sky2_set_vlan_mode(hw
, port
, grp
!= NULL
);
1289 sky2_read32(hw
, B0_Y2_SP_LISR
);
1290 napi_enable(&hw
->napi
);
1291 netif_tx_unlock_bh(dev
);
1295 /* Amount of required worst case padding in rx buffer */
1296 static inline unsigned sky2_rx_pad(const struct sky2_hw
*hw
)
1298 return (hw
->flags
& SKY2_HW_RAM_BUFFER
) ? 8 : 2;
1302 * Allocate an skb for receiving. If the MTU is large enough
1303 * make the skb non-linear with a fragment list of pages.
1305 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1307 struct sk_buff
*skb
;
1310 skb
= netdev_alloc_skb(sky2
->netdev
,
1311 sky2
->rx_data_size
+ sky2_rx_pad(sky2
->hw
));
1315 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1316 unsigned char *start
;
1318 * Workaround for a bug in FIFO that cause hang
1319 * if the FIFO if the receive buffer is not 64 byte aligned.
1320 * The buffer returned from netdev_alloc_skb is
1321 * aligned except if slab debugging is enabled.
1323 start
= PTR_ALIGN(skb
->data
, 8);
1324 skb_reserve(skb
, start
- skb
->data
);
1326 skb_reserve(skb
, NET_IP_ALIGN
);
1328 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1329 struct page
*page
= alloc_page(GFP_ATOMIC
);
1333 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1343 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1345 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1349 * Allocate and setup receiver buffer pool.
1350 * Normal case this ends up creating one list element for skb
1351 * in the receive ring. Worst case if using large MTU and each
1352 * allocation falls on a different 64 bit region, that results
1353 * in 6 list elements per ring entry.
1354 * One element is used for checksum enable/disable, and one
1355 * extra to avoid wrap.
1357 static int sky2_rx_start(struct sky2_port
*sky2
)
1359 struct sky2_hw
*hw
= sky2
->hw
;
1360 struct rx_ring_info
*re
;
1361 unsigned rxq
= rxqaddr
[sky2
->port
];
1362 unsigned i
, size
, thresh
;
1364 sky2
->rx_put
= sky2
->rx_next
= 0;
1367 /* On PCI express lowering the watermark gives better performance */
1368 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1369 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1371 /* These chips have no ram buffer?
1372 * MAC Rx RAM Read is controlled by hardware */
1373 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1374 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
||
1375 hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1376 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1378 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1380 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1381 rx_set_checksum(sky2
);
1383 /* Space needed for frame data + headers rounded up */
1384 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1386 /* Stopping point for hardware truncation */
1387 thresh
= (size
- 8) / sizeof(u32
);
1389 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1390 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1392 /* Compute residue after pages */
1393 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1395 /* Optimize to handle small packets and headers */
1396 if (size
< copybreak
)
1398 if (size
< ETH_HLEN
)
1401 sky2
->rx_data_size
= size
;
1404 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1405 re
= sky2
->rx_ring
+ i
;
1407 re
->skb
= sky2_rx_alloc(sky2
);
1411 if (sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
)) {
1412 dev_kfree_skb(re
->skb
);
1417 sky2_rx_submit(sky2
, re
);
1421 * The receiver hangs if it receives frames larger than the
1422 * packet buffer. As a workaround, truncate oversize frames, but
1423 * the register is limited to 9 bits, so if you do frames > 2052
1424 * you better get the MTU right!
1427 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1429 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1430 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1433 /* Tell chip about available buffers */
1434 sky2_rx_update(sky2
, rxq
);
1436 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
1437 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
1439 * Disable flushing of non ASF packets;
1440 * must be done after initializing the BMUs;
1441 * drivers without ASF support should do this too, otherwise
1442 * it may happen that they cannot run on ASF devices;
1443 * remember that the MAC FIFO isn't reset during initialization.
1445 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_MACSEC_FLUSH_OFF
);
1448 if (hw
->chip_id
>= CHIP_ID_YUKON_SUPR
) {
1449 /* Enable RX Home Address & Routing Header checksum fix */
1450 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_FL_CTRL
),
1451 RX_IPV6_SA_MOB_ENA
| RX_IPV6_DA_MOB_ENA
);
1453 /* Enable TX Home Address & Routing Header checksum fix */
1454 sky2_write32(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_TEST
),
1455 TBMU_TEST_HOME_ADD_FIX_EN
| TBMU_TEST_ROUTING_ADD_FIX_EN
);
1462 sky2_rx_clean(sky2
);
1466 static int sky2_alloc_buffers(struct sky2_port
*sky2
)
1468 struct sky2_hw
*hw
= sky2
->hw
;
1470 /* must be power of 2 */
1471 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1472 sky2
->tx_ring_size
*
1473 sizeof(struct sky2_tx_le
),
1478 sky2
->tx_ring
= kcalloc(sky2
->tx_ring_size
, sizeof(struct tx_ring_info
),
1483 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1487 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1489 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1499 static void sky2_free_buffers(struct sky2_port
*sky2
)
1501 struct sky2_hw
*hw
= sky2
->hw
;
1504 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1505 sky2
->rx_le
, sky2
->rx_le_map
);
1509 pci_free_consistent(hw
->pdev
,
1510 sky2
->tx_ring_size
* sizeof(struct sky2_tx_le
),
1511 sky2
->tx_le
, sky2
->tx_le_map
);
1514 kfree(sky2
->tx_ring
);
1515 kfree(sky2
->rx_ring
);
1517 sky2
->tx_ring
= NULL
;
1518 sky2
->rx_ring
= NULL
;
1521 /* Bring up network interface. */
1522 static int sky2_up(struct net_device
*dev
)
1524 struct sky2_port
*sky2
= netdev_priv(dev
);
1525 struct sky2_hw
*hw
= sky2
->hw
;
1526 unsigned port
= sky2
->port
;
1529 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1532 * On dual port PCI-X card, there is an problem where status
1533 * can be received out of order due to split transactions
1535 if (otherdev
&& netif_running(otherdev
) &&
1536 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1539 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1540 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1541 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1545 netif_carrier_off(dev
);
1547 err
= sky2_alloc_buffers(sky2
);
1553 sky2_mac_init(hw
, port
);
1555 /* Register is number of 4K blocks on internal RAM buffer. */
1556 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1560 pr_debug(PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1562 rxspace
= ramsize
/ 2;
1564 rxspace
= 8 + (2*(ramsize
- 16))/3;
1566 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1567 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1569 /* Make sure SyncQ is disabled */
1570 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1574 sky2_qset(hw
, txqaddr
[port
]);
1576 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1577 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1578 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1580 /* Set almost empty threshold */
1581 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1582 hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1583 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1585 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1586 sky2
->tx_ring_size
- 1);
1588 #ifdef SKY2_VLAN_TAG_USED
1589 sky2_set_vlan_mode(hw
, port
, sky2
->vlgrp
!= NULL
);
1592 err
= sky2_rx_start(sky2
);
1596 /* Enable interrupts from phy/mac for port */
1597 imask
= sky2_read32(hw
, B0_IMSK
);
1598 imask
|= portirq_msk
[port
];
1599 sky2_write32(hw
, B0_IMSK
, imask
);
1600 sky2_read32(hw
, B0_IMSK
);
1602 if (netif_msg_ifup(sky2
))
1603 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1608 sky2_free_buffers(sky2
);
1612 /* Modular subtraction in ring */
1613 static inline int tx_inuse(const struct sky2_port
*sky2
)
1615 return (sky2
->tx_prod
- sky2
->tx_cons
) & (sky2
->tx_ring_size
- 1);
1618 /* Number of list elements available for next tx */
1619 static inline int tx_avail(const struct sky2_port
*sky2
)
1621 return sky2
->tx_pending
- tx_inuse(sky2
);
1624 /* Estimate of number of transmit list elements required */
1625 static unsigned tx_le_req(const struct sk_buff
*skb
)
1629 count
= (skb_shinfo(skb
)->nr_frags
+ 1)
1630 * (sizeof(dma_addr_t
) / sizeof(u32
));
1632 if (skb_is_gso(skb
))
1634 else if (sizeof(dma_addr_t
) == sizeof(u32
))
1635 ++count
; /* possible vlan */
1637 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1643 static void sky2_tx_unmap(struct pci_dev
*pdev
, struct tx_ring_info
*re
)
1645 if (re
->flags
& TX_MAP_SINGLE
)
1646 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1647 pci_unmap_len(re
, maplen
),
1649 else if (re
->flags
& TX_MAP_PAGE
)
1650 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1651 pci_unmap_len(re
, maplen
),
1657 * Put one packet in ring for transmit.
1658 * A single packet can generate multiple list elements, and
1659 * the number of ring elements will probably be less than the number
1660 * of list elements used.
1662 static netdev_tx_t
sky2_xmit_frame(struct sk_buff
*skb
,
1663 struct net_device
*dev
)
1665 struct sky2_port
*sky2
= netdev_priv(dev
);
1666 struct sky2_hw
*hw
= sky2
->hw
;
1667 struct sky2_tx_le
*le
= NULL
;
1668 struct tx_ring_info
*re
;
1676 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1677 return NETDEV_TX_BUSY
;
1679 len
= skb_headlen(skb
);
1680 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1682 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1685 slot
= sky2
->tx_prod
;
1686 if (unlikely(netif_msg_tx_queued(sky2
)))
1687 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1688 dev
->name
, slot
, skb
->len
);
1690 /* Send high bits if needed */
1691 upper
= upper_32_bits(mapping
);
1692 if (upper
!= sky2
->tx_last_upper
) {
1693 le
= get_tx_le(sky2
, &slot
);
1694 le
->addr
= cpu_to_le32(upper
);
1695 sky2
->tx_last_upper
= upper
;
1696 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1699 /* Check for TCP Segmentation Offload */
1700 mss
= skb_shinfo(skb
)->gso_size
;
1703 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1704 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1706 if (mss
!= sky2
->tx_last_mss
) {
1707 le
= get_tx_le(sky2
, &slot
);
1708 le
->addr
= cpu_to_le32(mss
);
1710 if (hw
->flags
& SKY2_HW_NEW_LE
)
1711 le
->opcode
= OP_MSS
| HW_OWNER
;
1713 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1714 sky2
->tx_last_mss
= mss
;
1719 #ifdef SKY2_VLAN_TAG_USED
1720 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1721 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1723 le
= get_tx_le(sky2
, &slot
);
1725 le
->opcode
= OP_VLAN
|HW_OWNER
;
1727 le
->opcode
|= OP_VLAN
;
1728 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1733 /* Handle TCP checksum offload */
1734 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1735 /* On Yukon EX (some versions) encoding change. */
1736 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1737 ctrl
|= CALSUM
; /* auto checksum */
1739 const unsigned offset
= skb_transport_offset(skb
);
1742 tcpsum
= offset
<< 16; /* sum start */
1743 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1745 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1746 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1749 if (tcpsum
!= sky2
->tx_tcpsum
) {
1750 sky2
->tx_tcpsum
= tcpsum
;
1752 le
= get_tx_le(sky2
, &slot
);
1753 le
->addr
= cpu_to_le32(tcpsum
);
1754 le
->length
= 0; /* initial checksum value */
1755 le
->ctrl
= 1; /* one packet */
1756 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1761 re
= sky2
->tx_ring
+ slot
;
1762 re
->flags
= TX_MAP_SINGLE
;
1763 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1764 pci_unmap_len_set(re
, maplen
, len
);
1766 le
= get_tx_le(sky2
, &slot
);
1767 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1768 le
->length
= cpu_to_le16(len
);
1770 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1773 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1774 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1776 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1777 frag
->size
, PCI_DMA_TODEVICE
);
1779 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1780 goto mapping_unwind
;
1782 upper
= upper_32_bits(mapping
);
1783 if (upper
!= sky2
->tx_last_upper
) {
1784 le
= get_tx_le(sky2
, &slot
);
1785 le
->addr
= cpu_to_le32(upper
);
1786 sky2
->tx_last_upper
= upper
;
1787 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1790 re
= sky2
->tx_ring
+ slot
;
1791 re
->flags
= TX_MAP_PAGE
;
1792 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1793 pci_unmap_len_set(re
, maplen
, frag
->size
);
1795 le
= get_tx_le(sky2
, &slot
);
1796 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1797 le
->length
= cpu_to_le16(frag
->size
);
1799 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1805 sky2
->tx_prod
= slot
;
1807 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1808 netif_stop_queue(dev
);
1810 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1812 return NETDEV_TX_OK
;
1815 for (i
= sky2
->tx_prod
; i
!= slot
; i
= RING_NEXT(i
, sky2
->tx_ring_size
)) {
1816 re
= sky2
->tx_ring
+ i
;
1818 sky2_tx_unmap(hw
->pdev
, re
);
1822 if (net_ratelimit())
1823 dev_warn(&hw
->pdev
->dev
, "%s: tx mapping error\n", dev
->name
);
1825 return NETDEV_TX_OK
;
1829 * Free ring elements from starting at tx_cons until "done"
1832 * 1. The hardware will tell us about partial completion of multi-part
1833 * buffers so make sure not to free skb to early.
1834 * 2. This may run in parallel start_xmit because the it only
1835 * looks at the tail of the queue of FIFO (tx_cons), not
1836 * the head (tx_prod)
1838 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1840 struct net_device
*dev
= sky2
->netdev
;
1843 BUG_ON(done
>= sky2
->tx_ring_size
);
1845 for (idx
= sky2
->tx_cons
; idx
!= done
;
1846 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
1847 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1848 struct sk_buff
*skb
= re
->skb
;
1850 sky2_tx_unmap(sky2
->hw
->pdev
, re
);
1853 if (unlikely(netif_msg_tx_done(sky2
)))
1854 printk(KERN_DEBUG
"%s: tx done %u\n",
1857 dev
->stats
.tx_packets
++;
1858 dev
->stats
.tx_bytes
+= skb
->len
;
1861 dev_kfree_skb_any(skb
);
1863 sky2
->tx_next
= RING_NEXT(idx
, sky2
->tx_ring_size
);
1867 sky2
->tx_cons
= idx
;
1870 /* Wake unless it's detached, and called e.g. from sky2_down() */
1871 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4 && netif_device_present(dev
))
1872 netif_wake_queue(dev
);
1875 static void sky2_tx_reset(struct sky2_hw
*hw
, unsigned port
)
1877 /* Disable Force Sync bit and Enable Alloc bit */
1878 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1879 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1881 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1882 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1883 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1885 /* Reset the PCI FIFO of the async Tx queue */
1886 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1887 BMU_RST_SET
| BMU_FIFO_RST
);
1889 /* Reset the Tx prefetch units */
1890 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1893 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1894 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1897 /* Network shutdown */
1898 static int sky2_down(struct net_device
*dev
)
1900 struct sky2_port
*sky2
= netdev_priv(dev
);
1901 struct sky2_hw
*hw
= sky2
->hw
;
1902 unsigned port
= sky2
->port
;
1906 /* Never really got started! */
1910 if (netif_msg_ifdown(sky2
))
1911 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1913 /* Force flow control off */
1914 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1916 /* Stop transmitter */
1917 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1918 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1920 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1921 RB_RST_SET
| RB_DIS_OP_MD
);
1923 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1924 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1925 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1927 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1929 /* Workaround shared GMAC reset */
1930 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 &&
1931 port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1932 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1934 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1936 /* Force any delayed status interrrupt and NAPI */
1937 sky2_write32(hw
, STAT_LEV_TIMER_CNT
, 0);
1938 sky2_write32(hw
, STAT_TX_TIMER_CNT
, 0);
1939 sky2_write32(hw
, STAT_ISR_TIMER_CNT
, 0);
1940 sky2_read8(hw
, STAT_ISR_TIMER_CTRL
);
1944 /* Disable port IRQ */
1945 imask
= sky2_read32(hw
, B0_IMSK
);
1946 imask
&= ~portirq_msk
[port
];
1947 sky2_write32(hw
, B0_IMSK
, imask
);
1948 sky2_read32(hw
, B0_IMSK
);
1950 synchronize_irq(hw
->pdev
->irq
);
1951 napi_synchronize(&hw
->napi
);
1953 spin_lock_bh(&sky2
->phy_lock
);
1954 sky2_phy_power_down(hw
, port
);
1955 spin_unlock_bh(&sky2
->phy_lock
);
1957 sky2_tx_reset(hw
, port
);
1959 /* Free any pending frames stuck in HW queue */
1960 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1962 sky2_rx_clean(sky2
);
1964 sky2_free_buffers(sky2
);
1969 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1971 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1974 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1975 if (aux
& PHY_M_PS_SPEED_100
)
1981 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1982 case PHY_M_PS_SPEED_1000
:
1984 case PHY_M_PS_SPEED_100
:
1991 static void sky2_link_up(struct sky2_port
*sky2
)
1993 struct sky2_hw
*hw
= sky2
->hw
;
1994 unsigned port
= sky2
->port
;
1996 static const char *fc_name
[] = {
2004 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2005 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
2006 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2008 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
2010 netif_carrier_on(sky2
->netdev
);
2012 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
2014 /* Turn on link LED */
2015 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
2016 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
2018 if (netif_msg_link(sky2
))
2019 printk(KERN_INFO PFX
2020 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2021 sky2
->netdev
->name
, sky2
->speed
,
2022 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
2023 fc_name
[sky2
->flow_status
]);
2026 static void sky2_link_down(struct sky2_port
*sky2
)
2028 struct sky2_hw
*hw
= sky2
->hw
;
2029 unsigned port
= sky2
->port
;
2032 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
2034 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2035 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2036 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2038 netif_carrier_off(sky2
->netdev
);
2040 /* Turn off link LED */
2041 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
2043 if (netif_msg_link(sky2
))
2044 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
2046 sky2_phy_init(hw
, port
);
2049 static enum flow_control
sky2_flow(int rx
, int tx
)
2052 return tx
? FC_BOTH
: FC_RX
;
2054 return tx
? FC_TX
: FC_NONE
;
2057 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
2059 struct sky2_hw
*hw
= sky2
->hw
;
2060 unsigned port
= sky2
->port
;
2063 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2064 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
2065 if (lpa
& PHY_M_AN_RF
) {
2066 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
2070 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
2071 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
2072 sky2
->netdev
->name
);
2076 sky2
->speed
= sky2_phy_speed(hw
, aux
);
2077 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2079 /* Since the pause result bits seem to in different positions on
2080 * different chips. look at registers.
2082 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
2083 /* Shift for bits in fiber PHY */
2084 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
2085 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
2087 if (advert
& ADVERTISE_1000XPAUSE
)
2088 advert
|= ADVERTISE_PAUSE_CAP
;
2089 if (advert
& ADVERTISE_1000XPSE_ASYM
)
2090 advert
|= ADVERTISE_PAUSE_ASYM
;
2091 if (lpa
& LPA_1000XPAUSE
)
2092 lpa
|= LPA_PAUSE_CAP
;
2093 if (lpa
& LPA_1000XPAUSE_ASYM
)
2094 lpa
|= LPA_PAUSE_ASYM
;
2097 sky2
->flow_status
= FC_NONE
;
2098 if (advert
& ADVERTISE_PAUSE_CAP
) {
2099 if (lpa
& LPA_PAUSE_CAP
)
2100 sky2
->flow_status
= FC_BOTH
;
2101 else if (advert
& ADVERTISE_PAUSE_ASYM
)
2102 sky2
->flow_status
= FC_RX
;
2103 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
2104 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
2105 sky2
->flow_status
= FC_TX
;
2108 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
&&
2109 !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
2110 sky2
->flow_status
= FC_NONE
;
2112 if (sky2
->flow_status
& FC_TX
)
2113 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2115 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2120 /* Interrupt from PHY */
2121 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2123 struct net_device
*dev
= hw
->dev
[port
];
2124 struct sky2_port
*sky2
= netdev_priv(dev
);
2125 u16 istatus
, phystat
;
2127 if (!netif_running(dev
))
2130 spin_lock(&sky2
->phy_lock
);
2131 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2132 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2134 if (netif_msg_intr(sky2
))
2135 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2136 sky2
->netdev
->name
, istatus
, phystat
);
2138 if (istatus
& PHY_M_IS_AN_COMPL
) {
2139 if (sky2_autoneg_done(sky2
, phystat
) == 0)
2144 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2145 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2147 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2149 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2151 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2152 if (phystat
& PHY_M_PS_LINK_UP
)
2155 sky2_link_down(sky2
);
2158 spin_unlock(&sky2
->phy_lock
);
2161 /* Special quick link interrupt (Yukon-2 Optima only) */
2162 static void sky2_qlink_intr(struct sky2_hw
*hw
)
2164 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[0]);
2169 imask
= sky2_read32(hw
, B0_IMSK
);
2170 imask
&= ~Y2_IS_PHY_QLNK
;
2171 sky2_write32(hw
, B0_IMSK
, imask
);
2173 /* reset PHY Link Detect */
2174 phy
= sky2_pci_read16(hw
, PSM_CONFIG_REG4
);
2175 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2176 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, phy
| 1);
2177 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2182 /* Transmit timeout is only called if we are running, carrier is up
2183 * and tx queue is full (stopped).
2185 static void sky2_tx_timeout(struct net_device
*dev
)
2187 struct sky2_port
*sky2
= netdev_priv(dev
);
2188 struct sky2_hw
*hw
= sky2
->hw
;
2190 if (netif_msg_timer(sky2
))
2191 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
2193 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
2194 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
2195 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2196 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2198 /* can't restart safely under softirq */
2199 schedule_work(&hw
->restart_work
);
2202 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2204 struct sky2_port
*sky2
= netdev_priv(dev
);
2205 struct sky2_hw
*hw
= sky2
->hw
;
2206 unsigned port
= sky2
->port
;
2211 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2214 if (new_mtu
> ETH_DATA_LEN
&&
2215 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2216 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2219 if (!netif_running(dev
)) {
2224 imask
= sky2_read32(hw
, B0_IMSK
);
2225 sky2_write32(hw
, B0_IMSK
, 0);
2227 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2228 netif_stop_queue(dev
);
2229 napi_disable(&hw
->napi
);
2231 synchronize_irq(hw
->pdev
->irq
);
2233 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2234 sky2_set_tx_stfwd(hw
, port
);
2236 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2237 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2239 sky2_rx_clean(sky2
);
2243 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2244 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2246 if (dev
->mtu
> ETH_DATA_LEN
)
2247 mode
|= GM_SMOD_JUMBO_ENA
;
2249 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2251 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2253 err
= sky2_rx_start(sky2
);
2254 sky2_write32(hw
, B0_IMSK
, imask
);
2256 sky2_read32(hw
, B0_Y2_SP_LISR
);
2257 napi_enable(&hw
->napi
);
2262 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2264 netif_wake_queue(dev
);
2270 /* For small just reuse existing skb for next receive */
2271 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2272 const struct rx_ring_info
*re
,
2275 struct sk_buff
*skb
;
2277 skb
= netdev_alloc_skb_ip_align(sky2
->netdev
, length
);
2279 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2280 length
, PCI_DMA_FROMDEVICE
);
2281 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2282 skb
->ip_summed
= re
->skb
->ip_summed
;
2283 skb
->csum
= re
->skb
->csum
;
2284 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2285 length
, PCI_DMA_FROMDEVICE
);
2286 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2287 skb_put(skb
, length
);
2292 /* Adjust length of skb with fragments to match received data */
2293 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2294 unsigned int length
)
2299 /* put header into skb */
2300 size
= min(length
, hdr_space
);
2305 num_frags
= skb_shinfo(skb
)->nr_frags
;
2306 for (i
= 0; i
< num_frags
; i
++) {
2307 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2310 /* don't need this page */
2311 __free_page(frag
->page
);
2312 --skb_shinfo(skb
)->nr_frags
;
2314 size
= min(length
, (unsigned) PAGE_SIZE
);
2317 skb
->data_len
+= size
;
2318 skb
->truesize
+= size
;
2325 /* Normal packet - take skb from ring element and put in a new one */
2326 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2327 struct rx_ring_info
*re
,
2328 unsigned int length
)
2330 struct sk_buff
*skb
;
2331 struct rx_ring_info nre
;
2332 unsigned hdr_space
= sky2
->rx_data_size
;
2334 nre
.skb
= sky2_rx_alloc(sky2
);
2335 if (unlikely(!nre
.skb
))
2338 if (sky2_rx_map_skb(sky2
->hw
->pdev
, &nre
, hdr_space
))
2342 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2343 prefetch(skb
->data
);
2346 if (skb_shinfo(skb
)->nr_frags
)
2347 skb_put_frags(skb
, hdr_space
, length
);
2349 skb_put(skb
, length
);
2353 dev_kfree_skb(nre
.skb
);
2359 * Receive one packet.
2360 * For larger packets, get new buffer.
2362 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2363 u16 length
, u32 status
)
2365 struct sky2_port
*sky2
= netdev_priv(dev
);
2366 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2367 struct sk_buff
*skb
= NULL
;
2368 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2370 #ifdef SKY2_VLAN_TAG_USED
2371 /* Account for vlan tag */
2372 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2376 if (unlikely(netif_msg_rx_status(sky2
)))
2377 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2378 dev
->name
, sky2
->rx_next
, status
, length
);
2380 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2381 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2383 /* This chip has hardware problems that generates bogus status.
2384 * So do only marginal checking and expect higher level protocols
2385 * to handle crap frames.
2387 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2388 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2392 if (status
& GMR_FS_ANY_ERR
)
2395 if (!(status
& GMR_FS_RX_OK
))
2398 /* if length reported by DMA does not match PHY, packet was truncated */
2399 if (length
!= count
)
2403 if (length
< copybreak
)
2404 skb
= receive_copy(sky2
, re
, length
);
2406 skb
= receive_new(sky2
, re
, length
);
2408 dev
->stats
.rx_dropped
+= (skb
== NULL
);
2411 sky2_rx_submit(sky2
, re
);
2416 /* Truncation of overlength packets
2417 causes PHY length to not match MAC length */
2418 ++dev
->stats
.rx_length_errors
;
2419 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2420 pr_info(PFX
"%s: rx length error: status %#x length %d\n",
2421 dev
->name
, status
, length
);
2425 ++dev
->stats
.rx_errors
;
2426 if (status
& GMR_FS_RX_FF_OV
) {
2427 dev
->stats
.rx_over_errors
++;
2431 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2432 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2433 dev
->name
, status
, length
);
2435 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2436 dev
->stats
.rx_length_errors
++;
2437 if (status
& GMR_FS_FRAGMENT
)
2438 dev
->stats
.rx_frame_errors
++;
2439 if (status
& GMR_FS_CRC_ERR
)
2440 dev
->stats
.rx_crc_errors
++;
2445 /* Transmit complete */
2446 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2448 struct sky2_port
*sky2
= netdev_priv(dev
);
2450 if (netif_running(dev
))
2451 sky2_tx_complete(sky2
, last
);
2454 static inline void sky2_skb_rx(const struct sky2_port
*sky2
,
2455 u32 status
, struct sk_buff
*skb
)
2457 #ifdef SKY2_VLAN_TAG_USED
2458 u16 vlan_tag
= be16_to_cpu(sky2
->rx_tag
);
2459 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2460 if (skb
->ip_summed
== CHECKSUM_NONE
)
2461 vlan_hwaccel_receive_skb(skb
, sky2
->vlgrp
, vlan_tag
);
2463 vlan_gro_receive(&sky2
->hw
->napi
, sky2
->vlgrp
,
2468 if (skb
->ip_summed
== CHECKSUM_NONE
)
2469 netif_receive_skb(skb
);
2471 napi_gro_receive(&sky2
->hw
->napi
, skb
);
2474 static inline void sky2_rx_done(struct sky2_hw
*hw
, unsigned port
,
2475 unsigned packets
, unsigned bytes
)
2478 struct net_device
*dev
= hw
->dev
[port
];
2480 dev
->stats
.rx_packets
+= packets
;
2481 dev
->stats
.rx_bytes
+= bytes
;
2482 dev
->last_rx
= jiffies
;
2483 sky2_rx_update(netdev_priv(dev
), rxqaddr
[port
]);
2487 /* Process status response ring */
2488 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2491 unsigned int total_bytes
[2] = { 0 };
2492 unsigned int total_packets
[2] = { 0 };
2496 struct sky2_port
*sky2
;
2497 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2499 struct net_device
*dev
;
2500 struct sk_buff
*skb
;
2503 u8 opcode
= le
->opcode
;
2505 if (!(opcode
& HW_OWNER
))
2508 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2510 port
= le
->css
& CSS_LINK_BIT
;
2511 dev
= hw
->dev
[port
];
2512 sky2
= netdev_priv(dev
);
2513 length
= le16_to_cpu(le
->length
);
2514 status
= le32_to_cpu(le
->status
);
2517 switch (opcode
& ~HW_OWNER
) {
2519 total_packets
[port
]++;
2520 total_bytes
[port
] += length
;
2522 skb
= sky2_receive(dev
, length
, status
);
2526 /* This chip reports checksum status differently */
2527 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2528 if ((sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
) &&
2529 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2530 (le
->css
& CSS_TCPUDPCSOK
))
2531 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2533 skb
->ip_summed
= CHECKSUM_NONE
;
2536 skb
->protocol
= eth_type_trans(skb
, dev
);
2538 sky2_skb_rx(sky2
, status
, skb
);
2540 /* Stop after net poll weight */
2541 if (++work_done
>= to_do
)
2545 #ifdef SKY2_VLAN_TAG_USED
2547 sky2
->rx_tag
= length
;
2551 sky2
->rx_tag
= length
;
2555 if (!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
))
2558 /* If this happens then driver assuming wrong format */
2559 if (unlikely(hw
->flags
& SKY2_HW_NEW_LE
)) {
2560 if (net_ratelimit())
2561 printk(KERN_NOTICE
"%s: unexpected"
2562 " checksum status\n",
2567 /* Both checksum counters are programmed to start at
2568 * the same offset, so unless there is a problem they
2569 * should match. This failure is an early indication that
2570 * hardware receive checksumming won't work.
2572 if (likely(status
>> 16 == (status
& 0xffff))) {
2573 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2574 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2575 skb
->csum
= le16_to_cpu(status
);
2577 printk(KERN_NOTICE PFX
"%s: hardware receive "
2578 "checksum problem (status = %#x)\n",
2580 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
2582 sky2_write32(sky2
->hw
,
2583 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2589 /* TX index reports status for both ports */
2590 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2592 sky2_tx_done(hw
->dev
[1],
2593 ((status
>> 24) & 0xff)
2594 | (u16
)(length
& 0xf) << 8);
2598 if (net_ratelimit())
2599 printk(KERN_WARNING PFX
2600 "unknown status opcode 0x%x\n", opcode
);
2602 } while (hw
->st_idx
!= idx
);
2604 /* Fully processed status ring so clear irq */
2605 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2608 sky2_rx_done(hw
, 0, total_packets
[0], total_bytes
[0]);
2609 sky2_rx_done(hw
, 1, total_packets
[1], total_bytes
[1]);
2614 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2616 struct net_device
*dev
= hw
->dev
[port
];
2618 if (net_ratelimit())
2619 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2622 if (status
& Y2_IS_PAR_RD1
) {
2623 if (net_ratelimit())
2624 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2627 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2630 if (status
& Y2_IS_PAR_WR1
) {
2631 if (net_ratelimit())
2632 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2635 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2638 if (status
& Y2_IS_PAR_MAC1
) {
2639 if (net_ratelimit())
2640 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2641 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2644 if (status
& Y2_IS_PAR_RX1
) {
2645 if (net_ratelimit())
2646 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2647 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2650 if (status
& Y2_IS_TCP_TXA1
) {
2651 if (net_ratelimit())
2652 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2654 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2658 static void sky2_hw_intr(struct sky2_hw
*hw
)
2660 struct pci_dev
*pdev
= hw
->pdev
;
2661 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2662 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2666 if (status
& Y2_IS_TIST_OV
)
2667 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2669 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2672 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2673 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2674 if (net_ratelimit())
2675 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2678 sky2_pci_write16(hw
, PCI_STATUS
,
2679 pci_err
| PCI_STATUS_ERROR_BITS
);
2680 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2683 if (status
& Y2_IS_PCI_EXP
) {
2684 /* PCI-Express uncorrectable Error occurred */
2687 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2688 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2689 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2691 if (net_ratelimit())
2692 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2694 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2695 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2698 if (status
& Y2_HWE_L1_MASK
)
2699 sky2_hw_error(hw
, 0, status
);
2701 if (status
& Y2_HWE_L1_MASK
)
2702 sky2_hw_error(hw
, 1, status
);
2705 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2707 struct net_device
*dev
= hw
->dev
[port
];
2708 struct sky2_port
*sky2
= netdev_priv(dev
);
2709 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2711 if (netif_msg_intr(sky2
))
2712 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2715 if (status
& GM_IS_RX_CO_OV
)
2716 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2718 if (status
& GM_IS_TX_CO_OV
)
2719 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2721 if (status
& GM_IS_RX_FF_OR
) {
2722 ++dev
->stats
.rx_fifo_errors
;
2723 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2726 if (status
& GM_IS_TX_FF_UR
) {
2727 ++dev
->stats
.tx_fifo_errors
;
2728 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2732 /* This should never happen it is a bug. */
2733 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
, u16 q
)
2735 struct net_device
*dev
= hw
->dev
[port
];
2736 u16 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2738 dev_err(&hw
->pdev
->dev
, PFX
2739 "%s: descriptor error q=%#x get=%u put=%u\n",
2740 dev
->name
, (unsigned) q
, (unsigned) idx
,
2741 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2743 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2746 static int sky2_rx_hung(struct net_device
*dev
)
2748 struct sky2_port
*sky2
= netdev_priv(dev
);
2749 struct sky2_hw
*hw
= sky2
->hw
;
2750 unsigned port
= sky2
->port
;
2751 unsigned rxq
= rxqaddr
[port
];
2752 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2753 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2754 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2755 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2757 /* If idle and MAC or PCI is stuck */
2758 if (sky2
->check
.last
== dev
->last_rx
&&
2759 ((mac_rp
== sky2
->check
.mac_rp
&&
2760 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2761 /* Check if the PCI RX hang */
2762 (fifo_rp
== sky2
->check
.fifo_rp
&&
2763 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2764 printk(KERN_DEBUG PFX
"%s: hung mac %d:%d fifo %d (%d:%d)\n",
2765 dev
->name
, mac_lev
, mac_rp
, fifo_lev
, fifo_rp
,
2766 sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2769 sky2
->check
.last
= dev
->last_rx
;
2770 sky2
->check
.mac_rp
= mac_rp
;
2771 sky2
->check
.mac_lev
= mac_lev
;
2772 sky2
->check
.fifo_rp
= fifo_rp
;
2773 sky2
->check
.fifo_lev
= fifo_lev
;
2778 static void sky2_watchdog(unsigned long arg
)
2780 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2782 /* Check for lost IRQ once a second */
2783 if (sky2_read32(hw
, B0_ISRC
)) {
2784 napi_schedule(&hw
->napi
);
2788 for (i
= 0; i
< hw
->ports
; i
++) {
2789 struct net_device
*dev
= hw
->dev
[i
];
2790 if (!netif_running(dev
))
2794 /* For chips with Rx FIFO, check if stuck */
2795 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
2796 sky2_rx_hung(dev
)) {
2797 pr_info(PFX
"%s: receiver hang detected\n",
2799 schedule_work(&hw
->restart_work
);
2808 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2811 /* Hardware/software error handling */
2812 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2814 if (net_ratelimit())
2815 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2817 if (status
& Y2_IS_HW_ERR
)
2820 if (status
& Y2_IS_IRQ_MAC1
)
2821 sky2_mac_intr(hw
, 0);
2823 if (status
& Y2_IS_IRQ_MAC2
)
2824 sky2_mac_intr(hw
, 1);
2826 if (status
& Y2_IS_CHK_RX1
)
2827 sky2_le_error(hw
, 0, Q_R1
);
2829 if (status
& Y2_IS_CHK_RX2
)
2830 sky2_le_error(hw
, 1, Q_R2
);
2832 if (status
& Y2_IS_CHK_TXA1
)
2833 sky2_le_error(hw
, 0, Q_XA1
);
2835 if (status
& Y2_IS_CHK_TXA2
)
2836 sky2_le_error(hw
, 1, Q_XA2
);
2839 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
2841 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
2842 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2846 if (unlikely(status
& Y2_IS_ERROR
))
2847 sky2_err_intr(hw
, status
);
2849 if (status
& Y2_IS_IRQ_PHY1
)
2850 sky2_phy_intr(hw
, 0);
2852 if (status
& Y2_IS_IRQ_PHY2
)
2853 sky2_phy_intr(hw
, 1);
2855 if (status
& Y2_IS_PHY_QLNK
)
2856 sky2_qlink_intr(hw
);
2858 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
2859 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
2861 if (work_done
>= work_limit
)
2865 napi_complete(napi
);
2866 sky2_read32(hw
, B0_Y2_SP_LISR
);
2872 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2874 struct sky2_hw
*hw
= dev_id
;
2877 /* Reading this mask interrupts as side effect */
2878 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2879 if (status
== 0 || status
== ~0)
2882 prefetch(&hw
->st_le
[hw
->st_idx
]);
2884 napi_schedule(&hw
->napi
);
2889 #ifdef CONFIG_NET_POLL_CONTROLLER
2890 static void sky2_netpoll(struct net_device
*dev
)
2892 struct sky2_port
*sky2
= netdev_priv(dev
);
2894 napi_schedule(&sky2
->hw
->napi
);
2898 /* Chip internal frequency for clock calculations */
2899 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2901 switch (hw
->chip_id
) {
2902 case CHIP_ID_YUKON_EC
:
2903 case CHIP_ID_YUKON_EC_U
:
2904 case CHIP_ID_YUKON_EX
:
2905 case CHIP_ID_YUKON_SUPR
:
2906 case CHIP_ID_YUKON_UL_2
:
2907 case CHIP_ID_YUKON_OPT
:
2910 case CHIP_ID_YUKON_FE
:
2913 case CHIP_ID_YUKON_FE_P
:
2916 case CHIP_ID_YUKON_XL
:
2924 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2926 return sky2_mhz(hw
) * us
;
2929 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2931 return clk
/ sky2_mhz(hw
);
2935 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2939 /* Enable all clocks and check for bad PCI access */
2940 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2942 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2944 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2945 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2947 switch(hw
->chip_id
) {
2948 case CHIP_ID_YUKON_XL
:
2949 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
2952 case CHIP_ID_YUKON_EC_U
:
2953 hw
->flags
= SKY2_HW_GIGABIT
2955 | SKY2_HW_ADV_POWER_CTL
;
2958 case CHIP_ID_YUKON_EX
:
2959 hw
->flags
= SKY2_HW_GIGABIT
2962 | SKY2_HW_ADV_POWER_CTL
;
2964 /* New transmit checksum */
2965 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2966 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2969 case CHIP_ID_YUKON_EC
:
2970 /* This rev is really old, and requires untested workarounds */
2971 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2972 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2975 hw
->flags
= SKY2_HW_GIGABIT
;
2978 case CHIP_ID_YUKON_FE
:
2981 case CHIP_ID_YUKON_FE_P
:
2982 hw
->flags
= SKY2_HW_NEWER_PHY
2984 | SKY2_HW_AUTO_TX_SUM
2985 | SKY2_HW_ADV_POWER_CTL
;
2988 case CHIP_ID_YUKON_SUPR
:
2989 hw
->flags
= SKY2_HW_GIGABIT
2992 | SKY2_HW_AUTO_TX_SUM
2993 | SKY2_HW_ADV_POWER_CTL
;
2996 case CHIP_ID_YUKON_UL_2
:
2997 hw
->flags
= SKY2_HW_GIGABIT
2998 | SKY2_HW_ADV_POWER_CTL
;
3001 case CHIP_ID_YUKON_OPT
:
3002 hw
->flags
= SKY2_HW_GIGABIT
3004 | SKY2_HW_ADV_POWER_CTL
;
3008 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
3013 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
3014 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
3015 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
3018 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
3019 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
3020 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
3024 if (sky2_read8(hw
, B2_E_0
))
3025 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
3030 static void sky2_reset(struct sky2_hw
*hw
)
3032 struct pci_dev
*pdev
= hw
->pdev
;
3035 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
3038 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
3039 status
= sky2_read16(hw
, HCU_CCSR
);
3040 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
3041 HCU_CCSR_UC_STATE_MSK
);
3042 sky2_write16(hw
, HCU_CCSR
, status
);
3044 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
3045 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
3048 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3049 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
3051 /* allow writes to PCI config */
3052 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3054 /* clear PCI errors, if any */
3055 status
= sky2_pci_read16(hw
, PCI_STATUS
);
3056 status
|= PCI_STATUS_ERROR_BITS
;
3057 sky2_pci_write16(hw
, PCI_STATUS
, status
);
3059 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3061 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3063 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
3066 /* If error bit is stuck on ignore it */
3067 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
3068 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
3070 hwe_mask
|= Y2_IS_PCI_EXP
;
3074 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3076 for (i
= 0; i
< hw
->ports
; i
++) {
3077 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3078 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3080 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
3081 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
3082 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
3083 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
3088 if (hw
->chip_id
== CHIP_ID_YUKON_SUPR
&& hw
->chip_rev
> CHIP_REV_YU_SU_B0
) {
3089 /* enable MACSec clock gating */
3090 sky2_pci_write32(hw
, PCI_DEV_REG3
, P_CLK_MACSEC_DIS
);
3093 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
) {
3097 if (hw
->chip_rev
== 0) {
3098 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3099 sky2_write32(hw
, Y2_PEX_PHY_DATA
, (0x80UL
<< 16) | (1 << 7));
3101 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3104 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3108 reg
<<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE
;
3110 /* reset PHY Link Detect */
3111 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3112 sky2_pci_write16(hw
, PSM_CONFIG_REG4
,
3113 reg
| PSM_CONFIG_REG4_RST_PHY_LINK_DETECT
);
3114 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, reg
);
3117 /* enable PHY Quick Link */
3118 msk
= sky2_read32(hw
, B0_IMSK
);
3119 msk
|= Y2_IS_PHY_QLNK
;
3120 sky2_write32(hw
, B0_IMSK
, msk
);
3122 /* check if PSMv2 was running before */
3123 reg
= sky2_pci_read16(hw
, PSM_CONFIG_REG3
);
3124 if (reg
& PCI_EXP_LNKCTL_ASPMC
) {
3125 int cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3126 /* restore the PCIe Link Control register */
3127 sky2_pci_write16(hw
, cap
+ PCI_EXP_LNKCTL
, reg
);
3129 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3131 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3132 sky2_write32(hw
, Y2_PEX_PHY_DATA
, PEX_DB_ACCESS
| (0x08UL
<< 16));
3135 /* Clear I2C IRQ noise */
3136 sky2_write32(hw
, B2_I2C_IRQ
, 1);
3138 /* turn off hardware timer (unused) */
3139 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3140 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3142 /* Turn off descriptor polling */
3143 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
3145 /* Turn off receive timestamp */
3146 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
3147 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3149 /* enable the Tx Arbiters */
3150 for (i
= 0; i
< hw
->ports
; i
++)
3151 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3153 /* Initialize ram interface */
3154 for (i
= 0; i
< hw
->ports
; i
++) {
3155 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
3157 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
3158 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
3159 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
3160 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
3161 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
3162 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
3163 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
3164 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
3165 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
3166 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
3167 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
3168 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
3171 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
3173 for (i
= 0; i
< hw
->ports
; i
++)
3174 sky2_gmac_reset(hw
, i
);
3176 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
3179 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
3180 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
3182 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
3183 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
3185 /* Set the list last index */
3186 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
3188 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
3189 sky2_write8(hw
, STAT_FIFO_WM
, 16);
3191 /* set Status-FIFO ISR watermark */
3192 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
3193 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
3195 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
3197 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
3198 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
3199 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
3201 /* enable status unit */
3202 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
3204 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3205 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3206 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3209 /* Take device down (offline).
3210 * Equivalent to doing dev_stop() but this does not
3211 * inform upper layers of the transistion.
3213 static void sky2_detach(struct net_device
*dev
)
3215 if (netif_running(dev
)) {
3217 netif_device_detach(dev
); /* stop txq */
3218 netif_tx_unlock(dev
);
3223 /* Bring device back after doing sky2_detach */
3224 static int sky2_reattach(struct net_device
*dev
)
3228 if (netif_running(dev
)) {
3231 printk(KERN_INFO PFX
"%s: could not restart %d\n",
3235 netif_device_attach(dev
);
3236 sky2_set_multicast(dev
);
3243 static void sky2_restart(struct work_struct
*work
)
3245 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
3249 for (i
= 0; i
< hw
->ports
; i
++)
3250 sky2_detach(hw
->dev
[i
]);
3252 napi_disable(&hw
->napi
);
3253 sky2_write32(hw
, B0_IMSK
, 0);
3255 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3256 napi_enable(&hw
->napi
);
3258 for (i
= 0; i
< hw
->ports
; i
++)
3259 sky2_reattach(hw
->dev
[i
]);
3264 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3266 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3269 static void sky2_hw_set_wol(struct sky2_hw
*hw
)
3274 for (i
= 0; i
< hw
->ports
; i
++) {
3275 struct net_device
*dev
= hw
->dev
[i
];
3276 struct sky2_port
*sky2
= netdev_priv(dev
);
3282 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3283 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3284 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
3285 sky2_write32(hw
, B0_CTST
, wol
? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
3287 device_set_wakeup_enable(&hw
->pdev
->dev
, wol
);
3290 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3292 const struct sky2_port
*sky2
= netdev_priv(dev
);
3294 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3295 wol
->wolopts
= sky2
->wol
;
3298 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3300 struct sky2_port
*sky2
= netdev_priv(dev
);
3301 struct sky2_hw
*hw
= sky2
->hw
;
3303 if ((wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
)) ||
3304 !device_can_wakeup(&hw
->pdev
->dev
))
3307 sky2
->wol
= wol
->wolopts
;
3309 sky2_hw_set_wol(hw
);
3311 if (!netif_running(dev
))
3312 sky2_wol_init(sky2
);
3316 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3318 if (sky2_is_copper(hw
)) {
3319 u32 modes
= SUPPORTED_10baseT_Half
3320 | SUPPORTED_10baseT_Full
3321 | SUPPORTED_100baseT_Half
3322 | SUPPORTED_100baseT_Full
3323 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
3325 if (hw
->flags
& SKY2_HW_GIGABIT
)
3326 modes
|= SUPPORTED_1000baseT_Half
3327 | SUPPORTED_1000baseT_Full
;
3330 return SUPPORTED_1000baseT_Half
3331 | SUPPORTED_1000baseT_Full
3336 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3338 struct sky2_port
*sky2
= netdev_priv(dev
);
3339 struct sky2_hw
*hw
= sky2
->hw
;
3341 ecmd
->transceiver
= XCVR_INTERNAL
;
3342 ecmd
->supported
= sky2_supported_modes(hw
);
3343 ecmd
->phy_address
= PHY_ADDR_MARV
;
3344 if (sky2_is_copper(hw
)) {
3345 ecmd
->port
= PORT_TP
;
3346 ecmd
->speed
= sky2
->speed
;
3348 ecmd
->speed
= SPEED_1000
;
3349 ecmd
->port
= PORT_FIBRE
;
3352 ecmd
->advertising
= sky2
->advertising
;
3353 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
3354 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3355 ecmd
->duplex
= sky2
->duplex
;
3359 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3361 struct sky2_port
*sky2
= netdev_priv(dev
);
3362 const struct sky2_hw
*hw
= sky2
->hw
;
3363 u32 supported
= sky2_supported_modes(hw
);
3365 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3366 sky2
->flags
|= SKY2_FLAG_AUTO_SPEED
;
3367 ecmd
->advertising
= supported
;
3373 switch (ecmd
->speed
) {
3375 if (ecmd
->duplex
== DUPLEX_FULL
)
3376 setting
= SUPPORTED_1000baseT_Full
;
3377 else if (ecmd
->duplex
== DUPLEX_HALF
)
3378 setting
= SUPPORTED_1000baseT_Half
;
3383 if (ecmd
->duplex
== DUPLEX_FULL
)
3384 setting
= SUPPORTED_100baseT_Full
;
3385 else if (ecmd
->duplex
== DUPLEX_HALF
)
3386 setting
= SUPPORTED_100baseT_Half
;
3392 if (ecmd
->duplex
== DUPLEX_FULL
)
3393 setting
= SUPPORTED_10baseT_Full
;
3394 else if (ecmd
->duplex
== DUPLEX_HALF
)
3395 setting
= SUPPORTED_10baseT_Half
;
3403 if ((setting
& supported
) == 0)
3406 sky2
->speed
= ecmd
->speed
;
3407 sky2
->duplex
= ecmd
->duplex
;
3408 sky2
->flags
&= ~SKY2_FLAG_AUTO_SPEED
;
3411 sky2
->advertising
= ecmd
->advertising
;
3413 if (netif_running(dev
)) {
3414 sky2_phy_reinit(sky2
);
3415 sky2_set_multicast(dev
);
3421 static void sky2_get_drvinfo(struct net_device
*dev
,
3422 struct ethtool_drvinfo
*info
)
3424 struct sky2_port
*sky2
= netdev_priv(dev
);
3426 strcpy(info
->driver
, DRV_NAME
);
3427 strcpy(info
->version
, DRV_VERSION
);
3428 strcpy(info
->fw_version
, "N/A");
3429 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3432 static const struct sky2_stat
{
3433 char name
[ETH_GSTRING_LEN
];
3436 { "tx_bytes", GM_TXO_OK_HI
},
3437 { "rx_bytes", GM_RXO_OK_HI
},
3438 { "tx_broadcast", GM_TXF_BC_OK
},
3439 { "rx_broadcast", GM_RXF_BC_OK
},
3440 { "tx_multicast", GM_TXF_MC_OK
},
3441 { "rx_multicast", GM_RXF_MC_OK
},
3442 { "tx_unicast", GM_TXF_UC_OK
},
3443 { "rx_unicast", GM_RXF_UC_OK
},
3444 { "tx_mac_pause", GM_TXF_MPAUSE
},
3445 { "rx_mac_pause", GM_RXF_MPAUSE
},
3446 { "collisions", GM_TXF_COL
},
3447 { "late_collision",GM_TXF_LAT_COL
},
3448 { "aborted", GM_TXF_ABO_COL
},
3449 { "single_collisions", GM_TXF_SNG_COL
},
3450 { "multi_collisions", GM_TXF_MUL_COL
},
3452 { "rx_short", GM_RXF_SHT
},
3453 { "rx_runt", GM_RXE_FRAG
},
3454 { "rx_64_byte_packets", GM_RXF_64B
},
3455 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3456 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3457 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3458 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3459 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3460 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3461 { "rx_too_long", GM_RXF_LNG_ERR
},
3462 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3463 { "rx_jabber", GM_RXF_JAB_PKT
},
3464 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3466 { "tx_64_byte_packets", GM_TXF_64B
},
3467 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3468 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3469 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3470 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3471 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3472 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3473 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3476 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3478 struct sky2_port
*sky2
= netdev_priv(dev
);
3480 return !!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
);
3483 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3485 struct sky2_port
*sky2
= netdev_priv(dev
);
3488 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
3490 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
3492 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3493 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3498 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3500 struct sky2_port
*sky2
= netdev_priv(netdev
);
3501 return sky2
->msg_enable
;
3504 static int sky2_nway_reset(struct net_device
*dev
)
3506 struct sky2_port
*sky2
= netdev_priv(dev
);
3508 if (!netif_running(dev
) || !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
))
3511 sky2_phy_reinit(sky2
);
3512 sky2_set_multicast(dev
);
3517 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3519 struct sky2_hw
*hw
= sky2
->hw
;
3520 unsigned port
= sky2
->port
;
3523 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3524 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3525 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3526 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3528 for (i
= 2; i
< count
; i
++)
3529 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3532 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3534 struct sky2_port
*sky2
= netdev_priv(netdev
);
3535 sky2
->msg_enable
= value
;
3538 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3542 return ARRAY_SIZE(sky2_stats
);
3548 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3549 struct ethtool_stats
*stats
, u64
* data
)
3551 struct sky2_port
*sky2
= netdev_priv(dev
);
3553 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3556 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3560 switch (stringset
) {
3562 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3563 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3564 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3569 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3571 struct sky2_port
*sky2
= netdev_priv(dev
);
3572 struct sky2_hw
*hw
= sky2
->hw
;
3573 unsigned port
= sky2
->port
;
3574 const struct sockaddr
*addr
= p
;
3576 if (!is_valid_ether_addr(addr
->sa_data
))
3577 return -EADDRNOTAVAIL
;
3579 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3580 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3581 dev
->dev_addr
, ETH_ALEN
);
3582 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3583 dev
->dev_addr
, ETH_ALEN
);
3585 /* virtual address for data */
3586 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3588 /* physical address: used for pause frames */
3589 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3594 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3598 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3599 filter
[bit
>> 3] |= 1 << (bit
& 7);
3602 static void sky2_set_multicast(struct net_device
*dev
)
3604 struct sky2_port
*sky2
= netdev_priv(dev
);
3605 struct sky2_hw
*hw
= sky2
->hw
;
3606 unsigned port
= sky2
->port
;
3607 struct dev_mc_list
*list
= dev
->mc_list
;
3611 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3613 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3614 memset(filter
, 0, sizeof(filter
));
3616 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3617 reg
|= GM_RXCR_UCF_ENA
;
3619 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3620 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3621 else if (dev
->flags
& IFF_ALLMULTI
)
3622 memset(filter
, 0xff, sizeof(filter
));
3623 else if (dev
->mc_count
== 0 && !rx_pause
)
3624 reg
&= ~GM_RXCR_MCF_ENA
;
3627 reg
|= GM_RXCR_MCF_ENA
;
3630 sky2_add_filter(filter
, pause_mc_addr
);
3632 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3633 sky2_add_filter(filter
, list
->dmi_addr
);
3636 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3637 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3638 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3639 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3640 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3641 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3642 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3643 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3645 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3648 /* Can have one global because blinking is controlled by
3649 * ethtool and that is always under RTNL mutex
3651 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3653 struct sky2_hw
*hw
= sky2
->hw
;
3654 unsigned port
= sky2
->port
;
3656 spin_lock_bh(&sky2
->phy_lock
);
3657 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3658 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3659 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3661 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3662 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3666 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3667 PHY_M_LEDC_LOS_CTRL(8) |
3668 PHY_M_LEDC_INIT_CTRL(8) |
3669 PHY_M_LEDC_STA1_CTRL(8) |
3670 PHY_M_LEDC_STA0_CTRL(8));
3673 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3674 PHY_M_LEDC_LOS_CTRL(9) |
3675 PHY_M_LEDC_INIT_CTRL(9) |
3676 PHY_M_LEDC_STA1_CTRL(9) |
3677 PHY_M_LEDC_STA0_CTRL(9));
3680 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3681 PHY_M_LEDC_LOS_CTRL(0xa) |
3682 PHY_M_LEDC_INIT_CTRL(0xa) |
3683 PHY_M_LEDC_STA1_CTRL(0xa) |
3684 PHY_M_LEDC_STA0_CTRL(0xa));
3687 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3688 PHY_M_LEDC_LOS_CTRL(1) |
3689 PHY_M_LEDC_INIT_CTRL(8) |
3690 PHY_M_LEDC_STA1_CTRL(7) |
3691 PHY_M_LEDC_STA0_CTRL(7));
3694 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3696 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3697 PHY_M_LED_MO_DUP(mode
) |
3698 PHY_M_LED_MO_10(mode
) |
3699 PHY_M_LED_MO_100(mode
) |
3700 PHY_M_LED_MO_1000(mode
) |
3701 PHY_M_LED_MO_RX(mode
) |
3702 PHY_M_LED_MO_TX(mode
));
3704 spin_unlock_bh(&sky2
->phy_lock
);
3707 /* blink LED's for finding board */
3708 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3710 struct sky2_port
*sky2
= netdev_priv(dev
);
3716 for (i
= 0; i
< data
; i
++) {
3717 sky2_led(sky2
, MO_LED_ON
);
3718 if (msleep_interruptible(500))
3720 sky2_led(sky2
, MO_LED_OFF
);
3721 if (msleep_interruptible(500))
3724 sky2_led(sky2
, MO_LED_NORM
);
3729 static void sky2_get_pauseparam(struct net_device
*dev
,
3730 struct ethtool_pauseparam
*ecmd
)
3732 struct sky2_port
*sky2
= netdev_priv(dev
);
3734 switch (sky2
->flow_mode
) {
3736 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3739 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3742 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3745 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3748 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
)
3749 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3752 static int sky2_set_pauseparam(struct net_device
*dev
,
3753 struct ethtool_pauseparam
*ecmd
)
3755 struct sky2_port
*sky2
= netdev_priv(dev
);
3757 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
3758 sky2
->flags
|= SKY2_FLAG_AUTO_PAUSE
;
3760 sky2
->flags
&= ~SKY2_FLAG_AUTO_PAUSE
;
3762 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3764 if (netif_running(dev
))
3765 sky2_phy_reinit(sky2
);
3770 static int sky2_get_coalesce(struct net_device
*dev
,
3771 struct ethtool_coalesce
*ecmd
)
3773 struct sky2_port
*sky2
= netdev_priv(dev
);
3774 struct sky2_hw
*hw
= sky2
->hw
;
3776 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3777 ecmd
->tx_coalesce_usecs
= 0;
3779 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3780 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3782 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3784 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3785 ecmd
->rx_coalesce_usecs
= 0;
3787 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3788 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3790 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3792 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3793 ecmd
->rx_coalesce_usecs_irq
= 0;
3795 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3796 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3799 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3804 /* Note: this affect both ports */
3805 static int sky2_set_coalesce(struct net_device
*dev
,
3806 struct ethtool_coalesce
*ecmd
)
3808 struct sky2_port
*sky2
= netdev_priv(dev
);
3809 struct sky2_hw
*hw
= sky2
->hw
;
3810 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3812 if (ecmd
->tx_coalesce_usecs
> tmax
||
3813 ecmd
->rx_coalesce_usecs
> tmax
||
3814 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3817 if (ecmd
->tx_max_coalesced_frames
>= sky2
->tx_ring_size
-1)
3819 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3821 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3824 if (ecmd
->tx_coalesce_usecs
== 0)
3825 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3827 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3828 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3829 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3831 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3833 if (ecmd
->rx_coalesce_usecs
== 0)
3834 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3836 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3837 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3838 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3840 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3842 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3843 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3845 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3846 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3847 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3849 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3853 static void sky2_get_ringparam(struct net_device
*dev
,
3854 struct ethtool_ringparam
*ering
)
3856 struct sky2_port
*sky2
= netdev_priv(dev
);
3858 ering
->rx_max_pending
= RX_MAX_PENDING
;
3859 ering
->rx_mini_max_pending
= 0;
3860 ering
->rx_jumbo_max_pending
= 0;
3861 ering
->tx_max_pending
= TX_MAX_PENDING
;
3863 ering
->rx_pending
= sky2
->rx_pending
;
3864 ering
->rx_mini_pending
= 0;
3865 ering
->rx_jumbo_pending
= 0;
3866 ering
->tx_pending
= sky2
->tx_pending
;
3869 static int sky2_set_ringparam(struct net_device
*dev
,
3870 struct ethtool_ringparam
*ering
)
3872 struct sky2_port
*sky2
= netdev_priv(dev
);
3874 if (ering
->rx_pending
> RX_MAX_PENDING
||
3875 ering
->rx_pending
< 8 ||
3876 ering
->tx_pending
< TX_MIN_PENDING
||
3877 ering
->tx_pending
> TX_MAX_PENDING
)
3882 sky2
->rx_pending
= ering
->rx_pending
;
3883 sky2
->tx_pending
= ering
->tx_pending
;
3884 sky2
->tx_ring_size
= roundup_pow_of_two(sky2
->tx_pending
+1);
3886 return sky2_reattach(dev
);
3889 static int sky2_get_regs_len(struct net_device
*dev
)
3894 static int sky2_reg_access_ok(struct sky2_hw
*hw
, unsigned int b
)
3896 /* This complicated switch statement is to make sure and
3897 * only access regions that are unreserved.
3898 * Some blocks are only valid on dual port cards.
3902 case 5: /* Tx Arbiter 2 */
3904 case 14 ... 15: /* TX2 */
3905 case 17: case 19: /* Ram Buffer 2 */
3906 case 22 ... 23: /* Tx Ram Buffer 2 */
3907 case 25: /* Rx MAC Fifo 1 */
3908 case 27: /* Tx MAC Fifo 2 */
3909 case 31: /* GPHY 2 */
3910 case 40 ... 47: /* Pattern Ram 2 */
3911 case 52: case 54: /* TCP Segmentation 2 */
3912 case 112 ... 116: /* GMAC 2 */
3913 return hw
->ports
> 1;
3915 case 0: /* Control */
3916 case 2: /* Mac address */
3917 case 4: /* Tx Arbiter 1 */
3918 case 7: /* PCI express reg */
3920 case 12 ... 13: /* TX1 */
3921 case 16: case 18:/* Rx Ram Buffer 1 */
3922 case 20 ... 21: /* Tx Ram Buffer 1 */
3923 case 24: /* Rx MAC Fifo 1 */
3924 case 26: /* Tx MAC Fifo 1 */
3925 case 28 ... 29: /* Descriptor and status unit */
3926 case 30: /* GPHY 1*/
3927 case 32 ... 39: /* Pattern Ram 1 */
3928 case 48: case 50: /* TCP Segmentation 1 */
3929 case 56 ... 60: /* PCI space */
3930 case 80 ... 84: /* GMAC 1 */
3939 * Returns copy of control register region
3940 * Note: ethtool_get_regs always provides full size (16k) buffer
3942 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3945 const struct sky2_port
*sky2
= netdev_priv(dev
);
3946 const void __iomem
*io
= sky2
->hw
->regs
;
3951 for (b
= 0; b
< 128; b
++) {
3952 /* skip poisonous diagnostic ram region in block 3 */
3954 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
3955 else if (sky2_reg_access_ok(sky2
->hw
, b
))
3956 memcpy_fromio(p
, io
, 128);
3965 /* In order to do Jumbo packets on these chips, need to turn off the
3966 * transmit store/forward. Therefore checksum offload won't work.
3968 static int no_tx_offload(struct net_device
*dev
)
3970 const struct sky2_port
*sky2
= netdev_priv(dev
);
3971 const struct sky2_hw
*hw
= sky2
->hw
;
3973 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3976 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3978 if (data
&& no_tx_offload(dev
))
3981 return ethtool_op_set_tx_csum(dev
, data
);
3985 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3987 if (data
&& no_tx_offload(dev
))
3990 return ethtool_op_set_tso(dev
, data
);
3993 static int sky2_get_eeprom_len(struct net_device
*dev
)
3995 struct sky2_port
*sky2
= netdev_priv(dev
);
3996 struct sky2_hw
*hw
= sky2
->hw
;
3999 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4000 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4003 static int sky2_vpd_wait(const struct sky2_hw
*hw
, int cap
, u16 busy
)
4005 unsigned long start
= jiffies
;
4007 while ( (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
) == busy
) {
4008 /* Can take up to 10.6 ms for write */
4009 if (time_after(jiffies
, start
+ HZ
/4)) {
4010 dev_err(&hw
->pdev
->dev
, PFX
"VPD cycle timed out");
4019 static int sky2_vpd_read(struct sky2_hw
*hw
, int cap
, void *data
,
4020 u16 offset
, size_t length
)
4024 while (length
> 0) {
4027 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
4028 rc
= sky2_vpd_wait(hw
, cap
, 0);
4032 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
4034 memcpy(data
, &val
, min(sizeof(val
), length
));
4035 offset
+= sizeof(u32
);
4036 data
+= sizeof(u32
);
4037 length
-= sizeof(u32
);
4043 static int sky2_vpd_write(struct sky2_hw
*hw
, int cap
, const void *data
,
4044 u16 offset
, unsigned int length
)
4049 for (i
= 0; i
< length
; i
+= sizeof(u32
)) {
4050 u32 val
= *(u32
*)(data
+ i
);
4052 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
4053 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
4055 rc
= sky2_vpd_wait(hw
, cap
, PCI_VPD_ADDR_F
);
4062 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4065 struct sky2_port
*sky2
= netdev_priv(dev
);
4066 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4071 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
4073 return sky2_vpd_read(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4076 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4079 struct sky2_port
*sky2
= netdev_priv(dev
);
4080 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4085 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
4088 /* Partial writes not supported */
4089 if ((eeprom
->offset
& 3) || (eeprom
->len
& 3))
4092 return sky2_vpd_write(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4096 static const struct ethtool_ops sky2_ethtool_ops
= {
4097 .get_settings
= sky2_get_settings
,
4098 .set_settings
= sky2_set_settings
,
4099 .get_drvinfo
= sky2_get_drvinfo
,
4100 .get_wol
= sky2_get_wol
,
4101 .set_wol
= sky2_set_wol
,
4102 .get_msglevel
= sky2_get_msglevel
,
4103 .set_msglevel
= sky2_set_msglevel
,
4104 .nway_reset
= sky2_nway_reset
,
4105 .get_regs_len
= sky2_get_regs_len
,
4106 .get_regs
= sky2_get_regs
,
4107 .get_link
= ethtool_op_get_link
,
4108 .get_eeprom_len
= sky2_get_eeprom_len
,
4109 .get_eeprom
= sky2_get_eeprom
,
4110 .set_eeprom
= sky2_set_eeprom
,
4111 .set_sg
= ethtool_op_set_sg
,
4112 .set_tx_csum
= sky2_set_tx_csum
,
4113 .set_tso
= sky2_set_tso
,
4114 .get_rx_csum
= sky2_get_rx_csum
,
4115 .set_rx_csum
= sky2_set_rx_csum
,
4116 .get_strings
= sky2_get_strings
,
4117 .get_coalesce
= sky2_get_coalesce
,
4118 .set_coalesce
= sky2_set_coalesce
,
4119 .get_ringparam
= sky2_get_ringparam
,
4120 .set_ringparam
= sky2_set_ringparam
,
4121 .get_pauseparam
= sky2_get_pauseparam
,
4122 .set_pauseparam
= sky2_set_pauseparam
,
4123 .phys_id
= sky2_phys_id
,
4124 .get_sset_count
= sky2_get_sset_count
,
4125 .get_ethtool_stats
= sky2_get_ethtool_stats
,
4128 #ifdef CONFIG_SKY2_DEBUG
4130 static struct dentry
*sky2_debug
;
4134 * Read and parse the first part of Vital Product Data
4136 #define VPD_SIZE 128
4137 #define VPD_MAGIC 0x82
4139 static const struct vpd_tag
{
4143 { "PN", "Part Number" },
4144 { "EC", "Engineering Level" },
4145 { "MN", "Manufacturer" },
4146 { "SN", "Serial Number" },
4147 { "YA", "Asset Tag" },
4148 { "VL", "First Error Log Message" },
4149 { "VF", "Second Error Log Message" },
4150 { "VB", "Boot Agent ROM Configuration" },
4151 { "VE", "EFI UNDI Configuration" },
4154 static void sky2_show_vpd(struct seq_file
*seq
, struct sky2_hw
*hw
)
4162 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4163 vpd_size
= 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4165 seq_printf(seq
, "%s Product Data\n", pci_name(hw
->pdev
));
4166 buf
= kmalloc(vpd_size
, GFP_KERNEL
);
4168 seq_puts(seq
, "no memory!\n");
4172 if (pci_read_vpd(hw
->pdev
, 0, vpd_size
, buf
) < 0) {
4173 seq_puts(seq
, "VPD read failed\n");
4177 if (buf
[0] != VPD_MAGIC
) {
4178 seq_printf(seq
, "VPD tag mismatch: %#x\n", buf
[0]);
4182 if (len
== 0 || len
> vpd_size
- 4) {
4183 seq_printf(seq
, "Invalid id length: %d\n", len
);
4187 seq_printf(seq
, "%.*s\n", len
, buf
+ 3);
4190 while (offs
< vpd_size
- 4) {
4193 if (!memcmp("RW", buf
+ offs
, 2)) /* end marker */
4195 len
= buf
[offs
+ 2];
4196 if (offs
+ len
+ 3 >= vpd_size
)
4199 for (i
= 0; i
< ARRAY_SIZE(vpd_tags
); i
++) {
4200 if (!memcmp(vpd_tags
[i
].tag
, buf
+ offs
, 2)) {
4201 seq_printf(seq
, " %s: %.*s\n",
4202 vpd_tags
[i
].label
, len
, buf
+ offs
+ 3);
4212 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
4214 struct net_device
*dev
= seq
->private;
4215 const struct sky2_port
*sky2
= netdev_priv(dev
);
4216 struct sky2_hw
*hw
= sky2
->hw
;
4217 unsigned port
= sky2
->port
;
4221 sky2_show_vpd(seq
, hw
);
4223 seq_printf(seq
, "\nIRQ src=%x mask=%x control=%x\n",
4224 sky2_read32(hw
, B0_ISRC
),
4225 sky2_read32(hw
, B0_IMSK
),
4226 sky2_read32(hw
, B0_Y2_SP_ICR
));
4228 if (!netif_running(dev
)) {
4229 seq_printf(seq
, "network not running\n");
4233 napi_disable(&hw
->napi
);
4234 last
= sky2_read16(hw
, STAT_PUT_IDX
);
4236 if (hw
->st_idx
== last
)
4237 seq_puts(seq
, "Status ring (empty)\n");
4239 seq_puts(seq
, "Status ring\n");
4240 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
4241 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
4242 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
4243 seq_printf(seq
, "[%d] %#x %d %#x\n",
4244 idx
, le
->opcode
, le
->length
, le
->status
);
4246 seq_puts(seq
, "\n");
4249 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
4250 sky2
->tx_cons
, sky2
->tx_prod
,
4251 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
4252 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
4254 /* Dump contents of tx ring */
4256 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< sky2
->tx_ring_size
;
4257 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
4258 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
4259 u32 a
= le32_to_cpu(le
->addr
);
4262 seq_printf(seq
, "%u:", idx
);
4265 switch(le
->opcode
& ~HW_OWNER
) {
4267 seq_printf(seq
, " %#x:", a
);
4270 seq_printf(seq
, " mtu=%d", a
);
4273 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
4276 seq_printf(seq
, " csum=%#x", a
);
4279 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
4282 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
4285 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
4288 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
4289 a
, le16_to_cpu(le
->length
));
4292 if (le
->ctrl
& EOP
) {
4293 seq_putc(seq
, '\n');
4298 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
4299 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
4300 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
4301 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
4303 sky2_read32(hw
, B0_Y2_SP_LISR
);
4304 napi_enable(&hw
->napi
);
4308 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
4310 return single_open(file
, sky2_debug_show
, inode
->i_private
);
4313 static const struct file_operations sky2_debug_fops
= {
4314 .owner
= THIS_MODULE
,
4315 .open
= sky2_debug_open
,
4317 .llseek
= seq_lseek
,
4318 .release
= single_release
,
4322 * Use network device events to create/remove/rename
4323 * debugfs file entries
4325 static int sky2_device_event(struct notifier_block
*unused
,
4326 unsigned long event
, void *ptr
)
4328 struct net_device
*dev
= ptr
;
4329 struct sky2_port
*sky2
= netdev_priv(dev
);
4331 if (dev
->netdev_ops
->ndo_open
!= sky2_up
|| !sky2_debug
)
4335 case NETDEV_CHANGENAME
:
4336 if (sky2
->debugfs
) {
4337 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
4338 sky2_debug
, dev
->name
);
4342 case NETDEV_GOING_DOWN
:
4343 if (sky2
->debugfs
) {
4344 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
4346 debugfs_remove(sky2
->debugfs
);
4347 sky2
->debugfs
= NULL
;
4352 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
4355 if (IS_ERR(sky2
->debugfs
))
4356 sky2
->debugfs
= NULL
;
4362 static struct notifier_block sky2_notifier
= {
4363 .notifier_call
= sky2_device_event
,
4367 static __init
void sky2_debug_init(void)
4371 ent
= debugfs_create_dir("sky2", NULL
);
4372 if (!ent
|| IS_ERR(ent
))
4376 register_netdevice_notifier(&sky2_notifier
);
4379 static __exit
void sky2_debug_cleanup(void)
4382 unregister_netdevice_notifier(&sky2_notifier
);
4383 debugfs_remove(sky2_debug
);
4389 #define sky2_debug_init()
4390 #define sky2_debug_cleanup()
4393 /* Two copies of network device operations to handle special case of
4394 not allowing netpoll on second port */
4395 static const struct net_device_ops sky2_netdev_ops
[2] = {
4397 .ndo_open
= sky2_up
,
4398 .ndo_stop
= sky2_down
,
4399 .ndo_start_xmit
= sky2_xmit_frame
,
4400 .ndo_do_ioctl
= sky2_ioctl
,
4401 .ndo_validate_addr
= eth_validate_addr
,
4402 .ndo_set_mac_address
= sky2_set_mac_address
,
4403 .ndo_set_multicast_list
= sky2_set_multicast
,
4404 .ndo_change_mtu
= sky2_change_mtu
,
4405 .ndo_tx_timeout
= sky2_tx_timeout
,
4406 #ifdef SKY2_VLAN_TAG_USED
4407 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4409 #ifdef CONFIG_NET_POLL_CONTROLLER
4410 .ndo_poll_controller
= sky2_netpoll
,
4414 .ndo_open
= sky2_up
,
4415 .ndo_stop
= sky2_down
,
4416 .ndo_start_xmit
= sky2_xmit_frame
,
4417 .ndo_do_ioctl
= sky2_ioctl
,
4418 .ndo_validate_addr
= eth_validate_addr
,
4419 .ndo_set_mac_address
= sky2_set_mac_address
,
4420 .ndo_set_multicast_list
= sky2_set_multicast
,
4421 .ndo_change_mtu
= sky2_change_mtu
,
4422 .ndo_tx_timeout
= sky2_tx_timeout
,
4423 #ifdef SKY2_VLAN_TAG_USED
4424 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4429 /* Initialize network device */
4430 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
4432 int highmem
, int wol
)
4434 struct sky2_port
*sky2
;
4435 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4438 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
4442 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4443 dev
->irq
= hw
->pdev
->irq
;
4444 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4445 dev
->watchdog_timeo
= TX_WATCHDOG
;
4446 dev
->netdev_ops
= &sky2_netdev_ops
[port
];
4448 sky2
= netdev_priv(dev
);
4451 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4453 /* Auto speed and flow control */
4454 sky2
->flags
= SKY2_FLAG_AUTO_SPEED
| SKY2_FLAG_AUTO_PAUSE
;
4455 if (hw
->chip_id
!= CHIP_ID_YUKON_XL
)
4456 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
4458 sky2
->flow_mode
= FC_BOTH
;
4462 sky2
->advertising
= sky2_supported_modes(hw
);
4465 spin_lock_init(&sky2
->phy_lock
);
4467 sky2
->tx_pending
= TX_DEF_PENDING
;
4468 sky2
->tx_ring_size
= roundup_pow_of_two(TX_DEF_PENDING
+1);
4469 sky2
->rx_pending
= RX_DEF_PENDING
;
4471 hw
->dev
[port
] = dev
;
4475 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
4477 dev
->features
|= NETIF_F_HIGHDMA
;
4479 #ifdef SKY2_VLAN_TAG_USED
4480 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4481 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
4482 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
4483 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4487 /* read the mac address */
4488 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4489 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4494 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4496 const struct sky2_port
*sky2
= netdev_priv(dev
);
4498 if (netif_msg_probe(sky2
))
4499 printk(KERN_INFO PFX
"%s: addr %pM\n",
4500 dev
->name
, dev
->dev_addr
);
4503 /* Handle software interrupt used during MSI test */
4504 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4506 struct sky2_hw
*hw
= dev_id
;
4507 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4512 if (status
& Y2_IS_IRQ_SW
) {
4513 hw
->flags
|= SKY2_HW_USE_MSI
;
4514 wake_up(&hw
->msi_wait
);
4515 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4517 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4522 /* Test interrupt path by forcing a a software IRQ */
4523 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4525 struct pci_dev
*pdev
= hw
->pdev
;
4528 init_waitqueue_head (&hw
->msi_wait
);
4530 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4532 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4534 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4538 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4539 sky2_read8(hw
, B0_CTST
);
4541 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4543 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4544 /* MSI test failed, go back to INTx mode */
4545 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4546 "switching to INTx mode.\n");
4549 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4552 sky2_write32(hw
, B0_IMSK
, 0);
4553 sky2_read32(hw
, B0_IMSK
);
4555 free_irq(pdev
->irq
, hw
);
4560 /* This driver supports yukon2 chipset only */
4561 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4563 const char *name
[] = {
4565 "EC Ultra", /* 0xb4 */
4566 "Extreme", /* 0xb5 */
4570 "Supreme", /* 0xb9 */
4572 "Unknown", /* 0xbb */
4573 "Optima", /* 0xbc */
4576 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
<= CHIP_ID_YUKON_OPT
)
4577 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4579 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4583 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4584 const struct pci_device_id
*ent
)
4586 struct net_device
*dev
;
4588 int err
, using_dac
= 0, wol_default
;
4592 err
= pci_enable_device(pdev
);
4594 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4598 /* Get configuration information
4599 * Note: only regular PCI config access once to test for HW issues
4600 * other PCI access through shared memory for speed and to
4601 * avoid MMCONFIG problems.
4603 err
= pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
4605 dev_err(&pdev
->dev
, "PCI read config failed\n");
4610 dev_err(&pdev
->dev
, "PCI configuration read error\n");
4614 err
= pci_request_regions(pdev
, DRV_NAME
);
4616 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4617 goto err_out_disable
;
4620 pci_set_master(pdev
);
4622 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4623 !(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
4625 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4627 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4628 "for consistent allocations\n");
4629 goto err_out_free_regions
;
4632 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4634 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4635 goto err_out_free_regions
;
4641 /* The sk98lin vendor driver uses hardware byte swapping but
4642 * this driver uses software swapping.
4644 reg
&= ~PCI_REV_DESC
;
4645 err
= pci_write_config_dword(pdev
,PCI_DEV_REG2
, reg
);
4647 dev_err(&pdev
->dev
, "PCI write config failed\n");
4648 goto err_out_free_regions
;
4652 wol_default
= device_may_wakeup(&pdev
->dev
) ? WAKE_MAGIC
: 0;
4656 hw
= kzalloc(sizeof(*hw
) + strlen(DRV_NAME
"@pci:")
4657 + strlen(pci_name(pdev
)) + 1, GFP_KERNEL
);
4659 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4660 goto err_out_free_regions
;
4664 sprintf(hw
->irq_name
, DRV_NAME
"@pci:%s", pci_name(pdev
));
4666 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4668 dev_err(&pdev
->dev
, "cannot map device registers\n");
4669 goto err_out_free_hw
;
4672 /* ring for status responses */
4673 hw
->st_le
= pci_alloc_consistent(pdev
, STATUS_LE_BYTES
, &hw
->st_dma
);
4675 goto err_out_iounmap
;
4677 err
= sky2_init(hw
);
4679 goto err_out_iounmap
;
4681 dev_info(&pdev
->dev
, "Yukon-2 %s chip revision %d\n",
4682 sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)), hw
->chip_rev
);
4686 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4689 goto err_out_free_pci
;
4692 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4693 err
= sky2_test_msi(hw
);
4694 if (err
== -EOPNOTSUPP
)
4695 pci_disable_msi(pdev
);
4697 goto err_out_free_netdev
;
4700 err
= register_netdev(dev
);
4702 dev_err(&pdev
->dev
, "cannot register net device\n");
4703 goto err_out_free_netdev
;
4706 netif_carrier_off(dev
);
4708 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
4710 err
= request_irq(pdev
->irq
, sky2_intr
,
4711 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4714 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4715 goto err_out_unregister
;
4717 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4718 napi_enable(&hw
->napi
);
4720 sky2_show_addr(dev
);
4722 if (hw
->ports
> 1) {
4723 struct net_device
*dev1
;
4726 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4727 if (dev1
&& (err
= register_netdev(dev1
)) == 0)
4728 sky2_show_addr(dev1
);
4730 dev_warn(&pdev
->dev
,
4731 "register of second port failed (%d)\n", err
);
4739 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4740 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4742 pci_set_drvdata(pdev
, hw
);
4743 pdev
->d3_delay
= 150;
4748 if (hw
->flags
& SKY2_HW_USE_MSI
)
4749 pci_disable_msi(pdev
);
4750 unregister_netdev(dev
);
4751 err_out_free_netdev
:
4754 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4755 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4760 err_out_free_regions
:
4761 pci_release_regions(pdev
);
4763 pci_disable_device(pdev
);
4765 pci_set_drvdata(pdev
, NULL
);
4769 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4771 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4777 del_timer_sync(&hw
->watchdog_timer
);
4778 cancel_work_sync(&hw
->restart_work
);
4780 for (i
= hw
->ports
-1; i
>= 0; --i
)
4781 unregister_netdev(hw
->dev
[i
]);
4783 sky2_write32(hw
, B0_IMSK
, 0);
4787 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4788 sky2_read8(hw
, B0_CTST
);
4790 free_irq(pdev
->irq
, hw
);
4791 if (hw
->flags
& SKY2_HW_USE_MSI
)
4792 pci_disable_msi(pdev
);
4793 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4794 pci_release_regions(pdev
);
4795 pci_disable_device(pdev
);
4797 for (i
= hw
->ports
-1; i
>= 0; --i
)
4798 free_netdev(hw
->dev
[i
]);
4803 pci_set_drvdata(pdev
, NULL
);
4807 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4809 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4815 del_timer_sync(&hw
->watchdog_timer
);
4816 cancel_work_sync(&hw
->restart_work
);
4819 for (i
= 0; i
< hw
->ports
; i
++) {
4820 struct net_device
*dev
= hw
->dev
[i
];
4821 struct sky2_port
*sky2
= netdev_priv(dev
);
4826 sky2_wol_init(sky2
);
4831 sky2_write32(hw
, B0_IMSK
, 0);
4832 napi_disable(&hw
->napi
);
4836 pci_save_state(pdev
);
4837 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4838 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4843 static int sky2_resume(struct pci_dev
*pdev
)
4845 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4851 err
= pci_set_power_state(pdev
, PCI_D0
);
4855 err
= pci_restore_state(pdev
);
4859 pci_enable_wake(pdev
, PCI_D0
, 0);
4861 /* Re-enable all clocks */
4862 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
4863 hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
4864 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
4865 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4868 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4869 napi_enable(&hw
->napi
);
4872 for (i
= 0; i
< hw
->ports
; i
++) {
4873 err
= sky2_reattach(hw
->dev
[i
]);
4883 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4884 pci_disable_device(pdev
);
4889 static void sky2_shutdown(struct pci_dev
*pdev
)
4891 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4898 del_timer_sync(&hw
->watchdog_timer
);
4900 for (i
= 0; i
< hw
->ports
; i
++) {
4901 struct net_device
*dev
= hw
->dev
[i
];
4902 struct sky2_port
*sky2
= netdev_priv(dev
);
4906 sky2_wol_init(sky2
);
4914 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4915 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4917 pci_disable_device(pdev
);
4918 pci_set_power_state(pdev
, PCI_D3hot
);
4921 static struct pci_driver sky2_driver
= {
4923 .id_table
= sky2_id_table
,
4924 .probe
= sky2_probe
,
4925 .remove
= __devexit_p(sky2_remove
),
4927 .suspend
= sky2_suspend
,
4928 .resume
= sky2_resume
,
4930 .shutdown
= sky2_shutdown
,
4933 static int __init
sky2_init_module(void)
4935 pr_info(PFX
"driver version " DRV_VERSION
"\n");
4938 return pci_register_driver(&sky2_driver
);
4941 static void __exit
sky2_cleanup_module(void)
4943 pci_unregister_driver(&sky2_driver
);
4944 sky2_debug_cleanup();
4947 module_init(sky2_init_module
);
4948 module_exit(sky2_cleanup_module
);
4950 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4951 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4952 MODULE_LICENSE("GPL");
4953 MODULE_VERSION(DRV_VERSION
);