1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/fcntl.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
36 #include <linux/crc32.h>
37 #include <linux/random.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/bitops.h>
42 #include <linux/gfp.h>
44 #include <asm/system.h>
46 #include <asm/byteorder.h>
47 #include <asm/uaccess.h>
52 #include <asm/idprom.h>
55 #ifdef CONFIG_PPC_PMAC
56 #include <asm/pci-bridge.h>
57 #include <asm/machdep.h>
58 #include <asm/pmac_feature.h>
61 #include "sungem_phy.h"
64 /* Stripping FCS is causing problems, disabled for now */
67 #define DEFAULT_MSG (NETIF_MSG_DRV | \
71 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
72 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
73 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
74 SUPPORTED_Pause | SUPPORTED_Autoneg)
76 #define DRV_NAME "sungem"
77 #define DRV_VERSION "1.0"
78 #define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
80 static char version
[] __devinitdata
=
81 DRV_NAME
".c:v" DRV_VERSION
" " DRV_AUTHOR
"\n";
83 MODULE_AUTHOR(DRV_AUTHOR
);
84 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
85 MODULE_LICENSE("GPL");
87 #define GEM_MODULE_NAME "gem"
89 static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl
) = {
90 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_GEM
,
91 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
93 /* These models only differ from the original GEM in
94 * that their tx/rx fifos are of a different size and
95 * they only support 10/100 speeds. -DaveM
97 * Apple's GMAC does support gigabit on machines with
98 * the BCM54xx PHYs. -BenH
100 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_RIO_GEM
,
101 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
102 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC
,
103 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMACP
,
105 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
106 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2
,
107 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
108 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_K2_GMAC
,
109 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
110 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_SH_SUNGEM
,
111 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
112 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID2_GMAC
,
113 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
117 MODULE_DEVICE_TABLE(pci
, gem_pci_tbl
);
119 static u16
__phy_read(struct gem
*gp
, int phy_addr
, int reg
)
126 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
127 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
128 cmd
|= (MIF_FRAME_TAMSB
);
129 writel(cmd
, gp
->regs
+ MIF_FRAME
);
132 cmd
= readl(gp
->regs
+ MIF_FRAME
);
133 if (cmd
& MIF_FRAME_TALSB
)
142 return cmd
& MIF_FRAME_DATA
;
145 static inline int _phy_read(struct net_device
*dev
, int mii_id
, int reg
)
147 struct gem
*gp
= netdev_priv(dev
);
148 return __phy_read(gp
, mii_id
, reg
);
151 static inline u16
phy_read(struct gem
*gp
, int reg
)
153 return __phy_read(gp
, gp
->mii_phy_addr
, reg
);
156 static void __phy_write(struct gem
*gp
, int phy_addr
, int reg
, u16 val
)
163 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
164 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
165 cmd
|= (MIF_FRAME_TAMSB
);
166 cmd
|= (val
& MIF_FRAME_DATA
);
167 writel(cmd
, gp
->regs
+ MIF_FRAME
);
170 cmd
= readl(gp
->regs
+ MIF_FRAME
);
171 if (cmd
& MIF_FRAME_TALSB
)
178 static inline void _phy_write(struct net_device
*dev
, int mii_id
, int reg
, int val
)
180 struct gem
*gp
= netdev_priv(dev
);
181 __phy_write(gp
, mii_id
, reg
, val
& 0xffff);
184 static inline void phy_write(struct gem
*gp
, int reg
, u16 val
)
186 __phy_write(gp
, gp
->mii_phy_addr
, reg
, val
);
189 static inline void gem_enable_ints(struct gem
*gp
)
191 /* Enable all interrupts but TXDONE */
192 writel(GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
195 static inline void gem_disable_ints(struct gem
*gp
)
197 /* Disable all interrupts, including TXDONE */
198 writel(GREG_STAT_NAPI
| GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
199 (void)readl(gp
->regs
+ GREG_IMASK
); /* write posting */
202 static void gem_get_cell(struct gem
*gp
)
204 BUG_ON(gp
->cell_enabled
< 0);
206 #ifdef CONFIG_PPC_PMAC
207 if (gp
->cell_enabled
== 1) {
209 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 1);
212 #endif /* CONFIG_PPC_PMAC */
215 /* Turn off the chip's clock */
216 static void gem_put_cell(struct gem
*gp
)
218 BUG_ON(gp
->cell_enabled
<= 0);
220 #ifdef CONFIG_PPC_PMAC
221 if (gp
->cell_enabled
== 0) {
223 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 0);
226 #endif /* CONFIG_PPC_PMAC */
229 static inline void gem_netif_stop(struct gem
*gp
)
231 gp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
232 napi_disable(&gp
->napi
);
233 netif_tx_disable(gp
->dev
);
236 static inline void gem_netif_start(struct gem
*gp
)
238 /* NOTE: unconditional netif_wake_queue is only
239 * appropriate so long as all callers are assured to
240 * have free tx slots.
242 netif_wake_queue(gp
->dev
);
243 napi_enable(&gp
->napi
);
246 static void gem_schedule_reset(struct gem
*gp
)
248 gp
->reset_task_pending
= 1;
249 schedule_work(&gp
->reset_task
);
252 static void gem_handle_mif_event(struct gem
*gp
, u32 reg_val
, u32 changed_bits
)
254 if (netif_msg_intr(gp
))
255 printk(KERN_DEBUG
"%s: mif interrupt\n", gp
->dev
->name
);
258 static int gem_pcs_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
260 u32 pcs_istat
= readl(gp
->regs
+ PCS_ISTAT
);
263 if (netif_msg_intr(gp
))
264 printk(KERN_DEBUG
"%s: pcs interrupt, pcs_istat: 0x%x\n",
265 gp
->dev
->name
, pcs_istat
);
267 if (!(pcs_istat
& PCS_ISTAT_LSC
)) {
268 netdev_err(dev
, "PCS irq but no link status change???\n");
272 /* The link status bit latches on zero, so you must
273 * read it twice in such a case to see a transition
274 * to the link being up.
276 pcs_miistat
= readl(gp
->regs
+ PCS_MIISTAT
);
277 if (!(pcs_miistat
& PCS_MIISTAT_LS
))
279 (readl(gp
->regs
+ PCS_MIISTAT
) &
282 if (pcs_miistat
& PCS_MIISTAT_ANC
) {
283 /* The remote-fault indication is only valid
284 * when autoneg has completed.
286 if (pcs_miistat
& PCS_MIISTAT_RF
)
287 netdev_info(dev
, "PCS AutoNEG complete, RemoteFault\n");
289 netdev_info(dev
, "PCS AutoNEG complete\n");
292 if (pcs_miistat
& PCS_MIISTAT_LS
) {
293 netdev_info(dev
, "PCS link is now up\n");
294 netif_carrier_on(gp
->dev
);
296 netdev_info(dev
, "PCS link is now down\n");
297 netif_carrier_off(gp
->dev
);
298 /* If this happens and the link timer is not running,
299 * reset so we re-negotiate.
301 if (!timer_pending(&gp
->link_timer
))
308 static int gem_txmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
310 u32 txmac_stat
= readl(gp
->regs
+ MAC_TXSTAT
);
312 if (netif_msg_intr(gp
))
313 printk(KERN_DEBUG
"%s: txmac interrupt, txmac_stat: 0x%x\n",
314 gp
->dev
->name
, txmac_stat
);
316 /* Defer timer expiration is quite normal,
317 * don't even log the event.
319 if ((txmac_stat
& MAC_TXSTAT_DTE
) &&
320 !(txmac_stat
& ~MAC_TXSTAT_DTE
))
323 if (txmac_stat
& MAC_TXSTAT_URUN
) {
324 netdev_err(dev
, "TX MAC xmit underrun\n");
325 dev
->stats
.tx_fifo_errors
++;
328 if (txmac_stat
& MAC_TXSTAT_MPE
) {
329 netdev_err(dev
, "TX MAC max packet size error\n");
330 dev
->stats
.tx_errors
++;
333 /* The rest are all cases of one of the 16-bit TX
336 if (txmac_stat
& MAC_TXSTAT_NCE
)
337 dev
->stats
.collisions
+= 0x10000;
339 if (txmac_stat
& MAC_TXSTAT_ECE
) {
340 dev
->stats
.tx_aborted_errors
+= 0x10000;
341 dev
->stats
.collisions
+= 0x10000;
344 if (txmac_stat
& MAC_TXSTAT_LCE
) {
345 dev
->stats
.tx_aborted_errors
+= 0x10000;
346 dev
->stats
.collisions
+= 0x10000;
349 /* We do not keep track of MAC_TXSTAT_FCE and
350 * MAC_TXSTAT_PCE events.
355 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
356 * so we do the following.
358 * If any part of the reset goes wrong, we return 1 and that causes the
359 * whole chip to be reset.
361 static int gem_rxmac_reset(struct gem
*gp
)
363 struct net_device
*dev
= gp
->dev
;
368 /* First, reset & disable MAC RX. */
369 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
370 for (limit
= 0; limit
< 5000; limit
++) {
371 if (!(readl(gp
->regs
+ MAC_RXRST
) & MAC_RXRST_CMD
))
376 netdev_err(dev
, "RX MAC will not reset, resetting whole chip\n");
380 writel(gp
->mac_rx_cfg
& ~MAC_RXCFG_ENAB
,
381 gp
->regs
+ MAC_RXCFG
);
382 for (limit
= 0; limit
< 5000; limit
++) {
383 if (!(readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
))
388 netdev_err(dev
, "RX MAC will not disable, resetting whole chip\n");
392 /* Second, disable RX DMA. */
393 writel(0, gp
->regs
+ RXDMA_CFG
);
394 for (limit
= 0; limit
< 5000; limit
++) {
395 if (!(readl(gp
->regs
+ RXDMA_CFG
) & RXDMA_CFG_ENABLE
))
400 netdev_err(dev
, "RX DMA will not disable, resetting whole chip\n");
406 /* Execute RX reset command. */
407 writel(gp
->swrst_base
| GREG_SWRST_RXRST
,
408 gp
->regs
+ GREG_SWRST
);
409 for (limit
= 0; limit
< 5000; limit
++) {
410 if (!(readl(gp
->regs
+ GREG_SWRST
) & GREG_SWRST_RXRST
))
415 netdev_err(dev
, "RX reset command will not execute, resetting whole chip\n");
419 /* Refresh the RX ring. */
420 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
421 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[i
];
423 if (gp
->rx_skbs
[i
] == NULL
) {
424 netdev_err(dev
, "Parts of RX ring empty, resetting whole chip\n");
428 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
430 gp
->rx_new
= gp
->rx_old
= 0;
432 /* Now we must reprogram the rest of RX unit. */
433 desc_dma
= (u64
) gp
->gblock_dvma
;
434 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
435 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
436 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
437 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
438 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
439 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
440 writel(val
, gp
->regs
+ RXDMA_CFG
);
441 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
442 writel(((5 & RXDMA_BLANK_IPKTS
) |
443 ((8 << 12) & RXDMA_BLANK_ITIME
)),
444 gp
->regs
+ RXDMA_BLANK
);
446 writel(((5 & RXDMA_BLANK_IPKTS
) |
447 ((4 << 12) & RXDMA_BLANK_ITIME
)),
448 gp
->regs
+ RXDMA_BLANK
);
449 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
450 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
451 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
452 val
= readl(gp
->regs
+ RXDMA_CFG
);
453 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
454 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
455 val
= readl(gp
->regs
+ MAC_RXCFG
);
456 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
461 static int gem_rxmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
463 u32 rxmac_stat
= readl(gp
->regs
+ MAC_RXSTAT
);
466 if (netif_msg_intr(gp
))
467 printk(KERN_DEBUG
"%s: rxmac interrupt, rxmac_stat: 0x%x\n",
468 gp
->dev
->name
, rxmac_stat
);
470 if (rxmac_stat
& MAC_RXSTAT_OFLW
) {
471 u32 smac
= readl(gp
->regs
+ MAC_SMACHINE
);
473 netdev_err(dev
, "RX MAC fifo overflow smac[%08x]\n", smac
);
474 dev
->stats
.rx_over_errors
++;
475 dev
->stats
.rx_fifo_errors
++;
477 ret
= gem_rxmac_reset(gp
);
480 if (rxmac_stat
& MAC_RXSTAT_ACE
)
481 dev
->stats
.rx_frame_errors
+= 0x10000;
483 if (rxmac_stat
& MAC_RXSTAT_CCE
)
484 dev
->stats
.rx_crc_errors
+= 0x10000;
486 if (rxmac_stat
& MAC_RXSTAT_LCE
)
487 dev
->stats
.rx_length_errors
+= 0x10000;
489 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
495 static int gem_mac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
497 u32 mac_cstat
= readl(gp
->regs
+ MAC_CSTAT
);
499 if (netif_msg_intr(gp
))
500 printk(KERN_DEBUG
"%s: mac interrupt, mac_cstat: 0x%x\n",
501 gp
->dev
->name
, mac_cstat
);
503 /* This interrupt is just for pause frame and pause
504 * tracking. It is useful for diagnostics and debug
505 * but probably by default we will mask these events.
507 if (mac_cstat
& MAC_CSTAT_PS
)
510 if (mac_cstat
& MAC_CSTAT_PRCV
)
511 gp
->pause_last_time_recvd
= (mac_cstat
>> 16);
516 static int gem_mif_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
518 u32 mif_status
= readl(gp
->regs
+ MIF_STATUS
);
519 u32 reg_val
, changed_bits
;
521 reg_val
= (mif_status
& MIF_STATUS_DATA
) >> 16;
522 changed_bits
= (mif_status
& MIF_STATUS_STAT
);
524 gem_handle_mif_event(gp
, reg_val
, changed_bits
);
529 static int gem_pci_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
531 u32 pci_estat
= readl(gp
->regs
+ GREG_PCIESTAT
);
533 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
534 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
535 netdev_err(dev
, "PCI error [%04x]", pci_estat
);
537 if (pci_estat
& GREG_PCIESTAT_BADACK
)
538 pr_cont(" <No ACK64# during ABS64 cycle>");
539 if (pci_estat
& GREG_PCIESTAT_DTRTO
)
540 pr_cont(" <Delayed transaction timeout>");
541 if (pci_estat
& GREG_PCIESTAT_OTHER
)
545 pci_estat
|= GREG_PCIESTAT_OTHER
;
546 netdev_err(dev
, "PCI error\n");
549 if (pci_estat
& GREG_PCIESTAT_OTHER
) {
552 /* Interrogate PCI config space for the
555 pci_read_config_word(gp
->pdev
, PCI_STATUS
,
557 netdev_err(dev
, "Read PCI cfg space status [%04x]\n",
559 if (pci_cfg_stat
& PCI_STATUS_PARITY
)
560 netdev_err(dev
, "PCI parity error detected\n");
561 if (pci_cfg_stat
& PCI_STATUS_SIG_TARGET_ABORT
)
562 netdev_err(dev
, "PCI target abort\n");
563 if (pci_cfg_stat
& PCI_STATUS_REC_TARGET_ABORT
)
564 netdev_err(dev
, "PCI master acks target abort\n");
565 if (pci_cfg_stat
& PCI_STATUS_REC_MASTER_ABORT
)
566 netdev_err(dev
, "PCI master abort\n");
567 if (pci_cfg_stat
& PCI_STATUS_SIG_SYSTEM_ERROR
)
568 netdev_err(dev
, "PCI system error SERR#\n");
569 if (pci_cfg_stat
& PCI_STATUS_DETECTED_PARITY
)
570 netdev_err(dev
, "PCI parity error\n");
572 /* Write the error bits back to clear them. */
573 pci_cfg_stat
&= (PCI_STATUS_PARITY
|
574 PCI_STATUS_SIG_TARGET_ABORT
|
575 PCI_STATUS_REC_TARGET_ABORT
|
576 PCI_STATUS_REC_MASTER_ABORT
|
577 PCI_STATUS_SIG_SYSTEM_ERROR
|
578 PCI_STATUS_DETECTED_PARITY
);
579 pci_write_config_word(gp
->pdev
,
580 PCI_STATUS
, pci_cfg_stat
);
583 /* For all PCI errors, we should reset the chip. */
587 /* All non-normal interrupt conditions get serviced here.
588 * Returns non-zero if we should just exit the interrupt
589 * handler right now (ie. if we reset the card which invalidates
590 * all of the other original irq status bits).
592 static int gem_abnormal_irq(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
594 if (gem_status
& GREG_STAT_RXNOBUF
) {
595 /* Frame arrived, no free RX buffers available. */
596 if (netif_msg_rx_err(gp
))
597 printk(KERN_DEBUG
"%s: no buffer for rx frame\n",
599 dev
->stats
.rx_dropped
++;
602 if (gem_status
& GREG_STAT_RXTAGERR
) {
603 /* corrupt RX tag framing */
604 if (netif_msg_rx_err(gp
))
605 printk(KERN_DEBUG
"%s: corrupt rx tag framing\n",
607 dev
->stats
.rx_errors
++;
612 if (gem_status
& GREG_STAT_PCS
) {
613 if (gem_pcs_interrupt(dev
, gp
, gem_status
))
617 if (gem_status
& GREG_STAT_TXMAC
) {
618 if (gem_txmac_interrupt(dev
, gp
, gem_status
))
622 if (gem_status
& GREG_STAT_RXMAC
) {
623 if (gem_rxmac_interrupt(dev
, gp
, gem_status
))
627 if (gem_status
& GREG_STAT_MAC
) {
628 if (gem_mac_interrupt(dev
, gp
, gem_status
))
632 if (gem_status
& GREG_STAT_MIF
) {
633 if (gem_mif_interrupt(dev
, gp
, gem_status
))
637 if (gem_status
& GREG_STAT_PCIERR
) {
638 if (gem_pci_interrupt(dev
, gp
, gem_status
))
645 static __inline__
void gem_tx(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
650 limit
= ((gem_status
& GREG_STAT_TXNR
) >> GREG_STAT_TXNR_SHIFT
);
651 while (entry
!= limit
) {
658 if (netif_msg_tx_done(gp
))
659 printk(KERN_DEBUG
"%s: tx done, slot %d\n",
660 gp
->dev
->name
, entry
);
661 skb
= gp
->tx_skbs
[entry
];
662 if (skb_shinfo(skb
)->nr_frags
) {
663 int last
= entry
+ skb_shinfo(skb
)->nr_frags
;
667 last
&= (TX_RING_SIZE
- 1);
669 walk
= NEXT_TX(walk
);
678 gp
->tx_skbs
[entry
] = NULL
;
679 dev
->stats
.tx_bytes
+= skb
->len
;
681 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
682 txd
= &gp
->init_block
->txd
[entry
];
684 dma_addr
= le64_to_cpu(txd
->buffer
);
685 dma_len
= le64_to_cpu(txd
->control_word
) & TXDCTRL_BUFSZ
;
687 pci_unmap_page(gp
->pdev
, dma_addr
, dma_len
, PCI_DMA_TODEVICE
);
688 entry
= NEXT_TX(entry
);
691 dev
->stats
.tx_packets
++;
696 /* Need to make the tx_old update visible to gem_start_xmit()
697 * before checking for netif_queue_stopped(). Without the
698 * memory barrier, there is a small possibility that gem_start_xmit()
699 * will miss it and cause the queue to be stopped forever.
703 if (unlikely(netif_queue_stopped(dev
) &&
704 TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))) {
705 struct netdev_queue
*txq
= netdev_get_tx_queue(dev
, 0);
707 __netif_tx_lock(txq
, smp_processor_id());
708 if (netif_queue_stopped(dev
) &&
709 TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))
710 netif_wake_queue(dev
);
711 __netif_tx_unlock(txq
);
715 static __inline__
void gem_post_rxds(struct gem
*gp
, int limit
)
717 int cluster_start
, curr
, count
, kick
;
719 cluster_start
= curr
= (gp
->rx_new
& ~(4 - 1));
723 while (curr
!= limit
) {
724 curr
= NEXT_RX(curr
);
726 struct gem_rxd
*rxd
=
727 &gp
->init_block
->rxd
[cluster_start
];
729 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
731 cluster_start
= NEXT_RX(cluster_start
);
732 if (cluster_start
== curr
)
741 writel(kick
, gp
->regs
+ RXDMA_KICK
);
745 #define ALIGNED_RX_SKB_ADDR(addr) \
746 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
747 static __inline__
struct sk_buff
*gem_alloc_skb(struct net_device
*dev
, int size
,
750 struct sk_buff
*skb
= alloc_skb(size
+ 64, gfp_flags
);
753 unsigned long offset
= ALIGNED_RX_SKB_ADDR(skb
->data
);
754 skb_reserve(skb
, offset
);
760 static int gem_rx(struct gem
*gp
, int work_to_do
)
762 struct net_device
*dev
= gp
->dev
;
763 int entry
, drops
, work_done
= 0;
767 if (netif_msg_rx_status(gp
))
768 printk(KERN_DEBUG
"%s: rx interrupt, done: %d, rx_new: %d\n",
769 gp
->dev
->name
, readl(gp
->regs
+ RXDMA_DONE
), gp
->rx_new
);
773 done
= readl(gp
->regs
+ RXDMA_DONE
);
775 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[entry
];
777 u64 status
= le64_to_cpu(rxd
->status_word
);
781 if ((status
& RXDCTRL_OWN
) != 0)
784 if (work_done
>= RX_RING_SIZE
|| work_done
>= work_to_do
)
787 /* When writing back RX descriptor, GEM writes status
788 * then buffer address, possibly in separate transactions.
789 * If we don't wait for the chip to write both, we could
790 * post a new buffer to this descriptor then have GEM spam
791 * on the buffer address. We sync on the RX completion
792 * register to prevent this from happening.
795 done
= readl(gp
->regs
+ RXDMA_DONE
);
800 /* We can now account for the work we're about to do */
803 skb
= gp
->rx_skbs
[entry
];
805 len
= (status
& RXDCTRL_BUFSZ
) >> 16;
806 if ((len
< ETH_ZLEN
) || (status
& RXDCTRL_BAD
)) {
807 dev
->stats
.rx_errors
++;
809 dev
->stats
.rx_length_errors
++;
810 if (len
& RXDCTRL_BAD
)
811 dev
->stats
.rx_crc_errors
++;
813 /* We'll just return it to GEM. */
815 dev
->stats
.rx_dropped
++;
819 dma_addr
= le64_to_cpu(rxd
->buffer
);
820 if (len
> RX_COPY_THRESHOLD
) {
821 struct sk_buff
*new_skb
;
823 new_skb
= gem_alloc_skb(dev
, RX_BUF_ALLOC_SIZE(gp
), GFP_ATOMIC
);
824 if (new_skb
== NULL
) {
828 pci_unmap_page(gp
->pdev
, dma_addr
,
829 RX_BUF_ALLOC_SIZE(gp
),
831 gp
->rx_skbs
[entry
] = new_skb
;
832 skb_put(new_skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
833 rxd
->buffer
= cpu_to_le64(pci_map_page(gp
->pdev
,
834 virt_to_page(new_skb
->data
),
835 offset_in_page(new_skb
->data
),
836 RX_BUF_ALLOC_SIZE(gp
),
837 PCI_DMA_FROMDEVICE
));
838 skb_reserve(new_skb
, RX_OFFSET
);
840 /* Trim the original skb for the netif. */
843 struct sk_buff
*copy_skb
= netdev_alloc_skb(dev
, len
+ 2);
845 if (copy_skb
== NULL
) {
850 skb_reserve(copy_skb
, 2);
851 skb_put(copy_skb
, len
);
852 pci_dma_sync_single_for_cpu(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
853 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
854 pci_dma_sync_single_for_device(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
856 /* We'll reuse the original ring buffer. */
860 csum
= (__force __sum16
)htons((status
& RXDCTRL_TCPCSUM
) ^ 0xffff);
861 skb
->csum
= csum_unfold(csum
);
862 skb
->ip_summed
= CHECKSUM_COMPLETE
;
863 skb
->protocol
= eth_type_trans(skb
, gp
->dev
);
865 napi_gro_receive(&gp
->napi
, skb
);
867 dev
->stats
.rx_packets
++;
868 dev
->stats
.rx_bytes
+= len
;
871 entry
= NEXT_RX(entry
);
874 gem_post_rxds(gp
, entry
);
879 netdev_info(gp
->dev
, "Memory squeeze, deferring packet\n");
884 static int gem_poll(struct napi_struct
*napi
, int budget
)
886 struct gem
*gp
= container_of(napi
, struct gem
, napi
);
887 struct net_device
*dev
= gp
->dev
;
892 /* Handle anomalies */
893 if (unlikely(gp
->status
& GREG_STAT_ABNORMAL
)) {
894 struct netdev_queue
*txq
= netdev_get_tx_queue(dev
, 0);
897 /* We run the abnormal interrupt handling code with
898 * the Tx lock. It only resets the Rx portion of the
899 * chip, but we need to guard it against DMA being
900 * restarted by the link poll timer
902 __netif_tx_lock(txq
, smp_processor_id());
903 reset
= gem_abnormal_irq(dev
, gp
, gp
->status
);
904 __netif_tx_unlock(txq
);
906 gem_schedule_reset(gp
);
912 /* Run TX completion thread */
913 gem_tx(dev
, gp
, gp
->status
);
915 /* Run RX thread. We don't use any locking here,
916 * code willing to do bad things - like cleaning the
917 * rx ring - must call napi_disable(), which
918 * schedule_timeout()'s if polling is already disabled.
920 work_done
+= gem_rx(gp
, budget
- work_done
);
922 if (work_done
>= budget
)
925 gp
->status
= readl(gp
->regs
+ GREG_STAT
);
926 } while (gp
->status
& GREG_STAT_NAPI
);
934 static irqreturn_t
gem_interrupt(int irq
, void *dev_id
)
936 struct net_device
*dev
= dev_id
;
937 struct gem
*gp
= netdev_priv(dev
);
939 if (napi_schedule_prep(&gp
->napi
)) {
940 u32 gem_status
= readl(gp
->regs
+ GREG_STAT
);
942 if (unlikely(gem_status
== 0)) {
943 napi_enable(&gp
->napi
);
946 if (netif_msg_intr(gp
))
947 printk(KERN_DEBUG
"%s: gem_interrupt() gem_status: 0x%x\n",
948 gp
->dev
->name
, gem_status
);
950 gp
->status
= gem_status
;
951 gem_disable_ints(gp
);
952 __napi_schedule(&gp
->napi
);
955 /* If polling was disabled at the time we received that
956 * interrupt, we may return IRQ_HANDLED here while we
957 * should return IRQ_NONE. No big deal...
962 #ifdef CONFIG_NET_POLL_CONTROLLER
963 static void gem_poll_controller(struct net_device
*dev
)
965 struct gem
*gp
= netdev_priv(dev
);
967 disable_irq(gp
->pdev
->irq
);
968 gem_interrupt(gp
->pdev
->irq
, dev
);
969 enable_irq(gp
->pdev
->irq
);
973 static void gem_tx_timeout(struct net_device
*dev
)
975 struct gem
*gp
= netdev_priv(dev
);
977 netdev_err(dev
, "transmit timed out, resetting\n");
979 netdev_err(dev
, "TX_STATE[%08x:%08x:%08x]\n",
980 readl(gp
->regs
+ TXDMA_CFG
),
981 readl(gp
->regs
+ MAC_TXSTAT
),
982 readl(gp
->regs
+ MAC_TXCFG
));
983 netdev_err(dev
, "RX_STATE[%08x:%08x:%08x]\n",
984 readl(gp
->regs
+ RXDMA_CFG
),
985 readl(gp
->regs
+ MAC_RXSTAT
),
986 readl(gp
->regs
+ MAC_RXCFG
));
988 gem_schedule_reset(gp
);
991 static __inline__
int gem_intme(int entry
)
993 /* Algorithm: IRQ every 1/2 of descriptors. */
994 if (!(entry
& ((TX_RING_SIZE
>>1)-1)))
1000 static netdev_tx_t
gem_start_xmit(struct sk_buff
*skb
,
1001 struct net_device
*dev
)
1003 struct gem
*gp
= netdev_priv(dev
);
1008 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1009 const u64 csum_start_off
= skb_checksum_start_offset(skb
);
1010 const u64 csum_stuff_off
= csum_start_off
+ skb
->csum_offset
;
1012 ctrl
= (TXDCTRL_CENAB
|
1013 (csum_start_off
<< 15) |
1014 (csum_stuff_off
<< 21));
1017 if (unlikely(TX_BUFFS_AVAIL(gp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
1018 /* This is a hard error, log it. */
1019 if (!netif_queue_stopped(dev
)) {
1020 netif_stop_queue(dev
);
1021 netdev_err(dev
, "BUG! Tx Ring full when queue awake!\n");
1023 return NETDEV_TX_BUSY
;
1027 gp
->tx_skbs
[entry
] = skb
;
1029 if (skb_shinfo(skb
)->nr_frags
== 0) {
1030 struct gem_txd
*txd
= &gp
->init_block
->txd
[entry
];
1035 mapping
= pci_map_page(gp
->pdev
,
1036 virt_to_page(skb
->data
),
1037 offset_in_page(skb
->data
),
1038 len
, PCI_DMA_TODEVICE
);
1039 ctrl
|= TXDCTRL_SOF
| TXDCTRL_EOF
| len
;
1040 if (gem_intme(entry
))
1041 ctrl
|= TXDCTRL_INTME
;
1042 txd
->buffer
= cpu_to_le64(mapping
);
1044 txd
->control_word
= cpu_to_le64(ctrl
);
1045 entry
= NEXT_TX(entry
);
1047 struct gem_txd
*txd
;
1050 dma_addr_t first_mapping
;
1051 int frag
, first_entry
= entry
;
1054 if (gem_intme(entry
))
1055 intme
|= TXDCTRL_INTME
;
1057 /* We must give this initial chunk to the device last.
1058 * Otherwise we could race with the device.
1060 first_len
= skb_headlen(skb
);
1061 first_mapping
= pci_map_page(gp
->pdev
, virt_to_page(skb
->data
),
1062 offset_in_page(skb
->data
),
1063 first_len
, PCI_DMA_TODEVICE
);
1064 entry
= NEXT_TX(entry
);
1066 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1067 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1072 len
= this_frag
->size
;
1073 mapping
= pci_map_page(gp
->pdev
,
1075 this_frag
->page_offset
,
1076 len
, PCI_DMA_TODEVICE
);
1078 if (frag
== skb_shinfo(skb
)->nr_frags
- 1)
1079 this_ctrl
|= TXDCTRL_EOF
;
1081 txd
= &gp
->init_block
->txd
[entry
];
1082 txd
->buffer
= cpu_to_le64(mapping
);
1084 txd
->control_word
= cpu_to_le64(this_ctrl
| len
);
1086 if (gem_intme(entry
))
1087 intme
|= TXDCTRL_INTME
;
1089 entry
= NEXT_TX(entry
);
1091 txd
= &gp
->init_block
->txd
[first_entry
];
1092 txd
->buffer
= cpu_to_le64(first_mapping
);
1095 cpu_to_le64(ctrl
| TXDCTRL_SOF
| intme
| first_len
);
1099 if (unlikely(TX_BUFFS_AVAIL(gp
) <= (MAX_SKB_FRAGS
+ 1))) {
1100 netif_stop_queue(dev
);
1102 /* netif_stop_queue() must be done before checking
1103 * checking tx index in TX_BUFFS_AVAIL() below, because
1104 * in gem_tx(), we update tx_old before checking for
1105 * netif_queue_stopped().
1108 if (TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))
1109 netif_wake_queue(dev
);
1111 if (netif_msg_tx_queued(gp
))
1112 printk(KERN_DEBUG
"%s: tx queued, slot %d, skblen %d\n",
1113 dev
->name
, entry
, skb
->len
);
1115 writel(gp
->tx_new
, gp
->regs
+ TXDMA_KICK
);
1117 return NETDEV_TX_OK
;
1120 static void gem_pcs_reset(struct gem
*gp
)
1125 /* Reset PCS unit. */
1126 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1127 val
|= PCS_MIICTRL_RST
;
1128 writel(val
, gp
->regs
+ PCS_MIICTRL
);
1131 while (readl(gp
->regs
+ PCS_MIICTRL
) & PCS_MIICTRL_RST
) {
1137 netdev_warn(gp
->dev
, "PCS reset bit would not clear\n");
1140 static void gem_pcs_reinit_adv(struct gem
*gp
)
1144 /* Make sure PCS is disabled while changing advertisement
1147 val
= readl(gp
->regs
+ PCS_CFG
);
1148 val
&= ~(PCS_CFG_ENABLE
| PCS_CFG_TO
);
1149 writel(val
, gp
->regs
+ PCS_CFG
);
1151 /* Advertise all capabilities except asymmetric
1154 val
= readl(gp
->regs
+ PCS_MIIADV
);
1155 val
|= (PCS_MIIADV_FD
| PCS_MIIADV_HD
|
1156 PCS_MIIADV_SP
| PCS_MIIADV_AP
);
1157 writel(val
, gp
->regs
+ PCS_MIIADV
);
1159 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1160 * and re-enable PCS.
1162 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1163 val
|= (PCS_MIICTRL_RAN
| PCS_MIICTRL_ANE
);
1164 val
&= ~PCS_MIICTRL_WB
;
1165 writel(val
, gp
->regs
+ PCS_MIICTRL
);
1167 val
= readl(gp
->regs
+ PCS_CFG
);
1168 val
|= PCS_CFG_ENABLE
;
1169 writel(val
, gp
->regs
+ PCS_CFG
);
1171 /* Make sure serialink loopback is off. The meaning
1172 * of this bit is logically inverted based upon whether
1173 * you are in Serialink or SERDES mode.
1175 val
= readl(gp
->regs
+ PCS_SCTRL
);
1176 if (gp
->phy_type
== phy_serialink
)
1177 val
&= ~PCS_SCTRL_LOOP
;
1179 val
|= PCS_SCTRL_LOOP
;
1180 writel(val
, gp
->regs
+ PCS_SCTRL
);
1183 #define STOP_TRIES 32
1185 static void gem_reset(struct gem
*gp
)
1190 /* Make sure we won't get any more interrupts */
1191 writel(0xffffffff, gp
->regs
+ GREG_IMASK
);
1193 /* Reset the chip */
1194 writel(gp
->swrst_base
| GREG_SWRST_TXRST
| GREG_SWRST_RXRST
,
1195 gp
->regs
+ GREG_SWRST
);
1201 val
= readl(gp
->regs
+ GREG_SWRST
);
1204 } while (val
& (GREG_SWRST_TXRST
| GREG_SWRST_RXRST
));
1207 netdev_err(gp
->dev
, "SW reset is ghetto\n");
1209 if (gp
->phy_type
== phy_serialink
|| gp
->phy_type
== phy_serdes
)
1210 gem_pcs_reinit_adv(gp
);
1213 static void gem_start_dma(struct gem
*gp
)
1217 /* We are ready to rock, turn everything on. */
1218 val
= readl(gp
->regs
+ TXDMA_CFG
);
1219 writel(val
| TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1220 val
= readl(gp
->regs
+ RXDMA_CFG
);
1221 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1222 val
= readl(gp
->regs
+ MAC_TXCFG
);
1223 writel(val
| MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1224 val
= readl(gp
->regs
+ MAC_RXCFG
);
1225 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1227 (void) readl(gp
->regs
+ MAC_RXCFG
);
1230 gem_enable_ints(gp
);
1232 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1235 /* DMA won't be actually stopped before about 4ms tho ...
1237 static void gem_stop_dma(struct gem
*gp
)
1241 /* We are done rocking, turn everything off. */
1242 val
= readl(gp
->regs
+ TXDMA_CFG
);
1243 writel(val
& ~TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1244 val
= readl(gp
->regs
+ RXDMA_CFG
);
1245 writel(val
& ~RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1246 val
= readl(gp
->regs
+ MAC_TXCFG
);
1247 writel(val
& ~MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1248 val
= readl(gp
->regs
+ MAC_RXCFG
);
1249 writel(val
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1251 (void) readl(gp
->regs
+ MAC_RXCFG
);
1253 /* Need to wait a bit ... done by the caller */
1257 // XXX dbl check what that function should do when called on PCS PHY
1258 static void gem_begin_auto_negotiation(struct gem
*gp
, struct ethtool_cmd
*ep
)
1260 u32 advertise
, features
;
1265 if (gp
->phy_type
!= phy_mii_mdio0
&&
1266 gp
->phy_type
!= phy_mii_mdio1
)
1269 /* Setup advertise */
1270 if (found_mii_phy(gp
))
1271 features
= gp
->phy_mii
.def
->features
;
1275 advertise
= features
& ADVERTISE_MASK
;
1276 if (gp
->phy_mii
.advertising
!= 0)
1277 advertise
&= gp
->phy_mii
.advertising
;
1279 autoneg
= gp
->want_autoneg
;
1280 speed
= gp
->phy_mii
.speed
;
1281 duplex
= gp
->phy_mii
.duplex
;
1283 /* Setup link parameters */
1286 if (ep
->autoneg
== AUTONEG_ENABLE
) {
1287 advertise
= ep
->advertising
;
1291 speed
= ethtool_cmd_speed(ep
);
1292 duplex
= ep
->duplex
;
1296 /* Sanitize settings based on PHY capabilities */
1297 if ((features
& SUPPORTED_Autoneg
) == 0)
1299 if (speed
== SPEED_1000
&&
1300 !(features
& (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full
)))
1302 if (speed
== SPEED_100
&&
1303 !(features
& (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
)))
1305 if (duplex
== DUPLEX_FULL
&&
1306 !(features
& (SUPPORTED_1000baseT_Full
|
1307 SUPPORTED_100baseT_Full
|
1308 SUPPORTED_10baseT_Full
)))
1309 duplex
= DUPLEX_HALF
;
1313 /* If we are asleep, we don't try to actually setup the PHY, we
1314 * just store the settings
1316 if (!netif_device_present(gp
->dev
)) {
1317 gp
->phy_mii
.autoneg
= gp
->want_autoneg
= autoneg
;
1318 gp
->phy_mii
.speed
= speed
;
1319 gp
->phy_mii
.duplex
= duplex
;
1323 /* Configure PHY & start aneg */
1324 gp
->want_autoneg
= autoneg
;
1326 if (found_mii_phy(gp
))
1327 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, advertise
);
1328 gp
->lstate
= link_aneg
;
1330 if (found_mii_phy(gp
))
1331 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, speed
, duplex
);
1332 gp
->lstate
= link_force_ok
;
1336 gp
->timer_ticks
= 0;
1337 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1340 /* A link-up condition has occurred, initialize and enable the
1343 static int gem_set_link_modes(struct gem
*gp
)
1345 struct netdev_queue
*txq
= netdev_get_tx_queue(gp
->dev
, 0);
1346 int full_duplex
, speed
, pause
;
1353 if (found_mii_phy(gp
)) {
1354 if (gp
->phy_mii
.def
->ops
->read_link(&gp
->phy_mii
))
1356 full_duplex
= (gp
->phy_mii
.duplex
== DUPLEX_FULL
);
1357 speed
= gp
->phy_mii
.speed
;
1358 pause
= gp
->phy_mii
.pause
;
1359 } else if (gp
->phy_type
== phy_serialink
||
1360 gp
->phy_type
== phy_serdes
) {
1361 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1363 if ((pcs_lpa
& PCS_MIIADV_FD
) || gp
->phy_type
== phy_serdes
)
1368 netif_info(gp
, link
, gp
->dev
, "Link is up at %d Mbps, %s-duplex\n",
1369 speed
, (full_duplex
? "full" : "half"));
1372 /* We take the tx queue lock to avoid collisions between
1373 * this code, the tx path and the NAPI-driven error path
1375 __netif_tx_lock(txq
, smp_processor_id());
1377 val
= (MAC_TXCFG_EIPG0
| MAC_TXCFG_NGU
);
1379 val
|= (MAC_TXCFG_ICS
| MAC_TXCFG_ICOLL
);
1381 /* MAC_TXCFG_NBO must be zero. */
1383 writel(val
, gp
->regs
+ MAC_TXCFG
);
1385 val
= (MAC_XIFCFG_OE
| MAC_XIFCFG_LLED
);
1387 (gp
->phy_type
== phy_mii_mdio0
||
1388 gp
->phy_type
== phy_mii_mdio1
)) {
1389 val
|= MAC_XIFCFG_DISE
;
1390 } else if (full_duplex
) {
1391 val
|= MAC_XIFCFG_FLED
;
1394 if (speed
== SPEED_1000
)
1395 val
|= (MAC_XIFCFG_GMII
);
1397 writel(val
, gp
->regs
+ MAC_XIFCFG
);
1399 /* If gigabit and half-duplex, enable carrier extension
1400 * mode. Else, disable it.
1402 if (speed
== SPEED_1000
&& !full_duplex
) {
1403 val
= readl(gp
->regs
+ MAC_TXCFG
);
1404 writel(val
| MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1406 val
= readl(gp
->regs
+ MAC_RXCFG
);
1407 writel(val
| MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1409 val
= readl(gp
->regs
+ MAC_TXCFG
);
1410 writel(val
& ~MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1412 val
= readl(gp
->regs
+ MAC_RXCFG
);
1413 writel(val
& ~MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1416 if (gp
->phy_type
== phy_serialink
||
1417 gp
->phy_type
== phy_serdes
) {
1418 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1420 if (pcs_lpa
& (PCS_MIIADV_SP
| PCS_MIIADV_AP
))
1425 writel(512, gp
->regs
+ MAC_STIME
);
1427 writel(64, gp
->regs
+ MAC_STIME
);
1428 val
= readl(gp
->regs
+ MAC_MCCFG
);
1430 val
|= (MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1432 val
&= ~(MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1433 writel(val
, gp
->regs
+ MAC_MCCFG
);
1437 __netif_tx_unlock(txq
);
1439 if (netif_msg_link(gp
)) {
1441 netdev_info(gp
->dev
,
1442 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1447 netdev_info(gp
->dev
, "Pause is disabled\n");
1454 static int gem_mdio_link_not_up(struct gem
*gp
)
1456 switch (gp
->lstate
) {
1457 case link_force_ret
:
1458 netif_info(gp
, link
, gp
->dev
,
1459 "Autoneg failed again, keeping forced mode\n");
1460 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
,
1461 gp
->last_forced_speed
, DUPLEX_HALF
);
1462 gp
->timer_ticks
= 5;
1463 gp
->lstate
= link_force_ok
;
1466 /* We try forced modes after a failed aneg only on PHYs that don't
1467 * have "magic_aneg" bit set, which means they internally do the
1468 * while forced-mode thingy. On these, we just restart aneg
1470 if (gp
->phy_mii
.def
->magic_aneg
)
1472 netif_info(gp
, link
, gp
->dev
, "switching to forced 100bt\n");
1473 /* Try forced modes. */
1474 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_100
,
1476 gp
->timer_ticks
= 5;
1477 gp
->lstate
= link_force_try
;
1479 case link_force_try
:
1480 /* Downgrade from 100 to 10 Mbps if necessary.
1481 * If already at 10Mbps, warn user about the
1482 * situation every 10 ticks.
1484 if (gp
->phy_mii
.speed
== SPEED_100
) {
1485 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_10
,
1487 gp
->timer_ticks
= 5;
1488 netif_info(gp
, link
, gp
->dev
,
1489 "switching to forced 10bt\n");
1498 static void gem_link_timer(unsigned long data
)
1500 struct gem
*gp
= (struct gem
*) data
;
1501 struct net_device
*dev
= gp
->dev
;
1502 int restart_aneg
= 0;
1504 /* There's no point doing anything if we're going to be reset */
1505 if (gp
->reset_task_pending
)
1508 if (gp
->phy_type
== phy_serialink
||
1509 gp
->phy_type
== phy_serdes
) {
1510 u32 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1512 if (!(val
& PCS_MIISTAT_LS
))
1513 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1515 if ((val
& PCS_MIISTAT_LS
) != 0) {
1516 if (gp
->lstate
== link_up
)
1519 gp
->lstate
= link_up
;
1520 netif_carrier_on(dev
);
1521 (void)gem_set_link_modes(gp
);
1525 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->poll_link(&gp
->phy_mii
)) {
1526 /* Ok, here we got a link. If we had it due to a forced
1527 * fallback, and we were configured for autoneg, we do
1528 * retry a short autoneg pass. If you know your hub is
1529 * broken, use ethtool ;)
1531 if (gp
->lstate
== link_force_try
&& gp
->want_autoneg
) {
1532 gp
->lstate
= link_force_ret
;
1533 gp
->last_forced_speed
= gp
->phy_mii
.speed
;
1534 gp
->timer_ticks
= 5;
1535 if (netif_msg_link(gp
))
1537 "Got link after fallback, retrying autoneg once...\n");
1538 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, gp
->phy_mii
.advertising
);
1539 } else if (gp
->lstate
!= link_up
) {
1540 gp
->lstate
= link_up
;
1541 netif_carrier_on(dev
);
1542 if (gem_set_link_modes(gp
))
1546 /* If the link was previously up, we restart the
1549 if (gp
->lstate
== link_up
) {
1550 gp
->lstate
= link_down
;
1551 netif_info(gp
, link
, dev
, "Link down\n");
1552 netif_carrier_off(dev
);
1553 gem_schedule_reset(gp
);
1554 /* The reset task will restart the timer */
1556 } else if (++gp
->timer_ticks
> 10) {
1557 if (found_mii_phy(gp
))
1558 restart_aneg
= gem_mdio_link_not_up(gp
);
1564 gem_begin_auto_negotiation(gp
, NULL
);
1568 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1571 static void gem_clean_rings(struct gem
*gp
)
1573 struct gem_init_block
*gb
= gp
->init_block
;
1574 struct sk_buff
*skb
;
1576 dma_addr_t dma_addr
;
1578 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1579 struct gem_rxd
*rxd
;
1582 if (gp
->rx_skbs
[i
] != NULL
) {
1583 skb
= gp
->rx_skbs
[i
];
1584 dma_addr
= le64_to_cpu(rxd
->buffer
);
1585 pci_unmap_page(gp
->pdev
, dma_addr
,
1586 RX_BUF_ALLOC_SIZE(gp
),
1587 PCI_DMA_FROMDEVICE
);
1588 dev_kfree_skb_any(skb
);
1589 gp
->rx_skbs
[i
] = NULL
;
1591 rxd
->status_word
= 0;
1596 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1597 if (gp
->tx_skbs
[i
] != NULL
) {
1598 struct gem_txd
*txd
;
1601 skb
= gp
->tx_skbs
[i
];
1602 gp
->tx_skbs
[i
] = NULL
;
1604 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
1605 int ent
= i
& (TX_RING_SIZE
- 1);
1607 txd
= &gb
->txd
[ent
];
1608 dma_addr
= le64_to_cpu(txd
->buffer
);
1609 pci_unmap_page(gp
->pdev
, dma_addr
,
1610 le64_to_cpu(txd
->control_word
) &
1611 TXDCTRL_BUFSZ
, PCI_DMA_TODEVICE
);
1613 if (frag
!= skb_shinfo(skb
)->nr_frags
)
1616 dev_kfree_skb_any(skb
);
1621 static void gem_init_rings(struct gem
*gp
)
1623 struct gem_init_block
*gb
= gp
->init_block
;
1624 struct net_device
*dev
= gp
->dev
;
1626 dma_addr_t dma_addr
;
1628 gp
->rx_new
= gp
->rx_old
= gp
->tx_new
= gp
->tx_old
= 0;
1630 gem_clean_rings(gp
);
1632 gp
->rx_buf_sz
= max(dev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
,
1633 (unsigned)VLAN_ETH_FRAME_LEN
);
1635 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1636 struct sk_buff
*skb
;
1637 struct gem_rxd
*rxd
= &gb
->rxd
[i
];
1639 skb
= gem_alloc_skb(dev
, RX_BUF_ALLOC_SIZE(gp
), GFP_KERNEL
);
1642 rxd
->status_word
= 0;
1646 gp
->rx_skbs
[i
] = skb
;
1647 skb_put(skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
1648 dma_addr
= pci_map_page(gp
->pdev
,
1649 virt_to_page(skb
->data
),
1650 offset_in_page(skb
->data
),
1651 RX_BUF_ALLOC_SIZE(gp
),
1652 PCI_DMA_FROMDEVICE
);
1653 rxd
->buffer
= cpu_to_le64(dma_addr
);
1655 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
1656 skb_reserve(skb
, RX_OFFSET
);
1659 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1660 struct gem_txd
*txd
= &gb
->txd
[i
];
1662 txd
->control_word
= 0;
1669 /* Init PHY interface and start link poll state machine */
1670 static void gem_init_phy(struct gem
*gp
)
1674 /* Revert MIF CFG setting done on stop_phy */
1675 mifcfg
= readl(gp
->regs
+ MIF_CFG
);
1676 mifcfg
&= ~MIF_CFG_BBMODE
;
1677 writel(mifcfg
, gp
->regs
+ MIF_CFG
);
1679 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
1682 /* Those delay sucks, the HW seem to love them though, I'll
1683 * serisouly consider breaking some locks here to be able
1684 * to schedule instead
1686 for (i
= 0; i
< 3; i
++) {
1687 #ifdef CONFIG_PPC_PMAC
1688 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET
, gp
->of_node
, 0, 0);
1691 /* Some PHYs used by apple have problem getting back to us,
1692 * we do an additional reset here
1694 phy_write(gp
, MII_BMCR
, BMCR_RESET
);
1696 if (phy_read(gp
, MII_BMCR
) != 0xffff)
1699 netdev_warn(gp
->dev
, "GMAC PHY not responding !\n");
1703 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1704 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
1707 /* Init datapath mode register. */
1708 if (gp
->phy_type
== phy_mii_mdio0
||
1709 gp
->phy_type
== phy_mii_mdio1
) {
1710 val
= PCS_DMODE_MGM
;
1711 } else if (gp
->phy_type
== phy_serialink
) {
1712 val
= PCS_DMODE_SM
| PCS_DMODE_GMOE
;
1714 val
= PCS_DMODE_ESM
;
1717 writel(val
, gp
->regs
+ PCS_DMODE
);
1720 if (gp
->phy_type
== phy_mii_mdio0
||
1721 gp
->phy_type
== phy_mii_mdio1
) {
1722 /* Reset and detect MII PHY */
1723 mii_phy_probe(&gp
->phy_mii
, gp
->mii_phy_addr
);
1726 if (gp
->phy_mii
.def
&& gp
->phy_mii
.def
->ops
->init
)
1727 gp
->phy_mii
.def
->ops
->init(&gp
->phy_mii
);
1730 gem_pcs_reinit_adv(gp
);
1733 /* Default aneg parameters */
1734 gp
->timer_ticks
= 0;
1735 gp
->lstate
= link_down
;
1736 netif_carrier_off(gp
->dev
);
1738 /* Print things out */
1739 if (gp
->phy_type
== phy_mii_mdio0
||
1740 gp
->phy_type
== phy_mii_mdio1
)
1741 netdev_info(gp
->dev
, "Found %s PHY\n",
1742 gp
->phy_mii
.def
? gp
->phy_mii
.def
->name
: "no");
1744 gem_begin_auto_negotiation(gp
, NULL
);
1747 static void gem_init_dma(struct gem
*gp
)
1749 u64 desc_dma
= (u64
) gp
->gblock_dvma
;
1752 val
= (TXDMA_CFG_BASE
| (0x7ff << 10) | TXDMA_CFG_PMODE
);
1753 writel(val
, gp
->regs
+ TXDMA_CFG
);
1755 writel(desc_dma
>> 32, gp
->regs
+ TXDMA_DBHI
);
1756 writel(desc_dma
& 0xffffffff, gp
->regs
+ TXDMA_DBLOW
);
1757 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
1759 writel(0, gp
->regs
+ TXDMA_KICK
);
1761 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
1762 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
1763 writel(val
, gp
->regs
+ RXDMA_CFG
);
1765 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
1766 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
1768 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1770 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
1771 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
1772 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
1774 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
1775 writel(((5 & RXDMA_BLANK_IPKTS
) |
1776 ((8 << 12) & RXDMA_BLANK_ITIME
)),
1777 gp
->regs
+ RXDMA_BLANK
);
1779 writel(((5 & RXDMA_BLANK_IPKTS
) |
1780 ((4 << 12) & RXDMA_BLANK_ITIME
)),
1781 gp
->regs
+ RXDMA_BLANK
);
1784 static u32
gem_setup_multicast(struct gem
*gp
)
1789 if ((gp
->dev
->flags
& IFF_ALLMULTI
) ||
1790 (netdev_mc_count(gp
->dev
) > 256)) {
1791 for (i
=0; i
<16; i
++)
1792 writel(0xffff, gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1793 rxcfg
|= MAC_RXCFG_HFE
;
1794 } else if (gp
->dev
->flags
& IFF_PROMISC
) {
1795 rxcfg
|= MAC_RXCFG_PROM
;
1799 struct netdev_hw_addr
*ha
;
1802 memset(hash_table
, 0, sizeof(hash_table
));
1803 netdev_for_each_mc_addr(ha
, gp
->dev
) {
1804 crc
= ether_crc_le(6, ha
->addr
);
1806 hash_table
[crc
>> 4] |= 1 << (15 - (crc
& 0xf));
1808 for (i
=0; i
<16; i
++)
1809 writel(hash_table
[i
], gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1810 rxcfg
|= MAC_RXCFG_HFE
;
1816 static void gem_init_mac(struct gem
*gp
)
1818 unsigned char *e
= &gp
->dev
->dev_addr
[0];
1820 writel(0x1bf0, gp
->regs
+ MAC_SNDPAUSE
);
1822 writel(0x00, gp
->regs
+ MAC_IPG0
);
1823 writel(0x08, gp
->regs
+ MAC_IPG1
);
1824 writel(0x04, gp
->regs
+ MAC_IPG2
);
1825 writel(0x40, gp
->regs
+ MAC_STIME
);
1826 writel(0x40, gp
->regs
+ MAC_MINFSZ
);
1828 /* Ethernet payload + header + FCS + optional VLAN tag. */
1829 writel(0x20000000 | (gp
->rx_buf_sz
+ 4), gp
->regs
+ MAC_MAXFSZ
);
1831 writel(0x07, gp
->regs
+ MAC_PASIZE
);
1832 writel(0x04, gp
->regs
+ MAC_JAMSIZE
);
1833 writel(0x10, gp
->regs
+ MAC_ATTLIM
);
1834 writel(0x8808, gp
->regs
+ MAC_MCTYPE
);
1836 writel((e
[5] | (e
[4] << 8)) & 0x3ff, gp
->regs
+ MAC_RANDSEED
);
1838 writel((e
[4] << 8) | e
[5], gp
->regs
+ MAC_ADDR0
);
1839 writel((e
[2] << 8) | e
[3], gp
->regs
+ MAC_ADDR1
);
1840 writel((e
[0] << 8) | e
[1], gp
->regs
+ MAC_ADDR2
);
1842 writel(0, gp
->regs
+ MAC_ADDR3
);
1843 writel(0, gp
->regs
+ MAC_ADDR4
);
1844 writel(0, gp
->regs
+ MAC_ADDR5
);
1846 writel(0x0001, gp
->regs
+ MAC_ADDR6
);
1847 writel(0xc200, gp
->regs
+ MAC_ADDR7
);
1848 writel(0x0180, gp
->regs
+ MAC_ADDR8
);
1850 writel(0, gp
->regs
+ MAC_AFILT0
);
1851 writel(0, gp
->regs
+ MAC_AFILT1
);
1852 writel(0, gp
->regs
+ MAC_AFILT2
);
1853 writel(0, gp
->regs
+ MAC_AF21MSK
);
1854 writel(0, gp
->regs
+ MAC_AF0MSK
);
1856 gp
->mac_rx_cfg
= gem_setup_multicast(gp
);
1858 gp
->mac_rx_cfg
|= MAC_RXCFG_SFCS
;
1860 writel(0, gp
->regs
+ MAC_NCOLL
);
1861 writel(0, gp
->regs
+ MAC_FASUCC
);
1862 writel(0, gp
->regs
+ MAC_ECOLL
);
1863 writel(0, gp
->regs
+ MAC_LCOLL
);
1864 writel(0, gp
->regs
+ MAC_DTIMER
);
1865 writel(0, gp
->regs
+ MAC_PATMPS
);
1866 writel(0, gp
->regs
+ MAC_RFCTR
);
1867 writel(0, gp
->regs
+ MAC_LERR
);
1868 writel(0, gp
->regs
+ MAC_AERR
);
1869 writel(0, gp
->regs
+ MAC_FCSERR
);
1870 writel(0, gp
->regs
+ MAC_RXCVERR
);
1872 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1873 * them once a link is established.
1875 writel(0, gp
->regs
+ MAC_TXCFG
);
1876 writel(gp
->mac_rx_cfg
, gp
->regs
+ MAC_RXCFG
);
1877 writel(0, gp
->regs
+ MAC_MCCFG
);
1878 writel(0, gp
->regs
+ MAC_XIFCFG
);
1880 /* Setup MAC interrupts. We want to get all of the interesting
1881 * counter expiration events, but we do not want to hear about
1882 * normal rx/tx as the DMA engine tells us that.
1884 writel(MAC_TXSTAT_XMIT
, gp
->regs
+ MAC_TXMASK
);
1885 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
1887 /* Don't enable even the PAUSE interrupts for now, we
1888 * make no use of those events other than to record them.
1890 writel(0xffffffff, gp
->regs
+ MAC_MCMASK
);
1892 /* Don't enable GEM's WOL in normal operations
1895 writel(0, gp
->regs
+ WOL_WAKECSR
);
1898 static void gem_init_pause_thresholds(struct gem
*gp
)
1902 /* Calculate pause thresholds. Setting the OFF threshold to the
1903 * full RX fifo size effectively disables PAUSE generation which
1904 * is what we do for 10/100 only GEMs which have FIFOs too small
1905 * to make real gains from PAUSE.
1907 if (gp
->rx_fifo_sz
<= (2 * 1024)) {
1908 gp
->rx_pause_off
= gp
->rx_pause_on
= gp
->rx_fifo_sz
;
1910 int max_frame
= (gp
->rx_buf_sz
+ 4 + 64) & ~63;
1911 int off
= (gp
->rx_fifo_sz
- (max_frame
* 2));
1912 int on
= off
- max_frame
;
1914 gp
->rx_pause_off
= off
;
1915 gp
->rx_pause_on
= on
;
1919 /* Configure the chip "burst" DMA mode & enable some
1920 * HW bug fixes on Apple version
1923 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
1924 cfg
|= GREG_CFG_RONPAULBIT
| GREG_CFG_ENBUG2FIX
;
1925 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1926 cfg
|= GREG_CFG_IBURST
;
1928 cfg
|= ((31 << 1) & GREG_CFG_TXDMALIM
);
1929 cfg
|= ((31 << 6) & GREG_CFG_RXDMALIM
);
1930 writel(cfg
, gp
->regs
+ GREG_CFG
);
1932 /* If Infinite Burst didn't stick, then use different
1933 * thresholds (and Apple bug fixes don't exist)
1935 if (!(readl(gp
->regs
+ GREG_CFG
) & GREG_CFG_IBURST
)) {
1936 cfg
= ((2 << 1) & GREG_CFG_TXDMALIM
);
1937 cfg
|= ((8 << 6) & GREG_CFG_RXDMALIM
);
1938 writel(cfg
, gp
->regs
+ GREG_CFG
);
1942 static int gem_check_invariants(struct gem
*gp
)
1944 struct pci_dev
*pdev
= gp
->pdev
;
1947 /* On Apple's sungem, we can't rely on registers as the chip
1948 * was been powered down by the firmware. The PHY is looked
1951 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
1952 gp
->phy_type
= phy_mii_mdio0
;
1953 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
1954 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
1957 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
1958 mif_cfg
&= ~(MIF_CFG_PSELECT
|MIF_CFG_POLL
|MIF_CFG_BBMODE
|MIF_CFG_MDI1
);
1959 mif_cfg
|= MIF_CFG_MDI0
;
1960 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
1961 writel(PCS_DMODE_MGM
, gp
->regs
+ PCS_DMODE
);
1962 writel(MAC_XIFCFG_OE
, gp
->regs
+ MAC_XIFCFG
);
1964 /* We hard-code the PHY address so we can properly bring it out of
1965 * reset later on, we can't really probe it at this point, though
1966 * that isn't an issue.
1968 if (gp
->pdev
->device
== PCI_DEVICE_ID_APPLE_K2_GMAC
)
1969 gp
->mii_phy_addr
= 1;
1971 gp
->mii_phy_addr
= 0;
1976 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
1978 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1979 pdev
->device
== PCI_DEVICE_ID_SUN_RIO_GEM
) {
1980 /* One of the MII PHYs _must_ be present
1981 * as this chip has no gigabit PHY.
1983 if ((mif_cfg
& (MIF_CFG_MDI0
| MIF_CFG_MDI1
)) == 0) {
1984 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1990 /* Determine initial PHY interface type guess. MDIO1 is the
1991 * external PHY and thus takes precedence over MDIO0.
1994 if (mif_cfg
& MIF_CFG_MDI1
) {
1995 gp
->phy_type
= phy_mii_mdio1
;
1996 mif_cfg
|= MIF_CFG_PSELECT
;
1997 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
1998 } else if (mif_cfg
& MIF_CFG_MDI0
) {
1999 gp
->phy_type
= phy_mii_mdio0
;
2000 mif_cfg
&= ~MIF_CFG_PSELECT
;
2001 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2006 p
= of_get_property(gp
->of_node
, "shared-pins", NULL
);
2007 if (p
&& !strcmp(p
, "serdes"))
2008 gp
->phy_type
= phy_serdes
;
2011 gp
->phy_type
= phy_serialink
;
2013 if (gp
->phy_type
== phy_mii_mdio1
||
2014 gp
->phy_type
== phy_mii_mdio0
) {
2017 for (i
= 0; i
< 32; i
++) {
2018 gp
->mii_phy_addr
= i
;
2019 if (phy_read(gp
, MII_BMCR
) != 0xffff)
2023 if (pdev
->device
!= PCI_DEVICE_ID_SUN_GEM
) {
2024 pr_err("RIO MII phy will not respond\n");
2027 gp
->phy_type
= phy_serdes
;
2031 /* Fetch the FIFO configurations now too. */
2032 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
2033 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
2035 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
) {
2036 if (pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
2037 if (gp
->tx_fifo_sz
!= (9 * 1024) ||
2038 gp
->rx_fifo_sz
!= (20 * 1024)) {
2039 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2040 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2045 if (gp
->tx_fifo_sz
!= (2 * 1024) ||
2046 gp
->rx_fifo_sz
!= (2 * 1024)) {
2047 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2048 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2051 gp
->swrst_base
= (64 / 4) << GREG_SWRST_CACHE_SHIFT
;
2058 static void gem_reinit_chip(struct gem
*gp
)
2060 /* Reset the chip */
2063 /* Make sure ints are disabled */
2064 gem_disable_ints(gp
);
2066 /* Allocate & setup ring buffers */
2069 /* Configure pause thresholds */
2070 gem_init_pause_thresholds(gp
);
2072 /* Init DMA & MAC engines */
2078 static void gem_stop_phy(struct gem
*gp
, int wol
)
2082 /* Let the chip settle down a bit, it seems that helps
2083 * for sleep mode on some models
2087 /* Make sure we aren't polling PHY status change. We
2088 * don't currently use that feature though
2090 mifcfg
= readl(gp
->regs
+ MIF_CFG
);
2091 mifcfg
&= ~MIF_CFG_POLL
;
2092 writel(mifcfg
, gp
->regs
+ MIF_CFG
);
2094 if (wol
&& gp
->has_wol
) {
2095 unsigned char *e
= &gp
->dev
->dev_addr
[0];
2098 /* Setup wake-on-lan for MAGIC packet */
2099 writel(MAC_RXCFG_HFE
| MAC_RXCFG_SFCS
| MAC_RXCFG_ENAB
,
2100 gp
->regs
+ MAC_RXCFG
);
2101 writel((e
[4] << 8) | e
[5], gp
->regs
+ WOL_MATCH0
);
2102 writel((e
[2] << 8) | e
[3], gp
->regs
+ WOL_MATCH1
);
2103 writel((e
[0] << 8) | e
[1], gp
->regs
+ WOL_MATCH2
);
2105 writel(WOL_MCOUNT_N
| WOL_MCOUNT_M
, gp
->regs
+ WOL_MCOUNT
);
2106 csr
= WOL_WAKECSR_ENABLE
;
2107 if ((readl(gp
->regs
+ MAC_XIFCFG
) & MAC_XIFCFG_GMII
) == 0)
2108 csr
|= WOL_WAKECSR_MII
;
2109 writel(csr
, gp
->regs
+ WOL_WAKECSR
);
2111 writel(0, gp
->regs
+ MAC_RXCFG
);
2112 (void)readl(gp
->regs
+ MAC_RXCFG
);
2113 /* Machine sleep will die in strange ways if we
2114 * dont wait a bit here, looks like the chip takes
2115 * some time to really shut down
2120 writel(0, gp
->regs
+ MAC_TXCFG
);
2121 writel(0, gp
->regs
+ MAC_XIFCFG
);
2122 writel(0, gp
->regs
+ TXDMA_CFG
);
2123 writel(0, gp
->regs
+ RXDMA_CFG
);
2127 writel(MAC_TXRST_CMD
, gp
->regs
+ MAC_TXRST
);
2128 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
2130 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->suspend
)
2131 gp
->phy_mii
.def
->ops
->suspend(&gp
->phy_mii
);
2133 /* According to Apple, we must set the MDIO pins to this begnign
2134 * state or we may 1) eat more current, 2) damage some PHYs
2136 writel(mifcfg
| MIF_CFG_BBMODE
, gp
->regs
+ MIF_CFG
);
2137 writel(0, gp
->regs
+ MIF_BBCLK
);
2138 writel(0, gp
->regs
+ MIF_BBDATA
);
2139 writel(0, gp
->regs
+ MIF_BBOENAB
);
2140 writel(MAC_XIFCFG_GMII
| MAC_XIFCFG_LBCK
, gp
->regs
+ MAC_XIFCFG
);
2141 (void) readl(gp
->regs
+ MAC_XIFCFG
);
2145 static int gem_do_start(struct net_device
*dev
)
2147 struct gem
*gp
= netdev_priv(dev
);
2150 /* Enable the cell */
2153 /* Make sure PCI access and bus master are enabled */
2154 rc
= pci_enable_device(gp
->pdev
);
2156 netdev_err(dev
, "Failed to enable chip on PCI bus !\n");
2158 /* Put cell and forget it for now, it will be considered as
2159 * still asleep, a new sleep cycle may bring it back
2164 pci_set_master(gp
->pdev
);
2166 /* Init & setup chip hardware */
2167 gem_reinit_chip(gp
);
2169 /* An interrupt might come in handy */
2170 rc
= request_irq(gp
->pdev
->irq
, gem_interrupt
,
2171 IRQF_SHARED
, dev
->name
, (void *)dev
);
2173 netdev_err(dev
, "failed to request irq !\n");
2176 gem_clean_rings(gp
);
2181 /* Mark us as attached again if we come from resume(), this has
2182 * no effect if we weren't detatched and needs to be done now.
2184 netif_device_attach(dev
);
2186 /* Restart NAPI & queues */
2187 gem_netif_start(gp
);
2189 /* Detect & init PHY, start autoneg etc... this will
2190 * eventually result in starting DMA operations when
2198 static void gem_do_stop(struct net_device
*dev
, int wol
)
2200 struct gem
*gp
= netdev_priv(dev
);
2202 /* Stop NAPI and stop tx queue */
2205 /* Make sure ints are disabled. We don't care about
2206 * synchronizing as NAPI is disabled, thus a stray
2207 * interrupt will do nothing bad (our irq handler
2208 * just schedules NAPI)
2210 gem_disable_ints(gp
);
2212 /* Stop the link timer */
2213 del_timer_sync(&gp
->link_timer
);
2215 /* We cannot cancel the reset task while holding the
2216 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2217 * if we did. This is not an issue however as the reset
2218 * task is synchronized vs. us (rtnl_lock) and will do
2219 * nothing if the device is down or suspended. We do
2220 * still clear reset_task_pending to avoid a spurrious
2221 * reset later on in case we do resume before it gets
2224 gp
->reset_task_pending
= 0;
2226 /* If we are going to sleep with WOL */
2233 /* Get rid of rings */
2234 gem_clean_rings(gp
);
2236 /* No irq needed anymore */
2237 free_irq(gp
->pdev
->irq
, (void *) dev
);
2239 /* Shut the PHY down eventually and setup WOL */
2240 gem_stop_phy(gp
, wol
);
2242 /* Make sure bus master is disabled */
2243 pci_disable_device(gp
->pdev
);
2245 /* Cell not needed neither if no WOL */
2250 static void gem_reset_task(struct work_struct
*work
)
2252 struct gem
*gp
= container_of(work
, struct gem
, reset_task
);
2254 /* Lock out the network stack (essentially shield ourselves
2255 * against a racing open, close, control call, or suspend
2259 /* Skip the reset task if suspended or closed, or if it's
2260 * been cancelled by gem_do_stop (see comment there)
2262 if (!netif_device_present(gp
->dev
) ||
2263 !netif_running(gp
->dev
) ||
2264 !gp
->reset_task_pending
) {
2269 /* Stop the link timer */
2270 del_timer_sync(&gp
->link_timer
);
2272 /* Stop NAPI and tx */
2275 /* Reset the chip & rings */
2276 gem_reinit_chip(gp
);
2277 if (gp
->lstate
== link_up
)
2278 gem_set_link_modes(gp
);
2280 /* Restart NAPI and Tx */
2281 gem_netif_start(gp
);
2284 gp
->reset_task_pending
= 0;
2286 /* If the link is not up, restart autoneg, else restart the
2289 if (gp
->lstate
!= link_up
)
2290 gem_begin_auto_negotiation(gp
, NULL
);
2292 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
2297 static int gem_open(struct net_device
*dev
)
2299 /* We allow open while suspended, we just do nothing,
2300 * the chip will be initialized in resume()
2302 if (netif_device_present(dev
))
2303 return gem_do_start(dev
);
2307 static int gem_close(struct net_device
*dev
)
2309 if (netif_device_present(dev
))
2310 gem_do_stop(dev
, 0);
2316 static int gem_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2318 struct net_device
*dev
= pci_get_drvdata(pdev
);
2319 struct gem
*gp
= netdev_priv(dev
);
2321 /* Lock the network stack first to avoid racing with open/close,
2322 * reset task and setting calls
2326 /* Not running, mark ourselves non-present, no need for
2329 if (!netif_running(dev
)) {
2330 netif_device_detach(dev
);
2334 netdev_info(dev
, "suspending, WakeOnLan %s\n",
2335 (gp
->wake_on_lan
&& netif_running(dev
)) ?
2336 "enabled" : "disabled");
2338 /* Tell the network stack we're gone. gem_do_stop() below will
2339 * synchronize with TX, stop NAPI etc...
2341 netif_device_detach(dev
);
2343 /* Switch off chip, remember WOL setting */
2344 gp
->asleep_wol
= gp
->wake_on_lan
;
2345 gem_do_stop(dev
, gp
->asleep_wol
);
2347 /* Unlock the network stack */
2353 static int gem_resume(struct pci_dev
*pdev
)
2355 struct net_device
*dev
= pci_get_drvdata(pdev
);
2356 struct gem
*gp
= netdev_priv(dev
);
2358 /* See locking comment in gem_suspend */
2361 /* Not running, mark ourselves present, no need for
2364 if (!netif_running(dev
)) {
2365 netif_device_attach(dev
);
2370 /* Restart chip. If that fails there isn't much we can do, we
2371 * leave things stopped.
2375 /* If we had WOL enabled, the cell clock was never turned off during
2376 * sleep, so we end up beeing unbalanced. Fix that here
2381 /* Unlock the network stack */
2386 #endif /* CONFIG_PM */
2388 static struct net_device_stats
*gem_get_stats(struct net_device
*dev
)
2390 struct gem
*gp
= netdev_priv(dev
);
2392 /* I have seen this being called while the PM was in progress,
2393 * so we shield against this. Let's also not poke at registers
2394 * while the reset task is going on.
2396 * TODO: Move stats collection elsewhere (link timer ?) and
2397 * make this a nop to avoid all those synchro issues
2399 if (!netif_device_present(dev
) || !netif_running(dev
))
2402 /* Better safe than sorry... */
2403 if (WARN_ON(!gp
->cell_enabled
))
2406 dev
->stats
.rx_crc_errors
+= readl(gp
->regs
+ MAC_FCSERR
);
2407 writel(0, gp
->regs
+ MAC_FCSERR
);
2409 dev
->stats
.rx_frame_errors
+= readl(gp
->regs
+ MAC_AERR
);
2410 writel(0, gp
->regs
+ MAC_AERR
);
2412 dev
->stats
.rx_length_errors
+= readl(gp
->regs
+ MAC_LERR
);
2413 writel(0, gp
->regs
+ MAC_LERR
);
2415 dev
->stats
.tx_aborted_errors
+= readl(gp
->regs
+ MAC_ECOLL
);
2416 dev
->stats
.collisions
+=
2417 (readl(gp
->regs
+ MAC_ECOLL
) + readl(gp
->regs
+ MAC_LCOLL
));
2418 writel(0, gp
->regs
+ MAC_ECOLL
);
2419 writel(0, gp
->regs
+ MAC_LCOLL
);
2424 static int gem_set_mac_address(struct net_device
*dev
, void *addr
)
2426 struct sockaddr
*macaddr
= (struct sockaddr
*) addr
;
2427 struct gem
*gp
= netdev_priv(dev
);
2428 unsigned char *e
= &dev
->dev_addr
[0];
2430 if (!is_valid_ether_addr(macaddr
->sa_data
))
2431 return -EADDRNOTAVAIL
;
2433 memcpy(dev
->dev_addr
, macaddr
->sa_data
, dev
->addr_len
);
2435 /* We'll just catch it later when the device is up'd or resumed */
2436 if (!netif_running(dev
) || !netif_device_present(dev
))
2439 /* Better safe than sorry... */
2440 if (WARN_ON(!gp
->cell_enabled
))
2443 writel((e
[4] << 8) | e
[5], gp
->regs
+ MAC_ADDR0
);
2444 writel((e
[2] << 8) | e
[3], gp
->regs
+ MAC_ADDR1
);
2445 writel((e
[0] << 8) | e
[1], gp
->regs
+ MAC_ADDR2
);
2450 static void gem_set_multicast(struct net_device
*dev
)
2452 struct gem
*gp
= netdev_priv(dev
);
2453 u32 rxcfg
, rxcfg_new
;
2456 if (!netif_running(dev
) || !netif_device_present(dev
))
2459 /* Better safe than sorry... */
2460 if (gp
->reset_task_pending
|| WARN_ON(!gp
->cell_enabled
))
2463 rxcfg
= readl(gp
->regs
+ MAC_RXCFG
);
2464 rxcfg_new
= gem_setup_multicast(gp
);
2466 rxcfg_new
|= MAC_RXCFG_SFCS
;
2468 gp
->mac_rx_cfg
= rxcfg_new
;
2470 writel(rxcfg
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
2471 while (readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
) {
2477 rxcfg
&= ~(MAC_RXCFG_PROM
| MAC_RXCFG_HFE
);
2480 writel(rxcfg
, gp
->regs
+ MAC_RXCFG
);
2483 /* Jumbo-grams don't seem to work :-( */
2484 #define GEM_MIN_MTU 68
2486 #define GEM_MAX_MTU 1500
2488 #define GEM_MAX_MTU 9000
2491 static int gem_change_mtu(struct net_device
*dev
, int new_mtu
)
2493 struct gem
*gp
= netdev_priv(dev
);
2495 if (new_mtu
< GEM_MIN_MTU
|| new_mtu
> GEM_MAX_MTU
)
2500 /* We'll just catch it later when the device is up'd or resumed */
2501 if (!netif_running(dev
) || !netif_device_present(dev
))
2504 /* Better safe than sorry... */
2505 if (WARN_ON(!gp
->cell_enabled
))
2509 gem_reinit_chip(gp
);
2510 if (gp
->lstate
== link_up
)
2511 gem_set_link_modes(gp
);
2512 gem_netif_start(gp
);
2517 static void gem_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
2519 struct gem
*gp
= netdev_priv(dev
);
2521 strcpy(info
->driver
, DRV_NAME
);
2522 strcpy(info
->version
, DRV_VERSION
);
2523 strcpy(info
->bus_info
, pci_name(gp
->pdev
));
2526 static int gem_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2528 struct gem
*gp
= netdev_priv(dev
);
2530 if (gp
->phy_type
== phy_mii_mdio0
||
2531 gp
->phy_type
== phy_mii_mdio1
) {
2532 if (gp
->phy_mii
.def
)
2533 cmd
->supported
= gp
->phy_mii
.def
->features
;
2535 cmd
->supported
= (SUPPORTED_10baseT_Half
|
2536 SUPPORTED_10baseT_Full
);
2538 /* XXX hardcoded stuff for now */
2539 cmd
->port
= PORT_MII
;
2540 cmd
->transceiver
= XCVR_EXTERNAL
;
2541 cmd
->phy_address
= 0; /* XXX fixed PHYAD */
2543 /* Return current PHY settings */
2544 cmd
->autoneg
= gp
->want_autoneg
;
2545 ethtool_cmd_speed_set(cmd
, gp
->phy_mii
.speed
);
2546 cmd
->duplex
= gp
->phy_mii
.duplex
;
2547 cmd
->advertising
= gp
->phy_mii
.advertising
;
2549 /* If we started with a forced mode, we don't have a default
2550 * advertise set, we need to return something sensible so
2551 * userland can re-enable autoneg properly.
2553 if (cmd
->advertising
== 0)
2554 cmd
->advertising
= cmd
->supported
;
2555 } else { // XXX PCS ?
2557 (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
2558 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
2560 cmd
->advertising
= cmd
->supported
;
2561 ethtool_cmd_speed_set(cmd
, 0);
2562 cmd
->duplex
= cmd
->port
= cmd
->phy_address
=
2563 cmd
->transceiver
= cmd
->autoneg
= 0;
2565 /* serdes means usually a Fibre connector, with most fixed */
2566 if (gp
->phy_type
== phy_serdes
) {
2567 cmd
->port
= PORT_FIBRE
;
2568 cmd
->supported
= (SUPPORTED_1000baseT_Half
|
2569 SUPPORTED_1000baseT_Full
|
2570 SUPPORTED_FIBRE
| SUPPORTED_Autoneg
|
2571 SUPPORTED_Pause
| SUPPORTED_Asym_Pause
);
2572 cmd
->advertising
= cmd
->supported
;
2573 cmd
->transceiver
= XCVR_INTERNAL
;
2574 if (gp
->lstate
== link_up
)
2575 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
2576 cmd
->duplex
= DUPLEX_FULL
;
2580 cmd
->maxtxpkt
= cmd
->maxrxpkt
= 0;
2585 static int gem_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2587 struct gem
*gp
= netdev_priv(dev
);
2588 u32 speed
= ethtool_cmd_speed(cmd
);
2590 /* Verify the settings we care about. */
2591 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
2592 cmd
->autoneg
!= AUTONEG_DISABLE
)
2595 if (cmd
->autoneg
== AUTONEG_ENABLE
&&
2596 cmd
->advertising
== 0)
2599 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
2600 ((speed
!= SPEED_1000
&&
2601 speed
!= SPEED_100
&&
2602 speed
!= SPEED_10
) ||
2603 (cmd
->duplex
!= DUPLEX_HALF
&&
2604 cmd
->duplex
!= DUPLEX_FULL
)))
2607 /* Apply settings and restart link process. */
2608 if (netif_device_present(gp
->dev
)) {
2609 del_timer_sync(&gp
->link_timer
);
2610 gem_begin_auto_negotiation(gp
, cmd
);
2616 static int gem_nway_reset(struct net_device
*dev
)
2618 struct gem
*gp
= netdev_priv(dev
);
2620 if (!gp
->want_autoneg
)
2623 /* Restart link process */
2624 if (netif_device_present(gp
->dev
)) {
2625 del_timer_sync(&gp
->link_timer
);
2626 gem_begin_auto_negotiation(gp
, NULL
);
2632 static u32
gem_get_msglevel(struct net_device
*dev
)
2634 struct gem
*gp
= netdev_priv(dev
);
2635 return gp
->msg_enable
;
2638 static void gem_set_msglevel(struct net_device
*dev
, u32 value
)
2640 struct gem
*gp
= netdev_priv(dev
);
2641 gp
->msg_enable
= value
;
2645 /* Add more when I understand how to program the chip */
2646 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2648 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2650 static void gem_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2652 struct gem
*gp
= netdev_priv(dev
);
2654 /* Add more when I understand how to program the chip */
2656 wol
->supported
= WOL_SUPPORTED_MASK
;
2657 wol
->wolopts
= gp
->wake_on_lan
;
2664 static int gem_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2666 struct gem
*gp
= netdev_priv(dev
);
2670 gp
->wake_on_lan
= wol
->wolopts
& WOL_SUPPORTED_MASK
;
2674 static const struct ethtool_ops gem_ethtool_ops
= {
2675 .get_drvinfo
= gem_get_drvinfo
,
2676 .get_link
= ethtool_op_get_link
,
2677 .get_settings
= gem_get_settings
,
2678 .set_settings
= gem_set_settings
,
2679 .nway_reset
= gem_nway_reset
,
2680 .get_msglevel
= gem_get_msglevel
,
2681 .set_msglevel
= gem_set_msglevel
,
2682 .get_wol
= gem_get_wol
,
2683 .set_wol
= gem_set_wol
,
2686 static int gem_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2688 struct gem
*gp
= netdev_priv(dev
);
2689 struct mii_ioctl_data
*data
= if_mii(ifr
);
2690 int rc
= -EOPNOTSUPP
;
2692 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2693 * netif_device_present() is true and holds rtnl_lock for us
2694 * so we have nothing to worry about
2698 case SIOCGMIIPHY
: /* Get address of MII PHY in use. */
2699 data
->phy_id
= gp
->mii_phy_addr
;
2700 /* Fallthrough... */
2702 case SIOCGMIIREG
: /* Read MII PHY register. */
2703 data
->val_out
= __phy_read(gp
, data
->phy_id
& 0x1f,
2704 data
->reg_num
& 0x1f);
2708 case SIOCSMIIREG
: /* Write MII PHY register. */
2709 __phy_write(gp
, data
->phy_id
& 0x1f, data
->reg_num
& 0x1f,
2717 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2718 /* Fetch MAC address from vital product data of PCI ROM. */
2719 static int find_eth_addr_in_vpd(void __iomem
*rom_base
, int len
, unsigned char *dev_addr
)
2723 for (this_offset
= 0x20; this_offset
< len
; this_offset
++) {
2724 void __iomem
*p
= rom_base
+ this_offset
;
2727 if (readb(p
+ 0) != 0x90 ||
2728 readb(p
+ 1) != 0x00 ||
2729 readb(p
+ 2) != 0x09 ||
2730 readb(p
+ 3) != 0x4e ||
2731 readb(p
+ 4) != 0x41 ||
2732 readb(p
+ 5) != 0x06)
2738 for (i
= 0; i
< 6; i
++)
2739 dev_addr
[i
] = readb(p
+ i
);
2745 static void get_gem_mac_nonobp(struct pci_dev
*pdev
, unsigned char *dev_addr
)
2748 void __iomem
*p
= pci_map_rom(pdev
, &size
);
2753 found
= readb(p
) == 0x55 &&
2754 readb(p
+ 1) == 0xaa &&
2755 find_eth_addr_in_vpd(p
, (64 * 1024), dev_addr
);
2756 pci_unmap_rom(pdev
, p
);
2761 /* Sun MAC prefix then 3 random bytes. */
2765 get_random_bytes(dev_addr
+ 3, 3);
2767 #endif /* not Sparc and not PPC */
2769 static int __devinit
gem_get_device_address(struct gem
*gp
)
2771 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2772 struct net_device
*dev
= gp
->dev
;
2773 const unsigned char *addr
;
2775 addr
= of_get_property(gp
->of_node
, "local-mac-address", NULL
);
2778 addr
= idprom
->id_ethaddr
;
2781 pr_err("%s: can't get mac-address\n", dev
->name
);
2785 memcpy(dev
->dev_addr
, addr
, 6);
2787 get_gem_mac_nonobp(gp
->pdev
, gp
->dev
->dev_addr
);
2792 static void gem_remove_one(struct pci_dev
*pdev
)
2794 struct net_device
*dev
= pci_get_drvdata(pdev
);
2797 struct gem
*gp
= netdev_priv(dev
);
2799 unregister_netdev(dev
);
2801 /* Ensure reset task is truely gone */
2802 cancel_work_sync(&gp
->reset_task
);
2804 /* Free resources */
2805 pci_free_consistent(pdev
,
2806 sizeof(struct gem_init_block
),
2810 pci_release_regions(pdev
);
2813 pci_set_drvdata(pdev
, NULL
);
2817 static const struct net_device_ops gem_netdev_ops
= {
2818 .ndo_open
= gem_open
,
2819 .ndo_stop
= gem_close
,
2820 .ndo_start_xmit
= gem_start_xmit
,
2821 .ndo_get_stats
= gem_get_stats
,
2822 .ndo_set_multicast_list
= gem_set_multicast
,
2823 .ndo_do_ioctl
= gem_ioctl
,
2824 .ndo_tx_timeout
= gem_tx_timeout
,
2825 .ndo_change_mtu
= gem_change_mtu
,
2826 .ndo_validate_addr
= eth_validate_addr
,
2827 .ndo_set_mac_address
= gem_set_mac_address
,
2828 #ifdef CONFIG_NET_POLL_CONTROLLER
2829 .ndo_poll_controller
= gem_poll_controller
,
2833 static int __devinit
gem_init_one(struct pci_dev
*pdev
,
2834 const struct pci_device_id
*ent
)
2836 unsigned long gemreg_base
, gemreg_len
;
2837 struct net_device
*dev
;
2839 int err
, pci_using_dac
;
2841 printk_once(KERN_INFO
"%s", version
);
2843 /* Apple gmac note: during probe, the chip is powered up by
2844 * the arch code to allow the code below to work (and to let
2845 * the chip be probed on the config space. It won't stay powered
2846 * up until the interface is brought up however, so we can't rely
2847 * on register configuration done at this point.
2849 err
= pci_enable_device(pdev
);
2851 pr_err("Cannot enable MMIO operation, aborting\n");
2854 pci_set_master(pdev
);
2856 /* Configure DMA attributes. */
2858 /* All of the GEM documentation states that 64-bit DMA addressing
2859 * is fully supported and should work just fine. However the
2860 * front end for RIO based GEMs is different and only supports
2861 * 32-bit addressing.
2863 * For now we assume the various PPC GEMs are 32-bit only as well.
2865 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
2866 pdev
->device
== PCI_DEVICE_ID_SUN_GEM
&&
2867 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
2870 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2872 pr_err("No usable DMA configuration, aborting\n");
2873 goto err_disable_device
;
2878 gemreg_base
= pci_resource_start(pdev
, 0);
2879 gemreg_len
= pci_resource_len(pdev
, 0);
2881 if ((pci_resource_flags(pdev
, 0) & IORESOURCE_IO
) != 0) {
2882 pr_err("Cannot find proper PCI device base address, aborting\n");
2884 goto err_disable_device
;
2887 dev
= alloc_etherdev(sizeof(*gp
));
2889 pr_err("Etherdev alloc failed, aborting\n");
2891 goto err_disable_device
;
2893 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2895 gp
= netdev_priv(dev
);
2897 err
= pci_request_regions(pdev
, DRV_NAME
);
2899 pr_err("Cannot obtain PCI resources, aborting\n");
2900 goto err_out_free_netdev
;
2904 dev
->base_addr
= (long) pdev
;
2907 gp
->msg_enable
= DEFAULT_MSG
;
2909 init_timer(&gp
->link_timer
);
2910 gp
->link_timer
.function
= gem_link_timer
;
2911 gp
->link_timer
.data
= (unsigned long) gp
;
2913 INIT_WORK(&gp
->reset_task
, gem_reset_task
);
2915 gp
->lstate
= link_down
;
2916 gp
->timer_ticks
= 0;
2917 netif_carrier_off(dev
);
2919 gp
->regs
= ioremap(gemreg_base
, gemreg_len
);
2921 pr_err("Cannot map device registers, aborting\n");
2923 goto err_out_free_res
;
2926 /* On Apple, we want a reference to the Open Firmware device-tree
2927 * node. We use it for clock control.
2929 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2930 gp
->of_node
= pci_device_to_OF_node(pdev
);
2933 /* Only Apple version supports WOL afaik */
2934 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
2937 /* Make sure cell is enabled */
2940 /* Make sure everything is stopped and in init state */
2943 /* Fill up the mii_phy structure (even if we won't use it) */
2944 gp
->phy_mii
.dev
= dev
;
2945 gp
->phy_mii
.mdio_read
= _phy_read
;
2946 gp
->phy_mii
.mdio_write
= _phy_write
;
2947 #ifdef CONFIG_PPC_PMAC
2948 gp
->phy_mii
.platform_data
= gp
->of_node
;
2950 /* By default, we start with autoneg */
2951 gp
->want_autoneg
= 1;
2953 /* Check fifo sizes, PHY type, etc... */
2954 if (gem_check_invariants(gp
)) {
2956 goto err_out_iounmap
;
2959 /* It is guaranteed that the returned buffer will be at least
2960 * PAGE_SIZE aligned.
2962 gp
->init_block
= (struct gem_init_block
*)
2963 pci_alloc_consistent(pdev
, sizeof(struct gem_init_block
),
2965 if (!gp
->init_block
) {
2966 pr_err("Cannot allocate init block, aborting\n");
2968 goto err_out_iounmap
;
2971 if (gem_get_device_address(gp
))
2972 goto err_out_free_consistent
;
2974 dev
->netdev_ops
= &gem_netdev_ops
;
2975 netif_napi_add(dev
, &gp
->napi
, gem_poll
, 64);
2976 dev
->ethtool_ops
= &gem_ethtool_ops
;
2977 dev
->watchdog_timeo
= 5 * HZ
;
2978 dev
->irq
= pdev
->irq
;
2981 /* Set that now, in case PM kicks in now */
2982 pci_set_drvdata(pdev
, dev
);
2984 /* We can do scatter/gather and HW checksum */
2985 dev
->hw_features
= NETIF_F_SG
| NETIF_F_HW_CSUM
;
2986 dev
->features
|= dev
->hw_features
| NETIF_F_RXCSUM
;
2988 dev
->features
|= NETIF_F_HIGHDMA
;
2990 /* Register with kernel */
2991 if (register_netdev(dev
)) {
2992 pr_err("Cannot register net device, aborting\n");
2994 goto err_out_free_consistent
;
2997 /* Undo the get_cell with appropriate locking (we could use
2998 * ndo_init/uninit but that would be even more clumsy imho)
3004 netdev_info(dev
, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3008 err_out_free_consistent
:
3009 gem_remove_one(pdev
);
3015 pci_release_regions(pdev
);
3017 err_out_free_netdev
:
3020 pci_disable_device(pdev
);
3026 static struct pci_driver gem_driver
= {
3027 .name
= GEM_MODULE_NAME
,
3028 .id_table
= gem_pci_tbl
,
3029 .probe
= gem_init_one
,
3030 .remove
= gem_remove_one
,
3032 .suspend
= gem_suspend
,
3033 .resume
= gem_resume
,
3034 #endif /* CONFIG_PM */
3037 static int __init
gem_init(void)
3039 return pci_register_driver(&gem_driver
);
3042 static void __exit
gem_cleanup(void)
3044 pci_unregister_driver(&gem_driver
);
3047 module_init(gem_init
);
3048 module_exit(gem_cleanup
);