2 * Broadcom specific AMBA
3 * ChipCommon Power Management Unit driver
5 * Copyright 2009, Michael Buesch <m@bues.ch>
6 * Copyright 2007, Broadcom Corporation
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "bcma_private.h"
12 #include <linux/bcma/bcma.h>
14 static u32
bcma_chipco_pll_read(struct bcma_drv_cc
*cc
, u32 offset
)
16 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
17 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
18 return bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
21 static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc
*cc
,
22 u32 offset
, u32 mask
, u32 set
)
26 bcma_cc_read32(cc
, BCMA_CC_CHIPCTL_ADDR
);
27 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL_ADDR
, offset
);
28 bcma_cc_read32(cc
, BCMA_CC_CHIPCTL_ADDR
);
29 value
= bcma_cc_read32(cc
, BCMA_CC_CHIPCTL_DATA
);
32 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL_DATA
, value
);
33 bcma_cc_read32(cc
, BCMA_CC_CHIPCTL_DATA
);
36 static void bcma_pmu_pll_init(struct bcma_drv_cc
*cc
)
38 struct bcma_bus
*bus
= cc
->core
->bus
;
40 switch (bus
->chipinfo
.id
) {
47 pr_err("PLL init unknown for device 0x%04X\n",
52 static void bcma_pmu_resources_init(struct bcma_drv_cc
*cc
)
54 struct bcma_bus
*bus
= cc
->core
->bus
;
55 u32 min_msk
= 0, max_msk
= 0;
57 switch (bus
->chipinfo
.id
) {
66 pr_err("PMU resource config unknown for device 0x%04X\n",
70 /* Set the resource masks. */
72 bcma_cc_write32(cc
, BCMA_CC_PMU_MINRES_MSK
, min_msk
);
74 bcma_cc_write32(cc
, BCMA_CC_PMU_MAXRES_MSK
, max_msk
);
77 void bcma_pmu_swreg_init(struct bcma_drv_cc
*cc
)
79 struct bcma_bus
*bus
= cc
->core
->bus
;
81 switch (bus
->chipinfo
.id
) {
88 pr_err("PMU switch/regulators init unknown for device "
89 "0x%04X\n", bus
->chipinfo
.id
);
93 void bcma_pmu_workarounds(struct bcma_drv_cc
*cc
)
95 struct bcma_bus
*bus
= cc
->core
->bus
;
97 switch (bus
->chipinfo
.id
) {
99 bcma_chipco_chipctl_maskset(cc
, 0, ~0, 0x7);
102 pr_err("Enabling Ext PA lines not implemented\n");
105 if (bus
->chipinfo
.rev
== 0) {
106 pr_err("Workarounds for 43224 rev 0 not fully "
108 bcma_chipco_chipctl_maskset(cc
, 0, ~0, 0x00F000F0);
110 bcma_chipco_chipctl_maskset(cc
, 0, ~0, 0xF0);
116 pr_err("Workarounds unknown for device 0x%04X\n",
121 void bcma_pmu_init(struct bcma_drv_cc
*cc
)
125 pmucap
= bcma_cc_read32(cc
, BCMA_CC_PMU_CAP
);
126 cc
->pmu
.rev
= (pmucap
& BCMA_CC_PMU_CAP_REVISION
);
128 pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc
->pmu
.rev
,
131 if (cc
->pmu
.rev
== 1)
132 bcma_cc_mask32(cc
, BCMA_CC_PMU_CTL
,
133 ~BCMA_CC_PMU_CTL_NOILPONW
);
135 bcma_cc_set32(cc
, BCMA_CC_PMU_CTL
,
136 BCMA_CC_PMU_CTL_NOILPONW
);
138 if (cc
->core
->id
.id
== 0x4329 && cc
->core
->id
.rev
== 2)
139 pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
141 bcma_pmu_pll_init(cc
);
142 bcma_pmu_resources_init(cc
);
143 bcma_pmu_swreg_init(cc
);
144 bcma_pmu_workarounds(cc
);
147 u32
bcma_pmu_alp_clock(struct bcma_drv_cc
*cc
)
149 struct bcma_bus
*bus
= cc
->core
->bus
;
151 switch (bus
->chipinfo
.id
) {
166 pr_warn("No ALP clock specified for %04X device, "
167 "pmu rev. %d, using default %d Hz\n",
168 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_ALP_CLOCK
);
170 return BCMA_CC_PMU_ALP_CLOCK
;
173 /* Find the output of the "m" pll divider given pll controls that start with
174 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
176 static u32
bcma_pmu_clock(struct bcma_drv_cc
*cc
, u32 pll0
, u32 m
)
178 u32 tmp
, div
, ndiv
, p1
, p2
, fc
;
179 struct bcma_bus
*bus
= cc
->core
->bus
;
181 BUG_ON((pll0
& 3) || (pll0
> BCMA_CC_PMU4716_MAINPLL_PLL0
));
185 if (bus
->chipinfo
.id
== 0x5357 || bus
->chipinfo
.id
== 0x4749) {
186 /* Detect failure in clock setting */
187 tmp
= bcma_cc_read32(cc
, BCMA_CC_CHIPSTAT
);
189 return 133 * 1000000;
192 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_P1P2_OFF
);
193 p1
= (tmp
& BCMA_CC_PPL_P1_MASK
) >> BCMA_CC_PPL_P1_SHIFT
;
194 p2
= (tmp
& BCMA_CC_PPL_P2_MASK
) >> BCMA_CC_PPL_P2_SHIFT
;
196 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_M14_OFF
);
197 div
= (tmp
>> ((m
- 1) * BCMA_CC_PPL_MDIV_WIDTH
)) &
198 BCMA_CC_PPL_MDIV_MASK
;
200 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_NM5_OFF
);
201 ndiv
= (tmp
& BCMA_CC_PPL_NDIV_MASK
) >> BCMA_CC_PPL_NDIV_SHIFT
;
203 /* Do calculation in Mhz */
204 fc
= bcma_pmu_alp_clock(cc
) / 1000000;
205 fc
= (p1
* ndiv
* fc
) / p2
;
207 /* Return clock in Hertz */
208 return (fc
/ div
) * 1000000;
211 /* query bus clock frequency for PMU-enabled chipcommon */
212 u32
bcma_pmu_get_clockcontrol(struct bcma_drv_cc
*cc
)
214 struct bcma_bus
*bus
= cc
->core
->bus
;
216 switch (bus
->chipinfo
.id
) {
220 return bcma_pmu_clock(cc
, BCMA_CC_PMU4716_MAINPLL_PLL0
,
221 BCMA_CC_PMU5_MAINPLL_SSB
);
223 return bcma_pmu_clock(cc
, BCMA_CC_PMU5356_MAINPLL_PLL0
,
224 BCMA_CC_PMU5_MAINPLL_SSB
);
227 return bcma_pmu_clock(cc
, BCMA_CC_PMU5357_MAINPLL_PLL0
,
228 BCMA_CC_PMU5_MAINPLL_SSB
);
230 return bcma_pmu_clock(cc
, BCMA_CC_PMU4706_MAINPLL_PLL0
,
231 BCMA_CC_PMU5_MAINPLL_SSB
);
235 pr_warn("No backplane clock specified for %04X device, "
236 "pmu rev. %d, using default %d Hz\n",
237 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_HT_CLOCK
);
239 return BCMA_CC_PMU_HT_CLOCK
;
242 /* query cpu clock frequency for PMU-enabled chipcommon */
243 u32
bcma_pmu_get_clockcpu(struct bcma_drv_cc
*cc
)
245 struct bcma_bus
*bus
= cc
->core
->bus
;
247 if (bus
->chipinfo
.id
== 53572)
250 if (cc
->pmu
.rev
>= 5) {
252 switch (bus
->chipinfo
.id
) {
254 pll
= BCMA_CC_PMU5356_MAINPLL_PLL0
;
258 pll
= BCMA_CC_PMU5357_MAINPLL_PLL0
;
261 pll
= BCMA_CC_PMU4716_MAINPLL_PLL0
;
265 /* TODO: if (bus->chipinfo.id == 0x5300)
266 return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
267 return bcma_pmu_clock(cc
, pll
, BCMA_CC_PMU5_MAINPLL_CPU
);
270 return bcma_pmu_get_clockcontrol(cc
);