| blob | 91e04d319d76fa195d036a5692f303a59495fb35 |
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt73usb
23 Abstract: Data structures and registers for the rt73usb module.
24 Supported chipsets: rt2571W & rt2671.
25 */
27 #ifndef RT73USB_H
28 #define RT73USB_H
30 /*
31 * RF chip defines.
32 */
33 #define RF5226 0x0001
34 #define RF2528 0x0002
35 #define RF5225 0x0003
36 #define RF2527 0x0004
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define DEFAULT_RSSI_OFFSET 120
44 /*
45 * Register layout information.
46 */
47 #define CSR_REG_BASE 0x3000
48 #define CSR_REG_SIZE 0x04b0
49 #define EEPROM_BASE 0x0000
50 #define EEPROM_SIZE 0x0100
51 #define BBP_SIZE 0x0080
52 #define RF_SIZE 0x0014
54 /*
55 * Number of TX queues.
56 */
57 #define NUM_TX_QUEUES 4
59 /*
60 * USB registers.
61 */
63 /*
64 * MCU_LEDCS: LED control for MCU Mailbox.
65 */
66 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
67 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
68 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
69 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
70 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
71 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
72 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
73 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
74 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
75 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
76 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
77 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
79 /*
80 * 8051 firmware image.
81 */
83 #define FIRMWARE_IMAGE_BASE 0x0800
85 /*
86 * Security key table memory.
87 * 16 entries 32-byte for shared key table
88 * 64 entries 32-byte for pairwise key table
89 * 64 entries 8-byte for pairwise ta key table
90 */
91 #define SHARED_KEY_TABLE_BASE 0x1000
92 #define PAIRWISE_KEY_TABLE_BASE 0x1200
93 #define PAIRWISE_TA_TABLE_BASE 0x1a00
95 #define SHARED_KEY_ENTRY(__idx) \
96 ( SHARED_KEY_TABLE_BASE + \
97 ((__idx) * sizeof(struct hw_key_entry)) )
98 #define PAIRWISE_KEY_ENTRY(__idx) \
99 ( PAIRWISE_KEY_TABLE_BASE + \
100 ((__idx) * sizeof(struct hw_key_entry)) )
101 #define PAIRWISE_TA_ENTRY(__idx) \
102 ( PAIRWISE_TA_TABLE_BASE + \
103 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
113 u8 cipher;
114 u8 reserved;
117 /*
118 * Since NULL frame won't be that long (256 byte),
119 * We steal 16 tail bytes to save debugging settings.
120 */
121 #define HW_DEBUG_SETTING_BASE 0x2bf0
123 /*
124 * On-chip BEACON frame space.
125 */
126 #define HW_BEACON_BASE0 0x2400
127 #define HW_BEACON_BASE1 0x2500
128 #define HW_BEACON_BASE2 0x2600
129 #define HW_BEACON_BASE3 0x2700
131 #define HW_BEACON_OFFSET(__index) \
132 ( HW_BEACON_BASE0 + (__index * 0x0100) )
134 /*
135 * MAC Control/Status Registers(CSR).
136 * Some values are set in TU, whereas 1 TU == 1024 us.
137 */
139 /*
140 * MAC_CSR0: ASIC revision number.
141 */
142 #define MAC_CSR0 0x3000
144 /*
145 * MAC_CSR1: System control register.
146 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
147 * BBP_RESET: Hardware reset BBP.
148 * HOST_READY: Host is ready after initialization, 1: ready.
149 */
150 #define MAC_CSR1 0x3004
151 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
152 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
153 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
155 /*
156 * MAC_CSR2: STA MAC register 0.
157 */
158 #define MAC_CSR2 0x3008
159 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
160 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
161 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
162 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
164 /*
165 * MAC_CSR3: STA MAC register 1.
166 * UNICAST_TO_ME_MASK:
167 * Used to mask off bits from byte 5 of the MAC address
168 * to determine the UNICAST_TO_ME bit for RX frames.
169 * The full mask is complemented by BSS_ID_MASK:
170 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
171 */
172 #define MAC_CSR3 0x300c
173 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
174 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
175 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
177 /*
178 * MAC_CSR4: BSSID register 0.
179 */
180 #define MAC_CSR4 0x3010
181 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
182 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
183 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
184 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
186 /*
187 * MAC_CSR5: BSSID register 1.
188 * BSS_ID_MASK:
189 * This mask is used to mask off bits 0 and 1 of byte 5 of the
190 * BSSID. This will make sure that those bits will be ignored
191 * when determining the MY_BSS of RX frames.
192 * 0: 1-BSSID mode (BSS index = 0)
193 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
194 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
195 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
196 */
197 #define MAC_CSR5 0x3014
198 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
199 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
200 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
202 /*
203 * MAC_CSR6: Maximum frame length register.
204 */
205 #define MAC_CSR6 0x3018
206 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
208 /*
209 * MAC_CSR7: Reserved
210 */
211 #define MAC_CSR7 0x301c
213 /*
214 * MAC_CSR8: SIFS/EIFS register.
215 * All units are in US.
216 */
217 #define MAC_CSR8 0x3020
218 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
219 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
220 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
222 /*
223 * MAC_CSR9: Back-Off control register.
224 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
225 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
226 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
227 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
228 */
229 #define MAC_CSR9 0x3024
230 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
231 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
232 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
233 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
235 /*
236 * MAC_CSR10: Power state configuration.
237 */
238 #define MAC_CSR10 0x3028
240 /*
241 * MAC_CSR11: Power saving transition time register.
242 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
243 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
244 * WAKEUP_LATENCY: In unit of TU.
245 */
246 #define MAC_CSR11 0x302c
247 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
248 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
249 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
250 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
252 /*
253 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
254 * CURRENT_STATE: 0:sleep, 1:awake.
255 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
256 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
257 */
258 #define MAC_CSR12 0x3030
259 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
260 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
261 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
262 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
264 /*
265 * MAC_CSR13: GPIO.
266 */
267 #define MAC_CSR13 0x3034
269 /*
270 * MAC_CSR14: LED control register.
271 * ON_PERIOD: On period, default 70ms.
272 * OFF_PERIOD: Off period, default 30ms.
273 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
274 * SW_LED: s/w LED, 1: ON, 0: OFF.
275 * HW_LED_POLARITY: 0: active low, 1: active high.
276 */
277 #define MAC_CSR14 0x3038
278 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
279 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
280 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
281 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
282 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
283 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
285 /*
286 * MAC_CSR15: NAV control.
287 */
288 #define MAC_CSR15 0x303c
290 /*
291 * TXRX control registers.
292 * Some values are set in TU, whereas 1 TU == 1024 us.
293 */
295 /*
296 * TXRX_CSR0: TX/RX configuration register.
297 * TSF_OFFSET: Default is 24.
298 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
299 * DISABLE_RX: Disable Rx engine.
300 * DROP_CRC: Drop CRC error.
301 * DROP_PHYSICAL: Drop physical error.
302 * DROP_CONTROL: Drop control frame.
303 * DROP_NOT_TO_ME: Drop not to me unicast frame.
304 * DROP_TO_DS: Drop fram ToDs bit is true.
305 * DROP_VERSION_ERROR: Drop version error frame.
306 * DROP_MULTICAST: Drop multicast frames.
307 * DROP_BORADCAST: Drop broadcast frames.
308 * ROP_ACK_CTS: Drop received ACK and CTS.
309 */
310 #define TXRX_CSR0 0x3040
311 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
312 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
313 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
314 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
315 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
316 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
317 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
318 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
319 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
320 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
321 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
322 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
323 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
324 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
326 /*
327 * TXRX_CSR1
328 */
329 #define TXRX_CSR1 0x3044
330 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
331 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
332 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
333 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
334 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
335 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
336 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
337 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
339 /*
340 * TXRX_CSR2
341 */
342 #define TXRX_CSR2 0x3048
343 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
344 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
345 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
346 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
347 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
348 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
349 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
350 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
352 /*
353 * TXRX_CSR3
354 */
355 #define TXRX_CSR3 0x304c
356 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
357 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
358 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
359 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
360 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
361 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
362 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
363 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
365 /*
366 * TXRX_CSR4: Auto-Responder/Tx-retry register.
367 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
368 * OFDM_TX_RATE_DOWN: 1:enable.
369 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
370 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
371 */
372 #define TXRX_CSR4 0x3050
373 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
374 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
375 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
376 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
377 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
378 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
379 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
380 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
381 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
382 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
384 /*
385 * TXRX_CSR5
386 */
387 #define TXRX_CSR5 0x3054
389 /*
390 * TXRX_CSR6: ACK/CTS payload consumed time
391 */
392 #define TXRX_CSR6 0x3058
394 /*
395 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
396 */
397 #define TXRX_CSR7 0x305c
398 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
399 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
400 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
401 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
403 /*
404 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
405 */
406 #define TXRX_CSR8 0x3060
407 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
408 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
409 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
410 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
412 /*
413 * TXRX_CSR9: Synchronization control register.
414 * BEACON_INTERVAL: In unit of 1/16 TU.
415 * TSF_TICKING: Enable TSF auto counting.
416 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
417 * BEACON_GEN: Enable beacon generator.
418 */
419 #define TXRX_CSR9 0x3064
420 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
421 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
422 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
423 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
424 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
425 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
427 /*
428 * TXRX_CSR10: BEACON alignment.
429 */
430 #define TXRX_CSR10 0x3068
432 /*
433 * TXRX_CSR11: AES mask.
434 */
435 #define TXRX_CSR11 0x306c
437 /*
438 * TXRX_CSR12: TSF low 32.
439 */
440 #define TXRX_CSR12 0x3070
441 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
443 /*
444 * TXRX_CSR13: TSF high 32.
445 */
446 #define TXRX_CSR13 0x3074
447 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
449 /*
450 * TXRX_CSR14: TBTT timer.
451 */
452 #define TXRX_CSR14 0x3078
454 /*
455 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
456 */
457 #define TXRX_CSR15 0x307c
459 /*
460 * PHY control registers.
461 * Some values are set in TU, whereas 1 TU == 1024 us.
462 */
464 /*
465 * PHY_CSR0: RF/PS control.
466 */
467 #define PHY_CSR0 0x3080
468 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
469 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
471 /*
472 * PHY_CSR1
473 */
474 #define PHY_CSR1 0x3084
475 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
477 /*
478 * PHY_CSR2: Pre-TX BBP control.
479 */
480 #define PHY_CSR2 0x3088
482 /*
483 * PHY_CSR3: BBP serial control register.
484 * VALUE: Register value to program into BBP.
485 * REG_NUM: Selected BBP register.
486 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
487 * BUSY: 1: ASIC is busy execute BBP programming.
488 */
489 #define PHY_CSR3 0x308c
490 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
491 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
492 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
493 #define PHY_CSR3_BUSY FIELD32(0x00010000)
495 /*
496 * PHY_CSR4: RF serial control register
497 * VALUE: Register value (include register id) serial out to RF/IF chip.
498 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
499 * IF_SELECT: 1: select IF to program, 0: select RF to program.
500 * PLL_LD: RF PLL_LD status.
501 * BUSY: 1: ASIC is busy execute RF programming.
502 */
503 #define PHY_CSR4 0x3090
504 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
505 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
506 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
507 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
508 #define PHY_CSR4_BUSY FIELD32(0x80000000)
510 /*
511 * PHY_CSR5: RX to TX signal switch timing control.
512 */
513 #define PHY_CSR5 0x3094
514 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
516 /*
517 * PHY_CSR6: TX to RX signal timing control.
518 */
519 #define PHY_CSR6 0x3098
520 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
522 /*
523 * PHY_CSR7: TX DAC switching timing control.
524 */
525 #define PHY_CSR7 0x309c
527 /*
528 * Security control register.
529 */
531 /*
532 * SEC_CSR0: Shared key table control.
533 */
534 #define SEC_CSR0 0x30a0
535 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
536 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
537 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
538 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
539 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
540 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
541 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
542 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
543 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
544 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
545 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
546 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
547 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
548 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
549 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
550 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
552 /*
553 * SEC_CSR1: Shared key table security mode register.
554 */
555 #define SEC_CSR1 0x30a4
556 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
557 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
558 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
559 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
560 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
561 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
562 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
563 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
565 /*
566 * Pairwise key table valid bitmap registers.
567 * SEC_CSR2: pairwise key table valid bitmap 0.
568 * SEC_CSR3: pairwise key table valid bitmap 1.
569 */
570 #define SEC_CSR2 0x30a8
571 #define SEC_CSR3 0x30ac
573 /*
574 * SEC_CSR4: Pairwise key table lookup control.
575 */
576 #define SEC_CSR4 0x30b0
577 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
578 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
579 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
580 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
582 /*
583 * SEC_CSR5: shared key table security mode register.
584 */
585 #define SEC_CSR5 0x30b4
586 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
587 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
588 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
589 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
590 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
591 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
592 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
593 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
595 /*
596 * STA control registers.
597 */
599 /*
600 * STA_CSR0: RX PLCP error count & RX FCS error count.
601 */
602 #define STA_CSR0 0x30c0
603 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
604 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
606 /*
607 * STA_CSR1: RX False CCA count & RX LONG frame count.
608 */
609 #define STA_CSR1 0x30c4
610 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
611 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
613 /*
614 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
615 */
616 #define STA_CSR2 0x30c8
617 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
618 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
620 /*
621 * STA_CSR3: TX Beacon count.
622 */
623 #define STA_CSR3 0x30cc
624 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
626 /*
627 * STA_CSR4: TX Retry count.
628 */
629 #define STA_CSR4 0x30d0
630 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
631 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
633 /*
634 * STA_CSR5: TX Retry count.
635 */
636 #define STA_CSR5 0x30d4
637 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
638 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
640 /*
641 * QOS control registers.
642 */
644 /*
645 * QOS_CSR1: TXOP holder MAC address register.
646 */
647 #define QOS_CSR1 0x30e4
648 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
649 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
651 /*
652 * QOS_CSR2: TXOP holder timeout register.
653 */
654 #define QOS_CSR2 0x30e8
656 /*
657 * RX QOS-CFPOLL MAC address register.
658 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
659 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
660 */
661 #define QOS_CSR3 0x30ec
662 #define QOS_CSR4 0x30f0
664 /*
665 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
666 */
667 #define QOS_CSR5 0x30f4
669 /*
670 * WMM Scheduler Register
671 */
673 /*
674 * AIFSN_CSR: AIFSN for each EDCA AC.
675 * AIFSN0: For AC_BK.
676 * AIFSN1: For AC_BE.
677 * AIFSN2: For AC_VI.
678 * AIFSN3: For AC_VO.
679 */
680 #define AIFSN_CSR 0x0400
681 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
682 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
683 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
684 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
686 /*
687 * CWMIN_CSR: CWmin for each EDCA AC.
688 * CWMIN0: For AC_BK.
689 * CWMIN1: For AC_BE.
690 * CWMIN2: For AC_VI.
691 * CWMIN3: For AC_VO.
692 */
693 #define CWMIN_CSR 0x0404
694 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
695 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
696 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
697 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
699 /*
700 * CWMAX_CSR: CWmax for each EDCA AC.
701 * CWMAX0: For AC_BK.
702 * CWMAX1: For AC_BE.
703 * CWMAX2: For AC_VI.
704 * CWMAX3: For AC_VO.
705 */
706 #define CWMAX_CSR 0x0408
707 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
708 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
709 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
710 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
712 /*
713 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
714 * AC0_TX_OP: For AC_BK, in unit of 32us.
715 * AC1_TX_OP: For AC_BE, in unit of 32us.
716 */
717 #define AC_TXOP_CSR0 0x040c
718 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
719 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
721 /*
722 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
723 * AC2_TX_OP: For AC_VI, in unit of 32us.
724 * AC3_TX_OP: For AC_VO, in unit of 32us.
725 */
726 #define AC_TXOP_CSR1 0x0410
727 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
728 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
730 /*
731 * BBP registers.
732 * The wordsize of the BBP is 8 bits.
733 */
735 /*
736 * R2
737 */
738 #define BBP_R2_BG_MODE FIELD8(0x20)
740 /*
741 * R3
742 */
743 #define BBP_R3_SMART_MODE FIELD8(0x01)
745 /*
746 * R4: RX antenna control
747 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
748 */
750 /*
751 * ANTENNA_CONTROL semantics (guessed):
752 * 0x1: Software controlled antenna switching (fixed or SW diversity)
753 * 0x2: Hardware diversity.
754 */
755 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
756 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
758 /*
759 * R77
760 */
761 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
763 /*
764 * RF registers
765 */
767 /*
768 * RF 3
769 */
770 #define RF3_TXPOWER FIELD32(0x00003e00)
772 /*
773 * RF 4
774 */
775 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
777 /*
778 * EEPROM content.
779 * The wordsize of the EEPROM is 16 bits.
780 */
782 /*
783 * HW MAC address.
784 */
785 #define EEPROM_MAC_ADDR_0 0x0002
786 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
787 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
788 #define EEPROM_MAC_ADDR1 0x0003
789 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
790 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
791 #define EEPROM_MAC_ADDR_2 0x0004
792 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
793 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
795 /*
796 * EEPROM antenna.
797 * ANTENNA_NUM: Number of antenna's.
798 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
799 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
800 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
801 * DYN_TXAGC: Dynamic TX AGC control.
802 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
803 * RF_TYPE: Rf_type of this adapter.
804 */
805 #define EEPROM_ANTENNA 0x0010
806 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
807 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
808 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
809 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
810 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
811 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
812 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
814 /*
815 * EEPROM NIC config.
816 * EXTERNAL_LNA: External LNA.
817 */
818 #define EEPROM_NIC 0x0011
819 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
821 /*
822 * EEPROM geography.
823 * GEO_A: Default geographical setting for 5GHz band
824 * GEO: Default geographical setting.
825 */
826 #define EEPROM_GEOGRAPHY 0x0012
827 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
828 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
830 /*
831 * EEPROM BBP.
832 */
833 #define EEPROM_BBP_START 0x0013
834 #define EEPROM_BBP_SIZE 16
835 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
836 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
838 /*
839 * EEPROM TXPOWER 802.11G
840 */
841 #define EEPROM_TXPOWER_G_START 0x0023
842 #define EEPROM_TXPOWER_G_SIZE 7
843 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
844 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
846 /*
847 * EEPROM Frequency
848 */
849 #define EEPROM_FREQ 0x002f
850 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
851 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
852 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
854 /*
855 * EEPROM LED.
856 * POLARITY_RDY_G: Polarity RDY_G setting.
857 * POLARITY_RDY_A: Polarity RDY_A setting.
858 * POLARITY_ACT: Polarity ACT setting.
859 * POLARITY_GPIO_0: Polarity GPIO0 setting.
860 * POLARITY_GPIO_1: Polarity GPIO1 setting.
861 * POLARITY_GPIO_2: Polarity GPIO2 setting.
862 * POLARITY_GPIO_3: Polarity GPIO3 setting.
863 * POLARITY_GPIO_4: Polarity GPIO4 setting.
864 * LED_MODE: Led mode.
865 */
866 #define EEPROM_LED 0x0030
867 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
868 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
869 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
870 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
871 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
872 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
873 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
874 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
875 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
877 /*
878 * EEPROM TXPOWER 802.11A
879 */
880 #define EEPROM_TXPOWER_A_START 0x0031
881 #define EEPROM_TXPOWER_A_SIZE 12
882 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
883 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
885 /*
886 * EEPROM RSSI offset 802.11BG
887 */
888 #define EEPROM_RSSI_OFFSET_BG 0x004d
889 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
890 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
892 /*
893 * EEPROM RSSI offset 802.11A
894 */
895 #define EEPROM_RSSI_OFFSET_A 0x004e
896 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
897 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
899 /*
900 * DMA descriptor defines.
901 */
902 #define TXD_DESC_SIZE ( 6 * sizeof(__le32) )
903 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
904 #define RXD_DESC_SIZE ( 6 * sizeof(__le32) )
906 /*
907 * TX descriptor format for TX, PRIO and Beacon Ring.
908 */
910 /*
911 * Word0
912 * BURST: Next frame belongs to same "burst" event.
913 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
914 * KEY_TABLE: Use per-client pairwise KEY table.
915 * KEY_INDEX:
916 * Key index (0~31) to the pairwise KEY table.
917 * 0~3 to shared KEY table 0 (BSS0).
918 * 4~7 to shared KEY table 1 (BSS1).
919 * 8~11 to shared KEY table 2 (BSS2).
920 * 12~15 to shared KEY table 3 (BSS3).
921 * BURST2: For backward compatibility, set to same value as BURST.
922 */
923 #define TXD_W0_BURST FIELD32(0x00000001)
924 #define TXD_W0_VALID FIELD32(0x00000002)
925 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
926 #define TXD_W0_ACK FIELD32(0x00000008)
927 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
928 #define TXD_W0_OFDM FIELD32(0x00000020)
929 #define TXD_W0_IFS FIELD32(0x00000040)
930 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
931 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
932 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
933 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
934 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
935 #define TXD_W0_BURST2 FIELD32(0x10000000)
936 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
938 /*
939 * Word1
940 * HOST_Q_ID: EDCA/HCCA queue ID.
941 * HW_SEQUENCE: MAC overwrites the frame sequence number.
942 * BUFFER_COUNT: Number of buffers in this TXD.
943 */
944 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
945 #define TXD_W1_AIFSN FIELD32(0x000000f0)
946 #define TXD_W1_CWMIN FIELD32(0x00000f00)
947 #define TXD_W1_CWMAX FIELD32(0x0000f000)
948 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
949 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
950 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
952 /*
953 * Word2: PLCP information
954 */
955 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
956 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
957 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
958 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
960 /*
961 * Word3
962 */
963 #define TXD_W3_IV FIELD32(0xffffffff)
965 /*
966 * Word4
967 */
968 #define TXD_W4_EIV FIELD32(0xffffffff)
970 /*
971 * Word5
972 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
973 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
974 * WAITING_DMA_DONE_INT: TXD been filled with data
975 * and waiting for TxDoneISR housekeeping.
976 */
977 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
978 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
979 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
980 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
982 /*
983 * RX descriptor format for RX Ring.
984 */
986 /*
987 * Word0
988 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
989 * KEY_INDEX: Decryption key actually used.
990 */
991 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
992 #define RXD_W0_DROP FIELD32(0x00000002)
993 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
994 #define RXD_W0_MULTICAST FIELD32(0x00000008)
995 #define RXD_W0_BROADCAST FIELD32(0x00000010)
996 #define RXD_W0_MY_BSS FIELD32(0x00000020)
997 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
998 #define RXD_W0_OFDM FIELD32(0x00000080)
999 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1000 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1001 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1002 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1004 /*
1005 * WORD1
1006 * SIGNAL: RX raw data rate reported by BBP.
1007 * RSSI: RSSI reported by BBP.
1008 */
1009 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1010 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1011 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1012 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1014 /*
1015 * Word2
1016 * IV: Received IV of originally encrypted.
1017 */
1018 #define RXD_W2_IV FIELD32(0xffffffff)
1020 /*
1021 * Word3
1022 * EIV: Received EIV of originally encrypted.
1023 */
1024 #define RXD_W3_EIV FIELD32(0xffffffff)
1026 /*
1027 * Word4
1028 * ICV: Received ICV of originally encrypted.
1029 * NOTE: This is a guess, the official definition is "reserved"
1030 */
1031 #define RXD_W4_ICV FIELD32(0xffffffff)
1033 /*
1034 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1035 * and passed to the HOST driver.
1036 * The following fields are for DMA block and HOST usage only.
1037 * Can't be touched by ASIC MAC block.
1038 */
1040 /*
1041 * Word5
1042 */
1043 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1045 /*
1046 * Macro's for converting txpower from EEPROM to mac80211 value
1047 * and from mac80211 value to register value.
1048 */
1049 #define MIN_TXPOWER 0
1050 #define MAX_TXPOWER 31
1051 #define DEFAULT_TXPOWER 24
1053 #define TXPOWER_FROM_DEV(__txpower) \
1054 ({ \
1055 ((__txpower) > MAX_TXPOWER) ? \
1056 DEFAULT_TXPOWER : (__txpower); \
1057 })
1059 #define TXPOWER_TO_DEV(__txpower) \
1060 ({ \
1061 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1062 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1063 (__txpower)); \
1064 })