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rt2x00: Fix race condition when using inderect registers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blob972b5a5c3864b3bfede5f6c586758044313e8a9b
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65 }
66
67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
69 {
70 u32 reg;
71
72 mutex_lock(&rt2x00dev->csr_mutex);
73
74 /*
75 * Wait until the BBP becomes ready.
76 */
77 reg = rt2500pci_bbp_check(rt2x00dev);
78 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
79 goto exit_fail;
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91
92 mutex_unlock(&rt2x00dev->csr_mutex);
93
94 return;
95
96 exit_fail:
97 mutex_unlock(&rt2x00dev->csr_mutex);
98
99 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
100 }
101
102 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
103 const unsigned int word, u8 *value)
104 {
105 u32 reg;
106
107 mutex_lock(&rt2x00dev->csr_mutex);
108
109 /*
110 * Wait until the BBP becomes ready.
111 */
112 reg = rt2500pci_bbp_check(rt2x00dev);
113 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
114 goto exit_fail;
115
116 /*
117 * Write the request into the BBP.
118 */
119 reg = 0;
120 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
121 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
122 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
123
124 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
125
126 /*
127 * Wait until the BBP becomes ready.
128 */
129 reg = rt2500pci_bbp_check(rt2x00dev);
130 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
131 goto exit_fail;
132
133 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
134
135 mutex_unlock(&rt2x00dev->csr_mutex);
136
137 return;
138
139 exit_fail:
140 mutex_unlock(&rt2x00dev->csr_mutex);
141
142 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
143 *value = 0xff;
144 }
145
146 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
147 const unsigned int word, const u32 value)
148 {
149 u32 reg;
150 unsigned int i;
151
152 if (!word)
153 return;
154
155 mutex_lock(&rt2x00dev->csr_mutex);
156
157 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
158 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
159 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
160 goto rf_write;
161 udelay(REGISTER_BUSY_DELAY);
162 }
163
164 mutex_unlock(&rt2x00dev->csr_mutex);
165 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
166 return;
167
168 rf_write:
169 reg = 0;
170 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
171 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
172 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
173 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
174
175 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
176 rt2x00_rf_write(rt2x00dev, word, value);
177
178 mutex_unlock(&rt2x00dev->csr_mutex);
179 }
180
181 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
182 {
183 struct rt2x00_dev *rt2x00dev = eeprom->data;
184 u32 reg;
185
186 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
187
188 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
189 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
190 eeprom->reg_data_clock =
191 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
192 eeprom->reg_chip_select =
193 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
194 }
195
196 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
197 {
198 struct rt2x00_dev *rt2x00dev = eeprom->data;
199 u32 reg = 0;
200
201 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
202 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
203 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
204 !!eeprom->reg_data_clock);
205 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
206 !!eeprom->reg_chip_select);
207
208 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
209 }
210
211 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
212 static const struct rt2x00debug rt2500pci_rt2x00debug = {
213 .owner = THIS_MODULE,
214 .csr = {
215 .read = rt2x00pci_register_read,
216 .write = rt2x00pci_register_write,
217 .flags = RT2X00DEBUGFS_OFFSET,
218 .word_base = CSR_REG_BASE,
219 .word_size = sizeof(u32),
220 .word_count = CSR_REG_SIZE / sizeof(u32),
221 },
222 .eeprom = {
223 .read = rt2x00_eeprom_read,
224 .write = rt2x00_eeprom_write,
225 .word_base = EEPROM_BASE,
226 .word_size = sizeof(u16),
227 .word_count = EEPROM_SIZE / sizeof(u16),
228 },
229 .bbp = {
230 .read = rt2500pci_bbp_read,
231 .write = rt2500pci_bbp_write,
232 .word_base = BBP_BASE,
233 .word_size = sizeof(u8),
234 .word_count = BBP_SIZE / sizeof(u8),
235 },
236 .rf = {
237 .read = rt2x00_rf_read,
238 .write = rt2500pci_rf_write,
239 .word_base = RF_BASE,
240 .word_size = sizeof(u32),
241 .word_count = RF_SIZE / sizeof(u32),
242 },
243 };
244 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
245
246 #ifdef CONFIG_RT2X00_LIB_RFKILL
247 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
248 {
249 u32 reg;
250
251 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
252 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
253 }
254 #else
255 #define rt2500pci_rfkill_poll NULL
256 #endif /* CONFIG_RT2X00_LIB_RFKILL */
257
258 #ifdef CONFIG_RT2X00_LIB_LEDS
259 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
260 enum led_brightness brightness)
261 {
262 struct rt2x00_led *led =
263 container_of(led_cdev, struct rt2x00_led, led_dev);
264 unsigned int enabled = brightness != LED_OFF;
265 u32 reg;
266
267 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
268
269 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
270 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
271 else if (led->type == LED_TYPE_ACTIVITY)
272 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
273
274 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
275 }
276
277 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
278 unsigned long *delay_on,
279 unsigned long *delay_off)
280 {
281 struct rt2x00_led *led =
282 container_of(led_cdev, struct rt2x00_led, led_dev);
283 u32 reg;
284
285 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
286 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
287 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
288 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
289
290 return 0;
291 }
292
293 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
294 struct rt2x00_led *led,
295 enum led_type type)
296 {
297 led->rt2x00dev = rt2x00dev;
298 led->type = type;
299 led->led_dev.brightness_set = rt2500pci_brightness_set;
300 led->led_dev.blink_set = rt2500pci_blink_set;
301 led->flags = LED_INITIALIZED;
302 }
303 #endif /* CONFIG_RT2X00_LIB_LEDS */
304
305 /*
306 * Configuration handlers.
307 */
308 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
309 const unsigned int filter_flags)
310 {
311 u32 reg;
312
313 /*
314 * Start configuration steps.
315 * Note that the version error will always be dropped
316 * and broadcast frames will always be accepted since
317 * there is no filter for it at this time.
318 */
319 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
320 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
321 !(filter_flags & FIF_FCSFAIL));
322 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
323 !(filter_flags & FIF_PLCPFAIL));
324 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
325 !(filter_flags & FIF_CONTROL));
326 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
327 !(filter_flags & FIF_PROMISC_IN_BSS));
328 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
329 !(filter_flags & FIF_PROMISC_IN_BSS) &&
330 !rt2x00dev->intf_ap_count);
331 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
332 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
333 !(filter_flags & FIF_ALLMULTI));
334 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
335 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
336 }
337
338 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
339 struct rt2x00_intf *intf,
340 struct rt2x00intf_conf *conf,
341 const unsigned int flags)
342 {
343 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
344 unsigned int bcn_preload;
345 u32 reg;
346
347 if (flags & CONFIG_UPDATE_TYPE) {
348 /*
349 * Enable beacon config
350 */
351 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
352 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
353 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
354 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
355 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
356
357 /*
358 * Enable synchronisation.
359 */
360 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
361 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
362 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
363 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
364 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
365 }
366
367 if (flags & CONFIG_UPDATE_MAC)
368 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
369 conf->mac, sizeof(conf->mac));
370
371 if (flags & CONFIG_UPDATE_BSSID)
372 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
373 conf->bssid, sizeof(conf->bssid));
374 }
375
376 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
377 struct rt2x00lib_erp *erp)
378 {
379 int preamble_mask;
380 u32 reg;
381
382 /*
383 * When short preamble is enabled, we should set bit 0x08
384 */
385 preamble_mask = erp->short_preamble << 3;
386
387 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
388 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
389 erp->ack_timeout);
390 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
391 erp->ack_consume_time);
392 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
393
394 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
395 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
396 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
397 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
398 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
399
400 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
401 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
402 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
403 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
404 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
405
406 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
407 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
408 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
409 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
410 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
411
412 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
413 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
414 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
415 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
416 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
417
418 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
419
420 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
421 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
422 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
423
424 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
425 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
426 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
427 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
428
429 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
430 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
431 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
432 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
433 }
434
435 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
436 struct antenna_setup *ant)
437 {
438 u32 reg;
439 u8 r14;
440 u8 r2;
441
442 /*
443 * We should never come here because rt2x00lib is supposed
444 * to catch this and send us the correct antenna explicitely.
445 */
446 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
447 ant->tx == ANTENNA_SW_DIVERSITY);
448
449 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
450 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
451 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
452
453 /*
454 * Configure the TX antenna.
455 */
456 switch (ant->tx) {
457 case ANTENNA_A:
458 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
459 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
460 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
461 break;
462 case ANTENNA_B:
463 default:
464 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
465 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
466 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
467 break;
468 }
469
470 /*
471 * Configure the RX antenna.
472 */
473 switch (ant->rx) {
474 case ANTENNA_A:
475 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
476 break;
477 case ANTENNA_B:
478 default:
479 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
480 break;
481 }
482
483 /*
484 * RT2525E and RT5222 need to flip TX I/Q
485 */
486 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
487 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
488 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
489 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
490 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
491
492 /*
493 * RT2525E does not need RX I/Q Flip.
494 */
495 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
496 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
497 } else {
498 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
499 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
500 }
501
502 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
503 rt2500pci_bbp_write(rt2x00dev, 14, r14);
504 rt2500pci_bbp_write(rt2x00dev, 2, r2);
505 }
506
507 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
508 struct rf_channel *rf, const int txpower)
509 {
510 u8 r70;
511
512 /*
513 * Set TXpower.
514 */
515 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
516
517 /*
518 * Switch on tuning bits.
519 * For RT2523 devices we do not need to update the R1 register.
520 */
521 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
522 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
523 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
524
525 /*
526 * For RT2525 we should first set the channel to half band higher.
527 */
528 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
529 static const u32 vals[] = {
530 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
531 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
532 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
533 0x00080d2e, 0x00080d3a
534 };
535
536 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
537 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
538 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
539 if (rf->rf4)
540 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
541 }
542
543 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
544 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
545 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
546 if (rf->rf4)
547 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
548
549 /*
550 * Channel 14 requires the Japan filter bit to be set.
551 */
552 r70 = 0x46;
553 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
554 rt2500pci_bbp_write(rt2x00dev, 70, r70);
555
556 msleep(1);
557
558 /*
559 * Switch off tuning bits.
560 * For RT2523 devices we do not need to update the R1 register.
561 */
562 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
563 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
564 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
565 }
566
567 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
568 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
569
570 /*
571 * Clear false CRC during channel switch.
572 */
573 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
574 }
575
576 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
577 const int txpower)
578 {
579 u32 rf3;
580
581 rt2x00_rf_read(rt2x00dev, 3, &rf3);
582 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
583 rt2500pci_rf_write(rt2x00dev, 3, rf3);
584 }
585
586 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00lib_conf *libconf)
588 {
589 u32 reg;
590
591 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
592 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
593 libconf->conf->long_frame_max_tx_count);
594 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
595 libconf->conf->short_frame_max_tx_count);
596 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
597 }
598
599 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
600 struct rt2x00lib_conf *libconf)
601 {
602 u32 reg;
603
604 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
605 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
606 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
607 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
608
609 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
610 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
611 libconf->conf->beacon_int * 16);
612 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
613 libconf->conf->beacon_int * 16);
614 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
615 }
616
617 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
618 struct rt2x00lib_conf *libconf,
619 const unsigned int flags)
620 {
621 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
622 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
623 libconf->conf->power_level);
624 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
625 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
626 rt2500pci_config_txpower(rt2x00dev,
627 libconf->conf->power_level);
628 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
629 rt2500pci_config_retry_limit(rt2x00dev, libconf);
630 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
631 rt2500pci_config_duration(rt2x00dev, libconf);
632 }
633
634 /*
635 * Link tuning
636 */
637 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
638 struct link_qual *qual)
639 {
640 u32 reg;
641
642 /*
643 * Update FCS error count from register.
644 */
645 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
646 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
647
648 /*
649 * Update False CCA count from register.
650 */
651 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
652 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
653 }
654
655 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
656 {
657 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
658 rt2x00dev->link.vgc_level = 0x48;
659 }
660
661 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
662 {
663 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
664 u8 r17;
665
666 /*
667 * To prevent collisions with MAC ASIC on chipsets
668 * up to version C the link tuning should halt after 20
669 * seconds while being associated.
670 */
671 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
672 rt2x00dev->intf_associated &&
673 rt2x00dev->link.count > 20)
674 return;
675
676 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
677
678 /*
679 * Chipset versions C and lower should directly continue
680 * to the dynamic CCA tuning. Chipset version D and higher
681 * should go straight to dynamic CCA tuning when they
682 * are not associated.
683 */
684 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
685 !rt2x00dev->intf_associated)
686 goto dynamic_cca_tune;
687
688 /*
689 * A too low RSSI will cause too much false CCA which will
690 * then corrupt the R17 tuning. To remidy this the tuning should
691 * be stopped (While making sure the R17 value will not exceed limits)
692 */
693 if (rssi < -80 && rt2x00dev->link.count > 20) {
694 if (r17 >= 0x41) {
695 r17 = rt2x00dev->link.vgc_level;
696 rt2500pci_bbp_write(rt2x00dev, 17, r17);
697 }
698 return;
699 }
700
701 /*
702 * Special big-R17 for short distance
703 */
704 if (rssi >= -58) {
705 if (r17 != 0x50)
706 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
707 return;
708 }
709
710 /*
711 * Special mid-R17 for middle distance
712 */
713 if (rssi >= -74) {
714 if (r17 != 0x41)
715 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
716 return;
717 }
718
719 /*
720 * Leave short or middle distance condition, restore r17
721 * to the dynamic tuning range.
722 */
723 if (r17 >= 0x41) {
724 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
725 return;
726 }
727
728 dynamic_cca_tune:
729
730 /*
731 * R17 is inside the dynamic tuning range,
732 * start tuning the link based on the false cca counter.
733 */
734 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
735 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
736 rt2x00dev->link.vgc_level = r17;
737 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
738 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
739 rt2x00dev->link.vgc_level = r17;
740 }
741 }
742
743 /*
744 * Initialization functions.
745 */
746 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
747 {
748 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
749 u32 word;
750
751 if (entry->queue->qid == QID_RX) {
752 rt2x00_desc_read(entry_priv->desc, 0, &word);
753
754 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
755 } else {
756 rt2x00_desc_read(entry_priv->desc, 0, &word);
757
758 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
759 rt2x00_get_field32(word, TXD_W0_VALID));
760 }
761 }
762
763 static void rt2500pci_clear_entry(struct queue_entry *entry)
764 {
765 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
766 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
767 u32 word;
768
769 if (entry->queue->qid == QID_RX) {
770 rt2x00_desc_read(entry_priv->desc, 1, &word);
771 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
772 rt2x00_desc_write(entry_priv->desc, 1, word);
773
774 rt2x00_desc_read(entry_priv->desc, 0, &word);
775 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
776 rt2x00_desc_write(entry_priv->desc, 0, word);
777 } else {
778 rt2x00_desc_read(entry_priv->desc, 0, &word);
779 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
780 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
781 rt2x00_desc_write(entry_priv->desc, 0, word);
782 }
783 }
784
785 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
786 {
787 struct queue_entry_priv_pci *entry_priv;
788 u32 reg;
789
790 /*
791 * Initialize registers.
792 */
793 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
794 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
795 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
796 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
797 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
798 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
799
800 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
801 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
802 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
803 entry_priv->desc_dma);
804 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
805
806 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
807 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
808 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
809 entry_priv->desc_dma);
810 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
811
812 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
813 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
814 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
815 entry_priv->desc_dma);
816 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
817
818 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
819 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
820 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
821 entry_priv->desc_dma);
822 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
823
824 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
825 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
826 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
827 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
828
829 entry_priv = rt2x00dev->rx->entries[0].priv_data;
830 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
831 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
832 entry_priv->desc_dma);
833 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
834
835 return 0;
836 }
837
838 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
839 {
840 u32 reg;
841
842 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
843 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
844 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
845 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
846
847 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
848 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
849 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
850 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
851 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
852
853 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
854 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
855 rt2x00dev->rx->data_size / 128);
856 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
857
858 /*
859 * Always use CWmin and CWmax set in descriptor.
860 */
861 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
862 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
863 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
864
865 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
866 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
867 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
868 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
869 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
870 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
871 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
872 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
873 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
874 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
875
876 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
877
878 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
879 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
880 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
881 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
882 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
883 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
884 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
885 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
886 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
887 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
888
889 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
890 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
891 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
892 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
893 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
894 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
895
896 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
897 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
898 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
899 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
900 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
901 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
902
903 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
904 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
905 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
906 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
907 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
908 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
909
910 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
911 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
912 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
913 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
914 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
915 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
916 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
917 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
918 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
919 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
920
921 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
922 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
923 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
924 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
925 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
926 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
927 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
928 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
929 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
930
931 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
932
933 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
934 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
935
936 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
937 return -EBUSY;
938
939 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
940 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
941
942 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
943 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
944 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
945
946 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
947 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
948 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
949 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
950 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
951 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
952 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
953 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
954
955 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
956
957 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
958
959 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
960 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
961 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
962 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
963 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
964
965 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
966 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
967 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
968 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
969
970 /*
971 * We must clear the FCS and FIFO error count.
972 * These registers are cleared on read,
973 * so we may pass a useless variable to store the value.
974 */
975 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
976 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
977
978 return 0;
979 }
980
981 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
982 {
983 unsigned int i;
984 u8 value;
985
986 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
987 rt2500pci_bbp_read(rt2x00dev, 0, &value);
988 if ((value != 0xff) && (value != 0x00))
989 return 0;
990 udelay(REGISTER_BUSY_DELAY);
991 }
992
993 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
994 return -EACCES;
995 }
996
997 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
998 {
999 unsigned int i;
1000 u16 eeprom;
1001 u8 reg_id;
1002 u8 value;
1003
1004 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1005 return -EACCES;
1006
1007 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1008 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1009 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1010 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1011 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1012 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1013 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1014 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1015 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1016 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1017 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1018 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1019 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1020 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1021 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1022 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1023 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1024 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1025 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1026 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1027 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1028 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1029 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1030 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1031 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1032 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1033 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1034 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1035 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1036 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1037
1038 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1039 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1040
1041 if (eeprom != 0xffff && eeprom != 0x0000) {
1042 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1043 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1044 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1045 }
1046 }
1047
1048 return 0;
1049 }
1050
1051 /*
1052 * Device state switch handlers.
1053 */
1054 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1055 enum dev_state state)
1056 {
1057 u32 reg;
1058
1059 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1060 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1061 (state == STATE_RADIO_RX_OFF) ||
1062 (state == STATE_RADIO_RX_OFF_LINK));
1063 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1064 }
1065
1066 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1067 enum dev_state state)
1068 {
1069 int mask = (state == STATE_RADIO_IRQ_OFF);
1070 u32 reg;
1071
1072 /*
1073 * When interrupts are being enabled, the interrupt registers
1074 * should clear the register to assure a clean state.
1075 */
1076 if (state == STATE_RADIO_IRQ_ON) {
1077 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1078 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1079 }
1080
1081 /*
1082 * Only toggle the interrupts bits we are going to use.
1083 * Non-checked interrupt bits are disabled by default.
1084 */
1085 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1086 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1087 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1088 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1089 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1090 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1091 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1092 }
1093
1094 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1095 {
1096 /*
1097 * Initialize all registers.
1098 */
1099 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1100 rt2500pci_init_registers(rt2x00dev) ||
1101 rt2500pci_init_bbp(rt2x00dev)))
1102 return -EIO;
1103
1104 return 0;
1105 }
1106
1107 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1108 {
1109 u32 reg;
1110
1111 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1112
1113 /*
1114 * Disable synchronisation.
1115 */
1116 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1117
1118 /*
1119 * Cancel RX and TX.
1120 */
1121 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1122 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1123 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1124 }
1125
1126 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1127 enum dev_state state)
1128 {
1129 u32 reg;
1130 unsigned int i;
1131 char put_to_sleep;
1132 char bbp_state;
1133 char rf_state;
1134
1135 put_to_sleep = (state != STATE_AWAKE);
1136
1137 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1138 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1139 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1140 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1141 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1142 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1143
1144 /*
1145 * Device is not guaranteed to be in the requested state yet.
1146 * We must wait until the register indicates that the
1147 * device has entered the correct state.
1148 */
1149 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1150 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1151 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1152 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1153 if (bbp_state == state && rf_state == state)
1154 return 0;
1155 msleep(10);
1156 }
1157
1158 return -EBUSY;
1159 }
1160
1161 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1162 enum dev_state state)
1163 {
1164 int retval = 0;
1165
1166 switch (state) {
1167 case STATE_RADIO_ON:
1168 retval = rt2500pci_enable_radio(rt2x00dev);
1169 break;
1170 case STATE_RADIO_OFF:
1171 rt2500pci_disable_radio(rt2x00dev);
1172 break;
1173 case STATE_RADIO_RX_ON:
1174 case STATE_RADIO_RX_ON_LINK:
1175 case STATE_RADIO_RX_OFF:
1176 case STATE_RADIO_RX_OFF_LINK:
1177 rt2500pci_toggle_rx(rt2x00dev, state);
1178 break;
1179 case STATE_RADIO_IRQ_ON:
1180 case STATE_RADIO_IRQ_OFF:
1181 rt2500pci_toggle_irq(rt2x00dev, state);
1182 break;
1183 case STATE_DEEP_SLEEP:
1184 case STATE_SLEEP:
1185 case STATE_STANDBY:
1186 case STATE_AWAKE:
1187 retval = rt2500pci_set_state(rt2x00dev, state);
1188 break;
1189 default:
1190 retval = -ENOTSUPP;
1191 break;
1192 }
1193
1194 if (unlikely(retval))
1195 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1196 state, retval);
1197
1198 return retval;
1199 }
1200
1201 /*
1202 * TX descriptor initialization
1203 */
1204 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1205 struct sk_buff *skb,
1206 struct txentry_desc *txdesc)
1207 {
1208 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1209 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1210 __le32 *txd = skbdesc->desc;
1211 u32 word;
1212
1213 /*
1214 * Start writing the descriptor words.
1215 */
1216 rt2x00_desc_read(entry_priv->desc, 1, &word);
1217 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1218 rt2x00_desc_write(entry_priv->desc, 1, word);
1219
1220 rt2x00_desc_read(txd, 2, &word);
1221 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1222 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1223 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1224 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1225 rt2x00_desc_write(txd, 2, word);
1226
1227 rt2x00_desc_read(txd, 3, &word);
1228 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1229 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1230 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1231 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1232 rt2x00_desc_write(txd, 3, word);
1233
1234 rt2x00_desc_read(txd, 10, &word);
1235 rt2x00_set_field32(&word, TXD_W10_RTS,
1236 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1237 rt2x00_desc_write(txd, 10, word);
1238
1239 rt2x00_desc_read(txd, 0, &word);
1240 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1241 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1242 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1243 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1244 rt2x00_set_field32(&word, TXD_W0_ACK,
1245 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1246 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1247 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1248 rt2x00_set_field32(&word, TXD_W0_OFDM,
1249 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1250 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1251 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1252 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1253 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1254 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1255 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1256 rt2x00_desc_write(txd, 0, word);
1257 }
1258
1259 /*
1260 * TX data initialization
1261 */
1262 static void rt2500pci_write_beacon(struct queue_entry *entry)
1263 {
1264 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1265 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1266 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1267 u32 word;
1268 u32 reg;
1269
1270 /*
1271 * Disable beaconing while we are reloading the beacon data,
1272 * otherwise we might be sending out invalid data.
1273 */
1274 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1275 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1276 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1277 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1278 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1279
1280 /*
1281 * Replace rt2x00lib allocated descriptor with the
1282 * pointer to the _real_ hardware descriptor.
1283 * After that, map the beacon to DMA and update the
1284 * descriptor.
1285 */
1286 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1287 skbdesc->desc = entry_priv->desc;
1288
1289 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1290
1291 rt2x00_desc_read(entry_priv->desc, 1, &word);
1292 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1293 rt2x00_desc_write(entry_priv->desc, 1, word);
1294 }
1295
1296 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1297 const enum data_queue_qid queue)
1298 {
1299 u32 reg;
1300
1301 if (queue == QID_BEACON) {
1302 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1303 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1304 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1305 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1306 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1307 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1308 }
1309 return;
1310 }
1311
1312 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1313 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1314 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1315 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1316 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1317 }
1318
1319 /*
1320 * RX control handlers
1321 */
1322 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1323 struct rxdone_entry_desc *rxdesc)
1324 {
1325 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1326 u32 word0;
1327 u32 word2;
1328
1329 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1330 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1331
1332 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1333 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1334 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1335 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1336
1337 /*
1338 * Obtain the status about this packet.
1339 * When frame was received with an OFDM bitrate,
1340 * the signal is the PLCP value. If it was received with
1341 * a CCK bitrate the signal is the rate in 100kbit/s.
1342 */
1343 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1344 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1345 entry->queue->rt2x00dev->rssi_offset;
1346 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1347
1348 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1349 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1350 else
1351 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1352 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1353 rxdesc->dev_flags |= RXDONE_MY_BSS;
1354 }
1355
1356 /*
1357 * Interrupt functions.
1358 */
1359 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1360 const enum data_queue_qid queue_idx)
1361 {
1362 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1363 struct queue_entry_priv_pci *entry_priv;
1364 struct queue_entry *entry;
1365 struct txdone_entry_desc txdesc;
1366 u32 word;
1367
1368 while (!rt2x00queue_empty(queue)) {
1369 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1370 entry_priv = entry->priv_data;
1371 rt2x00_desc_read(entry_priv->desc, 0, &word);
1372
1373 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1374 !rt2x00_get_field32(word, TXD_W0_VALID))
1375 break;
1376
1377 /*
1378 * Obtain the status about this packet.
1379 */
1380 txdesc.flags = 0;
1381 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1382 case 0: /* Success */
1383 case 1: /* Success with retry */
1384 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1385 break;
1386 case 2: /* Failure, excessive retries */
1387 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1388 /* Don't break, this is a failed frame! */
1389 default: /* Failure */
1390 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1391 }
1392 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1393
1394 rt2x00lib_txdone(entry, &txdesc);
1395 }
1396 }
1397
1398 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1399 {
1400 struct rt2x00_dev *rt2x00dev = dev_instance;
1401 u32 reg;
1402
1403 /*
1404 * Get the interrupt sources & saved to local variable.
1405 * Write register value back to clear pending interrupts.
1406 */
1407 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1408 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1409
1410 if (!reg)
1411 return IRQ_NONE;
1412
1413 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1414 return IRQ_HANDLED;
1415
1416 /*
1417 * Handle interrupts, walk through all bits
1418 * and run the tasks, the bits are checked in order of
1419 * priority.
1420 */
1421
1422 /*
1423 * 1 - Beacon timer expired interrupt.
1424 */
1425 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1426 rt2x00lib_beacondone(rt2x00dev);
1427
1428 /*
1429 * 2 - Rx ring done interrupt.
1430 */
1431 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1432 rt2x00pci_rxdone(rt2x00dev);
1433
1434 /*
1435 * 3 - Atim ring transmit done interrupt.
1436 */
1437 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1438 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1439
1440 /*
1441 * 4 - Priority ring transmit done interrupt.
1442 */
1443 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1444 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1445
1446 /*
1447 * 5 - Tx ring transmit done interrupt.
1448 */
1449 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1450 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1451
1452 return IRQ_HANDLED;
1453 }
1454
1455 /*
1456 * Device probe functions.
1457 */
1458 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1459 {
1460 struct eeprom_93cx6 eeprom;
1461 u32 reg;
1462 u16 word;
1463 u8 *mac;
1464
1465 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1466
1467 eeprom.data = rt2x00dev;
1468 eeprom.register_read = rt2500pci_eepromregister_read;
1469 eeprom.register_write = rt2500pci_eepromregister_write;
1470 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1471 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1472 eeprom.reg_data_in = 0;
1473 eeprom.reg_data_out = 0;
1474 eeprom.reg_data_clock = 0;
1475 eeprom.reg_chip_select = 0;
1476
1477 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1478 EEPROM_SIZE / sizeof(u16));
1479
1480 /*
1481 * Start validation of the data that has been read.
1482 */
1483 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1484 if (!is_valid_ether_addr(mac)) {
1485 random_ether_addr(mac);
1486 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1487 }
1488
1489 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1490 if (word == 0xffff) {
1491 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1492 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1493 ANTENNA_SW_DIVERSITY);
1494 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1495 ANTENNA_SW_DIVERSITY);
1496 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1497 LED_MODE_DEFAULT);
1498 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1499 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1500 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1501 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1502 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1503 }
1504
1505 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1506 if (word == 0xffff) {
1507 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1508 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1509 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1510 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1511 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1512 }
1513
1514 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1515 if (word == 0xffff) {
1516 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1517 DEFAULT_RSSI_OFFSET);
1518 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1519 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1520 }
1521
1522 return 0;
1523 }
1524
1525 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1526 {
1527 u32 reg;
1528 u16 value;
1529 u16 eeprom;
1530
1531 /*
1532 * Read EEPROM word for configuration.
1533 */
1534 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1535
1536 /*
1537 * Identify RF chipset.
1538 */
1539 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1540 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1541 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1542
1543 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1544 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1545 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1546 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1547 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1548 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1549 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1550 return -ENODEV;
1551 }
1552
1553 /*
1554 * Identify default antenna configuration.
1555 */
1556 rt2x00dev->default_ant.tx =
1557 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1558 rt2x00dev->default_ant.rx =
1559 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1560
1561 /*
1562 * Store led mode, for correct led behaviour.
1563 */
1564 #ifdef CONFIG_RT2X00_LIB_LEDS
1565 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1566
1567 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1568 if (value == LED_MODE_TXRX_ACTIVITY)
1569 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1570 LED_TYPE_ACTIVITY);
1571 #endif /* CONFIG_RT2X00_LIB_LEDS */
1572
1573 /*
1574 * Detect if this device has an hardware controlled radio.
1575 */
1576 #ifdef CONFIG_RT2X00_LIB_RFKILL
1577 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1578 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1579 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1580
1581 /*
1582 * Check if the BBP tuning should be enabled.
1583 */
1584 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1585
1586 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1587 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1588
1589 /*
1590 * Read the RSSI <-> dBm offset information.
1591 */
1592 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1593 rt2x00dev->rssi_offset =
1594 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1595
1596 return 0;
1597 }
1598
1599 /*
1600 * RF value list for RF2522
1601 * Supports: 2.4 GHz
1602 */
1603 static const struct rf_channel rf_vals_bg_2522[] = {
1604 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1605 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1606 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1607 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1608 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1609 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1610 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1611 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1612 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1613 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1614 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1615 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1616 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1617 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1618 };
1619
1620 /*
1621 * RF value list for RF2523
1622 * Supports: 2.4 GHz
1623 */
1624 static const struct rf_channel rf_vals_bg_2523[] = {
1625 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1626 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1627 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1628 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1629 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1630 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1631 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1632 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1633 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1634 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1635 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1636 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1637 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1638 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1639 };
1640
1641 /*
1642 * RF value list for RF2524
1643 * Supports: 2.4 GHz
1644 */
1645 static const struct rf_channel rf_vals_bg_2524[] = {
1646 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1647 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1648 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1649 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1650 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1651 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1652 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1653 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1654 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1655 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1656 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1657 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1658 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1659 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1660 };
1661
1662 /*
1663 * RF value list for RF2525
1664 * Supports: 2.4 GHz
1665 */
1666 static const struct rf_channel rf_vals_bg_2525[] = {
1667 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1668 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1669 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1670 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1671 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1672 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1673 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1674 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1675 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1676 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1677 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1678 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1679 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1680 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1681 };
1682
1683 /*
1684 * RF value list for RF2525e
1685 * Supports: 2.4 GHz
1686 */
1687 static const struct rf_channel rf_vals_bg_2525e[] = {
1688 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1689 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1690 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1691 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1692 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1693 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1694 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1695 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1696 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1697 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1698 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1699 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1700 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1701 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1702 };
1703
1704 /*
1705 * RF value list for RF5222
1706 * Supports: 2.4 GHz & 5.2 GHz
1707 */
1708 static const struct rf_channel rf_vals_5222[] = {
1709 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1710 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1711 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1712 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1713 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1714 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1715 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1716 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1717 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1718 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1719 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1720 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1721 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1722 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1723
1724 /* 802.11 UNI / HyperLan 2 */
1725 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1726 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1727 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1728 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1729 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1730 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1731 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1732 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1733
1734 /* 802.11 HyperLan 2 */
1735 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1736 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1737 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1738 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1739 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1740 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1741 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1742 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1743 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1744 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1745
1746 /* 802.11 UNII */
1747 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1748 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1749 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1750 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1751 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1752 };
1753
1754 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1755 {
1756 struct hw_mode_spec *spec = &rt2x00dev->spec;
1757 struct channel_info *info;
1758 char *tx_power;
1759 unsigned int i;
1760
1761 /*
1762 * Initialize all hw fields.
1763 */
1764 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1765 IEEE80211_HW_SIGNAL_DBM;
1766
1767 rt2x00dev->hw->extra_tx_headroom = 0;
1768
1769 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1770 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1771 rt2x00_eeprom_addr(rt2x00dev,
1772 EEPROM_MAC_ADDR_0));
1773
1774 /*
1775 * Initialize hw_mode information.
1776 */
1777 spec->supported_bands = SUPPORT_BAND_2GHZ;
1778 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1779
1780 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1781 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1782 spec->channels = rf_vals_bg_2522;
1783 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1784 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1785 spec->channels = rf_vals_bg_2523;
1786 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1787 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1788 spec->channels = rf_vals_bg_2524;
1789 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1790 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1791 spec->channels = rf_vals_bg_2525;
1792 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1793 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1794 spec->channels = rf_vals_bg_2525e;
1795 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1796 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1797 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1798 spec->channels = rf_vals_5222;
1799 }
1800
1801 /*
1802 * Create channel information array
1803 */
1804 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1805 if (!info)
1806 return -ENOMEM;
1807
1808 spec->channels_info = info;
1809
1810 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1811 for (i = 0; i < 14; i++)
1812 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1813
1814 if (spec->num_channels > 14) {
1815 for (i = 14; i < spec->num_channels; i++)
1816 info[i].tx_power1 = DEFAULT_TXPOWER;
1817 }
1818
1819 return 0;
1820 }
1821
1822 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1823 {
1824 int retval;
1825
1826 /*
1827 * Allocate eeprom data.
1828 */
1829 retval = rt2500pci_validate_eeprom(rt2x00dev);
1830 if (retval)
1831 return retval;
1832
1833 retval = rt2500pci_init_eeprom(rt2x00dev);
1834 if (retval)
1835 return retval;
1836
1837 /*
1838 * Initialize hw specifications.
1839 */
1840 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1841 if (retval)
1842 return retval;
1843
1844 /*
1845 * This device requires the atim queue and DMA-mapped skbs.
1846 */
1847 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1848 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1849
1850 /*
1851 * Set the rssi offset.
1852 */
1853 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1854
1855 return 0;
1856 }
1857
1858 /*
1859 * IEEE80211 stack callback functions.
1860 */
1861 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1862 {
1863 struct rt2x00_dev *rt2x00dev = hw->priv;
1864 u64 tsf;
1865 u32 reg;
1866
1867 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1868 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1869 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1870 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1871
1872 return tsf;
1873 }
1874
1875 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1876 {
1877 struct rt2x00_dev *rt2x00dev = hw->priv;
1878 u32 reg;
1879
1880 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1881 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1882 }
1883
1884 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1885 .tx = rt2x00mac_tx,
1886 .start = rt2x00mac_start,
1887 .stop = rt2x00mac_stop,
1888 .add_interface = rt2x00mac_add_interface,
1889 .remove_interface = rt2x00mac_remove_interface,
1890 .config = rt2x00mac_config,
1891 .config_interface = rt2x00mac_config_interface,
1892 .configure_filter = rt2x00mac_configure_filter,
1893 .get_stats = rt2x00mac_get_stats,
1894 .bss_info_changed = rt2x00mac_bss_info_changed,
1895 .conf_tx = rt2x00mac_conf_tx,
1896 .get_tx_stats = rt2x00mac_get_tx_stats,
1897 .get_tsf = rt2500pci_get_tsf,
1898 .tx_last_beacon = rt2500pci_tx_last_beacon,
1899 };
1900
1901 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1902 .irq_handler = rt2500pci_interrupt,
1903 .probe_hw = rt2500pci_probe_hw,
1904 .initialize = rt2x00pci_initialize,
1905 .uninitialize = rt2x00pci_uninitialize,
1906 .get_entry_state = rt2500pci_get_entry_state,
1907 .clear_entry = rt2500pci_clear_entry,
1908 .set_device_state = rt2500pci_set_device_state,
1909 .rfkill_poll = rt2500pci_rfkill_poll,
1910 .link_stats = rt2500pci_link_stats,
1911 .reset_tuner = rt2500pci_reset_tuner,
1912 .link_tuner = rt2500pci_link_tuner,
1913 .write_tx_desc = rt2500pci_write_tx_desc,
1914 .write_tx_data = rt2x00pci_write_tx_data,
1915 .write_beacon = rt2500pci_write_beacon,
1916 .kick_tx_queue = rt2500pci_kick_tx_queue,
1917 .fill_rxdone = rt2500pci_fill_rxdone,
1918 .config_filter = rt2500pci_config_filter,
1919 .config_intf = rt2500pci_config_intf,
1920 .config_erp = rt2500pci_config_erp,
1921 .config_ant = rt2500pci_config_ant,
1922 .config = rt2500pci_config,
1923 };
1924
1925 static const struct data_queue_desc rt2500pci_queue_rx = {
1926 .entry_num = RX_ENTRIES,
1927 .data_size = DATA_FRAME_SIZE,
1928 .desc_size = RXD_DESC_SIZE,
1929 .priv_size = sizeof(struct queue_entry_priv_pci),
1930 };
1931
1932 static const struct data_queue_desc rt2500pci_queue_tx = {
1933 .entry_num = TX_ENTRIES,
1934 .data_size = DATA_FRAME_SIZE,
1935 .desc_size = TXD_DESC_SIZE,
1936 .priv_size = sizeof(struct queue_entry_priv_pci),
1937 };
1938
1939 static const struct data_queue_desc rt2500pci_queue_bcn = {
1940 .entry_num = BEACON_ENTRIES,
1941 .data_size = MGMT_FRAME_SIZE,
1942 .desc_size = TXD_DESC_SIZE,
1943 .priv_size = sizeof(struct queue_entry_priv_pci),
1944 };
1945
1946 static const struct data_queue_desc rt2500pci_queue_atim = {
1947 .entry_num = ATIM_ENTRIES,
1948 .data_size = DATA_FRAME_SIZE,
1949 .desc_size = TXD_DESC_SIZE,
1950 .priv_size = sizeof(struct queue_entry_priv_pci),
1951 };
1952
1953 static const struct rt2x00_ops rt2500pci_ops = {
1954 .name = KBUILD_MODNAME,
1955 .max_sta_intf = 1,
1956 .max_ap_intf = 1,
1957 .eeprom_size = EEPROM_SIZE,
1958 .rf_size = RF_SIZE,
1959 .tx_queues = NUM_TX_QUEUES,
1960 .rx = &rt2500pci_queue_rx,
1961 .tx = &rt2500pci_queue_tx,
1962 .bcn = &rt2500pci_queue_bcn,
1963 .atim = &rt2500pci_queue_atim,
1964 .lib = &rt2500pci_rt2x00_ops,
1965 .hw = &rt2500pci_mac80211_ops,
1966 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1967 .debugfs = &rt2500pci_rt2x00debug,
1968 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1969 };
1970
1971 /*
1972 * RT2500pci module information.
1973 */
1974 static struct pci_device_id rt2500pci_device_table[] = {
1975 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1976 { 0, }
1977 };
1978
1979 MODULE_AUTHOR(DRV_PROJECT);
1980 MODULE_VERSION(DRV_VERSION);
1981 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1982 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1983 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1984 MODULE_LICENSE("GPL");
1985
1986 static struct pci_driver rt2500pci_driver = {
1987 .name = KBUILD_MODNAME,
1988 .id_table = rt2500pci_device_table,
1989 .probe = rt2x00pci_probe,
1990 .remove = __devexit_p(rt2x00pci_remove),
1991 .suspend = rt2x00pci_suspend,
1992 .resume = rt2x00pci_resume,
1993 };
1994
1995 static int __init rt2500pci_init(void)
1996 {
1997 return pci_register_driver(&rt2500pci_driver);
1998 }
1999
2000 static void __exit rt2500pci_exit(void)
2001 {
2002 pci_unregister_driver(&rt2500pci_driver);
2003 }
2004
2005 module_init(rt2500pci_init);
2006 module_exit(rt2500pci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree