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rt2x00: Fix race condition when using inderect registers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
blob78fca1bcc5447e13e08bf468189af3625ef068c0
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65 }
66
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
69 {
70 u32 reg;
71
72 mutex_lock(&rt2x00dev->csr_mutex);
73
74 /*
75 * Wait until the BBP becomes ready.
76 */
77 reg = rt2400pci_bbp_check(rt2x00dev);
78 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
79 goto exit_fail;
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91
92 mutex_unlock(&rt2x00dev->csr_mutex);
93
94 return;
95
96 exit_fail:
97 mutex_unlock(&rt2x00dev->csr_mutex);
98
99 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
100 }
101
102 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
103 const unsigned int word, u8 *value)
104 {
105 u32 reg;
106
107 mutex_lock(&rt2x00dev->csr_mutex);
108
109 /*
110 * Wait until the BBP becomes ready.
111 */
112 reg = rt2400pci_bbp_check(rt2x00dev);
113 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
114 goto exit_fail;
115
116 /*
117 * Write the request into the BBP.
118 */
119 reg = 0;
120 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
121 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
122 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
123
124 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
125
126 /*
127 * Wait until the BBP becomes ready.
128 */
129 reg = rt2400pci_bbp_check(rt2x00dev);
130 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
131 goto exit_fail;
132
133 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
134
135 mutex_unlock(&rt2x00dev->csr_mutex);
136
137 return;
138
139 exit_fail:
140 mutex_unlock(&rt2x00dev->csr_mutex);
141
142 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
143 *value = 0xff;
144 }
145
146 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
147 const unsigned int word, const u32 value)
148 {
149 u32 reg;
150 unsigned int i;
151
152 if (!word)
153 return;
154
155 mutex_lock(&rt2x00dev->csr_mutex);
156
157 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
158 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
159 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
160 goto rf_write;
161 udelay(REGISTER_BUSY_DELAY);
162 }
163
164 mutex_unlock(&rt2x00dev->csr_mutex);
165 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
166 return;
167
168 rf_write:
169 reg = 0;
170 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
171 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
172 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
173 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
174
175 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
176 rt2x00_rf_write(rt2x00dev, word, value);
177
178 mutex_unlock(&rt2x00dev->csr_mutex);
179 }
180
181 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
182 {
183 struct rt2x00_dev *rt2x00dev = eeprom->data;
184 u32 reg;
185
186 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
187
188 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
189 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
190 eeprom->reg_data_clock =
191 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
192 eeprom->reg_chip_select =
193 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
194 }
195
196 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
197 {
198 struct rt2x00_dev *rt2x00dev = eeprom->data;
199 u32 reg = 0;
200
201 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
202 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
203 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
204 !!eeprom->reg_data_clock);
205 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
206 !!eeprom->reg_chip_select);
207
208 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
209 }
210
211 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
212 static const struct rt2x00debug rt2400pci_rt2x00debug = {
213 .owner = THIS_MODULE,
214 .csr = {
215 .read = rt2x00pci_register_read,
216 .write = rt2x00pci_register_write,
217 .flags = RT2X00DEBUGFS_OFFSET,
218 .word_base = CSR_REG_BASE,
219 .word_size = sizeof(u32),
220 .word_count = CSR_REG_SIZE / sizeof(u32),
221 },
222 .eeprom = {
223 .read = rt2x00_eeprom_read,
224 .write = rt2x00_eeprom_write,
225 .word_base = EEPROM_BASE,
226 .word_size = sizeof(u16),
227 .word_count = EEPROM_SIZE / sizeof(u16),
228 },
229 .bbp = {
230 .read = rt2400pci_bbp_read,
231 .write = rt2400pci_bbp_write,
232 .word_base = BBP_BASE,
233 .word_size = sizeof(u8),
234 .word_count = BBP_SIZE / sizeof(u8),
235 },
236 .rf = {
237 .read = rt2x00_rf_read,
238 .write = rt2400pci_rf_write,
239 .word_base = RF_BASE,
240 .word_size = sizeof(u32),
241 .word_count = RF_SIZE / sizeof(u32),
242 },
243 };
244 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
245
246 #ifdef CONFIG_RT2X00_LIB_RFKILL
247 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
248 {
249 u32 reg;
250
251 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
252 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
253 }
254 #else
255 #define rt2400pci_rfkill_poll NULL
256 #endif /* CONFIG_RT2X00_LIB_RFKILL */
257
258 #ifdef CONFIG_RT2X00_LIB_LEDS
259 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
260 enum led_brightness brightness)
261 {
262 struct rt2x00_led *led =
263 container_of(led_cdev, struct rt2x00_led, led_dev);
264 unsigned int enabled = brightness != LED_OFF;
265 u32 reg;
266
267 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
268
269 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
270 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
271 else if (led->type == LED_TYPE_ACTIVITY)
272 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
273
274 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
275 }
276
277 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
278 unsigned long *delay_on,
279 unsigned long *delay_off)
280 {
281 struct rt2x00_led *led =
282 container_of(led_cdev, struct rt2x00_led, led_dev);
283 u32 reg;
284
285 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
286 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
287 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
288 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
289
290 return 0;
291 }
292
293 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
294 struct rt2x00_led *led,
295 enum led_type type)
296 {
297 led->rt2x00dev = rt2x00dev;
298 led->type = type;
299 led->led_dev.brightness_set = rt2400pci_brightness_set;
300 led->led_dev.blink_set = rt2400pci_blink_set;
301 led->flags = LED_INITIALIZED;
302 }
303 #endif /* CONFIG_RT2X00_LIB_LEDS */
304
305 /*
306 * Configuration handlers.
307 */
308 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
309 const unsigned int filter_flags)
310 {
311 u32 reg;
312
313 /*
314 * Start configuration steps.
315 * Note that the version error will always be dropped
316 * since there is no filter for it at this time.
317 */
318 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
319 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
320 !(filter_flags & FIF_FCSFAIL));
321 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
322 !(filter_flags & FIF_PLCPFAIL));
323 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
324 !(filter_flags & FIF_CONTROL));
325 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
326 !(filter_flags & FIF_PROMISC_IN_BSS));
327 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
328 !(filter_flags & FIF_PROMISC_IN_BSS) &&
329 !rt2x00dev->intf_ap_count);
330 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
331 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
332 }
333
334 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
335 struct rt2x00_intf *intf,
336 struct rt2x00intf_conf *conf,
337 const unsigned int flags)
338 {
339 unsigned int bcn_preload;
340 u32 reg;
341
342 if (flags & CONFIG_UPDATE_TYPE) {
343 /*
344 * Enable beacon config
345 */
346 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
347 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
348 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
349 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
350
351 /*
352 * Enable synchronisation.
353 */
354 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
355 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
356 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
357 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
358 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
359 }
360
361 if (flags & CONFIG_UPDATE_MAC)
362 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
363 conf->mac, sizeof(conf->mac));
364
365 if (flags & CONFIG_UPDATE_BSSID)
366 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
367 conf->bssid, sizeof(conf->bssid));
368 }
369
370 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
371 struct rt2x00lib_erp *erp)
372 {
373 int preamble_mask;
374 u32 reg;
375
376 /*
377 * When short preamble is enabled, we should set bit 0x08
378 */
379 preamble_mask = erp->short_preamble << 3;
380
381 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
382 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
383 erp->ack_timeout);
384 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
385 erp->ack_consume_time);
386 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
387
388 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
389 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
390 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
391 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
392 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
393
394 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
395 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
396 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
397 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
398 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
399
400 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
401 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
402 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
403 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
404 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
405
406 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
407 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
408 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
409 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
410 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
411
412 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
413
414 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
415 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
416 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
417
418 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
419 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
420 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
421 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
422
423 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
424 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
425 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
426 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
427 }
428
429 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
430 struct antenna_setup *ant)
431 {
432 u8 r1;
433 u8 r4;
434
435 /*
436 * We should never come here because rt2x00lib is supposed
437 * to catch this and send us the correct antenna explicitely.
438 */
439 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
440 ant->tx == ANTENNA_SW_DIVERSITY);
441
442 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
443 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
444
445 /*
446 * Configure the TX antenna.
447 */
448 switch (ant->tx) {
449 case ANTENNA_HW_DIVERSITY:
450 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
451 break;
452 case ANTENNA_A:
453 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
454 break;
455 case ANTENNA_B:
456 default:
457 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
458 break;
459 }
460
461 /*
462 * Configure the RX antenna.
463 */
464 switch (ant->rx) {
465 case ANTENNA_HW_DIVERSITY:
466 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
467 break;
468 case ANTENNA_A:
469 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
470 break;
471 case ANTENNA_B:
472 default:
473 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
474 break;
475 }
476
477 rt2400pci_bbp_write(rt2x00dev, 4, r4);
478 rt2400pci_bbp_write(rt2x00dev, 1, r1);
479 }
480
481 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
482 struct rf_channel *rf)
483 {
484 /*
485 * Switch on tuning bits.
486 */
487 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
488 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
489
490 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
491 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
492 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
493
494 /*
495 * RF2420 chipset don't need any additional actions.
496 */
497 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
498 return;
499
500 /*
501 * For the RT2421 chipsets we need to write an invalid
502 * reference clock rate to activate auto_tune.
503 * After that we set the value back to the correct channel.
504 */
505 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
506 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
507 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
508
509 msleep(1);
510
511 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
512 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
513 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
514
515 msleep(1);
516
517 /*
518 * Switch off tuning bits.
519 */
520 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
521 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
522
523 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
524 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
525
526 /*
527 * Clear false CRC during channel switch.
528 */
529 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
530 }
531
532 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
533 {
534 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
535 }
536
537 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
538 struct rt2x00lib_conf *libconf)
539 {
540 u32 reg;
541
542 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
543 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
544 libconf->conf->long_frame_max_tx_count);
545 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
546 libconf->conf->short_frame_max_tx_count);
547 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
548 }
549
550 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
551 struct rt2x00lib_conf *libconf)
552 {
553 u32 reg;
554
555 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
556 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
557 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
558 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
559
560 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
561 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
562 libconf->conf->beacon_int * 16);
563 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
564 libconf->conf->beacon_int * 16);
565 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
566 }
567
568 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
569 struct rt2x00lib_conf *libconf,
570 const unsigned int flags)
571 {
572 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
573 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
574 if (flags & IEEE80211_CONF_CHANGE_POWER)
575 rt2400pci_config_txpower(rt2x00dev,
576 libconf->conf->power_level);
577 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
578 rt2400pci_config_retry_limit(rt2x00dev, libconf);
579 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
580 rt2400pci_config_duration(rt2x00dev, libconf);
581 }
582
583 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
584 const int cw_min, const int cw_max)
585 {
586 u32 reg;
587
588 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
589 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
590 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
591 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
592 }
593
594 /*
595 * Link tuning
596 */
597 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
598 struct link_qual *qual)
599 {
600 u32 reg;
601 u8 bbp;
602
603 /*
604 * Update FCS error count from register.
605 */
606 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
607 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
608
609 /*
610 * Update False CCA count from register.
611 */
612 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
613 qual->false_cca = bbp;
614 }
615
616 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
617 {
618 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
619 rt2x00dev->link.vgc_level = 0x08;
620 }
621
622 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
623 {
624 u8 reg;
625
626 /*
627 * The link tuner should not run longer then 60 seconds,
628 * and should run once every 2 seconds.
629 */
630 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
631 return;
632
633 /*
634 * Base r13 link tuning on the false cca count.
635 */
636 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
637
638 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
639 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
640 rt2x00dev->link.vgc_level = reg;
641 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
642 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
643 rt2x00dev->link.vgc_level = reg;
644 }
645 }
646
647 /*
648 * Initialization functions.
649 */
650 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
651 {
652 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
653 u32 word;
654
655 if (entry->queue->qid == QID_RX) {
656 rt2x00_desc_read(entry_priv->desc, 0, &word);
657
658 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
659 } else {
660 rt2x00_desc_read(entry_priv->desc, 0, &word);
661
662 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
663 rt2x00_get_field32(word, TXD_W0_VALID));
664 }
665 }
666
667 static void rt2400pci_clear_entry(struct queue_entry *entry)
668 {
669 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
670 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
671 u32 word;
672
673 if (entry->queue->qid == QID_RX) {
674 rt2x00_desc_read(entry_priv->desc, 2, &word);
675 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
676 rt2x00_desc_write(entry_priv->desc, 2, word);
677
678 rt2x00_desc_read(entry_priv->desc, 1, &word);
679 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
680 rt2x00_desc_write(entry_priv->desc, 1, word);
681
682 rt2x00_desc_read(entry_priv->desc, 0, &word);
683 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
684 rt2x00_desc_write(entry_priv->desc, 0, word);
685 } else {
686 rt2x00_desc_read(entry_priv->desc, 0, &word);
687 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
688 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
689 rt2x00_desc_write(entry_priv->desc, 0, word);
690 }
691 }
692
693 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
694 {
695 struct queue_entry_priv_pci *entry_priv;
696 u32 reg;
697
698 /*
699 * Initialize registers.
700 */
701 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
702 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
703 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
704 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
705 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
706 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
707
708 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
709 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
710 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
711 entry_priv->desc_dma);
712 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
713
714 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
715 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
716 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
717 entry_priv->desc_dma);
718 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
719
720 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
721 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
722 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
723 entry_priv->desc_dma);
724 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
725
726 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
727 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
728 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
729 entry_priv->desc_dma);
730 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
731
732 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
733 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
734 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
735 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
736
737 entry_priv = rt2x00dev->rx->entries[0].priv_data;
738 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
739 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
740 entry_priv->desc_dma);
741 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
742
743 return 0;
744 }
745
746 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
747 {
748 u32 reg;
749
750 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
751 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
752 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
753 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
754
755 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
756 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
757 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
758 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
759 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
760
761 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
762 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
763 (rt2x00dev->rx->data_size / 128));
764 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
765
766 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
767 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
768 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
769 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
770 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
771 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
772 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
773 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
774 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
775 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
776
777 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
778
779 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
780 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
781 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
782 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
783 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
784 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
785
786 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
787 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
788 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
789 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
790 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
791 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
792 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
793 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
794
795 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
796
797 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
798 return -EBUSY;
799
800 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
801 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
802
803 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
804 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
805 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
806
807 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
808 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
809 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
810 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
811 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
812 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
813
814 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
815 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
816 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
817 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
818 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
819
820 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
821 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
822 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
823 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
824
825 /*
826 * We must clear the FCS and FIFO error count.
827 * These registers are cleared on read,
828 * so we may pass a useless variable to store the value.
829 */
830 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
831 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
832
833 return 0;
834 }
835
836 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
837 {
838 unsigned int i;
839 u8 value;
840
841 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
842 rt2400pci_bbp_read(rt2x00dev, 0, &value);
843 if ((value != 0xff) && (value != 0x00))
844 return 0;
845 udelay(REGISTER_BUSY_DELAY);
846 }
847
848 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
849 return -EACCES;
850 }
851
852 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
853 {
854 unsigned int i;
855 u16 eeprom;
856 u8 reg_id;
857 u8 value;
858
859 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
860 return -EACCES;
861
862 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
863 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
864 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
865 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
866 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
867 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
868 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
869 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
870 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
871 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
872 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
873 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
874 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
875 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
876
877 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
878 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
879
880 if (eeprom != 0xffff && eeprom != 0x0000) {
881 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
882 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
883 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
884 }
885 }
886
887 return 0;
888 }
889
890 /*
891 * Device state switch handlers.
892 */
893 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
894 enum dev_state state)
895 {
896 u32 reg;
897
898 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
899 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
900 (state == STATE_RADIO_RX_OFF) ||
901 (state == STATE_RADIO_RX_OFF_LINK));
902 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
903 }
904
905 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
906 enum dev_state state)
907 {
908 int mask = (state == STATE_RADIO_IRQ_OFF);
909 u32 reg;
910
911 /*
912 * When interrupts are being enabled, the interrupt registers
913 * should clear the register to assure a clean state.
914 */
915 if (state == STATE_RADIO_IRQ_ON) {
916 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
917 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
918 }
919
920 /*
921 * Only toggle the interrupts bits we are going to use.
922 * Non-checked interrupt bits are disabled by default.
923 */
924 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
925 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
926 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
927 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
928 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
929 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
930 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
931 }
932
933 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
934 {
935 /*
936 * Initialize all registers.
937 */
938 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
939 rt2400pci_init_registers(rt2x00dev) ||
940 rt2400pci_init_bbp(rt2x00dev)))
941 return -EIO;
942
943 return 0;
944 }
945
946 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
947 {
948 u32 reg;
949
950 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
951
952 /*
953 * Disable synchronisation.
954 */
955 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
956
957 /*
958 * Cancel RX and TX.
959 */
960 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
961 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
962 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
963 }
964
965 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
966 enum dev_state state)
967 {
968 u32 reg;
969 unsigned int i;
970 char put_to_sleep;
971 char bbp_state;
972 char rf_state;
973
974 put_to_sleep = (state != STATE_AWAKE);
975
976 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
977 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
978 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
979 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
980 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
981 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
982
983 /*
984 * Device is not guaranteed to be in the requested state yet.
985 * We must wait until the register indicates that the
986 * device has entered the correct state.
987 */
988 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
989 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
990 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
991 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
992 if (bbp_state == state && rf_state == state)
993 return 0;
994 msleep(10);
995 }
996
997 return -EBUSY;
998 }
999
1000 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1001 enum dev_state state)
1002 {
1003 int retval = 0;
1004
1005 switch (state) {
1006 case STATE_RADIO_ON:
1007 retval = rt2400pci_enable_radio(rt2x00dev);
1008 break;
1009 case STATE_RADIO_OFF:
1010 rt2400pci_disable_radio(rt2x00dev);
1011 break;
1012 case STATE_RADIO_RX_ON:
1013 case STATE_RADIO_RX_ON_LINK:
1014 case STATE_RADIO_RX_OFF:
1015 case STATE_RADIO_RX_OFF_LINK:
1016 rt2400pci_toggle_rx(rt2x00dev, state);
1017 break;
1018 case STATE_RADIO_IRQ_ON:
1019 case STATE_RADIO_IRQ_OFF:
1020 rt2400pci_toggle_irq(rt2x00dev, state);
1021 break;
1022 case STATE_DEEP_SLEEP:
1023 case STATE_SLEEP:
1024 case STATE_STANDBY:
1025 case STATE_AWAKE:
1026 retval = rt2400pci_set_state(rt2x00dev, state);
1027 break;
1028 default:
1029 retval = -ENOTSUPP;
1030 break;
1031 }
1032
1033 if (unlikely(retval))
1034 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1035 state, retval);
1036
1037 return retval;
1038 }
1039
1040 /*
1041 * TX descriptor initialization
1042 */
1043 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1044 struct sk_buff *skb,
1045 struct txentry_desc *txdesc)
1046 {
1047 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1048 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1049 __le32 *txd = skbdesc->desc;
1050 u32 word;
1051
1052 /*
1053 * Start writing the descriptor words.
1054 */
1055 rt2x00_desc_read(entry_priv->desc, 1, &word);
1056 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1057 rt2x00_desc_write(entry_priv->desc, 1, word);
1058
1059 rt2x00_desc_read(txd, 2, &word);
1060 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1061 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1062 rt2x00_desc_write(txd, 2, word);
1063
1064 rt2x00_desc_read(txd, 3, &word);
1065 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1066 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1067 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1068 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1069 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1070 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1071 rt2x00_desc_write(txd, 3, word);
1072
1073 rt2x00_desc_read(txd, 4, &word);
1074 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1075 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1076 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1077 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1078 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1079 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1080 rt2x00_desc_write(txd, 4, word);
1081
1082 rt2x00_desc_read(txd, 0, &word);
1083 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1084 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1085 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1086 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1087 rt2x00_set_field32(&word, TXD_W0_ACK,
1088 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1089 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1090 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1091 rt2x00_set_field32(&word, TXD_W0_RTS,
1092 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1093 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1094 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1095 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1096 rt2x00_desc_write(txd, 0, word);
1097 }
1098
1099 /*
1100 * TX data initialization
1101 */
1102 static void rt2400pci_write_beacon(struct queue_entry *entry)
1103 {
1104 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1105 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1106 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1107 u32 word;
1108 u32 reg;
1109
1110 /*
1111 * Disable beaconing while we are reloading the beacon data,
1112 * otherwise we might be sending out invalid data.
1113 */
1114 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1115 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1116 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1117 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1118 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1119
1120 /*
1121 * Replace rt2x00lib allocated descriptor with the
1122 * pointer to the _real_ hardware descriptor.
1123 * After that, map the beacon to DMA and update the
1124 * descriptor.
1125 */
1126 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1127 skbdesc->desc = entry_priv->desc;
1128
1129 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1130
1131 rt2x00_desc_read(entry_priv->desc, 1, &word);
1132 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1133 rt2x00_desc_write(entry_priv->desc, 1, word);
1134 }
1135
1136 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1137 const enum data_queue_qid queue)
1138 {
1139 u32 reg;
1140
1141 if (queue == QID_BEACON) {
1142 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1143 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1144 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1145 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1146 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1147 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1148 }
1149 return;
1150 }
1151
1152 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1153 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1154 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1155 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1156 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1157 }
1158
1159 /*
1160 * RX control handlers
1161 */
1162 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1163 struct rxdone_entry_desc *rxdesc)
1164 {
1165 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1166 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1167 u32 word0;
1168 u32 word2;
1169 u32 word3;
1170 u32 word4;
1171 u64 tsf;
1172 u32 rx_low;
1173 u32 rx_high;
1174
1175 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1176 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1177 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1178 rt2x00_desc_read(entry_priv->desc, 4, &word4);
1179
1180 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1181 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1182 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1183 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1184
1185 /*
1186 * We only get the lower 32bits from the timestamp,
1187 * to get the full 64bits we must complement it with
1188 * the timestamp from get_tsf().
1189 * Note that when a wraparound of the lower 32bits
1190 * has occurred between the frame arrival and the get_tsf()
1191 * call, we must decrease the higher 32bits with 1 to get
1192 * to correct value.
1193 */
1194 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1195 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1196 rx_high = upper_32_bits(tsf);
1197
1198 if ((u32)tsf <= rx_low)
1199 rx_high--;
1200
1201 /*
1202 * Obtain the status about this packet.
1203 * The signal is the PLCP value, and needs to be stripped
1204 * of the preamble bit (0x08).
1205 */
1206 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1207 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1208 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1209 entry->queue->rt2x00dev->rssi_offset;
1210 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1211
1212 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1213 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1214 rxdesc->dev_flags |= RXDONE_MY_BSS;
1215 }
1216
1217 /*
1218 * Interrupt functions.
1219 */
1220 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1221 const enum data_queue_qid queue_idx)
1222 {
1223 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1224 struct queue_entry_priv_pci *entry_priv;
1225 struct queue_entry *entry;
1226 struct txdone_entry_desc txdesc;
1227 u32 word;
1228
1229 while (!rt2x00queue_empty(queue)) {
1230 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1231 entry_priv = entry->priv_data;
1232 rt2x00_desc_read(entry_priv->desc, 0, &word);
1233
1234 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1235 !rt2x00_get_field32(word, TXD_W0_VALID))
1236 break;
1237
1238 /*
1239 * Obtain the status about this packet.
1240 */
1241 txdesc.flags = 0;
1242 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1243 case 0: /* Success */
1244 case 1: /* Success with retry */
1245 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1246 break;
1247 case 2: /* Failure, excessive retries */
1248 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1249 /* Don't break, this is a failed frame! */
1250 default: /* Failure */
1251 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1252 }
1253 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1254
1255 rt2x00lib_txdone(entry, &txdesc);
1256 }
1257 }
1258
1259 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1260 {
1261 struct rt2x00_dev *rt2x00dev = dev_instance;
1262 u32 reg;
1263
1264 /*
1265 * Get the interrupt sources & saved to local variable.
1266 * Write register value back to clear pending interrupts.
1267 */
1268 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1269 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1270
1271 if (!reg)
1272 return IRQ_NONE;
1273
1274 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1275 return IRQ_HANDLED;
1276
1277 /*
1278 * Handle interrupts, walk through all bits
1279 * and run the tasks, the bits are checked in order of
1280 * priority.
1281 */
1282
1283 /*
1284 * 1 - Beacon timer expired interrupt.
1285 */
1286 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1287 rt2x00lib_beacondone(rt2x00dev);
1288
1289 /*
1290 * 2 - Rx ring done interrupt.
1291 */
1292 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1293 rt2x00pci_rxdone(rt2x00dev);
1294
1295 /*
1296 * 3 - Atim ring transmit done interrupt.
1297 */
1298 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1299 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1300
1301 /*
1302 * 4 - Priority ring transmit done interrupt.
1303 */
1304 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1305 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1306
1307 /*
1308 * 5 - Tx ring transmit done interrupt.
1309 */
1310 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1311 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1312
1313 return IRQ_HANDLED;
1314 }
1315
1316 /*
1317 * Device probe functions.
1318 */
1319 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1320 {
1321 struct eeprom_93cx6 eeprom;
1322 u32 reg;
1323 u16 word;
1324 u8 *mac;
1325
1326 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1327
1328 eeprom.data = rt2x00dev;
1329 eeprom.register_read = rt2400pci_eepromregister_read;
1330 eeprom.register_write = rt2400pci_eepromregister_write;
1331 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1332 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1333 eeprom.reg_data_in = 0;
1334 eeprom.reg_data_out = 0;
1335 eeprom.reg_data_clock = 0;
1336 eeprom.reg_chip_select = 0;
1337
1338 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1339 EEPROM_SIZE / sizeof(u16));
1340
1341 /*
1342 * Start validation of the data that has been read.
1343 */
1344 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1345 if (!is_valid_ether_addr(mac)) {
1346 random_ether_addr(mac);
1347 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1348 }
1349
1350 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1351 if (word == 0xffff) {
1352 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1353 return -EINVAL;
1354 }
1355
1356 return 0;
1357 }
1358
1359 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1360 {
1361 u32 reg;
1362 u16 value;
1363 u16 eeprom;
1364
1365 /*
1366 * Read EEPROM word for configuration.
1367 */
1368 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1369
1370 /*
1371 * Identify RF chipset.
1372 */
1373 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1374 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1375 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1376
1377 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1378 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1379 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1380 return -ENODEV;
1381 }
1382
1383 /*
1384 * Identify default antenna configuration.
1385 */
1386 rt2x00dev->default_ant.tx =
1387 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1388 rt2x00dev->default_ant.rx =
1389 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1390
1391 /*
1392 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1393 * I am not 100% sure about this, but the legacy drivers do not
1394 * indicate antenna swapping in software is required when
1395 * diversity is enabled.
1396 */
1397 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1398 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1399 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1400 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1401
1402 /*
1403 * Store led mode, for correct led behaviour.
1404 */
1405 #ifdef CONFIG_RT2X00_LIB_LEDS
1406 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1407
1408 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1409 if (value == LED_MODE_TXRX_ACTIVITY)
1410 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1411 LED_TYPE_ACTIVITY);
1412 #endif /* CONFIG_RT2X00_LIB_LEDS */
1413
1414 /*
1415 * Detect if this device has an hardware controlled radio.
1416 */
1417 #ifdef CONFIG_RT2X00_LIB_RFKILL
1418 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1419 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1420 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1421
1422 /*
1423 * Check if the BBP tuning should be enabled.
1424 */
1425 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1426 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1427
1428 return 0;
1429 }
1430
1431 /*
1432 * RF value list for RF2420 & RF2421
1433 * Supports: 2.4 GHz
1434 */
1435 static const struct rf_channel rf_vals_b[] = {
1436 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1437 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1438 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1439 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1440 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1441 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1442 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1443 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1444 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1445 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1446 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1447 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1448 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1449 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1450 };
1451
1452 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1453 {
1454 struct hw_mode_spec *spec = &rt2x00dev->spec;
1455 struct channel_info *info;
1456 char *tx_power;
1457 unsigned int i;
1458
1459 /*
1460 * Initialize all hw fields.
1461 */
1462 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1463 IEEE80211_HW_SIGNAL_DBM;
1464 rt2x00dev->hw->extra_tx_headroom = 0;
1465
1466 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1467 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1468 rt2x00_eeprom_addr(rt2x00dev,
1469 EEPROM_MAC_ADDR_0));
1470
1471 /*
1472 * Initialize hw_mode information.
1473 */
1474 spec->supported_bands = SUPPORT_BAND_2GHZ;
1475 spec->supported_rates = SUPPORT_RATE_CCK;
1476
1477 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1478 spec->channels = rf_vals_b;
1479
1480 /*
1481 * Create channel information array
1482 */
1483 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1484 if (!info)
1485 return -ENOMEM;
1486
1487 spec->channels_info = info;
1488
1489 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1490 for (i = 0; i < 14; i++)
1491 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1492
1493 return 0;
1494 }
1495
1496 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1497 {
1498 int retval;
1499
1500 /*
1501 * Allocate eeprom data.
1502 */
1503 retval = rt2400pci_validate_eeprom(rt2x00dev);
1504 if (retval)
1505 return retval;
1506
1507 retval = rt2400pci_init_eeprom(rt2x00dev);
1508 if (retval)
1509 return retval;
1510
1511 /*
1512 * Initialize hw specifications.
1513 */
1514 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1515 if (retval)
1516 return retval;
1517
1518 /*
1519 * This device requires the atim queue and DMA-mapped skbs.
1520 */
1521 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1522 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1523
1524 /*
1525 * Set the rssi offset.
1526 */
1527 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1528
1529 return 0;
1530 }
1531
1532 /*
1533 * IEEE80211 stack callback functions.
1534 */
1535 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1536 const struct ieee80211_tx_queue_params *params)
1537 {
1538 struct rt2x00_dev *rt2x00dev = hw->priv;
1539
1540 /*
1541 * We don't support variating cw_min and cw_max variables
1542 * per queue. So by default we only configure the TX queue,
1543 * and ignore all other configurations.
1544 */
1545 if (queue != 0)
1546 return -EINVAL;
1547
1548 if (rt2x00mac_conf_tx(hw, queue, params))
1549 return -EINVAL;
1550
1551 /*
1552 * Write configuration to register.
1553 */
1554 rt2400pci_config_cw(rt2x00dev,
1555 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1556
1557 return 0;
1558 }
1559
1560 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1561 {
1562 struct rt2x00_dev *rt2x00dev = hw->priv;
1563 u64 tsf;
1564 u32 reg;
1565
1566 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1567 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1568 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1569 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1570
1571 return tsf;
1572 }
1573
1574 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1575 {
1576 struct rt2x00_dev *rt2x00dev = hw->priv;
1577 u32 reg;
1578
1579 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1580 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1581 }
1582
1583 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1584 .tx = rt2x00mac_tx,
1585 .start = rt2x00mac_start,
1586 .stop = rt2x00mac_stop,
1587 .add_interface = rt2x00mac_add_interface,
1588 .remove_interface = rt2x00mac_remove_interface,
1589 .config = rt2x00mac_config,
1590 .config_interface = rt2x00mac_config_interface,
1591 .configure_filter = rt2x00mac_configure_filter,
1592 .get_stats = rt2x00mac_get_stats,
1593 .bss_info_changed = rt2x00mac_bss_info_changed,
1594 .conf_tx = rt2400pci_conf_tx,
1595 .get_tx_stats = rt2x00mac_get_tx_stats,
1596 .get_tsf = rt2400pci_get_tsf,
1597 .tx_last_beacon = rt2400pci_tx_last_beacon,
1598 };
1599
1600 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1601 .irq_handler = rt2400pci_interrupt,
1602 .probe_hw = rt2400pci_probe_hw,
1603 .initialize = rt2x00pci_initialize,
1604 .uninitialize = rt2x00pci_uninitialize,
1605 .get_entry_state = rt2400pci_get_entry_state,
1606 .clear_entry = rt2400pci_clear_entry,
1607 .set_device_state = rt2400pci_set_device_state,
1608 .rfkill_poll = rt2400pci_rfkill_poll,
1609 .link_stats = rt2400pci_link_stats,
1610 .reset_tuner = rt2400pci_reset_tuner,
1611 .link_tuner = rt2400pci_link_tuner,
1612 .write_tx_desc = rt2400pci_write_tx_desc,
1613 .write_tx_data = rt2x00pci_write_tx_data,
1614 .write_beacon = rt2400pci_write_beacon,
1615 .kick_tx_queue = rt2400pci_kick_tx_queue,
1616 .fill_rxdone = rt2400pci_fill_rxdone,
1617 .config_filter = rt2400pci_config_filter,
1618 .config_intf = rt2400pci_config_intf,
1619 .config_erp = rt2400pci_config_erp,
1620 .config_ant = rt2400pci_config_ant,
1621 .config = rt2400pci_config,
1622 };
1623
1624 static const struct data_queue_desc rt2400pci_queue_rx = {
1625 .entry_num = RX_ENTRIES,
1626 .data_size = DATA_FRAME_SIZE,
1627 .desc_size = RXD_DESC_SIZE,
1628 .priv_size = sizeof(struct queue_entry_priv_pci),
1629 };
1630
1631 static const struct data_queue_desc rt2400pci_queue_tx = {
1632 .entry_num = TX_ENTRIES,
1633 .data_size = DATA_FRAME_SIZE,
1634 .desc_size = TXD_DESC_SIZE,
1635 .priv_size = sizeof(struct queue_entry_priv_pci),
1636 };
1637
1638 static const struct data_queue_desc rt2400pci_queue_bcn = {
1639 .entry_num = BEACON_ENTRIES,
1640 .data_size = MGMT_FRAME_SIZE,
1641 .desc_size = TXD_DESC_SIZE,
1642 .priv_size = sizeof(struct queue_entry_priv_pci),
1643 };
1644
1645 static const struct data_queue_desc rt2400pci_queue_atim = {
1646 .entry_num = ATIM_ENTRIES,
1647 .data_size = DATA_FRAME_SIZE,
1648 .desc_size = TXD_DESC_SIZE,
1649 .priv_size = sizeof(struct queue_entry_priv_pci),
1650 };
1651
1652 static const struct rt2x00_ops rt2400pci_ops = {
1653 .name = KBUILD_MODNAME,
1654 .max_sta_intf = 1,
1655 .max_ap_intf = 1,
1656 .eeprom_size = EEPROM_SIZE,
1657 .rf_size = RF_SIZE,
1658 .tx_queues = NUM_TX_QUEUES,
1659 .rx = &rt2400pci_queue_rx,
1660 .tx = &rt2400pci_queue_tx,
1661 .bcn = &rt2400pci_queue_bcn,
1662 .atim = &rt2400pci_queue_atim,
1663 .lib = &rt2400pci_rt2x00_ops,
1664 .hw = &rt2400pci_mac80211_ops,
1665 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1666 .debugfs = &rt2400pci_rt2x00debug,
1667 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1668 };
1669
1670 /*
1671 * RT2400pci module information.
1672 */
1673 static struct pci_device_id rt2400pci_device_table[] = {
1674 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1675 { 0, }
1676 };
1677
1678 MODULE_AUTHOR(DRV_PROJECT);
1679 MODULE_VERSION(DRV_VERSION);
1680 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1681 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1682 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1683 MODULE_LICENSE("GPL");
1684
1685 static struct pci_driver rt2400pci_driver = {
1686 .name = KBUILD_MODNAME,
1687 .id_table = rt2400pci_device_table,
1688 .probe = rt2x00pci_probe,
1689 .remove = __devexit_p(rt2x00pci_remove),
1690 .suspend = rt2x00pci_suspend,
1691 .resume = rt2x00pci_resume,
1692 };
1693
1694 static int __init rt2400pci_init(void)
1695 {
1696 return pci_register_driver(&rt2400pci_driver);
1697 }
1698
1699 static void __exit rt2400pci_exit(void)
1700 {
1701 pci_unregister_driver(&rt2400pci_driver);
1702 }
1703
1704 module_init(rt2400pci_init);
1705 module_exit(rt2400pci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree