2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.14"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82 static const u32 default_msg
=
83 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
84 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
87 static int debug
= -1; /* defaults above */
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly
= 128;
92 module_param(copybreak
, int, 0);
93 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
95 static int disable_msi
= 0;
96 module_param(disable_msi
, int, 0);
97 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
99 static int idle_timeout
= 0;
100 module_param(idle_timeout
, int, 0);
101 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
103 static const struct pci_device_id sky2_id_table
[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
133 // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
139 /* Avoid conditionals by using array */
140 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
141 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
142 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
144 /* This driver supports yukon2 chipset only */
145 static const char *yukon2_name
[] = {
147 "EC Ultra", /* 0xb4 */
148 "Extreme", /* 0xb5 */
153 /* Access to external PHY */
154 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
158 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
159 gma_write16(hw
, port
, GM_SMI_CTRL
,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
162 for (i
= 0; i
< PHY_RETRIES
; i
++) {
163 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
168 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
172 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
176 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
177 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
179 for (i
= 0; i
< PHY_RETRIES
; i
++) {
180 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
181 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
191 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
195 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
196 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
201 static void sky2_power_on(struct sky2_hw
*hw
)
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw
, B0_POWER_CTRL
,
205 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
207 /* disable Core Clock Division, */
208 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
210 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
211 /* enable bits are inverted */
212 sky2_write8(hw
, B2_Y2_CLK_GATE
,
213 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
214 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
215 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
217 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
219 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
222 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
223 /* set all bits to 0 except bits 15..12 and 8 */
224 reg
&= P_ASPM_CONTROL_MSK
;
225 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
227 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
228 /* set all bits to 0 except bits 28 & 27 */
229 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
230 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
232 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
234 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
235 reg
= sky2_read32(hw
, B2_GP_IO
);
236 reg
|= GLB_GPIO_STAT_RACE_DIS
;
237 sky2_write32(hw
, B2_GP_IO
, reg
);
241 static void sky2_power_aux(struct sky2_hw
*hw
)
243 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
244 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
246 /* enable bits are inverted */
247 sky2_write8(hw
, B2_Y2_CLK_GATE
,
248 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
249 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
250 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
252 /* switch power to VAUX */
253 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
254 sky2_write8(hw
, B0_POWER_CTRL
,
255 (PC_VAUX_ENA
| PC_VCC_ENA
|
256 PC_VAUX_ON
| PC_VCC_OFF
));
259 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
263 /* disable all GMAC IRQ's */
264 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
265 /* disable PHY IRQs */
266 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
268 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
269 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
270 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
271 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
273 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
274 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
275 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
278 /* flow control to advertise bits */
279 static const u16 copper_fc_adv
[] = {
281 [FC_TX
] = PHY_M_AN_ASP
,
282 [FC_RX
] = PHY_M_AN_PC
,
283 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
286 /* flow control to advertise bits when using 1000BaseX */
287 static const u16 fiber_fc_adv
[] = {
288 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
289 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
290 [FC_RX
] = PHY_M_P_SYM_MD_X
,
291 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
294 /* flow control to GMA disable bits */
295 static const u16 gm_fc_disable
[] = {
296 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
297 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
298 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
303 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
305 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
306 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
308 if (sky2
->autoneg
== AUTONEG_ENABLE
309 && !(hw
->chip_id
== CHIP_ID_YUKON_XL
310 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
311 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
312 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
314 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
316 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
318 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
319 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
320 /* set downshift counter to 3x and enable downshift */
321 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
323 /* set master & slave downshift counter to 1x */
324 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
326 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
329 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
330 if (sky2_is_copper(hw
)) {
331 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
332 /* enable automatic crossover */
333 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
335 /* disable energy detect */
336 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
338 /* enable automatic crossover */
339 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
341 /* downshift on PHY 88E1112 and 88E1149 is changed */
342 if (sky2
->autoneg
== AUTONEG_ENABLE
343 && (hw
->chip_id
== CHIP_ID_YUKON_XL
344 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
345 || hw
->chip_id
== CHIP_ID_YUKON_EX
)) {
346 /* set downshift counter to 3x and enable downshift */
347 ctrl
&= ~PHY_M_PC_DSC_MSK
;
348 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
352 /* workaround for deviation #4.88 (CRC errors) */
353 /* disable Automatic Crossover */
355 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
358 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
360 /* special setup for PHY 88E1112 Fiber */
361 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
362 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
364 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
365 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
366 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
367 ctrl
&= ~PHY_M_MAC_MD_MSK
;
368 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
369 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
371 if (hw
->pmd_type
== 'P') {
372 /* select page 1 to access Fiber registers */
373 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
375 /* for SFP-module set SIGDET polarity to low */
376 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
377 ctrl
|= PHY_M_FIB_SIGD_POL
;
378 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
381 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
389 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
390 if (sky2_is_copper(hw
)) {
391 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
392 ct1000
|= PHY_M_1000C_AFD
;
393 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
394 ct1000
|= PHY_M_1000C_AHD
;
395 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
396 adv
|= PHY_M_AN_100_FD
;
397 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
398 adv
|= PHY_M_AN_100_HD
;
399 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
400 adv
|= PHY_M_AN_10_FD
;
401 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
402 adv
|= PHY_M_AN_10_HD
;
404 adv
|= copper_fc_adv
[sky2
->flow_mode
];
405 } else { /* special defines for FIBER (88E1040S only) */
406 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
407 adv
|= PHY_M_AN_1000X_AFD
;
408 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
409 adv
|= PHY_M_AN_1000X_AHD
;
411 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
414 /* Restart Auto-negotiation */
415 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
417 /* forced speed/duplex settings */
418 ct1000
= PHY_M_1000C_MSE
;
420 /* Disable auto update for duplex flow control and speed */
421 reg
|= GM_GPCR_AU_ALL_DIS
;
423 switch (sky2
->speed
) {
425 ctrl
|= PHY_CT_SP1000
;
426 reg
|= GM_GPCR_SPEED_1000
;
429 ctrl
|= PHY_CT_SP100
;
430 reg
|= GM_GPCR_SPEED_100
;
434 if (sky2
->duplex
== DUPLEX_FULL
) {
435 reg
|= GM_GPCR_DUP_FULL
;
436 ctrl
|= PHY_CT_DUP_MD
;
437 } else if (sky2
->speed
< SPEED_1000
)
438 sky2
->flow_mode
= FC_NONE
;
441 reg
|= gm_fc_disable
[sky2
->flow_mode
];
443 /* Forward pause packets to GMAC? */
444 if (sky2
->flow_mode
& FC_RX
)
445 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
447 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
450 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
452 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
453 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
455 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
456 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
458 /* Setup Phy LED's */
459 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
462 switch (hw
->chip_id
) {
463 case CHIP_ID_YUKON_FE
:
464 /* on 88E3082 these bits are at 11..9 (shifted left) */
465 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
467 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
469 /* delete ACT LED control bits */
470 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
471 /* change ACT LED control to blink mode */
472 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
473 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
476 case CHIP_ID_YUKON_XL
:
477 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
482 /* set LED Function Control register */
483 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
489 /* set Polarity Control register */
490 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
491 (PHY_M_POLC_LS1_P_MIX(4) |
492 PHY_M_POLC_IS0_P_MIX(4) |
493 PHY_M_POLC_LOS_CTRL(2) |
494 PHY_M_POLC_INIT_CTRL(2) |
495 PHY_M_POLC_STA1_CTRL(2) |
496 PHY_M_POLC_STA0_CTRL(2)));
498 /* restore page register */
499 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
502 case CHIP_ID_YUKON_EC_U
:
503 case CHIP_ID_YUKON_EX
:
504 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
506 /* select page 3 to access LED control register */
507 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
509 /* set LED Function Control register */
510 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
511 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
512 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
513 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
514 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
516 /* set Blink Rate in LED Timer Control Register */
517 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
518 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
519 /* restore page register */
520 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
524 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
525 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
526 /* turn off the Rx LED (LED_RX) */
527 ledover
&= ~PHY_M_LED_MO_RX
;
530 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
531 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
532 /* apply fixes in PHY AFE */
533 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
535 /* increase differential signal amplitude in 10BASE-T */
536 gm_phy_write(hw
, port
, 0x18, 0xaa99);
537 gm_phy_write(hw
, port
, 0x17, 0x2011);
539 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
540 gm_phy_write(hw
, port
, 0x18, 0xa204);
541 gm_phy_write(hw
, port
, 0x17, 0x2002);
543 /* set page register to 0 */
544 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
545 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
546 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
548 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
549 /* turn on 100 Mbps LED (LED_LINK100) */
550 ledover
|= PHY_M_LED_MO_100
;
554 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
558 /* Enable phy interrupt on auto-negotiation complete (or link up) */
559 if (sky2
->autoneg
== AUTONEG_ENABLE
)
560 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
562 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
565 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
568 static const u32 phy_power
[]
569 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
571 /* looks like this XL is back asswards .. */
572 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
575 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
576 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
578 /* Turn off phy power saving */
579 reg1
&= ~phy_power
[port
];
581 reg1
|= phy_power
[port
];
583 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
584 sky2_pci_read32(hw
, PCI_DEV_REG1
);
585 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
589 /* Force a renegotiation */
590 static void sky2_phy_reinit(struct sky2_port
*sky2
)
592 spin_lock_bh(&sky2
->phy_lock
);
593 sky2_phy_init(sky2
->hw
, sky2
->port
);
594 spin_unlock_bh(&sky2
->phy_lock
);
597 /* Put device in state to listen for Wake On Lan */
598 static void sky2_wol_init(struct sky2_port
*sky2
)
600 struct sky2_hw
*hw
= sky2
->hw
;
601 unsigned port
= sky2
->port
;
602 enum flow_control save_mode
;
606 /* Bring hardware out of reset */
607 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
608 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
610 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
611 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
614 * sky2_reset will re-enable on resume
616 save_mode
= sky2
->flow_mode
;
617 ctrl
= sky2
->advertising
;
619 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
620 sky2
->flow_mode
= FC_NONE
;
621 sky2_phy_power(hw
, port
, 1);
622 sky2_phy_reinit(sky2
);
624 sky2
->flow_mode
= save_mode
;
625 sky2
->advertising
= ctrl
;
627 /* Set GMAC to no flow control and auto update for speed/duplex */
628 gma_write16(hw
, port
, GM_GP_CTRL
,
629 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
630 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
632 /* Set WOL address */
633 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
634 sky2
->netdev
->dev_addr
, ETH_ALEN
);
636 /* Turn on appropriate WOL control bits */
637 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
639 if (sky2
->wol
& WAKE_PHY
)
640 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
642 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
644 if (sky2
->wol
& WAKE_MAGIC
)
645 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
647 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
649 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
650 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
652 /* Turn on legacy PCI-Express PME mode */
653 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
654 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
655 reg1
|= PCI_Y2_PME_LEGACY
;
656 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
657 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
660 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
664 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
666 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
669 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
671 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
672 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
674 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
676 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
677 /* WA DEV_472 -- looks like crossed wires on port 2 */
678 /* clear GMAC 1 Control reset */
679 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
681 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
682 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
683 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
684 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
685 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
688 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
690 /* Enable Transmit FIFO Underrun */
691 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
693 spin_lock_bh(&sky2
->phy_lock
);
694 sky2_phy_init(hw
, port
);
695 spin_unlock_bh(&sky2
->phy_lock
);
698 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
699 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
701 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
702 gma_read16(hw
, port
, i
);
703 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
705 /* transmit control */
706 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
708 /* receive control reg: unicast + multicast + no FCS */
709 gma_write16(hw
, port
, GM_RX_CTRL
,
710 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
712 /* transmit flow control */
713 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
715 /* transmit parameter */
716 gma_write16(hw
, port
, GM_TX_PARAM
,
717 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
718 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
719 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
720 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
722 /* serial mode register */
723 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
724 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
726 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
727 reg
|= GM_SMOD_JUMBO_ENA
;
729 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
731 /* virtual address for data */
732 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
734 /* physical address: used for pause frames */
735 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
737 /* ignore counter overflows */
738 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
739 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
740 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
742 /* Configure Rx MAC FIFO */
743 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
744 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
745 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
747 /* Flush Rx MAC FIFO on any flow control or error */
748 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
750 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
751 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
753 /* Configure Tx MAC FIFO */
754 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
755 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
757 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
758 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
759 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
761 /* set Tx GMAC FIFO Almost Empty Threshold */
762 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
763 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
765 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
766 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
767 TX_JUMBO_ENA
| TX_STFW_DIS
);
769 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
770 TX_JUMBO_DIS
| TX_STFW_ENA
);
775 /* Assign Ram Buffer allocation to queue */
776 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
780 /* convert from K bytes to qwords used for hw register */
783 end
= start
+ space
- 1;
785 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
786 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
787 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
788 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
789 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
791 if (q
== Q_R1
|| q
== Q_R2
) {
792 u32 tp
= space
- space
/4;
794 /* On receive queue's set the thresholds
795 * give receiver priority when > 3/4 full
796 * send pause when down to 2K
798 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
799 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
802 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
803 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
805 /* Enable store & forward on Tx queue's because
806 * Tx FIFO is only 1K on Yukon
808 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
811 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
812 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
815 /* Setup Bus Memory Interface */
816 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
818 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
819 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
820 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
821 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
824 /* Setup prefetch unit registers. This is the interface between
825 * hardware and driver list elements
827 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
830 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
831 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
832 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
833 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
834 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
835 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
837 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
840 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
842 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
844 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
849 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
850 struct sky2_tx_le
*le
)
852 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
855 /* Update chip's next pointer */
856 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
858 /* Make sure write' to descriptors are complete before we tell hardware */
860 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
862 /* Synchronize I/O on since next processor may write to tail */
867 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
869 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
870 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
875 /* Return high part of DMA address (could be 32 or 64 bit) */
876 static inline u32
high32(dma_addr_t a
)
878 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
881 /* Build description to hardware for one receive segment */
882 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
883 dma_addr_t map
, unsigned len
)
885 struct sky2_rx_le
*le
;
886 u32 hi
= high32(map
);
888 if (sky2
->rx_addr64
!= hi
) {
889 le
= sky2_next_rx(sky2
);
890 le
->addr
= cpu_to_le32(hi
);
891 le
->opcode
= OP_ADDR64
| HW_OWNER
;
892 sky2
->rx_addr64
= high32(map
+ len
);
895 le
= sky2_next_rx(sky2
);
896 le
->addr
= cpu_to_le32((u32
) map
);
897 le
->length
= cpu_to_le16(len
);
898 le
->opcode
= op
| HW_OWNER
;
901 /* Build description to hardware for one possibly fragmented skb */
902 static void sky2_rx_submit(struct sky2_port
*sky2
,
903 const struct rx_ring_info
*re
)
907 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
909 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
910 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
914 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
917 struct sk_buff
*skb
= re
->skb
;
920 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
921 pci_unmap_len_set(re
, data_size
, size
);
923 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
924 re
->frag_addr
[i
] = pci_map_page(pdev
,
925 skb_shinfo(skb
)->frags
[i
].page
,
926 skb_shinfo(skb
)->frags
[i
].page_offset
,
927 skb_shinfo(skb
)->frags
[i
].size
,
931 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
933 struct sk_buff
*skb
= re
->skb
;
936 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
939 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
940 pci_unmap_page(pdev
, re
->frag_addr
[i
],
941 skb_shinfo(skb
)->frags
[i
].size
,
945 /* Tell chip where to start receive checksum.
946 * Actually has two checksums, but set both same to avoid possible byte
949 static void rx_set_checksum(struct sky2_port
*sky2
)
951 struct sky2_rx_le
*le
;
953 le
= sky2_next_rx(sky2
);
954 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
956 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
958 sky2_write32(sky2
->hw
,
959 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
960 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
965 * The RX Stop command will not work for Yukon-2 if the BMU does not
966 * reach the end of packet and since we can't make sure that we have
967 * incoming data, we must reset the BMU while it is not doing a DMA
968 * transfer. Since it is possible that the RX path is still active,
969 * the RX RAM buffer will be stopped first, so any possible incoming
970 * data will not trigger a DMA. After the RAM buffer is stopped, the
971 * BMU is polled until any DMA in progress is ended and only then it
974 static void sky2_rx_stop(struct sky2_port
*sky2
)
976 struct sky2_hw
*hw
= sky2
->hw
;
977 unsigned rxq
= rxqaddr
[sky2
->port
];
980 /* disable the RAM Buffer receive queue */
981 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
983 for (i
= 0; i
< 0xffff; i
++)
984 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
985 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
988 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
991 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
993 /* reset the Rx prefetch unit */
994 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
998 /* Clean out receive buffer area, assumes receiver hardware stopped */
999 static void sky2_rx_clean(struct sky2_port
*sky2
)
1003 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1004 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1005 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1008 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1015 /* Basic MII support */
1016 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1018 struct mii_ioctl_data
*data
= if_mii(ifr
);
1019 struct sky2_port
*sky2
= netdev_priv(dev
);
1020 struct sky2_hw
*hw
= sky2
->hw
;
1021 int err
= -EOPNOTSUPP
;
1023 if (!netif_running(dev
))
1024 return -ENODEV
; /* Phy still in reset */
1028 data
->phy_id
= PHY_ADDR_MARV
;
1034 spin_lock_bh(&sky2
->phy_lock
);
1035 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1036 spin_unlock_bh(&sky2
->phy_lock
);
1038 data
->val_out
= val
;
1043 if (!capable(CAP_NET_ADMIN
))
1046 spin_lock_bh(&sky2
->phy_lock
);
1047 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1049 spin_unlock_bh(&sky2
->phy_lock
);
1055 #ifdef SKY2_VLAN_TAG_USED
1056 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1058 struct sky2_port
*sky2
= netdev_priv(dev
);
1059 struct sky2_hw
*hw
= sky2
->hw
;
1060 u16 port
= sky2
->port
;
1062 netif_tx_lock_bh(dev
);
1063 netif_poll_disable(sky2
->hw
->dev
[0]);
1067 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1069 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1072 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1074 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1078 netif_poll_enable(sky2
->hw
->dev
[0]);
1079 netif_tx_unlock_bh(dev
);
1084 * Allocate an skb for receiving. If the MTU is large enough
1085 * make the skb non-linear with a fragment list of pages.
1087 * It appears the hardware has a bug in the FIFO logic that
1088 * cause it to hang if the FIFO gets overrun and the receive buffer
1089 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1090 * aligned except if slab debugging is enabled.
1092 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1094 struct sk_buff
*skb
;
1098 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1102 p
= (unsigned long) skb
->data
;
1103 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1105 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1106 struct page
*page
= alloc_page(GFP_ATOMIC
);
1110 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1121 * Allocate and setup receiver buffer pool.
1122 * Normal case this ends up creating one list element for skb
1123 * in the receive ring. Worst case if using large MTU and each
1124 * allocation falls on a different 64 bit region, that results
1125 * in 6 list elements per ring entry.
1126 * One element is used for checksum enable/disable, and one
1127 * extra to avoid wrap.
1129 static int sky2_rx_start(struct sky2_port
*sky2
)
1131 struct sky2_hw
*hw
= sky2
->hw
;
1132 struct rx_ring_info
*re
;
1133 unsigned rxq
= rxqaddr
[sky2
->port
];
1134 unsigned i
, size
, space
, thresh
;
1136 sky2
->rx_put
= sky2
->rx_next
= 0;
1139 /* On PCI express lowering the watermark gives better performance */
1140 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1141 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1143 /* These chips have no ram buffer?
1144 * MAC Rx RAM Read is controlled by hardware */
1145 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1146 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1147 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1148 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1150 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1152 rx_set_checksum(sky2
);
1154 /* Space needed for frame data + headers rounded up */
1155 size
= ALIGN(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8)
1158 /* Stopping point for hardware truncation */
1159 thresh
= (size
- 8) / sizeof(u32
);
1161 /* Account for overhead of skb - to avoid order > 0 allocation */
1162 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1163 + sizeof(struct skb_shared_info
);
1165 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1166 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1168 if (sky2
->rx_nfrags
!= 0) {
1169 /* Compute residue after pages */
1170 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1177 /* Optimize to handle small packets and headers */
1178 if (size
< copybreak
)
1180 if (size
< ETH_HLEN
)
1183 sky2
->rx_data_size
= size
;
1186 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1187 re
= sky2
->rx_ring
+ i
;
1189 re
->skb
= sky2_rx_alloc(sky2
);
1193 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1194 sky2_rx_submit(sky2
, re
);
1198 * The receiver hangs if it receives frames larger than the
1199 * packet buffer. As a workaround, truncate oversize frames, but
1200 * the register is limited to 9 bits, so if you do frames > 2052
1201 * you better get the MTU right!
1204 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1206 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1207 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1210 /* Tell chip about available buffers */
1211 sky2_put_idx(hw
, rxq
, sky2
->rx_put
);
1214 sky2_rx_clean(sky2
);
1218 /* Bring up network interface. */
1219 static int sky2_up(struct net_device
*dev
)
1221 struct sky2_port
*sky2
= netdev_priv(dev
);
1222 struct sky2_hw
*hw
= sky2
->hw
;
1223 unsigned port
= sky2
->port
;
1225 int cap
, err
= -ENOMEM
;
1226 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1229 * On dual port PCI-X card, there is an problem where status
1230 * can be received out of order due to split transactions
1232 if (otherdev
&& netif_running(otherdev
) &&
1233 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1234 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1237 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1238 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1239 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1245 if (netif_msg_ifup(sky2
))
1246 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1248 /* must be power of 2 */
1249 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1251 sizeof(struct sky2_tx_le
),
1256 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1260 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1262 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1266 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1268 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1273 sky2_phy_power(hw
, port
, 1);
1275 sky2_mac_init(hw
, port
);
1277 /* Register is number of 4K blocks on internal RAM buffer. */
1278 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1279 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1285 rxspace
= ramsize
/ 2;
1287 rxspace
= 8 + (2*(ramsize
- 16))/3;
1289 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1290 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1292 /* Make sure SyncQ is disabled */
1293 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1297 sky2_qset(hw
, txqaddr
[port
]);
1299 /* Set almost empty threshold */
1300 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1301 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1302 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1304 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1307 err
= sky2_rx_start(sky2
);
1311 /* Enable interrupts from phy/mac for port */
1312 imask
= sky2_read32(hw
, B0_IMSK
);
1313 imask
|= portirq_msk
[port
];
1314 sky2_write32(hw
, B0_IMSK
, imask
);
1320 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1321 sky2
->rx_le
, sky2
->rx_le_map
);
1325 pci_free_consistent(hw
->pdev
,
1326 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1327 sky2
->tx_le
, sky2
->tx_le_map
);
1330 kfree(sky2
->tx_ring
);
1331 kfree(sky2
->rx_ring
);
1333 sky2
->tx_ring
= NULL
;
1334 sky2
->rx_ring
= NULL
;
1338 /* Modular subtraction in ring */
1339 static inline int tx_dist(unsigned tail
, unsigned head
)
1341 return (head
- tail
) & (TX_RING_SIZE
- 1);
1344 /* Number of list elements available for next tx */
1345 static inline int tx_avail(const struct sky2_port
*sky2
)
1347 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1350 /* Estimate of number of transmit list elements required */
1351 static unsigned tx_le_req(const struct sk_buff
*skb
)
1355 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1356 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1358 if (skb_is_gso(skb
))
1361 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1368 * Put one packet in ring for transmit.
1369 * A single packet can generate multiple list elements, and
1370 * the number of ring elements will probably be less than the number
1371 * of list elements used.
1373 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1375 struct sky2_port
*sky2
= netdev_priv(dev
);
1376 struct sky2_hw
*hw
= sky2
->hw
;
1377 struct sky2_tx_le
*le
= NULL
;
1378 struct tx_ring_info
*re
;
1385 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1386 return NETDEV_TX_BUSY
;
1388 if (unlikely(netif_msg_tx_queued(sky2
)))
1389 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1390 dev
->name
, sky2
->tx_prod
, skb
->len
);
1392 len
= skb_headlen(skb
);
1393 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1394 addr64
= high32(mapping
);
1396 /* Send high bits if changed or crosses boundary */
1397 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1398 le
= get_tx_le(sky2
);
1399 le
->addr
= cpu_to_le32(addr64
);
1400 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1401 sky2
->tx_addr64
= high32(mapping
+ len
);
1404 /* Check for TCP Segmentation Offload */
1405 mss
= skb_shinfo(skb
)->gso_size
;
1407 mss
+= tcp_optlen(skb
); /* TCP options */
1408 mss
+= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
1411 if (mss
!= sky2
->tx_last_mss
) {
1412 le
= get_tx_le(sky2
);
1413 le
->addr
= cpu_to_le32(mss
);
1414 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1415 sky2
->tx_last_mss
= mss
;
1420 #ifdef SKY2_VLAN_TAG_USED
1421 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1422 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1424 le
= get_tx_le(sky2
);
1426 le
->opcode
= OP_VLAN
|HW_OWNER
;
1428 le
->opcode
|= OP_VLAN
;
1429 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1434 /* Handle TCP checksum offload */
1435 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1436 const unsigned offset
= skb_transport_offset(skb
);
1439 tcpsum
= offset
<< 16; /* sum start */
1440 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1442 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1443 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1446 if (tcpsum
!= sky2
->tx_tcpsum
) {
1447 sky2
->tx_tcpsum
= tcpsum
;
1449 le
= get_tx_le(sky2
);
1450 le
->addr
= cpu_to_le32(tcpsum
);
1451 le
->length
= 0; /* initial checksum value */
1452 le
->ctrl
= 1; /* one packet */
1453 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1457 le
= get_tx_le(sky2
);
1458 le
->addr
= cpu_to_le32((u32
) mapping
);
1459 le
->length
= cpu_to_le16(len
);
1461 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1463 re
= tx_le_re(sky2
, le
);
1465 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1466 pci_unmap_len_set(re
, maplen
, len
);
1468 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1469 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1471 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1472 frag
->size
, PCI_DMA_TODEVICE
);
1473 addr64
= high32(mapping
);
1474 if (addr64
!= sky2
->tx_addr64
) {
1475 le
= get_tx_le(sky2
);
1476 le
->addr
= cpu_to_le32(addr64
);
1478 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1479 sky2
->tx_addr64
= addr64
;
1482 le
= get_tx_le(sky2
);
1483 le
->addr
= cpu_to_le32((u32
) mapping
);
1484 le
->length
= cpu_to_le16(frag
->size
);
1486 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1488 re
= tx_le_re(sky2
, le
);
1490 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1491 pci_unmap_len_set(re
, maplen
, frag
->size
);
1496 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1497 netif_stop_queue(dev
);
1499 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1501 dev
->trans_start
= jiffies
;
1502 return NETDEV_TX_OK
;
1506 * Free ring elements from starting at tx_cons until "done"
1508 * NB: the hardware will tell us about partial completion of multi-part
1509 * buffers so make sure not to free skb to early.
1511 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1513 struct net_device
*dev
= sky2
->netdev
;
1514 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1517 BUG_ON(done
>= TX_RING_SIZE
);
1519 for (idx
= sky2
->tx_cons
; idx
!= done
;
1520 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1521 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1522 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1524 switch(le
->opcode
& ~HW_OWNER
) {
1527 pci_unmap_single(pdev
,
1528 pci_unmap_addr(re
, mapaddr
),
1529 pci_unmap_len(re
, maplen
),
1533 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1534 pci_unmap_len(re
, maplen
),
1539 if (le
->ctrl
& EOP
) {
1540 if (unlikely(netif_msg_tx_done(sky2
)))
1541 printk(KERN_DEBUG
"%s: tx done %u\n",
1543 sky2
->net_stats
.tx_packets
++;
1544 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1546 dev_kfree_skb_any(re
->skb
);
1549 le
->opcode
= 0; /* paranoia */
1552 sky2
->tx_cons
= idx
;
1555 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1556 netif_wake_queue(dev
);
1559 /* Cleanup all untransmitted buffers, assume transmitter not running */
1560 static void sky2_tx_clean(struct net_device
*dev
)
1562 struct sky2_port
*sky2
= netdev_priv(dev
);
1564 netif_tx_lock_bh(dev
);
1565 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1566 netif_tx_unlock_bh(dev
);
1569 /* Network shutdown */
1570 static int sky2_down(struct net_device
*dev
)
1572 struct sky2_port
*sky2
= netdev_priv(dev
);
1573 struct sky2_hw
*hw
= sky2
->hw
;
1574 unsigned port
= sky2
->port
;
1578 /* Never really got started! */
1582 if (netif_msg_ifdown(sky2
))
1583 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1585 /* Stop more packets from being queued */
1586 netif_stop_queue(dev
);
1587 netif_carrier_off(dev
);
1589 /* Disable port IRQ */
1590 imask
= sky2_read32(hw
, B0_IMSK
);
1591 imask
&= ~portirq_msk
[port
];
1592 sky2_write32(hw
, B0_IMSK
, imask
);
1594 sky2_gmac_reset(hw
, port
);
1596 /* Stop transmitter */
1597 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1598 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1600 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1601 RB_RST_SET
| RB_DIS_OP_MD
);
1603 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1604 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1605 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1607 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1609 /* Workaround shared GMAC reset */
1610 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1611 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1612 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1614 /* Disable Force Sync bit and Enable Alloc bit */
1615 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1616 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1618 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1619 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1620 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1622 /* Reset the PCI FIFO of the async Tx queue */
1623 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1624 BMU_RST_SET
| BMU_FIFO_RST
);
1626 /* Reset the Tx prefetch units */
1627 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1630 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1634 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1635 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1637 sky2_phy_power(hw
, port
, 0);
1639 /* turn off LED's */
1640 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1642 synchronize_irq(hw
->pdev
->irq
);
1645 sky2_rx_clean(sky2
);
1647 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1648 sky2
->rx_le
, sky2
->rx_le_map
);
1649 kfree(sky2
->rx_ring
);
1651 pci_free_consistent(hw
->pdev
,
1652 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1653 sky2
->tx_le
, sky2
->tx_le_map
);
1654 kfree(sky2
->tx_ring
);
1659 sky2
->rx_ring
= NULL
;
1660 sky2
->tx_ring
= NULL
;
1665 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1667 if (!sky2_is_copper(hw
))
1670 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1671 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1673 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1674 case PHY_M_PS_SPEED_1000
:
1676 case PHY_M_PS_SPEED_100
:
1683 static void sky2_link_up(struct sky2_port
*sky2
)
1685 struct sky2_hw
*hw
= sky2
->hw
;
1686 unsigned port
= sky2
->port
;
1688 static const char *fc_name
[] = {
1696 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1697 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1698 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1700 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1702 netif_carrier_on(sky2
->netdev
);
1703 netif_wake_queue(sky2
->netdev
);
1705 /* Turn on link LED */
1706 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1707 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1709 if (hw
->chip_id
== CHIP_ID_YUKON_XL
1710 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
1711 || hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1712 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1713 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1715 switch(sky2
->speed
) {
1717 led
|= PHY_M_LEDC_INIT_CTRL(7);
1721 led
|= PHY_M_LEDC_STA1_CTRL(7);
1725 led
|= PHY_M_LEDC_STA0_CTRL(7);
1729 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1730 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1731 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1734 if (netif_msg_link(sky2
))
1735 printk(KERN_INFO PFX
1736 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1737 sky2
->netdev
->name
, sky2
->speed
,
1738 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1739 fc_name
[sky2
->flow_status
]);
1742 static void sky2_link_down(struct sky2_port
*sky2
)
1744 struct sky2_hw
*hw
= sky2
->hw
;
1745 unsigned port
= sky2
->port
;
1748 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1750 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1751 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1752 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1754 netif_carrier_off(sky2
->netdev
);
1755 netif_stop_queue(sky2
->netdev
);
1757 /* Turn on link LED */
1758 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1760 if (netif_msg_link(sky2
))
1761 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1763 sky2_phy_init(hw
, port
);
1766 static enum flow_control
sky2_flow(int rx
, int tx
)
1769 return tx
? FC_BOTH
: FC_RX
;
1771 return tx
? FC_TX
: FC_NONE
;
1774 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1776 struct sky2_hw
*hw
= sky2
->hw
;
1777 unsigned port
= sky2
->port
;
1780 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1781 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1782 if (lpa
& PHY_M_AN_RF
) {
1783 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1787 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1788 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1789 sky2
->netdev
->name
);
1793 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1794 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1796 /* Since the pause result bits seem to in different positions on
1797 * different chips. look at registers.
1799 if (!sky2_is_copper(hw
)) {
1800 /* Shift for bits in fiber PHY */
1801 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1802 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1804 if (advert
& ADVERTISE_1000XPAUSE
)
1805 advert
|= ADVERTISE_PAUSE_CAP
;
1806 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1807 advert
|= ADVERTISE_PAUSE_ASYM
;
1808 if (lpa
& LPA_1000XPAUSE
)
1809 lpa
|= LPA_PAUSE_CAP
;
1810 if (lpa
& LPA_1000XPAUSE_ASYM
)
1811 lpa
|= LPA_PAUSE_ASYM
;
1814 sky2
->flow_status
= FC_NONE
;
1815 if (advert
& ADVERTISE_PAUSE_CAP
) {
1816 if (lpa
& LPA_PAUSE_CAP
)
1817 sky2
->flow_status
= FC_BOTH
;
1818 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1819 sky2
->flow_status
= FC_RX
;
1820 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1821 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1822 sky2
->flow_status
= FC_TX
;
1825 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1826 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1827 sky2
->flow_status
= FC_NONE
;
1829 if (sky2
->flow_status
& FC_TX
)
1830 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1832 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1837 /* Interrupt from PHY */
1838 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1840 struct net_device
*dev
= hw
->dev
[port
];
1841 struct sky2_port
*sky2
= netdev_priv(dev
);
1842 u16 istatus
, phystat
;
1844 if (!netif_running(dev
))
1847 spin_lock(&sky2
->phy_lock
);
1848 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1849 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1851 if (netif_msg_intr(sky2
))
1852 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1853 sky2
->netdev
->name
, istatus
, phystat
);
1855 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1856 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1861 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1862 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1864 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1866 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1868 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1869 if (phystat
& PHY_M_PS_LINK_UP
)
1872 sky2_link_down(sky2
);
1875 spin_unlock(&sky2
->phy_lock
);
1878 /* Transmit timeout is only called if we are running, carrier is up
1879 * and tx queue is full (stopped).
1881 static void sky2_tx_timeout(struct net_device
*dev
)
1883 struct sky2_port
*sky2
= netdev_priv(dev
);
1884 struct sky2_hw
*hw
= sky2
->hw
;
1886 if (netif_msg_timer(sky2
))
1887 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1889 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1890 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1891 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1892 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1894 /* can't restart safely under softirq */
1895 schedule_work(&hw
->restart_work
);
1898 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1900 struct sky2_port
*sky2
= netdev_priv(dev
);
1901 struct sky2_hw
*hw
= sky2
->hw
;
1902 unsigned port
= sky2
->port
;
1907 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1910 if (new_mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_FE
)
1913 if (!netif_running(dev
)) {
1918 imask
= sky2_read32(hw
, B0_IMSK
);
1919 sky2_write32(hw
, B0_IMSK
, 0);
1921 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1922 netif_stop_queue(dev
);
1923 netif_poll_disable(hw
->dev
[0]);
1925 synchronize_irq(hw
->pdev
->irq
);
1927 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
) {
1928 if (new_mtu
> ETH_DATA_LEN
) {
1929 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1930 TX_JUMBO_ENA
| TX_STFW_DIS
);
1931 dev
->features
&= NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_IP_CSUM
;
1933 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1934 TX_JUMBO_DIS
| TX_STFW_ENA
);
1937 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1938 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1940 sky2_rx_clean(sky2
);
1944 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1945 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1947 if (dev
->mtu
> ETH_DATA_LEN
)
1948 mode
|= GM_SMOD_JUMBO_ENA
;
1950 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
1952 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
1954 err
= sky2_rx_start(sky2
);
1955 sky2_write32(hw
, B0_IMSK
, imask
);
1960 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
1962 netif_poll_enable(hw
->dev
[0]);
1963 netif_wake_queue(dev
);
1969 /* For small just reuse existing skb for next receive */
1970 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
1971 const struct rx_ring_info
*re
,
1974 struct sk_buff
*skb
;
1976 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
1978 skb_reserve(skb
, 2);
1979 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
1980 length
, PCI_DMA_FROMDEVICE
);
1981 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
1982 skb
->ip_summed
= re
->skb
->ip_summed
;
1983 skb
->csum
= re
->skb
->csum
;
1984 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
1985 length
, PCI_DMA_FROMDEVICE
);
1986 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1987 skb_put(skb
, length
);
1992 /* Adjust length of skb with fragments to match received data */
1993 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
1994 unsigned int length
)
1999 /* put header into skb */
2000 size
= min(length
, hdr_space
);
2005 num_frags
= skb_shinfo(skb
)->nr_frags
;
2006 for (i
= 0; i
< num_frags
; i
++) {
2007 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2010 /* don't need this page */
2011 __free_page(frag
->page
);
2012 --skb_shinfo(skb
)->nr_frags
;
2014 size
= min(length
, (unsigned) PAGE_SIZE
);
2017 skb
->data_len
+= size
;
2018 skb
->truesize
+= size
;
2025 /* Normal packet - take skb from ring element and put in a new one */
2026 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2027 struct rx_ring_info
*re
,
2028 unsigned int length
)
2030 struct sk_buff
*skb
, *nskb
;
2031 unsigned hdr_space
= sky2
->rx_data_size
;
2033 pr_debug(PFX
"receive new length=%d\n", length
);
2035 /* Don't be tricky about reusing pages (yet) */
2036 nskb
= sky2_rx_alloc(sky2
);
2037 if (unlikely(!nskb
))
2041 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2043 prefetch(skb
->data
);
2045 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2047 if (skb_shinfo(skb
)->nr_frags
)
2048 skb_put_frags(skb
, hdr_space
, length
);
2050 skb_put(skb
, length
);
2055 * Receive one packet.
2056 * For larger packets, get new buffer.
2058 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2059 u16 length
, u32 status
)
2061 struct sky2_port
*sky2
= netdev_priv(dev
);
2062 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2063 struct sk_buff
*skb
= NULL
;
2065 if (unlikely(netif_msg_rx_status(sky2
)))
2066 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2067 dev
->name
, sky2
->rx_next
, status
, length
);
2069 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2070 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2072 if (status
& GMR_FS_ANY_ERR
)
2075 if (!(status
& GMR_FS_RX_OK
))
2078 if (length
< copybreak
)
2079 skb
= receive_copy(sky2
, re
, length
);
2081 skb
= receive_new(sky2
, re
, length
);
2083 sky2_rx_submit(sky2
, re
);
2088 ++sky2
->net_stats
.rx_errors
;
2089 if (status
& GMR_FS_RX_FF_OV
) {
2090 sky2
->net_stats
.rx_over_errors
++;
2094 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2095 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2096 dev
->name
, status
, length
);
2098 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2099 sky2
->net_stats
.rx_length_errors
++;
2100 if (status
& GMR_FS_FRAGMENT
)
2101 sky2
->net_stats
.rx_frame_errors
++;
2102 if (status
& GMR_FS_CRC_ERR
)
2103 sky2
->net_stats
.rx_crc_errors
++;
2108 /* Transmit complete */
2109 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2111 struct sky2_port
*sky2
= netdev_priv(dev
);
2113 if (netif_running(dev
)) {
2115 sky2_tx_complete(sky2
, last
);
2116 netif_tx_unlock(dev
);
2120 /* Process status response ring */
2121 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2123 struct sky2_port
*sky2
;
2125 unsigned buf_write
[2] = { 0, 0 };
2126 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2130 while (hw
->st_idx
!= hwidx
) {
2131 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2132 struct net_device
*dev
;
2133 struct sk_buff
*skb
;
2137 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2139 BUG_ON(le
->link
>= 2);
2140 dev
= hw
->dev
[le
->link
];
2142 sky2
= netdev_priv(dev
);
2143 length
= le16_to_cpu(le
->length
);
2144 status
= le32_to_cpu(le
->status
);
2146 switch (le
->opcode
& ~HW_OWNER
) {
2148 skb
= sky2_receive(dev
, length
, status
);
2149 if (unlikely(!skb
)) {
2150 sky2
->net_stats
.rx_dropped
++;
2154 skb
->protocol
= eth_type_trans(skb
, dev
);
2155 sky2
->net_stats
.rx_packets
++;
2156 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2157 dev
->last_rx
= jiffies
;
2159 #ifdef SKY2_VLAN_TAG_USED
2160 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2161 vlan_hwaccel_receive_skb(skb
,
2163 be16_to_cpu(sky2
->rx_tag
));
2166 netif_receive_skb(skb
);
2168 /* Update receiver after 16 frames */
2169 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
2171 sky2_put_idx(hw
, rxqaddr
[le
->link
], sky2
->rx_put
);
2172 buf_write
[le
->link
] = 0;
2175 /* Stop after net poll weight */
2176 if (++work_done
>= to_do
)
2180 #ifdef SKY2_VLAN_TAG_USED
2182 sky2
->rx_tag
= length
;
2186 sky2
->rx_tag
= length
;
2193 /* Both checksum counters are programmed to start at
2194 * the same offset, so unless there is a problem they
2195 * should match. This failure is an early indication that
2196 * hardware receive checksumming won't work.
2198 if (likely(status
>> 16 == (status
& 0xffff))) {
2199 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2200 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2201 skb
->csum
= status
& 0xffff;
2203 printk(KERN_NOTICE PFX
"%s: hardware receive "
2204 "checksum problem (status = %#x)\n",
2207 sky2_write32(sky2
->hw
,
2208 Q_ADDR(rxqaddr
[le
->link
], Q_CSR
),
2214 /* TX index reports status for both ports */
2215 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2216 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2218 sky2_tx_done(hw
->dev
[1],
2219 ((status
>> 24) & 0xff)
2220 | (u16
)(length
& 0xf) << 8);
2224 if (net_ratelimit())
2225 printk(KERN_WARNING PFX
2226 "unknown status opcode 0x%x\n", le
->opcode
);
2231 /* Fully processed status ring so clear irq */
2232 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2237 sky2
= netdev_priv(hw
->dev
[0]);
2238 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2242 sky2
= netdev_priv(hw
->dev
[1]);
2243 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2249 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2251 struct net_device
*dev
= hw
->dev
[port
];
2253 if (net_ratelimit())
2254 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2257 if (status
& Y2_IS_PAR_RD1
) {
2258 if (net_ratelimit())
2259 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2262 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2265 if (status
& Y2_IS_PAR_WR1
) {
2266 if (net_ratelimit())
2267 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2270 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2273 if (status
& Y2_IS_PAR_MAC1
) {
2274 if (net_ratelimit())
2275 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2276 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2279 if (status
& Y2_IS_PAR_RX1
) {
2280 if (net_ratelimit())
2281 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2282 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2285 if (status
& Y2_IS_TCP_TXA1
) {
2286 if (net_ratelimit())
2287 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2289 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2293 static void sky2_hw_intr(struct sky2_hw
*hw
)
2295 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2297 if (status
& Y2_IS_TIST_OV
)
2298 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2300 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2303 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2304 if (net_ratelimit())
2305 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2308 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2309 sky2_pci_write16(hw
, PCI_STATUS
,
2310 pci_err
| PCI_STATUS_ERROR_BITS
);
2311 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2314 if (status
& Y2_IS_PCI_EXP
) {
2315 /* PCI-Express uncorrectable Error occurred */
2318 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2320 if (net_ratelimit())
2321 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2324 /* clear the interrupt */
2325 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2326 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2328 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2330 if (pex_err
& PEX_FATAL_ERRORS
) {
2331 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2332 hwmsk
&= ~Y2_IS_PCI_EXP
;
2333 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2337 if (status
& Y2_HWE_L1_MASK
)
2338 sky2_hw_error(hw
, 0, status
);
2340 if (status
& Y2_HWE_L1_MASK
)
2341 sky2_hw_error(hw
, 1, status
);
2344 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2346 struct net_device
*dev
= hw
->dev
[port
];
2347 struct sky2_port
*sky2
= netdev_priv(dev
);
2348 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2350 if (netif_msg_intr(sky2
))
2351 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2354 if (status
& GM_IS_RX_CO_OV
)
2355 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2357 if (status
& GM_IS_TX_CO_OV
)
2358 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2360 if (status
& GM_IS_RX_FF_OR
) {
2361 ++sky2
->net_stats
.rx_fifo_errors
;
2362 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2365 if (status
& GM_IS_TX_FF_UR
) {
2366 ++sky2
->net_stats
.tx_fifo_errors
;
2367 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2371 /* This should never happen it is a bug. */
2372 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2373 u16 q
, unsigned ring_size
)
2375 struct net_device
*dev
= hw
->dev
[port
];
2376 struct sky2_port
*sky2
= netdev_priv(dev
);
2378 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2379 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2381 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2382 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2383 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2384 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2386 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2389 /* If idle then force a fake soft NAPI poll once a second
2390 * to work around cases where sharing an edge triggered interrupt.
2392 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2394 if (idle_timeout
> 0)
2395 mod_timer(&hw
->idle_timer
,
2396 jiffies
+ msecs_to_jiffies(idle_timeout
));
2399 static void sky2_idle(unsigned long arg
)
2401 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2402 struct net_device
*dev
= hw
->dev
[0];
2404 if (__netif_rx_schedule_prep(dev
))
2405 __netif_rx_schedule(dev
);
2407 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2410 /* Hardware/software error handling */
2411 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2413 if (net_ratelimit())
2414 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2416 if (status
& Y2_IS_HW_ERR
)
2419 if (status
& Y2_IS_IRQ_MAC1
)
2420 sky2_mac_intr(hw
, 0);
2422 if (status
& Y2_IS_IRQ_MAC2
)
2423 sky2_mac_intr(hw
, 1);
2425 if (status
& Y2_IS_CHK_RX1
)
2426 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2428 if (status
& Y2_IS_CHK_RX2
)
2429 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2431 if (status
& Y2_IS_CHK_TXA1
)
2432 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2434 if (status
& Y2_IS_CHK_TXA2
)
2435 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2438 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2440 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2441 int work_limit
= min(dev0
->quota
, *budget
);
2443 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2445 if (unlikely(status
& Y2_IS_ERROR
))
2446 sky2_err_intr(hw
, status
);
2448 if (status
& Y2_IS_IRQ_PHY1
)
2449 sky2_phy_intr(hw
, 0);
2451 if (status
& Y2_IS_IRQ_PHY2
)
2452 sky2_phy_intr(hw
, 1);
2454 work_done
= sky2_status_intr(hw
, work_limit
);
2455 if (work_done
< work_limit
) {
2456 netif_rx_complete(dev0
);
2458 /* end of interrupt, re-enables also acts as I/O synchronization */
2459 sky2_read32(hw
, B0_Y2_SP_LISR
);
2462 *budget
-= work_done
;
2463 dev0
->quota
-= work_done
;
2468 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2470 struct sky2_hw
*hw
= dev_id
;
2471 struct net_device
*dev0
= hw
->dev
[0];
2474 /* Reading this mask interrupts as side effect */
2475 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2476 if (status
== 0 || status
== ~0)
2479 prefetch(&hw
->st_le
[hw
->st_idx
]);
2480 if (likely(__netif_rx_schedule_prep(dev0
)))
2481 __netif_rx_schedule(dev0
);
2486 #ifdef CONFIG_NET_POLL_CONTROLLER
2487 static void sky2_netpoll(struct net_device
*dev
)
2489 struct sky2_port
*sky2
= netdev_priv(dev
);
2490 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2492 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2493 __netif_rx_schedule(dev0
);
2497 /* Chip internal frequency for clock calculations */
2498 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2500 switch (hw
->chip_id
) {
2501 case CHIP_ID_YUKON_EC
:
2502 case CHIP_ID_YUKON_EC_U
:
2503 case CHIP_ID_YUKON_EX
:
2504 return 125; /* 125 Mhz */
2505 case CHIP_ID_YUKON_FE
:
2506 return 100; /* 100 Mhz */
2507 default: /* YUKON_XL */
2508 return 156; /* 156 Mhz */
2512 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2514 return sky2_mhz(hw
) * us
;
2517 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2519 return clk
/ sky2_mhz(hw
);
2523 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2527 /* Enable all clocks */
2528 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2530 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2532 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2533 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2534 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2539 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2540 dev_warn(&hw
->pdev
->dev
, "this driver not yet tested on this chip type\n"
2541 "Please report success or failure to <netdev@vger.kernel.org>\n");
2543 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2545 /* This rev is really old, and requires untested workarounds */
2546 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2547 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2548 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2549 hw
->chip_id
, hw
->chip_rev
);
2553 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2555 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2556 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2557 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2564 static void sky2_reset(struct sky2_hw
*hw
)
2570 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2571 status
= sky2_read16(hw
, HCU_CCSR
);
2572 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2573 HCU_CCSR_UC_STATE_MSK
);
2574 sky2_write16(hw
, HCU_CCSR
, status
);
2576 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2577 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2580 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2581 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2583 /* clear PCI errors, if any */
2584 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2586 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2587 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2590 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2592 /* clear any PEX errors */
2593 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2594 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2599 for (i
= 0; i
< hw
->ports
; i
++) {
2600 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2601 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2604 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2606 /* Clear I2C IRQ noise */
2607 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2609 /* turn off hardware timer (unused) */
2610 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2611 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2613 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2615 /* Turn off descriptor polling */
2616 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2618 /* Turn off receive timestamp */
2619 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2620 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2622 /* enable the Tx Arbiters */
2623 for (i
= 0; i
< hw
->ports
; i
++)
2624 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2626 /* Initialize ram interface */
2627 for (i
= 0; i
< hw
->ports
; i
++) {
2628 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2630 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2631 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2632 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2633 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2634 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2635 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2636 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2637 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2638 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2639 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2640 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2641 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2644 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2646 for (i
= 0; i
< hw
->ports
; i
++)
2647 sky2_gmac_reset(hw
, i
);
2649 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2652 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2653 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2655 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2656 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2658 /* Set the list last index */
2659 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2661 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2662 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2664 /* set Status-FIFO ISR watermark */
2665 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2666 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2668 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2670 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2671 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2672 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2674 /* enable status unit */
2675 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2677 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2678 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2679 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2682 static void sky2_restart(struct work_struct
*work
)
2684 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2685 struct net_device
*dev
;
2688 dev_dbg(&hw
->pdev
->dev
, "restarting\n");
2690 del_timer_sync(&hw
->idle_timer
);
2693 sky2_write32(hw
, B0_IMSK
, 0);
2694 sky2_read32(hw
, B0_IMSK
);
2696 netif_poll_disable(hw
->dev
[0]);
2698 for (i
= 0; i
< hw
->ports
; i
++) {
2700 if (netif_running(dev
))
2705 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2706 netif_poll_enable(hw
->dev
[0]);
2708 for (i
= 0; i
< hw
->ports
; i
++) {
2710 if (netif_running(dev
)) {
2713 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2720 sky2_idle_start(hw
);
2725 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2727 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2730 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2732 const struct sky2_port
*sky2
= netdev_priv(dev
);
2734 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2735 wol
->wolopts
= sky2
->wol
;
2738 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2740 struct sky2_port
*sky2
= netdev_priv(dev
);
2741 struct sky2_hw
*hw
= sky2
->hw
;
2743 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2746 sky2
->wol
= wol
->wolopts
;
2748 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2749 sky2_write32(hw
, B0_CTST
, sky2
->wol
2750 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2752 if (!netif_running(dev
))
2753 sky2_wol_init(sky2
);
2757 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2759 if (sky2_is_copper(hw
)) {
2760 u32 modes
= SUPPORTED_10baseT_Half
2761 | SUPPORTED_10baseT_Full
2762 | SUPPORTED_100baseT_Half
2763 | SUPPORTED_100baseT_Full
2764 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2766 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2767 modes
|= SUPPORTED_1000baseT_Half
2768 | SUPPORTED_1000baseT_Full
;
2771 return SUPPORTED_1000baseT_Half
2772 | SUPPORTED_1000baseT_Full
2777 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2779 struct sky2_port
*sky2
= netdev_priv(dev
);
2780 struct sky2_hw
*hw
= sky2
->hw
;
2782 ecmd
->transceiver
= XCVR_INTERNAL
;
2783 ecmd
->supported
= sky2_supported_modes(hw
);
2784 ecmd
->phy_address
= PHY_ADDR_MARV
;
2785 if (sky2_is_copper(hw
)) {
2786 ecmd
->supported
= SUPPORTED_10baseT_Half
2787 | SUPPORTED_10baseT_Full
2788 | SUPPORTED_100baseT_Half
2789 | SUPPORTED_100baseT_Full
2790 | SUPPORTED_1000baseT_Half
2791 | SUPPORTED_1000baseT_Full
2792 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2793 ecmd
->port
= PORT_TP
;
2794 ecmd
->speed
= sky2
->speed
;
2796 ecmd
->speed
= SPEED_1000
;
2797 ecmd
->port
= PORT_FIBRE
;
2800 ecmd
->advertising
= sky2
->advertising
;
2801 ecmd
->autoneg
= sky2
->autoneg
;
2802 ecmd
->duplex
= sky2
->duplex
;
2806 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2808 struct sky2_port
*sky2
= netdev_priv(dev
);
2809 const struct sky2_hw
*hw
= sky2
->hw
;
2810 u32 supported
= sky2_supported_modes(hw
);
2812 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2813 ecmd
->advertising
= supported
;
2819 switch (ecmd
->speed
) {
2821 if (ecmd
->duplex
== DUPLEX_FULL
)
2822 setting
= SUPPORTED_1000baseT_Full
;
2823 else if (ecmd
->duplex
== DUPLEX_HALF
)
2824 setting
= SUPPORTED_1000baseT_Half
;
2829 if (ecmd
->duplex
== DUPLEX_FULL
)
2830 setting
= SUPPORTED_100baseT_Full
;
2831 else if (ecmd
->duplex
== DUPLEX_HALF
)
2832 setting
= SUPPORTED_100baseT_Half
;
2838 if (ecmd
->duplex
== DUPLEX_FULL
)
2839 setting
= SUPPORTED_10baseT_Full
;
2840 else if (ecmd
->duplex
== DUPLEX_HALF
)
2841 setting
= SUPPORTED_10baseT_Half
;
2849 if ((setting
& supported
) == 0)
2852 sky2
->speed
= ecmd
->speed
;
2853 sky2
->duplex
= ecmd
->duplex
;
2856 sky2
->autoneg
= ecmd
->autoneg
;
2857 sky2
->advertising
= ecmd
->advertising
;
2859 if (netif_running(dev
))
2860 sky2_phy_reinit(sky2
);
2865 static void sky2_get_drvinfo(struct net_device
*dev
,
2866 struct ethtool_drvinfo
*info
)
2868 struct sky2_port
*sky2
= netdev_priv(dev
);
2870 strcpy(info
->driver
, DRV_NAME
);
2871 strcpy(info
->version
, DRV_VERSION
);
2872 strcpy(info
->fw_version
, "N/A");
2873 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2876 static const struct sky2_stat
{
2877 char name
[ETH_GSTRING_LEN
];
2880 { "tx_bytes", GM_TXO_OK_HI
},
2881 { "rx_bytes", GM_RXO_OK_HI
},
2882 { "tx_broadcast", GM_TXF_BC_OK
},
2883 { "rx_broadcast", GM_RXF_BC_OK
},
2884 { "tx_multicast", GM_TXF_MC_OK
},
2885 { "rx_multicast", GM_RXF_MC_OK
},
2886 { "tx_unicast", GM_TXF_UC_OK
},
2887 { "rx_unicast", GM_RXF_UC_OK
},
2888 { "tx_mac_pause", GM_TXF_MPAUSE
},
2889 { "rx_mac_pause", GM_RXF_MPAUSE
},
2890 { "collisions", GM_TXF_COL
},
2891 { "late_collision",GM_TXF_LAT_COL
},
2892 { "aborted", GM_TXF_ABO_COL
},
2893 { "single_collisions", GM_TXF_SNG_COL
},
2894 { "multi_collisions", GM_TXF_MUL_COL
},
2896 { "rx_short", GM_RXF_SHT
},
2897 { "rx_runt", GM_RXE_FRAG
},
2898 { "rx_64_byte_packets", GM_RXF_64B
},
2899 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2900 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2901 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2902 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2903 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2904 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2905 { "rx_too_long", GM_RXF_LNG_ERR
},
2906 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2907 { "rx_jabber", GM_RXF_JAB_PKT
},
2908 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2910 { "tx_64_byte_packets", GM_TXF_64B
},
2911 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2912 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2913 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2914 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2915 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2916 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2917 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2920 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2922 struct sky2_port
*sky2
= netdev_priv(dev
);
2924 return sky2
->rx_csum
;
2927 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2929 struct sky2_port
*sky2
= netdev_priv(dev
);
2931 sky2
->rx_csum
= data
;
2933 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2934 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2939 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2941 struct sky2_port
*sky2
= netdev_priv(netdev
);
2942 return sky2
->msg_enable
;
2945 static int sky2_nway_reset(struct net_device
*dev
)
2947 struct sky2_port
*sky2
= netdev_priv(dev
);
2949 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2952 sky2_phy_reinit(sky2
);
2957 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2959 struct sky2_hw
*hw
= sky2
->hw
;
2960 unsigned port
= sky2
->port
;
2963 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2964 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2965 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2966 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2968 for (i
= 2; i
< count
; i
++)
2969 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2972 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2974 struct sky2_port
*sky2
= netdev_priv(netdev
);
2975 sky2
->msg_enable
= value
;
2978 static int sky2_get_stats_count(struct net_device
*dev
)
2980 return ARRAY_SIZE(sky2_stats
);
2983 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2984 struct ethtool_stats
*stats
, u64
* data
)
2986 struct sky2_port
*sky2
= netdev_priv(dev
);
2988 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2991 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2995 switch (stringset
) {
2997 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2998 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2999 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3004 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
3006 struct sky2_port
*sky2
= netdev_priv(dev
);
3007 return &sky2
->net_stats
;
3010 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3012 struct sky2_port
*sky2
= netdev_priv(dev
);
3013 struct sky2_hw
*hw
= sky2
->hw
;
3014 unsigned port
= sky2
->port
;
3015 const struct sockaddr
*addr
= p
;
3017 if (!is_valid_ether_addr(addr
->sa_data
))
3018 return -EADDRNOTAVAIL
;
3020 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3021 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3022 dev
->dev_addr
, ETH_ALEN
);
3023 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3024 dev
->dev_addr
, ETH_ALEN
);
3026 /* virtual address for data */
3027 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3029 /* physical address: used for pause frames */
3030 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3035 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3039 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3040 filter
[bit
>> 3] |= 1 << (bit
& 7);
3043 static void sky2_set_multicast(struct net_device
*dev
)
3045 struct sky2_port
*sky2
= netdev_priv(dev
);
3046 struct sky2_hw
*hw
= sky2
->hw
;
3047 unsigned port
= sky2
->port
;
3048 struct dev_mc_list
*list
= dev
->mc_list
;
3052 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3054 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3055 memset(filter
, 0, sizeof(filter
));
3057 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3058 reg
|= GM_RXCR_UCF_ENA
;
3060 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3061 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3062 else if (dev
->flags
& IFF_ALLMULTI
)
3063 memset(filter
, 0xff, sizeof(filter
));
3064 else if (dev
->mc_count
== 0 && !rx_pause
)
3065 reg
&= ~GM_RXCR_MCF_ENA
;
3068 reg
|= GM_RXCR_MCF_ENA
;
3071 sky2_add_filter(filter
, pause_mc_addr
);
3073 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3074 sky2_add_filter(filter
, list
->dmi_addr
);
3077 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3078 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3079 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3080 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3081 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3082 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3083 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3084 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3086 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3089 /* Can have one global because blinking is controlled by
3090 * ethtool and that is always under RTNL mutex
3092 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3096 switch (hw
->chip_id
) {
3097 case CHIP_ID_YUKON_XL
:
3098 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3099 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3100 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3101 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3102 PHY_M_LEDC_INIT_CTRL(7) |
3103 PHY_M_LEDC_STA1_CTRL(7) |
3104 PHY_M_LEDC_STA0_CTRL(7))
3107 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3111 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3112 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3113 on
? PHY_M_LED_ALL
: 0);
3117 /* blink LED's for finding board */
3118 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3120 struct sky2_port
*sky2
= netdev_priv(dev
);
3121 struct sky2_hw
*hw
= sky2
->hw
;
3122 unsigned port
= sky2
->port
;
3123 u16 ledctrl
, ledover
= 0;
3128 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3129 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3133 /* save initial values */
3134 spin_lock_bh(&sky2
->phy_lock
);
3135 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3136 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3137 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3138 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3139 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3141 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3142 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3146 while (!interrupted
&& ms
> 0) {
3147 sky2_led(hw
, port
, onoff
);
3150 spin_unlock_bh(&sky2
->phy_lock
);
3151 interrupted
= msleep_interruptible(250);
3152 spin_lock_bh(&sky2
->phy_lock
);
3157 /* resume regularly scheduled programming */
3158 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3159 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3160 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3161 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3162 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3164 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3165 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3167 spin_unlock_bh(&sky2
->phy_lock
);
3172 static void sky2_get_pauseparam(struct net_device
*dev
,
3173 struct ethtool_pauseparam
*ecmd
)
3175 struct sky2_port
*sky2
= netdev_priv(dev
);
3177 switch (sky2
->flow_mode
) {
3179 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3182 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3185 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3188 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3191 ecmd
->autoneg
= sky2
->autoneg
;
3194 static int sky2_set_pauseparam(struct net_device
*dev
,
3195 struct ethtool_pauseparam
*ecmd
)
3197 struct sky2_port
*sky2
= netdev_priv(dev
);
3199 sky2
->autoneg
= ecmd
->autoneg
;
3200 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3202 if (netif_running(dev
))
3203 sky2_phy_reinit(sky2
);
3208 static int sky2_get_coalesce(struct net_device
*dev
,
3209 struct ethtool_coalesce
*ecmd
)
3211 struct sky2_port
*sky2
= netdev_priv(dev
);
3212 struct sky2_hw
*hw
= sky2
->hw
;
3214 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3215 ecmd
->tx_coalesce_usecs
= 0;
3217 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3218 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3220 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3222 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3223 ecmd
->rx_coalesce_usecs
= 0;
3225 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3226 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3228 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3230 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3231 ecmd
->rx_coalesce_usecs_irq
= 0;
3233 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3234 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3237 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3242 /* Note: this affect both ports */
3243 static int sky2_set_coalesce(struct net_device
*dev
,
3244 struct ethtool_coalesce
*ecmd
)
3246 struct sky2_port
*sky2
= netdev_priv(dev
);
3247 struct sky2_hw
*hw
= sky2
->hw
;
3248 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3250 if (ecmd
->tx_coalesce_usecs
> tmax
||
3251 ecmd
->rx_coalesce_usecs
> tmax
||
3252 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3255 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3257 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3259 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3262 if (ecmd
->tx_coalesce_usecs
== 0)
3263 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3265 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3266 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3267 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3269 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3271 if (ecmd
->rx_coalesce_usecs
== 0)
3272 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3274 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3275 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3276 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3278 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3280 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3281 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3283 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3284 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3285 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3287 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3291 static void sky2_get_ringparam(struct net_device
*dev
,
3292 struct ethtool_ringparam
*ering
)
3294 struct sky2_port
*sky2
= netdev_priv(dev
);
3296 ering
->rx_max_pending
= RX_MAX_PENDING
;
3297 ering
->rx_mini_max_pending
= 0;
3298 ering
->rx_jumbo_max_pending
= 0;
3299 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3301 ering
->rx_pending
= sky2
->rx_pending
;
3302 ering
->rx_mini_pending
= 0;
3303 ering
->rx_jumbo_pending
= 0;
3304 ering
->tx_pending
= sky2
->tx_pending
;
3307 static int sky2_set_ringparam(struct net_device
*dev
,
3308 struct ethtool_ringparam
*ering
)
3310 struct sky2_port
*sky2
= netdev_priv(dev
);
3313 if (ering
->rx_pending
> RX_MAX_PENDING
||
3314 ering
->rx_pending
< 8 ||
3315 ering
->tx_pending
< MAX_SKB_TX_LE
||
3316 ering
->tx_pending
> TX_RING_SIZE
- 1)
3319 if (netif_running(dev
))
3322 sky2
->rx_pending
= ering
->rx_pending
;
3323 sky2
->tx_pending
= ering
->tx_pending
;
3325 if (netif_running(dev
)) {
3330 sky2_set_multicast(dev
);
3336 static int sky2_get_regs_len(struct net_device
*dev
)
3342 * Returns copy of control register region
3343 * Note: ethtool_get_regs always provides full size (16k) buffer
3345 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3348 const struct sky2_port
*sky2
= netdev_priv(dev
);
3349 const void __iomem
*io
= sky2
->hw
->regs
;
3352 memset(p
, 0, regs
->len
);
3354 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3356 /* skip diagnostic ram region */
3357 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
, 0x2000 - B3_RI_WTO_R1
);
3359 /* copy GMAC registers */
3360 memcpy_fromio(p
+ BASE_GMAC_1
, io
+ BASE_GMAC_1
, 0x1000);
3361 if (sky2
->hw
->ports
> 1)
3362 memcpy_fromio(p
+ BASE_GMAC_2
, io
+ BASE_GMAC_2
, 0x1000);
3366 /* In order to do Jumbo packets on these chips, need to turn off the
3367 * transmit store/forward. Therefore checksum offload won't work.
3369 static int no_tx_offload(struct net_device
*dev
)
3371 const struct sky2_port
*sky2
= netdev_priv(dev
);
3372 const struct sky2_hw
*hw
= sky2
->hw
;
3374 return dev
->mtu
> ETH_DATA_LEN
&&
3375 (hw
->chip_id
== CHIP_ID_YUKON_EX
3376 || hw
->chip_id
== CHIP_ID_YUKON_EC_U
);
3379 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3381 if (data
&& no_tx_offload(dev
))
3384 return ethtool_op_set_tx_csum(dev
, data
);
3388 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3390 if (data
&& no_tx_offload(dev
))
3393 return ethtool_op_set_tso(dev
, data
);
3396 static const struct ethtool_ops sky2_ethtool_ops
= {
3397 .get_settings
= sky2_get_settings
,
3398 .set_settings
= sky2_set_settings
,
3399 .get_drvinfo
= sky2_get_drvinfo
,
3400 .get_wol
= sky2_get_wol
,
3401 .set_wol
= sky2_set_wol
,
3402 .get_msglevel
= sky2_get_msglevel
,
3403 .set_msglevel
= sky2_set_msglevel
,
3404 .nway_reset
= sky2_nway_reset
,
3405 .get_regs_len
= sky2_get_regs_len
,
3406 .get_regs
= sky2_get_regs
,
3407 .get_link
= ethtool_op_get_link
,
3408 .get_sg
= ethtool_op_get_sg
,
3409 .set_sg
= ethtool_op_set_sg
,
3410 .get_tx_csum
= ethtool_op_get_tx_csum
,
3411 .set_tx_csum
= sky2_set_tx_csum
,
3412 .get_tso
= ethtool_op_get_tso
,
3413 .set_tso
= sky2_set_tso
,
3414 .get_rx_csum
= sky2_get_rx_csum
,
3415 .set_rx_csum
= sky2_set_rx_csum
,
3416 .get_strings
= sky2_get_strings
,
3417 .get_coalesce
= sky2_get_coalesce
,
3418 .set_coalesce
= sky2_set_coalesce
,
3419 .get_ringparam
= sky2_get_ringparam
,
3420 .set_ringparam
= sky2_set_ringparam
,
3421 .get_pauseparam
= sky2_get_pauseparam
,
3422 .set_pauseparam
= sky2_set_pauseparam
,
3423 .phys_id
= sky2_phys_id
,
3424 .get_stats_count
= sky2_get_stats_count
,
3425 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3426 .get_perm_addr
= ethtool_op_get_perm_addr
,
3429 /* Initialize network device */
3430 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3432 int highmem
, int wol
)
3434 struct sky2_port
*sky2
;
3435 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3438 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3442 SET_MODULE_OWNER(dev
);
3443 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3444 dev
->irq
= hw
->pdev
->irq
;
3445 dev
->open
= sky2_up
;
3446 dev
->stop
= sky2_down
;
3447 dev
->do_ioctl
= sky2_ioctl
;
3448 dev
->hard_start_xmit
= sky2_xmit_frame
;
3449 dev
->get_stats
= sky2_get_stats
;
3450 dev
->set_multicast_list
= sky2_set_multicast
;
3451 dev
->set_mac_address
= sky2_set_mac_address
;
3452 dev
->change_mtu
= sky2_change_mtu
;
3453 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3454 dev
->tx_timeout
= sky2_tx_timeout
;
3455 dev
->watchdog_timeo
= TX_WATCHDOG
;
3457 dev
->poll
= sky2_poll
;
3458 dev
->weight
= NAPI_WEIGHT
;
3459 #ifdef CONFIG_NET_POLL_CONTROLLER
3460 /* Network console (only works on port 0)
3461 * because netpoll makes assumptions about NAPI
3464 dev
->poll_controller
= sky2_netpoll
;
3467 sky2
= netdev_priv(dev
);
3470 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3472 /* Auto speed and flow control */
3473 sky2
->autoneg
= AUTONEG_ENABLE
;
3474 sky2
->flow_mode
= FC_BOTH
;
3478 sky2
->advertising
= sky2_supported_modes(hw
);
3482 spin_lock_init(&sky2
->phy_lock
);
3483 sky2
->tx_pending
= TX_DEF_PENDING
;
3484 sky2
->rx_pending
= RX_DEF_PENDING
;
3486 hw
->dev
[port
] = dev
;
3490 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3492 dev
->features
|= NETIF_F_HIGHDMA
;
3494 #ifdef SKY2_VLAN_TAG_USED
3495 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3496 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3499 /* read the mac address */
3500 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3501 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3503 /* device is off until link detection */
3504 netif_carrier_off(dev
);
3505 netif_stop_queue(dev
);
3510 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3512 const struct sky2_port
*sky2
= netdev_priv(dev
);
3514 if (netif_msg_probe(sky2
))
3515 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3517 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3518 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3521 /* Handle software interrupt used during MSI test */
3522 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3524 struct sky2_hw
*hw
= dev_id
;
3525 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3530 if (status
& Y2_IS_IRQ_SW
) {
3532 wake_up(&hw
->msi_wait
);
3533 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3535 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3540 /* Test interrupt path by forcing a a software IRQ */
3541 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3543 struct pci_dev
*pdev
= hw
->pdev
;
3546 init_waitqueue_head (&hw
->msi_wait
);
3548 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3550 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3552 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3556 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3557 sky2_read8(hw
, B0_CTST
);
3559 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3562 /* MSI test failed, go back to INTx mode */
3563 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
3564 "switching to INTx mode.\n");
3567 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3570 sky2_write32(hw
, B0_IMSK
, 0);
3571 sky2_read32(hw
, B0_IMSK
);
3573 free_irq(pdev
->irq
, hw
);
3578 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3580 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3585 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3587 return value
& PCI_PM_CTRL_PME_ENABLE
;
3590 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3591 const struct pci_device_id
*ent
)
3593 struct net_device
*dev
;
3595 int err
, using_dac
= 0, wol_default
;
3597 err
= pci_enable_device(pdev
);
3599 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
3603 err
= pci_request_regions(pdev
, DRV_NAME
);
3605 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
3606 goto err_out_disable
;
3609 pci_set_master(pdev
);
3611 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3612 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3614 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3616 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
3617 "for consistent allocations\n");
3618 goto err_out_free_regions
;
3621 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3623 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
3624 goto err_out_free_regions
;
3628 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3631 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3633 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
3634 goto err_out_free_regions
;
3639 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3641 dev_err(&pdev
->dev
, "cannot map device registers\n");
3642 goto err_out_free_hw
;
3646 /* The sk98lin vendor driver uses hardware byte swapping but
3647 * this driver uses software swapping.
3651 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3652 reg
&= ~PCI_REV_DESC
;
3653 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3657 /* ring for status responses */
3658 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3661 goto err_out_iounmap
;
3663 err
= sky2_init(hw
);
3665 goto err_out_iounmap
;
3667 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3668 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3669 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3670 hw
->chip_id
, hw
->chip_rev
);
3674 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3677 goto err_out_free_pci
;
3680 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3681 err
= sky2_test_msi(hw
);
3682 if (err
== -EOPNOTSUPP
)
3683 pci_disable_msi(pdev
);
3685 goto err_out_free_netdev
;
3688 err
= register_netdev(dev
);
3690 dev_err(&pdev
->dev
, "cannot register net device\n");
3691 goto err_out_free_netdev
;
3694 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
3697 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
3698 goto err_out_unregister
;
3700 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3702 sky2_show_addr(dev
);
3704 if (hw
->ports
> 1) {
3705 struct net_device
*dev1
;
3707 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
3709 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
3710 else if ((err
= register_netdev(dev1
))) {
3711 dev_warn(&pdev
->dev
,
3712 "register of second port failed (%d)\n", err
);
3716 sky2_show_addr(dev1
);
3719 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3720 INIT_WORK(&hw
->restart_work
, sky2_restart
);
3722 sky2_idle_start(hw
);
3724 pci_set_drvdata(pdev
, hw
);
3730 pci_disable_msi(pdev
);
3731 unregister_netdev(dev
);
3732 err_out_free_netdev
:
3735 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3736 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3741 err_out_free_regions
:
3742 pci_release_regions(pdev
);
3744 pci_disable_device(pdev
);
3746 pci_set_drvdata(pdev
, NULL
);
3750 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3752 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3753 struct net_device
*dev0
, *dev1
;
3758 del_timer_sync(&hw
->idle_timer
);
3760 flush_scheduled_work();
3762 sky2_write32(hw
, B0_IMSK
, 0);
3763 synchronize_irq(hw
->pdev
->irq
);
3768 unregister_netdev(dev1
);
3769 unregister_netdev(dev0
);
3773 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3774 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3775 sky2_read8(hw
, B0_CTST
);
3777 free_irq(pdev
->irq
, hw
);
3779 pci_disable_msi(pdev
);
3780 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3781 pci_release_regions(pdev
);
3782 pci_disable_device(pdev
);
3790 pci_set_drvdata(pdev
, NULL
);
3794 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3796 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3802 del_timer_sync(&hw
->idle_timer
);
3803 netif_poll_disable(hw
->dev
[0]);
3805 for (i
= 0; i
< hw
->ports
; i
++) {
3806 struct net_device
*dev
= hw
->dev
[i
];
3807 struct sky2_port
*sky2
= netdev_priv(dev
);
3809 if (netif_running(dev
))
3813 sky2_wol_init(sky2
);
3818 sky2_write32(hw
, B0_IMSK
, 0);
3821 pci_save_state(pdev
);
3822 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3823 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3828 static int sky2_resume(struct pci_dev
*pdev
)
3830 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3836 err
= pci_set_power_state(pdev
, PCI_D0
);
3840 err
= pci_restore_state(pdev
);
3844 pci_enable_wake(pdev
, PCI_D0
, 0);
3846 /* Re-enable all clocks */
3847 if (hw
->chip_id
== CHIP_ID_YUKON_EX
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
3848 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
3852 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3854 for (i
= 0; i
< hw
->ports
; i
++) {
3855 struct net_device
*dev
= hw
->dev
[i
];
3856 if (netif_running(dev
)) {
3859 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3867 netif_poll_enable(hw
->dev
[0]);
3868 sky2_idle_start(hw
);
3871 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
3872 pci_disable_device(pdev
);
3877 static void sky2_shutdown(struct pci_dev
*pdev
)
3879 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3885 del_timer_sync(&hw
->idle_timer
);
3886 netif_poll_disable(hw
->dev
[0]);
3888 for (i
= 0; i
< hw
->ports
; i
++) {
3889 struct net_device
*dev
= hw
->dev
[i
];
3890 struct sky2_port
*sky2
= netdev_priv(dev
);
3894 sky2_wol_init(sky2
);
3901 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
3902 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
3904 pci_disable_device(pdev
);
3905 pci_set_power_state(pdev
, PCI_D3hot
);
3909 static struct pci_driver sky2_driver
= {
3911 .id_table
= sky2_id_table
,
3912 .probe
= sky2_probe
,
3913 .remove
= __devexit_p(sky2_remove
),
3915 .suspend
= sky2_suspend
,
3916 .resume
= sky2_resume
,
3918 .shutdown
= sky2_shutdown
,
3921 static int __init
sky2_init_module(void)
3923 return pci_register_driver(&sky2_driver
);
3926 static void __exit
sky2_cleanup_module(void)
3928 pci_unregister_driver(&sky2_driver
);
3931 module_init(sky2_init_module
);
3932 module_exit(sky2_cleanup_module
);
3934 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3935 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3936 MODULE_LICENSE("GPL");
3937 MODULE_VERSION(DRV_VERSION
);