drivers/hwmon/lis3lv02d.h

   1 /*
   2  *  lis3lv02d.h - ST LIS3LV02DL accelerometer driver
   3  *
   4  *  Copyright (C) 2007-2008 Yan Burman
   5  *  Copyright (C) 2008 Eric Piel
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/platform_device.h>
  22 #include <linux/input-polldev.h>
  23
  24 /*
  25  * The actual chip is STMicroelectronics LIS3LV02DL or LIS3LV02DQ that seems to
  26  * be connected via SPI. There exists also several similar chips (such as LIS302DL or
  27  * LIS3L02DQ) and they have slightly different registers, but we can provide a
  28  * common interface for all of them.
  29  * They can also be connected via I²C.
  30  */
  31
  32 #include <linux/lis3lv02d.h>
  33
  34 /* 2-byte registers */
  35 #define LIS_DOUBLE_ID   0x3A /* LIS3LV02D[LQ] */
  36 /* 1-byte registers */
  37 #define LIS_SINGLE_ID   0x3B /* LIS[32]02DL and others */
  38
  39 enum lis3_reg {
  40         WHO_AM_I        = 0x0F,
  41         OFFSET_X        = 0x16,
  42         OFFSET_Y        = 0x17,
  43         OFFSET_Z        = 0x18,
  44         GAIN_X          = 0x19,
  45         GAIN_Y          = 0x1A,
  46         GAIN_Z          = 0x1B,
  47         CTRL_REG1       = 0x20,
  48         CTRL_REG2       = 0x21,
  49         CTRL_REG3       = 0x22,
  50         HP_FILTER_RESET = 0x23,
  51         STATUS_REG      = 0x27,
  52         OUTX_L          = 0x28,
  53         OUTX_H          = 0x29,
  54         OUTX            = 0x29,
  55         OUTY_L          = 0x2A,
  56         OUTY_H          = 0x2B,
  57         OUTY            = 0x2B,
  58         OUTZ_L          = 0x2C,
  59         OUTZ_H          = 0x2D,
  60         OUTZ            = 0x2D,
  61         FF_WU_CFG       = 0x30,
  62         FF_WU_SRC       = 0x31,
  63         FF_WU_ACK       = 0x32,
  64         FF_WU_THS_L     = 0x34,
  65         FF_WU_THS_H     = 0x35,
  66         FF_WU_DURATION  = 0x36,
  67 };
  68
  69 enum lis302d_reg {
  70         CLICK_CFG       = 0x38,
  71         CLICK_SRC       = 0x39,
  72         CLICK_THSY_X    = 0x3B,
  73         CLICK_THSZ      = 0x3C,
  74         CLICK_TIMELIMIT = 0x3D,
  75         CLICK_LATENCY   = 0x3E,
  76         CLICK_WINDOW    = 0x3F,
  77 };
  78
  79 enum lis3lv02d_reg {
  80         DD_CFG          = 0x38,
  81         DD_SRC          = 0x39,
  82         DD_ACK          = 0x3A,
  83         DD_THSI_L       = 0x3C,
  84         DD_THSI_H       = 0x3D,
  85         DD_THSE_L       = 0x3E,
  86         DD_THSE_H       = 0x3F,
  87 };
  88
  89 enum lis3lv02d_ctrl1 {
  90         CTRL1_Xen       = 0x01,
  91         CTRL1_Yen       = 0x02,
  92         CTRL1_Zen       = 0x04,
  93         CTRL1_ST        = 0x08,
  94         CTRL1_DF0       = 0x10,
  95         CTRL1_DF1       = 0x20,
  96         CTRL1_PD0       = 0x40,
  97         CTRL1_PD1       = 0x80,
  98 };
  99 enum lis3lv02d_ctrl2 {
 100         CTRL2_DAS       = 0x01,
 101         CTRL2_SIM       = 0x02,
 102         CTRL2_DRDY      = 0x04,
 103         CTRL2_IEN       = 0x08,
 104         CTRL2_BOOT      = 0x10,
 105         CTRL2_BLE       = 0x20,
 106         CTRL2_BDU       = 0x40, /* Block Data Update */
 107         CTRL2_FS        = 0x80, /* Full Scale selection */
 108 };
 109
 110
 111 enum lis3lv02d_ctrl3 {
 112         CTRL3_CFS0      = 0x01,
 113         CTRL3_CFS1      = 0x02,
 114         CTRL3_FDS       = 0x10,
 115         CTRL3_HPFF      = 0x20,
 116         CTRL3_HPDD      = 0x40,
 117         CTRL3_ECK       = 0x80,
 118 };
 119
 120 enum lis3lv02d_status_reg {
 121         STATUS_XDA      = 0x01,
 122         STATUS_YDA      = 0x02,
 123         STATUS_ZDA      = 0x04,
 124         STATUS_XYZDA    = 0x08,
 125         STATUS_XOR      = 0x10,
 126         STATUS_YOR      = 0x20,
 127         STATUS_ZOR      = 0x40,
 128         STATUS_XYZOR    = 0x80,
 129 };
 130
 131 enum lis3lv02d_ff_wu_cfg {
 132         FF_WU_CFG_XLIE  = 0x01,
 133         FF_WU_CFG_XHIE  = 0x02,
 134         FF_WU_CFG_YLIE  = 0x04,
 135         FF_WU_CFG_YHIE  = 0x08,
 136         FF_WU_CFG_ZLIE  = 0x10,
 137         FF_WU_CFG_ZHIE  = 0x20,
 138         FF_WU_CFG_LIR   = 0x40,
 139         FF_WU_CFG_AOI   = 0x80,
 140 };
 141
 142 enum lis3lv02d_ff_wu_src {
 143         FF_WU_SRC_XL    = 0x01,
 144         FF_WU_SRC_XH    = 0x02,
 145         FF_WU_SRC_YL    = 0x04,
 146         FF_WU_SRC_YH    = 0x08,
 147         FF_WU_SRC_ZL    = 0x10,
 148         FF_WU_SRC_ZH    = 0x20,
 149         FF_WU_SRC_IA    = 0x40,
 150 };
 151
 152 enum lis3lv02d_dd_cfg {
 153         DD_CFG_XLIE     = 0x01,
 154         DD_CFG_XHIE     = 0x02,
 155         DD_CFG_YLIE     = 0x04,
 156         DD_CFG_YHIE     = 0x08,
 157         DD_CFG_ZLIE     = 0x10,
 158         DD_CFG_ZHIE     = 0x20,
 159         DD_CFG_LIR      = 0x40,
 160         DD_CFG_IEND     = 0x80,
 161 };
 162
 163 enum lis3lv02d_dd_src {
 164         DD_SRC_XL       = 0x01,
 165         DD_SRC_XH       = 0x02,
 166         DD_SRC_YL       = 0x04,
 167         DD_SRC_YH       = 0x08,
 168         DD_SRC_ZL       = 0x10,
 169         DD_SRC_ZH       = 0x20,
 170         DD_SRC_IA       = 0x40,
 171 };
 172
 173 struct axis_conversion {
 174         s8      x;
 175         s8      y;
 176         s8      z;
 177 };
 178
 179 struct lis3lv02d {
 180         void                    *bus_priv; /* used by the bus layer only */
 181         int (*init) (struct lis3lv02d *lis3);
 182         int (*write) (struct lis3lv02d *lis3, int reg, u8 val);
 183         int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret);
 184
 185         u8                      whoami;    /* 3Ah: 2-byte registries, 3Bh: 1-byte registries */
 186         s16 (*read_data) (struct lis3lv02d *lis3, int reg);
 187         int                     mdps_max_val;
 188
 189         struct input_polled_dev *idev;     /* input device */
 190         struct platform_device  *pdev;     /* platform device */
 191         atomic_t                count;     /* interrupt count after last read */
 192         int                     xcalib;    /* calibrated null value for x */
 193         int                     ycalib;    /* calibrated null value for y */
 194         int                     zcalib;    /* calibrated null value for z */
 195         struct axis_conversion  ac;        /* hw -> logical axis */
 196
 197         u32                     irq;       /* IRQ number */
 198         struct fasync_struct    *async_queue; /* queue for the misc device */
 199         wait_queue_head_t       misc_wait; /* Wait queue for the misc device */
 200         unsigned long           misc_opened; /* bit0: whether the device is open */
 201
 202         struct lis3lv02d_platform_data *pdata;  /* for passing board config */
 203 };
 204
 205 int lis3lv02d_init_device(struct lis3lv02d *lis3);
 206 int lis3lv02d_joystick_enable(void);
 207 void lis3lv02d_joystick_disable(void);
 208 void lis3lv02d_poweroff(struct lis3lv02d *lis3);
 209 void lis3lv02d_poweron(struct lis3lv02d *lis3);
 210 int lis3lv02d_remove_fs(struct lis3lv02d *lis3);
 211
 212 extern struct lis3lv02d lis3_dev;