1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
31 #include "e1000_mac.h"
32 #include "e1000_phy.h"
34 static s32
igb_get_phy_cfg_done(struct e1000_hw
*hw
);
35 static void igb_release_phy(struct e1000_hw
*hw
);
36 static s32
igb_acquire_phy(struct e1000_hw
*hw
);
37 static s32
igb_phy_reset_dsp(struct e1000_hw
*hw
);
38 static s32
igb_phy_setup_autoneg(struct e1000_hw
*hw
);
39 static void igb_phy_force_speed_duplex_setup(struct e1000_hw
*hw
,
41 static s32
igb_wait_autoneg(struct e1000_hw
*hw
);
43 /* Cable length tables */
44 static const u16 e1000_m88_cable_length_table
[] =
45 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
46 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47 (sizeof(e1000_m88_cable_length_table) / \
48 sizeof(e1000_m88_cable_length_table[0]))
50 static const u16 e1000_igp_2_cable_length_table
[] =
51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
52 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
53 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
54 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
55 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
56 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
57 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
58 104, 109, 114, 118, 121, 124};
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 (sizeof(e1000_igp_2_cable_length_table) / \
61 sizeof(e1000_igp_2_cable_length_table[0]))
64 * igb_check_reset_block - Check if PHY reset is blocked
65 * @hw: pointer to the HW structure
67 * Read the PHY management control register and check whether a PHY reset
68 * is blocked. If a reset is not blocked return 0, otherwise
69 * return E1000_BLK_PHY_RESET (12).
71 s32
igb_check_reset_block(struct e1000_hw
*hw
)
75 manc
= rd32(E1000_MANC
);
77 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
78 E1000_BLK_PHY_RESET
: 0;
82 * igb_get_phy_id - Retrieve the PHY ID and revision
83 * @hw: pointer to the HW structure
85 * Reads the PHY registers and stores the PHY ID and possibly the PHY
86 * revision in the hardware structure.
88 s32
igb_get_phy_id(struct e1000_hw
*hw
)
90 struct e1000_phy_info
*phy
= &hw
->phy
;
94 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_ID1
, &phy_id
);
98 phy
->id
= (u32
)(phy_id
<< 16);
100 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_ID2
, &phy_id
);
104 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
105 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
112 * igb_phy_reset_dsp - Reset PHY DSP
113 * @hw: pointer to the HW structure
115 * Reset the digital signal processor.
117 static s32
igb_phy_reset_dsp(struct e1000_hw
*hw
)
121 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
125 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
132 * igb_read_phy_reg_mdic - Read MDI control register
133 * @hw: pointer to the HW structure
134 * @offset: register offset to be read
135 * @data: pointer to the read data
137 * Reads the MDI control regsiter in the PHY at offset and stores the
138 * information read to data.
140 static s32
igb_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
142 struct e1000_phy_info
*phy
= &hw
->phy
;
146 if (offset
> MAX_PHY_REG_ADDRESS
) {
147 hw_dbg("PHY Address %d is out of range\n", offset
);
148 ret_val
= -E1000_ERR_PARAM
;
153 * Set up Op-code, Phy Address, and register offset in the MDI
154 * Control register. The MAC will take care of interfacing with the
155 * PHY to retrieve the desired data.
157 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
158 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
159 (E1000_MDIC_OP_READ
));
161 wr32(E1000_MDIC
, mdic
);
164 * Poll the ready bit to see if the MDI read completed
165 * Increasing the time out as testing showed failures with
168 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
170 mdic
= rd32(E1000_MDIC
);
171 if (mdic
& E1000_MDIC_READY
)
174 if (!(mdic
& E1000_MDIC_READY
)) {
175 hw_dbg("MDI Read did not complete\n");
176 ret_val
= -E1000_ERR_PHY
;
179 if (mdic
& E1000_MDIC_ERROR
) {
180 hw_dbg("MDI Error\n");
181 ret_val
= -E1000_ERR_PHY
;
191 * igb_write_phy_reg_mdic - Write MDI control register
192 * @hw: pointer to the HW structure
193 * @offset: register offset to write to
194 * @data: data to write to register at offset
196 * Writes data to MDI control register in the PHY at offset.
198 static s32
igb_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
200 struct e1000_phy_info
*phy
= &hw
->phy
;
204 if (offset
> MAX_PHY_REG_ADDRESS
) {
205 hw_dbg("PHY Address %d is out of range\n", offset
);
206 ret_val
= -E1000_ERR_PARAM
;
211 * Set up Op-code, Phy Address, and register offset in the MDI
212 * Control register. The MAC will take care of interfacing with the
213 * PHY to retrieve the desired data.
215 mdic
= (((u32
)data
) |
216 (offset
<< E1000_MDIC_REG_SHIFT
) |
217 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
218 (E1000_MDIC_OP_WRITE
));
220 wr32(E1000_MDIC
, mdic
);
223 * Poll the ready bit to see if the MDI read completed
224 * Increasing the time out as testing showed failures with
227 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
229 mdic
= rd32(E1000_MDIC
);
230 if (mdic
& E1000_MDIC_READY
)
233 if (!(mdic
& E1000_MDIC_READY
)) {
234 hw_dbg("MDI Write did not complete\n");
235 ret_val
= -E1000_ERR_PHY
;
238 if (mdic
& E1000_MDIC_ERROR
) {
239 hw_dbg("MDI Error\n");
240 ret_val
= -E1000_ERR_PHY
;
249 * igb_read_phy_reg_igp - Read igp PHY register
250 * @hw: pointer to the HW structure
251 * @offset: register offset to be read
252 * @data: pointer to the read data
254 * Acquires semaphore, if necessary, then reads the PHY register at offset
255 * and storing the retrieved information in data. Release any acquired
256 * semaphores before exiting.
258 s32
igb_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
262 ret_val
= igb_acquire_phy(hw
);
266 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
267 ret_val
= igb_write_phy_reg_mdic(hw
,
268 IGP01E1000_PHY_PAGE_SELECT
,
276 ret_val
= igb_read_phy_reg_mdic(hw
,
277 MAX_PHY_REG_ADDRESS
& offset
,
287 * igb_write_phy_reg_igp - Write igp PHY register
288 * @hw: pointer to the HW structure
289 * @offset: register offset to write to
290 * @data: data to write at register offset
292 * Acquires semaphore, if necessary, then writes the data to PHY register
293 * at the offset. Release any acquired semaphores before exiting.
295 s32
igb_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
299 ret_val
= igb_acquire_phy(hw
);
303 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
304 ret_val
= igb_write_phy_reg_mdic(hw
,
305 IGP01E1000_PHY_PAGE_SELECT
,
313 ret_val
= igb_write_phy_reg_mdic(hw
,
314 MAX_PHY_REG_ADDRESS
& offset
,
324 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
325 * @hw: pointer to the HW structure
327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
328 * and downshift values are set also.
330 s32
igb_copper_link_setup_m88(struct e1000_hw
*hw
)
332 struct e1000_phy_info
*phy
= &hw
->phy
;
336 if (phy
->reset_disable
) {
341 /* Enable CRS on TX. This must be set for half-duplex operation. */
342 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
347 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
351 * MDI/MDI-X = 0 (default)
352 * 0 - Auto for all speeds
355 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
357 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
361 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
364 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
367 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
371 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
377 * disable_polarity_correction = 0 (default)
378 * Automatic Correction for Reversed Cable Polarity
382 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
383 if (phy
->disable_polarity_correction
== 1)
384 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
386 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
391 if (phy
->revision
< E1000_REVISION_4
) {
393 * Force TX_CLK in the Extended PHY Specific Control Register
396 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
,
397 M88E1000_EXT_PHY_SPEC_CTRL
,
402 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
404 if ((phy
->revision
== E1000_REVISION_2
) &&
405 (phy
->id
== M88E1111_I_PHY_ID
)) {
406 /* 82573L PHY - set the downshift counter to 5x. */
407 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
408 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
410 /* Configure Master and Slave downshift values */
411 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
412 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
413 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
414 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
416 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
417 M88E1000_EXT_PHY_SPEC_CTRL
,
423 /* Commit the changes. */
424 ret_val
= igb_phy_sw_reset(hw
);
426 hw_dbg("Error committing the PHY changes\n");
435 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
436 * @hw: pointer to the HW structure
438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
441 s32
igb_copper_link_setup_igp(struct e1000_hw
*hw
)
443 struct e1000_phy_info
*phy
= &hw
->phy
;
447 if (phy
->reset_disable
) {
452 ret_val
= hw
->phy
.ops
.reset_phy(hw
);
454 hw_dbg("Error resetting the PHY.\n");
458 /* Wait 15ms for MAC to configure PHY from NVM settings. */
462 * The NVM settings will configure LPLU in D3 for
465 if (phy
->type
== e1000_phy_igp
) {
466 /* disable lplu d3 during driver init */
467 if (hw
->phy
.ops
.set_d3_lplu_state
)
468 ret_val
= hw
->phy
.ops
.set_d3_lplu_state(hw
, false);
470 hw_dbg("Error Disabling LPLU D3\n");
475 /* disable lplu d0 during driver init */
476 ret_val
= hw
->phy
.ops
.set_d0_lplu_state(hw
, false);
478 hw_dbg("Error Disabling LPLU D0\n");
481 /* Configure mdi-mdix settings */
482 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
486 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
490 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
493 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
497 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
500 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
504 /* set auto-master slave resolution settings */
505 if (hw
->mac
.autoneg
) {
507 * when autonegotiation advertisement is only 1000Mbps then we
508 * should disable SmartSpeed and enable Auto MasterSlave
509 * resolution as hardware default.
511 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
512 /* Disable SmartSpeed */
513 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
,
514 IGP01E1000_PHY_PORT_CONFIG
,
519 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
520 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
521 IGP01E1000_PHY_PORT_CONFIG
,
526 /* Set auto Master/Slave resolution process */
527 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_1000T_CTRL
,
532 data
&= ~CR_1000T_MS_ENABLE
;
533 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, PHY_1000T_CTRL
,
539 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_1000T_CTRL
, &data
);
543 /* load defaults for future use */
544 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
545 ((data
& CR_1000T_MS_VALUE
) ?
546 e1000_ms_force_master
:
547 e1000_ms_force_slave
) :
550 switch (phy
->ms_type
) {
551 case e1000_ms_force_master
:
552 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
554 case e1000_ms_force_slave
:
555 data
|= CR_1000T_MS_ENABLE
;
556 data
&= ~(CR_1000T_MS_VALUE
);
559 data
&= ~CR_1000T_MS_ENABLE
;
563 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, PHY_1000T_CTRL
, data
);
573 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
574 * @hw: pointer to the HW structure
576 * Performs initial bounds checking on autoneg advertisement parameter, then
577 * configure to advertise the full capability. Setup the PHY to autoneg
578 * and restart the negotiation process between the link partner. If
579 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
581 s32
igb_copper_link_autoneg(struct e1000_hw
*hw
)
583 struct e1000_phy_info
*phy
= &hw
->phy
;
588 * Perform some bounds checking on the autoneg advertisement
591 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
594 * If autoneg_advertised is zero, we assume it was not defaulted
595 * by the calling code so we set to advertise full capability.
597 if (phy
->autoneg_advertised
== 0)
598 phy
->autoneg_advertised
= phy
->autoneg_mask
;
600 hw_dbg("Reconfiguring auto-neg advertisement params\n");
601 ret_val
= igb_phy_setup_autoneg(hw
);
603 hw_dbg("Error Setting up Auto-Negotiation\n");
606 hw_dbg("Restarting Auto-Neg\n");
609 * Restart auto-negotiation by setting the Auto Neg Enable bit and
610 * the Auto Neg Restart bit in the PHY control register.
612 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_CONTROL
, &phy_ctrl
);
616 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
617 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, PHY_CONTROL
, phy_ctrl
);
622 * Does the user want to wait for Auto-Neg to complete here, or
623 * check at a later time (for example, callback routine).
625 if (phy
->autoneg_wait_to_complete
) {
626 ret_val
= igb_wait_autoneg(hw
);
628 hw_dbg("Error while waiting for "
629 "autoneg to complete\n");
634 hw
->mac
.get_link_status
= true;
641 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
642 * @hw: pointer to the HW structure
644 * Reads the MII auto-neg advertisement register and/or the 1000T control
645 * register and if the PHY is already setup for auto-negotiation, then
646 * return successful. Otherwise, setup advertisement and flow control to
647 * the appropriate values for the wanted auto-negotiation.
649 static s32
igb_phy_setup_autoneg(struct e1000_hw
*hw
)
651 struct e1000_phy_info
*phy
= &hw
->phy
;
653 u16 mii_autoneg_adv_reg
;
654 u16 mii_1000t_ctrl_reg
= 0;
656 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
658 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
659 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_AUTONEG_ADV
,
660 &mii_autoneg_adv_reg
);
664 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
665 /* Read the MII 1000Base-T Control Register (Address 9). */
666 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
,
668 &mii_1000t_ctrl_reg
);
674 * Need to parse both autoneg_advertised and fc and set up
675 * the appropriate PHY registers. First we will parse for
676 * autoneg_advertised software override. Since we can advertise
677 * a plethora of combinations, we need to check each bit
682 * First we clear all the 10/100 mb speed bits in the Auto-Neg
683 * Advertisement Register (Address 4) and the 1000 mb speed bits in
684 * the 1000Base-T Control Register (Address 9).
686 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
687 NWAY_AR_100TX_HD_CAPS
|
688 NWAY_AR_10T_FD_CAPS
|
689 NWAY_AR_10T_HD_CAPS
);
690 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
692 hw_dbg("autoneg_advertised %x\n", phy
->autoneg_advertised
);
694 /* Do we want to advertise 10 Mb Half Duplex? */
695 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
696 hw_dbg("Advertise 10mb Half duplex\n");
697 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
700 /* Do we want to advertise 10 Mb Full Duplex? */
701 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
702 hw_dbg("Advertise 10mb Full duplex\n");
703 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
706 /* Do we want to advertise 100 Mb Half Duplex? */
707 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
708 hw_dbg("Advertise 100mb Half duplex\n");
709 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
712 /* Do we want to advertise 100 Mb Full Duplex? */
713 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
714 hw_dbg("Advertise 100mb Full duplex\n");
715 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
719 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
720 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
722 /* Do we want to advertise 1000 Mb Full Duplex? */
723 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
724 hw_dbg("Advertise 1000mb Full duplex\n");
725 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
729 * Check for a software override of the flow control settings, and
730 * setup the PHY advertisement registers accordingly. If
731 * auto-negotiation is enabled, then software will have to set the
732 * "PAUSE" bits to the correct value in the Auto-Negotiation
733 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
736 * The possible values of the "fc" parameter are:
737 * 0: Flow control is completely disabled
738 * 1: Rx flow control is enabled (we can receive pause frames
739 * but not send pause frames).
740 * 2: Tx flow control is enabled (we can send pause frames
741 * but we do not support receiving pause frames).
742 * 3: Both Rx and TX flow control (symmetric) are enabled.
743 * other: No software override. The flow control configuration
744 * in the EEPROM is used.
746 switch (hw
->fc
.type
) {
749 * Flow control (RX & TX) is completely disabled by a
750 * software over-ride.
752 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
754 case e1000_fc_rx_pause
:
756 * RX Flow control is enabled, and TX Flow control is
757 * disabled, by a software over-ride.
759 * Since there really isn't a way to advertise that we are
760 * capable of RX Pause ONLY, we will advertise that we
761 * support both symmetric and asymmetric RX PAUSE. Later
762 * (in e1000_config_fc_after_link_up) we will disable the
763 * hw's ability to send PAUSE frames.
765 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
767 case e1000_fc_tx_pause
:
769 * TX Flow control is enabled, and RX Flow control is
770 * disabled, by a software over-ride.
772 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
773 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
777 * Flow control (both RX and TX) is enabled by a software
780 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
783 hw_dbg("Flow control param set incorrectly\n");
784 ret_val
= -E1000_ERR_CONFIG
;
788 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, PHY_AUTONEG_ADV
,
789 mii_autoneg_adv_reg
);
793 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
795 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
796 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
808 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
809 * @hw: pointer to the HW structure
811 * Calls the PHY setup function to force speed and duplex. Clears the
812 * auto-crossover to force MDI manually. Waits for link and returns
813 * successful if link up is successful, else -E1000_ERR_PHY (-2).
815 s32
igb_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
817 struct e1000_phy_info
*phy
= &hw
->phy
;
822 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_CONTROL
, &phy_data
);
826 igb_phy_force_speed_duplex_setup(hw
, &phy_data
);
828 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, PHY_CONTROL
, phy_data
);
833 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
834 * forced whenever speed and duplex are forced.
836 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
,
841 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
842 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
844 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
,
849 hw_dbg("IGP PSCR: %X\n", phy_data
);
853 if (phy
->autoneg_wait_to_complete
) {
854 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
856 ret_val
= igb_phy_has_link(hw
,
864 hw_dbg("Link taking longer than expected.\n");
867 ret_val
= igb_phy_has_link(hw
,
880 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
881 * @hw: pointer to the HW structure
883 * Calls the PHY setup function to force speed and duplex. Clears the
884 * auto-crossover to force MDI manually. Resets the PHY to commit the
885 * changes. If time expires while waiting for link up, we reset the DSP.
886 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
887 * successful completion, else return corresponding error code.
889 s32
igb_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
891 struct e1000_phy_info
*phy
= &hw
->phy
;
897 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
898 * forced whenever speed and duplex are forced.
900 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
905 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
906 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
911 hw_dbg("M88E1000 PSCR: %X\n", phy_data
);
913 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_CONTROL
, &phy_data
);
917 igb_phy_force_speed_duplex_setup(hw
, &phy_data
);
919 /* Reset the phy to commit changes. */
920 phy_data
|= MII_CR_RESET
;
922 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, PHY_CONTROL
, phy_data
);
928 if (phy
->autoneg_wait_to_complete
) {
929 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
931 ret_val
= igb_phy_has_link(hw
,
940 * We didn't get link.
941 * Reset the DSP and cross our fingers.
943 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
944 M88E1000_PHY_PAGE_SELECT
,
948 ret_val
= igb_phy_reset_dsp(hw
);
954 ret_val
= igb_phy_has_link(hw
, PHY_FORCE_LIMIT
,
960 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
966 * Resetting the phy means we need to re-force TX_CLK in the
967 * Extended PHY Specific Control Register to 25MHz clock from
968 * the reset value of 2.5MHz.
970 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
971 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
977 * In addition, we must re-enable CRS on Tx for both half and full
980 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
985 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
986 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
994 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
995 * @hw: pointer to the HW structure
996 * @phy_ctrl: pointer to current value of PHY_CONTROL
998 * Forces speed and duplex on the PHY by doing the following: disable flow
999 * control, force speed/duplex on the MAC, disable auto speed detection,
1000 * disable auto-negotiation, configure duplex, configure speed, configure
1001 * the collision distance, write configuration to CTRL register. The
1002 * caller must write to the PHY_CONTROL register for these settings to
1005 static void igb_phy_force_speed_duplex_setup(struct e1000_hw
*hw
,
1008 struct e1000_mac_info
*mac
= &hw
->mac
;
1011 /* Turn off flow control when forcing speed/duplex */
1012 hw
->fc
.type
= e1000_fc_none
;
1014 /* Force speed/duplex on the mac */
1015 ctrl
= rd32(E1000_CTRL
);
1016 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1017 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1019 /* Disable Auto Speed Detection */
1020 ctrl
&= ~E1000_CTRL_ASDE
;
1022 /* Disable autoneg on the phy */
1023 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1025 /* Forcing Full or Half Duplex? */
1026 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1027 ctrl
&= ~E1000_CTRL_FD
;
1028 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1029 hw_dbg("Half Duplex\n");
1031 ctrl
|= E1000_CTRL_FD
;
1032 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1033 hw_dbg("Full Duplex\n");
1036 /* Forcing 10mb or 100mb? */
1037 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1038 ctrl
|= E1000_CTRL_SPD_100
;
1039 *phy_ctrl
|= MII_CR_SPEED_100
;
1040 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1041 hw_dbg("Forcing 100mb\n");
1043 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1044 *phy_ctrl
|= MII_CR_SPEED_10
;
1045 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1046 hw_dbg("Forcing 10mb\n");
1049 igb_config_collision_dist(hw
);
1051 wr32(E1000_CTRL
, ctrl
);
1055 * igb_set_d3_lplu_state - Sets low power link up state for D3
1056 * @hw: pointer to the HW structure
1057 * @active: boolean used to enable/disable lplu
1059 * Success returns 0, Failure returns 1
1061 * The low power link up (lplu) state is set to the power management level D3
1062 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1063 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1064 * is used during Dx states where the power conservation is most important.
1065 * During driver activity, SmartSpeed should be enabled so performance is
1068 s32
igb_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
1070 struct e1000_phy_info
*phy
= &hw
->phy
;
1074 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
1080 data
&= ~IGP02E1000_PM_D3_LPLU
;
1081 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
1082 IGP02E1000_PHY_POWER_MGMT
,
1087 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1088 * during Dx states where the power conservation is most
1089 * important. During driver activity we should enable
1090 * SmartSpeed, so performance is maintained.
1092 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1093 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
,
1094 IGP01E1000_PHY_PORT_CONFIG
,
1099 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1100 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
1101 IGP01E1000_PHY_PORT_CONFIG
,
1105 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1106 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
,
1107 IGP01E1000_PHY_PORT_CONFIG
,
1112 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1113 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
1114 IGP01E1000_PHY_PORT_CONFIG
,
1119 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1120 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1121 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1122 data
|= IGP02E1000_PM_D3_LPLU
;
1123 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
1124 IGP02E1000_PHY_POWER_MGMT
,
1129 /* When LPLU is enabled, we should disable SmartSpeed */
1130 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
,
1131 IGP01E1000_PHY_PORT_CONFIG
,
1136 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1137 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
,
1138 IGP01E1000_PHY_PORT_CONFIG
,
1147 * igb_check_downshift - Checks whether a downshift in speed occured
1148 * @hw: pointer to the HW structure
1150 * Success returns 0, Failure returns 1
1152 * A downshift is detected by querying the PHY link health.
1154 s32
igb_check_downshift(struct e1000_hw
*hw
)
1156 struct e1000_phy_info
*phy
= &hw
->phy
;
1158 u16 phy_data
, offset
, mask
;
1160 switch (phy
->type
) {
1162 case e1000_phy_gg82563
:
1163 offset
= M88E1000_PHY_SPEC_STATUS
;
1164 mask
= M88E1000_PSSR_DOWNSHIFT
;
1166 case e1000_phy_igp_2
:
1168 case e1000_phy_igp_3
:
1169 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1170 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1173 /* speed downshift not supported */
1174 phy
->speed_downgraded
= false;
1179 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, offset
, &phy_data
);
1182 phy
->speed_downgraded
= (phy_data
& mask
) ? true : false;
1189 * igb_check_polarity_m88 - Checks the polarity.
1190 * @hw: pointer to the HW structure
1192 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1194 * Polarity is determined based on the PHY specific status register.
1196 static s32
igb_check_polarity_m88(struct e1000_hw
*hw
)
1198 struct e1000_phy_info
*phy
= &hw
->phy
;
1202 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1205 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1206 ? e1000_rev_polarity_reversed
1207 : e1000_rev_polarity_normal
;
1213 * igb_check_polarity_igp - Checks the polarity.
1214 * @hw: pointer to the HW structure
1216 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1218 * Polarity is determined based on the PHY port status register, and the
1219 * current speed (since there is no polarity at 100Mbps).
1221 static s32
igb_check_polarity_igp(struct e1000_hw
*hw
)
1223 struct e1000_phy_info
*phy
= &hw
->phy
;
1225 u16 data
, offset
, mask
;
1228 * Polarity is determined based on the speed of
1231 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
,
1236 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1237 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1238 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1239 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1242 * This really only applies to 10Mbps since
1243 * there is no polarity for 100Mbps (always 0).
1245 offset
= IGP01E1000_PHY_PORT_STATUS
;
1246 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1249 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, offset
, &data
);
1252 phy
->cable_polarity
= (data
& mask
)
1253 ? e1000_rev_polarity_reversed
1254 : e1000_rev_polarity_normal
;
1261 * igb_wait_autoneg - Wait for auto-neg compeletion
1262 * @hw: pointer to the HW structure
1264 * Waits for auto-negotiation to complete or for the auto-negotiation time
1265 * limit to expire, which ever happens first.
1267 static s32
igb_wait_autoneg(struct e1000_hw
*hw
)
1272 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1273 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1274 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_STATUS
, &phy_status
);
1277 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_STATUS
, &phy_status
);
1280 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1286 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1293 * igb_phy_has_link - Polls PHY for link
1294 * @hw: pointer to the HW structure
1295 * @iterations: number of times to poll for link
1296 * @usec_interval: delay between polling attempts
1297 * @success: pointer to whether polling was successful or not
1299 * Polls the PHY status register for link, 'iterations' number of times.
1301 s32
igb_phy_has_link(struct e1000_hw
*hw
, u32 iterations
,
1302 u32 usec_interval
, bool *success
)
1307 for (i
= 0; i
< iterations
; i
++) {
1309 * Some PHYs require the PHY_STATUS register to be read
1310 * twice due to the link bit being sticky. No harm doing
1311 * it across the board.
1313 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_STATUS
, &phy_status
);
1316 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_STATUS
, &phy_status
);
1319 if (phy_status
& MII_SR_LINK_STATUS
)
1321 if (usec_interval
>= 1000)
1322 mdelay(usec_interval
/1000);
1324 udelay(usec_interval
);
1327 *success
= (i
< iterations
) ? true : false;
1333 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1334 * @hw: pointer to the HW structure
1336 * Reads the PHY specific status register to retrieve the cable length
1337 * information. The cable length is determined by averaging the minimum and
1338 * maximum values to get the "average" cable length. The m88 PHY has four
1339 * possible cable length values, which are:
1340 * Register Value Cable Length
1344 * 3 110 - 140 meters
1347 s32
igb_get_cable_length_m88(struct e1000_hw
*hw
)
1349 struct e1000_phy_info
*phy
= &hw
->phy
;
1351 u16 phy_data
, index
;
1353 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
1358 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
1359 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
1360 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
1361 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+1];
1363 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1370 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1371 * @hw: pointer to the HW structure
1373 * The automatic gain control (agc) normalizes the amplitude of the
1374 * received signal, adjusting for the attenuation produced by the
1375 * cable. By reading the AGC registers, which reperesent the
1376 * cobination of course and fine gain value, the value can be put
1377 * into a lookup table to obtain the approximate cable length
1380 s32
igb_get_cable_length_igp_2(struct e1000_hw
*hw
)
1382 struct e1000_phy_info
*phy
= &hw
->phy
;
1384 u16 phy_data
, i
, agc_value
= 0;
1385 u16 cur_agc_index
, max_agc_index
= 0;
1386 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
1387 u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
1388 {IGP02E1000_PHY_AGC_A
,
1389 IGP02E1000_PHY_AGC_B
,
1390 IGP02E1000_PHY_AGC_C
,
1391 IGP02E1000_PHY_AGC_D
};
1393 /* Read the AGC registers for all channels */
1394 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
1395 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, agc_reg_array
[i
],
1401 * Getting bits 15:9, which represent the combination of
1402 * course and fine gain values. The result is a number
1403 * that can be put into the lookup table to obtain the
1404 * approximate cable length.
1406 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
1407 IGP02E1000_AGC_LENGTH_MASK
;
1409 /* Array index bound check. */
1410 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
1411 (cur_agc_index
== 0)) {
1412 ret_val
= -E1000_ERR_PHY
;
1416 /* Remove min & max AGC values from calculation. */
1417 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
1418 e1000_igp_2_cable_length_table
[cur_agc_index
])
1419 min_agc_index
= cur_agc_index
;
1420 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
1421 e1000_igp_2_cable_length_table
[cur_agc_index
])
1422 max_agc_index
= cur_agc_index
;
1424 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
1427 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
1428 e1000_igp_2_cable_length_table
[max_agc_index
]);
1429 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
1431 /* Calculate cable length with the error range of +/- 10 meters. */
1432 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
1433 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
1434 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
1436 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1443 * igb_get_phy_info_m88 - Retrieve PHY information
1444 * @hw: pointer to the HW structure
1446 * Valid for only copper links. Read the PHY status register (sticky read)
1447 * to verify that link is up. Read the PHY special control register to
1448 * determine the polarity and 10base-T extended distance. Read the PHY
1449 * special status register to determine MDI/MDIx and current speed. If
1450 * speed is 1000, then determine cable length, local and remote receiver.
1452 s32
igb_get_phy_info_m88(struct e1000_hw
*hw
)
1454 struct e1000_phy_info
*phy
= &hw
->phy
;
1459 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1460 hw_dbg("Phy info is only valid for copper media\n");
1461 ret_val
= -E1000_ERR_CONFIG
;
1465 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
1470 hw_dbg("Phy info is only valid if link is up\n");
1471 ret_val
= -E1000_ERR_CONFIG
;
1475 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
1480 phy
->polarity_correction
= (phy_data
& M88E1000_PSCR_POLARITY_REVERSAL
)
1484 ret_val
= igb_check_polarity_m88(hw
);
1488 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
1493 phy
->is_mdix
= (phy_data
& M88E1000_PSSR_MDIX
) ? true : false;
1495 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
1496 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
1500 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_1000T_STATUS
,
1505 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
1506 ? e1000_1000t_rx_status_ok
1507 : e1000_1000t_rx_status_not_ok
;
1509 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
1510 ? e1000_1000t_rx_status_ok
1511 : e1000_1000t_rx_status_not_ok
;
1513 /* Set values to "undefined" */
1514 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1515 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1516 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1524 * igb_get_phy_info_igp - Retrieve igp PHY information
1525 * @hw: pointer to the HW structure
1527 * Read PHY status to determine if link is up. If link is up, then
1528 * set/determine 10base-T extended distance and polarity correction. Read
1529 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1530 * determine on the cable length, local and remote receiver.
1532 s32
igb_get_phy_info_igp(struct e1000_hw
*hw
)
1534 struct e1000_phy_info
*phy
= &hw
->phy
;
1539 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
1544 hw_dbg("Phy info is only valid if link is up\n");
1545 ret_val
= -E1000_ERR_CONFIG
;
1549 phy
->polarity_correction
= true;
1551 ret_val
= igb_check_polarity_igp(hw
);
1555 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
,
1560 phy
->is_mdix
= (data
& IGP01E1000_PSSR_MDIX
) ? true : false;
1562 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1563 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1564 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
1568 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_1000T_STATUS
,
1573 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
1574 ? e1000_1000t_rx_status_ok
1575 : e1000_1000t_rx_status_not_ok
;
1577 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
1578 ? e1000_1000t_rx_status_ok
1579 : e1000_1000t_rx_status_not_ok
;
1581 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1582 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1583 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1591 * igb_phy_sw_reset - PHY software reset
1592 * @hw: pointer to the HW structure
1594 * Does a software reset of the PHY by reading the PHY control register and
1595 * setting/write the control register reset bit to the PHY.
1597 s32
igb_phy_sw_reset(struct e1000_hw
*hw
)
1602 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_CONTROL
, &phy_ctrl
);
1606 phy_ctrl
|= MII_CR_RESET
;
1607 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, PHY_CONTROL
, phy_ctrl
);
1618 * igb_phy_hw_reset - PHY hardware reset
1619 * @hw: pointer to the HW structure
1621 * Verify the reset block is not blocking us from resetting. Acquire
1622 * semaphore (if necessary) and read/set/write the device control reset
1623 * bit in the PHY. Wait the appropriate delay time for the device to
1624 * reset and relase the semaphore (if necessary).
1626 s32
igb_phy_hw_reset(struct e1000_hw
*hw
)
1628 struct e1000_phy_info
*phy
= &hw
->phy
;
1632 ret_val
= igb_check_reset_block(hw
);
1638 ret_val
= igb_acquire_phy(hw
);
1642 ctrl
= rd32(E1000_CTRL
);
1643 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
1646 udelay(phy
->reset_delay_us
);
1648 wr32(E1000_CTRL
, ctrl
);
1653 igb_release_phy(hw
);
1655 ret_val
= igb_get_phy_cfg_done(hw
);
1661 /* Internal function pointers */
1664 * igb_get_phy_cfg_done - Generic PHY configuration done
1665 * @hw: pointer to the HW structure
1667 * Return success if silicon family did not implement a family specific
1668 * get_cfg_done function.
1670 static s32
igb_get_phy_cfg_done(struct e1000_hw
*hw
)
1672 if (hw
->phy
.ops
.get_cfg_done
)
1673 return hw
->phy
.ops
.get_cfg_done(hw
);
1679 * igb_release_phy - Generic release PHY
1680 * @hw: pointer to the HW structure
1682 * Return if silicon family does not require a semaphore when accessing the
1685 static void igb_release_phy(struct e1000_hw
*hw
)
1687 if (hw
->phy
.ops
.release_phy
)
1688 hw
->phy
.ops
.release_phy(hw
);
1692 * igb_acquire_phy - Generic acquire PHY
1693 * @hw: pointer to the HW structure
1695 * Return success if silicon family does not require a semaphore when
1696 * accessing the PHY.
1698 static s32
igb_acquire_phy(struct e1000_hw
*hw
)
1700 if (hw
->phy
.ops
.acquire_phy
)
1701 return hw
->phy
.ops
.acquire_phy(hw
);
1707 * igb_phy_force_speed_duplex - Generic force PHY speed/duplex
1708 * @hw: pointer to the HW structure
1710 * When the silicon family has not implemented a forced speed/duplex
1711 * function for the PHY, simply return 0.
1713 s32
igb_phy_force_speed_duplex(struct e1000_hw
*hw
)
1715 if (hw
->phy
.ops
.force_speed_duplex
)
1716 return hw
->phy
.ops
.force_speed_duplex(hw
);
1722 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
1723 * @hw: pointer to the HW structure
1725 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1727 s32
igb_phy_init_script_igp3(struct e1000_hw
*hw
)
1729 hw_dbg("Running IGP 3 PHY init script\n");
1731 /* PHY init IGP 3 */
1732 /* Enable rise/fall, 10-mode work in class-A */
1733 hw
->phy
.ops
.write_phy_reg(hw
, 0x2F5B, 0x9018);
1734 /* Remove all caps from Replica path filter */
1735 hw
->phy
.ops
.write_phy_reg(hw
, 0x2F52, 0x0000);
1736 /* Bias trimming for ADC, AFE and Driver (Default) */
1737 hw
->phy
.ops
.write_phy_reg(hw
, 0x2FB1, 0x8B24);
1738 /* Increase Hybrid poly bias */
1739 hw
->phy
.ops
.write_phy_reg(hw
, 0x2FB2, 0xF8F0);
1740 /* Add 4% to TX amplitude in Giga mode */
1741 hw
->phy
.ops
.write_phy_reg(hw
, 0x2010, 0x10B0);
1742 /* Disable trimming (TTT) */
1743 hw
->phy
.ops
.write_phy_reg(hw
, 0x2011, 0x0000);
1744 /* Poly DC correction to 94.6% + 2% for all channels */
1745 hw
->phy
.ops
.write_phy_reg(hw
, 0x20DD, 0x249A);
1746 /* ABS DC correction to 95.9% */
1747 hw
->phy
.ops
.write_phy_reg(hw
, 0x20DE, 0x00D3);
1748 /* BG temp curve trim */
1749 hw
->phy
.ops
.write_phy_reg(hw
, 0x28B4, 0x04CE);
1750 /* Increasing ADC OPAMP stage 1 currents to max */
1751 hw
->phy
.ops
.write_phy_reg(hw
, 0x2F70, 0x29E4);
1752 /* Force 1000 ( required for enabling PHY regs configuration) */
1753 hw
->phy
.ops
.write_phy_reg(hw
, 0x0000, 0x0140);
1754 /* Set upd_freq to 6 */
1755 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F30, 0x1606);
1757 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F31, 0xB814);
1758 /* Disable adaptive fixed FFE (Default) */
1759 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F35, 0x002A);
1760 /* Enable FFE hysteresis */
1761 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F3E, 0x0067);
1762 /* Fixed FFE for short cable lengths */
1763 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F54, 0x0065);
1764 /* Fixed FFE for medium cable lengths */
1765 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F55, 0x002A);
1766 /* Fixed FFE for long cable lengths */
1767 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F56, 0x002A);
1768 /* Enable Adaptive Clip Threshold */
1769 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F72, 0x3FB0);
1770 /* AHT reset limit to 1 */
1771 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F76, 0xC0FF);
1772 /* Set AHT master delay to 127 msec */
1773 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F77, 0x1DEC);
1774 /* Set scan bits for AHT */
1775 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F78, 0xF9EF);
1776 /* Set AHT Preset bits */
1777 hw
->phy
.ops
.write_phy_reg(hw
, 0x1F79, 0x0210);
1778 /* Change integ_factor of channel A to 3 */
1779 hw
->phy
.ops
.write_phy_reg(hw
, 0x1895, 0x0003);
1780 /* Change prop_factor of channels BCD to 8 */
1781 hw
->phy
.ops
.write_phy_reg(hw
, 0x1796, 0x0008);
1782 /* Change cg_icount + enable integbp for channels BCD */
1783 hw
->phy
.ops
.write_phy_reg(hw
, 0x1798, 0xD008);
1785 * Change cg_icount + enable integbp + change prop_factor_master
1786 * to 8 for channel A
1788 hw
->phy
.ops
.write_phy_reg(hw
, 0x1898, 0xD918);
1789 /* Disable AHT in Slave mode on channel A */
1790 hw
->phy
.ops
.write_phy_reg(hw
, 0x187A, 0x0800);
1792 * Enable LPLU and disable AN to 1000 in non-D0a states,
1795 hw
->phy
.ops
.write_phy_reg(hw
, 0x0019, 0x008D);
1796 /* Enable restart AN on an1000_dis change */
1797 hw
->phy
.ops
.write_phy_reg(hw
, 0x001B, 0x2080);
1798 /* Enable wh_fifo read clock in 10/100 modes */
1799 hw
->phy
.ops
.write_phy_reg(hw
, 0x0014, 0x0045);
1800 /* Restart AN, Speed selection is 1000 */
1801 hw
->phy
.ops
.write_phy_reg(hw
, 0x0000, 0x1340);