?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
AMD IOMMU: add statistics about total number of map requests
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / amd_iommu.c
blob0c504b207bf97a2d31f4327fe64099619b0bd5f7
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
28 #endif
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
47 #endif
48
49 /*
50 * general struct to manage commands send to an IOMMU
51 */
52 struct iommu_cmd {
53 u32 data[4];
54 };
55
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
59
60
61 #ifdef CONFIG_AMD_IOMMU_STATS
62
63 /*
64 * Initialization code for statistics collection
65 */
66
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69 DECLARE_STATS_COUNTER(cnt_unmap_single);
70 DECLARE_STATS_COUNTER(cnt_map_sg);
71 DECLARE_STATS_COUNTER(cnt_unmap_sg);
72 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
73 DECLARE_STATS_COUNTER(cnt_free_coherent);
74 DECLARE_STATS_COUNTER(cross_page);
75 DECLARE_STATS_COUNTER(domain_flush_single);
76 DECLARE_STATS_COUNTER(domain_flush_all);
77 DECLARE_STATS_COUNTER(alloced_io_mem);
78 DECLARE_STATS_COUNTER(total_map_requests);
79
80 static struct dentry *stats_dir;
81 static struct dentry *de_isolate;
82 static struct dentry *de_fflush;
83
84 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
85 {
86 if (stats_dir == NULL)
87 return;
88
89 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
90 &cnt->value);
91 }
92
93 static void amd_iommu_stats_init(void)
94 {
95 stats_dir = debugfs_create_dir("amd-iommu", NULL);
96 if (stats_dir == NULL)
97 return;
98
99 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
100 (u32 *)&amd_iommu_isolate);
101
102 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
103 (u32 *)&amd_iommu_unmap_flush);
104
105 amd_iommu_stats_add(&compl_wait);
106 amd_iommu_stats_add(&cnt_map_single);
107 amd_iommu_stats_add(&cnt_unmap_single);
108 amd_iommu_stats_add(&cnt_map_sg);
109 amd_iommu_stats_add(&cnt_unmap_sg);
110 amd_iommu_stats_add(&cnt_alloc_coherent);
111 amd_iommu_stats_add(&cnt_free_coherent);
112 amd_iommu_stats_add(&cross_page);
113 amd_iommu_stats_add(&domain_flush_single);
114 amd_iommu_stats_add(&domain_flush_all);
115 amd_iommu_stats_add(&alloced_io_mem);
116 amd_iommu_stats_add(&total_map_requests);
117 }
118
119 #endif
120
121 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
122 static int iommu_has_npcache(struct amd_iommu *iommu)
123 {
124 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
125 }
126
127 /****************************************************************************
128 *
129 * Interrupt handling functions
130 *
131 ****************************************************************************/
132
133 static void iommu_print_event(void *__evt)
134 {
135 u32 *event = __evt;
136 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
137 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
138 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
139 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
140 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
141
142 printk(KERN_ERR "AMD IOMMU: Event logged [");
143
144 switch (type) {
145 case EVENT_TYPE_ILL_DEV:
146 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
147 "address=0x%016llx flags=0x%04x]\n",
148 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
149 address, flags);
150 break;
151 case EVENT_TYPE_IO_FAULT:
152 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
153 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
154 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
155 domid, address, flags);
156 break;
157 case EVENT_TYPE_DEV_TAB_ERR:
158 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
159 "address=0x%016llx flags=0x%04x]\n",
160 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
161 address, flags);
162 break;
163 case EVENT_TYPE_PAGE_TAB_ERR:
164 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
165 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
166 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
167 domid, address, flags);
168 break;
169 case EVENT_TYPE_ILL_CMD:
170 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
171 break;
172 case EVENT_TYPE_CMD_HARD_ERR:
173 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
174 "flags=0x%04x]\n", address, flags);
175 break;
176 case EVENT_TYPE_IOTLB_INV_TO:
177 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
178 "address=0x%016llx]\n",
179 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
180 address);
181 break;
182 case EVENT_TYPE_INV_DEV_REQ:
183 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
184 "address=0x%016llx flags=0x%04x]\n",
185 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
186 address, flags);
187 break;
188 default:
189 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
190 }
191 }
192
193 static void iommu_poll_events(struct amd_iommu *iommu)
194 {
195 u32 head, tail;
196 unsigned long flags;
197
198 spin_lock_irqsave(&iommu->lock, flags);
199
200 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
201 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
202
203 while (head != tail) {
204 iommu_print_event(iommu->evt_buf + head);
205 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
206 }
207
208 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
209
210 spin_unlock_irqrestore(&iommu->lock, flags);
211 }
212
213 irqreturn_t amd_iommu_int_handler(int irq, void *data)
214 {
215 struct amd_iommu *iommu;
216
217 list_for_each_entry(iommu, &amd_iommu_list, list)
218 iommu_poll_events(iommu);
219
220 return IRQ_HANDLED;
221 }
222
223 /****************************************************************************
224 *
225 * IOMMU command queuing functions
226 *
227 ****************************************************************************/
228
229 /*
230 * Writes the command to the IOMMUs command buffer and informs the
231 * hardware about the new command. Must be called with iommu->lock held.
232 */
233 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
234 {
235 u32 tail, head;
236 u8 *target;
237
238 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
239 target = iommu->cmd_buf + tail;
240 memcpy_toio(target, cmd, sizeof(*cmd));
241 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
242 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
243 if (tail == head)
244 return -ENOMEM;
245 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
246
247 return 0;
248 }
249
250 /*
251 * General queuing function for commands. Takes iommu->lock and calls
252 * __iommu_queue_command().
253 */
254 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
255 {
256 unsigned long flags;
257 int ret;
258
259 spin_lock_irqsave(&iommu->lock, flags);
260 ret = __iommu_queue_command(iommu, cmd);
261 if (!ret)
262 iommu->need_sync = true;
263 spin_unlock_irqrestore(&iommu->lock, flags);
264
265 return ret;
266 }
267
268 /*
269 * This function waits until an IOMMU has completed a completion
270 * wait command
271 */
272 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
273 {
274 int ready = 0;
275 unsigned status = 0;
276 unsigned long i = 0;
277
278 INC_STATS_COUNTER(compl_wait);
279
280 while (!ready && (i < EXIT_LOOP_COUNT)) {
281 ++i;
282 /* wait for the bit to become one */
283 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
284 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
285 }
286
287 /* set bit back to zero */
288 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
289 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
290
291 if (unlikely(i == EXIT_LOOP_COUNT))
292 panic("AMD IOMMU: Completion wait loop failed\n");
293 }
294
295 /*
296 * This function queues a completion wait command into the command
297 * buffer of an IOMMU
298 */
299 static int __iommu_completion_wait(struct amd_iommu *iommu)
300 {
301 struct iommu_cmd cmd;
302
303 memset(&cmd, 0, sizeof(cmd));
304 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
305 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
306
307 return __iommu_queue_command(iommu, &cmd);
308 }
309
310 /*
311 * This function is called whenever we need to ensure that the IOMMU has
312 * completed execution of all commands we sent. It sends a
313 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
314 * us about that by writing a value to a physical address we pass with
315 * the command.
316 */
317 static int iommu_completion_wait(struct amd_iommu *iommu)
318 {
319 int ret = 0;
320 unsigned long flags;
321
322 spin_lock_irqsave(&iommu->lock, flags);
323
324 if (!iommu->need_sync)
325 goto out;
326
327 ret = __iommu_completion_wait(iommu);
328
329 iommu->need_sync = false;
330
331 if (ret)
332 goto out;
333
334 __iommu_wait_for_completion(iommu);
335
336 out:
337 spin_unlock_irqrestore(&iommu->lock, flags);
338
339 return 0;
340 }
341
342 /*
343 * Command send function for invalidating a device table entry
344 */
345 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
346 {
347 struct iommu_cmd cmd;
348 int ret;
349
350 BUG_ON(iommu == NULL);
351
352 memset(&cmd, 0, sizeof(cmd));
353 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
354 cmd.data[0] = devid;
355
356 ret = iommu_queue_command(iommu, &cmd);
357
358 return ret;
359 }
360
361 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
362 u16 domid, int pde, int s)
363 {
364 memset(cmd, 0, sizeof(*cmd));
365 address &= PAGE_MASK;
366 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
367 cmd->data[1] |= domid;
368 cmd->data[2] = lower_32_bits(address);
369 cmd->data[3] = upper_32_bits(address);
370 if (s) /* size bit - we flush more than one 4kb page */
371 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
372 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
373 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
374 }
375
376 /*
377 * Generic command send function for invalidaing TLB entries
378 */
379 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
380 u64 address, u16 domid, int pde, int s)
381 {
382 struct iommu_cmd cmd;
383 int ret;
384
385 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
386
387 ret = iommu_queue_command(iommu, &cmd);
388
389 return ret;
390 }
391
392 /*
393 * TLB invalidation function which is called from the mapping functions.
394 * It invalidates a single PTE if the range to flush is within a single
395 * page. Otherwise it flushes the whole TLB of the IOMMU.
396 */
397 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
398 u64 address, size_t size)
399 {
400 int s = 0;
401 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
402
403 address &= PAGE_MASK;
404
405 if (pages > 1) {
406 /*
407 * If we have to flush more than one page, flush all
408 * TLB entries for this domain
409 */
410 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
411 s = 1;
412 }
413
414 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
415
416 return 0;
417 }
418
419 /* Flush the whole IO/TLB for a given protection domain */
420 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
421 {
422 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
423
424 INC_STATS_COUNTER(domain_flush_single);
425
426 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
427 }
428
429 #ifdef CONFIG_IOMMU_API
430 /*
431 * This function is used to flush the IO/TLB for a given protection domain
432 * on every IOMMU in the system
433 */
434 static void iommu_flush_domain(u16 domid)
435 {
436 unsigned long flags;
437 struct amd_iommu *iommu;
438 struct iommu_cmd cmd;
439
440 INC_STATS_COUNTER(domain_flush_all);
441
442 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
443 domid, 1, 1);
444
445 list_for_each_entry(iommu, &amd_iommu_list, list) {
446 spin_lock_irqsave(&iommu->lock, flags);
447 __iommu_queue_command(iommu, &cmd);
448 __iommu_completion_wait(iommu);
449 __iommu_wait_for_completion(iommu);
450 spin_unlock_irqrestore(&iommu->lock, flags);
451 }
452 }
453 #endif
454
455 /****************************************************************************
456 *
457 * The functions below are used the create the page table mappings for
458 * unity mapped regions.
459 *
460 ****************************************************************************/
461
462 /*
463 * Generic mapping functions. It maps a physical address into a DMA
464 * address space. It allocates the page table pages if necessary.
465 * In the future it can be extended to a generic mapping function
466 * supporting all features of AMD IOMMU page tables like level skipping
467 * and full 64 bit address spaces.
468 */
469 static int iommu_map_page(struct protection_domain *dom,
470 unsigned long bus_addr,
471 unsigned long phys_addr,
472 int prot)
473 {
474 u64 __pte, *pte, *page;
475
476 bus_addr = PAGE_ALIGN(bus_addr);
477 phys_addr = PAGE_ALIGN(phys_addr);
478
479 /* only support 512GB address spaces for now */
480 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
481 return -EINVAL;
482
483 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
484
485 if (!IOMMU_PTE_PRESENT(*pte)) {
486 page = (u64 *)get_zeroed_page(GFP_KERNEL);
487 if (!page)
488 return -ENOMEM;
489 *pte = IOMMU_L2_PDE(virt_to_phys(page));
490 }
491
492 pte = IOMMU_PTE_PAGE(*pte);
493 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
494
495 if (!IOMMU_PTE_PRESENT(*pte)) {
496 page = (u64 *)get_zeroed_page(GFP_KERNEL);
497 if (!page)
498 return -ENOMEM;
499 *pte = IOMMU_L1_PDE(virt_to_phys(page));
500 }
501
502 pte = IOMMU_PTE_PAGE(*pte);
503 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
504
505 if (IOMMU_PTE_PRESENT(*pte))
506 return -EBUSY;
507
508 __pte = phys_addr | IOMMU_PTE_P;
509 if (prot & IOMMU_PROT_IR)
510 __pte |= IOMMU_PTE_IR;
511 if (prot & IOMMU_PROT_IW)
512 __pte |= IOMMU_PTE_IW;
513
514 *pte = __pte;
515
516 return 0;
517 }
518
519 #ifdef CONFIG_IOMMU_API
520 static void iommu_unmap_page(struct protection_domain *dom,
521 unsigned long bus_addr)
522 {
523 u64 *pte;
524
525 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
526
527 if (!IOMMU_PTE_PRESENT(*pte))
528 return;
529
530 pte = IOMMU_PTE_PAGE(*pte);
531 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
532
533 if (!IOMMU_PTE_PRESENT(*pte))
534 return;
535
536 pte = IOMMU_PTE_PAGE(*pte);
537 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
538
539 *pte = 0;
540 }
541 #endif
542
543 /*
544 * This function checks if a specific unity mapping entry is needed for
545 * this specific IOMMU.
546 */
547 static int iommu_for_unity_map(struct amd_iommu *iommu,
548 struct unity_map_entry *entry)
549 {
550 u16 bdf, i;
551
552 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
553 bdf = amd_iommu_alias_table[i];
554 if (amd_iommu_rlookup_table[bdf] == iommu)
555 return 1;
556 }
557
558 return 0;
559 }
560
561 /*
562 * Init the unity mappings for a specific IOMMU in the system
563 *
564 * Basically iterates over all unity mapping entries and applies them to
565 * the default domain DMA of that IOMMU if necessary.
566 */
567 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
568 {
569 struct unity_map_entry *entry;
570 int ret;
571
572 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
573 if (!iommu_for_unity_map(iommu, entry))
574 continue;
575 ret = dma_ops_unity_map(iommu->default_dom, entry);
576 if (ret)
577 return ret;
578 }
579
580 return 0;
581 }
582
583 /*
584 * This function actually applies the mapping to the page table of the
585 * dma_ops domain.
586 */
587 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
588 struct unity_map_entry *e)
589 {
590 u64 addr;
591 int ret;
592
593 for (addr = e->address_start; addr < e->address_end;
594 addr += PAGE_SIZE) {
595 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
596 if (ret)
597 return ret;
598 /*
599 * if unity mapping is in aperture range mark the page
600 * as allocated in the aperture
601 */
602 if (addr < dma_dom->aperture_size)
603 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
604 }
605
606 return 0;
607 }
608
609 /*
610 * Inits the unity mappings required for a specific device
611 */
612 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
613 u16 devid)
614 {
615 struct unity_map_entry *e;
616 int ret;
617
618 list_for_each_entry(e, &amd_iommu_unity_map, list) {
619 if (!(devid >= e->devid_start && devid <= e->devid_end))
620 continue;
621 ret = dma_ops_unity_map(dma_dom, e);
622 if (ret)
623 return ret;
624 }
625
626 return 0;
627 }
628
629 /****************************************************************************
630 *
631 * The next functions belong to the address allocator for the dma_ops
632 * interface functions. They work like the allocators in the other IOMMU
633 * drivers. Its basically a bitmap which marks the allocated pages in
634 * the aperture. Maybe it could be enhanced in the future to a more
635 * efficient allocator.
636 *
637 ****************************************************************************/
638
639 /*
640 * The address allocator core function.
641 *
642 * called with domain->lock held
643 */
644 static unsigned long dma_ops_alloc_addresses(struct device *dev,
645 struct dma_ops_domain *dom,
646 unsigned int pages,
647 unsigned long align_mask,
648 u64 dma_mask)
649 {
650 unsigned long limit;
651 unsigned long address;
652 unsigned long boundary_size;
653
654 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
655 PAGE_SIZE) >> PAGE_SHIFT;
656 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
657 dma_mask >> PAGE_SHIFT);
658
659 if (dom->next_bit >= limit) {
660 dom->next_bit = 0;
661 dom->need_flush = true;
662 }
663
664 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
665 0 , boundary_size, align_mask);
666 if (address == -1) {
667 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
668 0, boundary_size, align_mask);
669 dom->need_flush = true;
670 }
671
672 if (likely(address != -1)) {
673 dom->next_bit = address + pages;
674 address <<= PAGE_SHIFT;
675 } else
676 address = bad_dma_address;
677
678 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
679
680 return address;
681 }
682
683 /*
684 * The address free function.
685 *
686 * called with domain->lock held
687 */
688 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
689 unsigned long address,
690 unsigned int pages)
691 {
692 address >>= PAGE_SHIFT;
693 iommu_area_free(dom->bitmap, address, pages);
694
695 if (address >= dom->next_bit)
696 dom->need_flush = true;
697 }
698
699 /****************************************************************************
700 *
701 * The next functions belong to the domain allocation. A domain is
702 * allocated for every IOMMU as the default domain. If device isolation
703 * is enabled, every device get its own domain. The most important thing
704 * about domains is the page table mapping the DMA address space they
705 * contain.
706 *
707 ****************************************************************************/
708
709 static u16 domain_id_alloc(void)
710 {
711 unsigned long flags;
712 int id;
713
714 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
715 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
716 BUG_ON(id == 0);
717 if (id > 0 && id < MAX_DOMAIN_ID)
718 __set_bit(id, amd_iommu_pd_alloc_bitmap);
719 else
720 id = 0;
721 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
722
723 return id;
724 }
725
726 #ifdef CONFIG_IOMMU_API
727 static void domain_id_free(int id)
728 {
729 unsigned long flags;
730
731 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
732 if (id > 0 && id < MAX_DOMAIN_ID)
733 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
734 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
735 }
736 #endif
737
738 /*
739 * Used to reserve address ranges in the aperture (e.g. for exclusion
740 * ranges.
741 */
742 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
743 unsigned long start_page,
744 unsigned int pages)
745 {
746 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
747
748 if (start_page + pages > last_page)
749 pages = last_page - start_page;
750
751 iommu_area_reserve(dom->bitmap, start_page, pages);
752 }
753
754 static void free_pagetable(struct protection_domain *domain)
755 {
756 int i, j;
757 u64 *p1, *p2, *p3;
758
759 p1 = domain->pt_root;
760
761 if (!p1)
762 return;
763
764 for (i = 0; i < 512; ++i) {
765 if (!IOMMU_PTE_PRESENT(p1[i]))
766 continue;
767
768 p2 = IOMMU_PTE_PAGE(p1[i]);
769 for (j = 0; j < 512; ++j) {
770 if (!IOMMU_PTE_PRESENT(p2[j]))
771 continue;
772 p3 = IOMMU_PTE_PAGE(p2[j]);
773 free_page((unsigned long)p3);
774 }
775
776 free_page((unsigned long)p2);
777 }
778
779 free_page((unsigned long)p1);
780
781 domain->pt_root = NULL;
782 }
783
784 /*
785 * Free a domain, only used if something went wrong in the
786 * allocation path and we need to free an already allocated page table
787 */
788 static void dma_ops_domain_free(struct dma_ops_domain *dom)
789 {
790 if (!dom)
791 return;
792
793 free_pagetable(&dom->domain);
794
795 kfree(dom->pte_pages);
796
797 kfree(dom->bitmap);
798
799 kfree(dom);
800 }
801
802 /*
803 * Allocates a new protection domain usable for the dma_ops functions.
804 * It also intializes the page table and the address allocator data
805 * structures required for the dma_ops interface
806 */
807 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
808 unsigned order)
809 {
810 struct dma_ops_domain *dma_dom;
811 unsigned i, num_pte_pages;
812 u64 *l2_pde;
813 u64 address;
814
815 /*
816 * Currently the DMA aperture must be between 32 MB and 1GB in size
817 */
818 if ((order < 25) || (order > 30))
819 return NULL;
820
821 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
822 if (!dma_dom)
823 return NULL;
824
825 spin_lock_init(&dma_dom->domain.lock);
826
827 dma_dom->domain.id = domain_id_alloc();
828 if (dma_dom->domain.id == 0)
829 goto free_dma_dom;
830 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
831 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
832 dma_dom->domain.flags = PD_DMA_OPS_MASK;
833 dma_dom->domain.priv = dma_dom;
834 if (!dma_dom->domain.pt_root)
835 goto free_dma_dom;
836 dma_dom->aperture_size = (1ULL << order);
837 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
838 GFP_KERNEL);
839 if (!dma_dom->bitmap)
840 goto free_dma_dom;
841 /*
842 * mark the first page as allocated so we never return 0 as
843 * a valid dma-address. So we can use 0 as error value
844 */
845 dma_dom->bitmap[0] = 1;
846 dma_dom->next_bit = 0;
847
848 dma_dom->need_flush = false;
849 dma_dom->target_dev = 0xffff;
850
851 /* Intialize the exclusion range if necessary */
852 if (iommu->exclusion_start &&
853 iommu->exclusion_start < dma_dom->aperture_size) {
854 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
855 int pages = iommu_num_pages(iommu->exclusion_start,
856 iommu->exclusion_length,
857 PAGE_SIZE);
858 dma_ops_reserve_addresses(dma_dom, startpage, pages);
859 }
860
861 /*
862 * At the last step, build the page tables so we don't need to
863 * allocate page table pages in the dma_ops mapping/unmapping
864 * path.
865 */
866 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
867 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
868 GFP_KERNEL);
869 if (!dma_dom->pte_pages)
870 goto free_dma_dom;
871
872 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
873 if (l2_pde == NULL)
874 goto free_dma_dom;
875
876 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
877
878 for (i = 0; i < num_pte_pages; ++i) {
879 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
880 if (!dma_dom->pte_pages[i])
881 goto free_dma_dom;
882 address = virt_to_phys(dma_dom->pte_pages[i]);
883 l2_pde[i] = IOMMU_L1_PDE(address);
884 }
885
886 return dma_dom;
887
888 free_dma_dom:
889 dma_ops_domain_free(dma_dom);
890
891 return NULL;
892 }
893
894 /*
895 * little helper function to check whether a given protection domain is a
896 * dma_ops domain
897 */
898 static bool dma_ops_domain(struct protection_domain *domain)
899 {
900 return domain->flags & PD_DMA_OPS_MASK;
901 }
902
903 /*
904 * Find out the protection domain structure for a given PCI device. This
905 * will give us the pointer to the page table root for example.
906 */
907 static struct protection_domain *domain_for_device(u16 devid)
908 {
909 struct protection_domain *dom;
910 unsigned long flags;
911
912 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
913 dom = amd_iommu_pd_table[devid];
914 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
915
916 return dom;
917 }
918
919 /*
920 * If a device is not yet associated with a domain, this function does
921 * assigns it visible for the hardware
922 */
923 static void attach_device(struct amd_iommu *iommu,
924 struct protection_domain *domain,
925 u16 devid)
926 {
927 unsigned long flags;
928 u64 pte_root = virt_to_phys(domain->pt_root);
929
930 domain->dev_cnt += 1;
931
932 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
933 << DEV_ENTRY_MODE_SHIFT;
934 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
935
936 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
937 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
938 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
939 amd_iommu_dev_table[devid].data[2] = domain->id;
940
941 amd_iommu_pd_table[devid] = domain;
942 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
943
944 iommu_queue_inv_dev_entry(iommu, devid);
945 }
946
947 /*
948 * Removes a device from a protection domain (unlocked)
949 */
950 static void __detach_device(struct protection_domain *domain, u16 devid)
951 {
952
953 /* lock domain */
954 spin_lock(&domain->lock);
955
956 /* remove domain from the lookup table */
957 amd_iommu_pd_table[devid] = NULL;
958
959 /* remove entry from the device table seen by the hardware */
960 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
961 amd_iommu_dev_table[devid].data[1] = 0;
962 amd_iommu_dev_table[devid].data[2] = 0;
963
964 /* decrease reference counter */
965 domain->dev_cnt -= 1;
966
967 /* ready */
968 spin_unlock(&domain->lock);
969 }
970
971 /*
972 * Removes a device from a protection domain (with devtable_lock held)
973 */
974 static void detach_device(struct protection_domain *domain, u16 devid)
975 {
976 unsigned long flags;
977
978 /* lock device table */
979 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
980 __detach_device(domain, devid);
981 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
982 }
983
984 static int device_change_notifier(struct notifier_block *nb,
985 unsigned long action, void *data)
986 {
987 struct device *dev = data;
988 struct pci_dev *pdev = to_pci_dev(dev);
989 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
990 struct protection_domain *domain;
991 struct dma_ops_domain *dma_domain;
992 struct amd_iommu *iommu;
993 int order = amd_iommu_aperture_order;
994 unsigned long flags;
995
996 if (devid > amd_iommu_last_bdf)
997 goto out;
998
999 devid = amd_iommu_alias_table[devid];
1000
1001 iommu = amd_iommu_rlookup_table[devid];
1002 if (iommu == NULL)
1003 goto out;
1004
1005 domain = domain_for_device(devid);
1006
1007 if (domain && !dma_ops_domain(domain))
1008 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1009 "to a non-dma-ops domain\n", dev_name(dev));
1010
1011 switch (action) {
1012 case BUS_NOTIFY_BOUND_DRIVER:
1013 if (domain)
1014 goto out;
1015 dma_domain = find_protection_domain(devid);
1016 if (!dma_domain)
1017 dma_domain = iommu->default_dom;
1018 attach_device(iommu, &dma_domain->domain, devid);
1019 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1020 "device %s\n", dma_domain->domain.id, dev_name(dev));
1021 break;
1022 case BUS_NOTIFY_UNBIND_DRIVER:
1023 if (!domain)
1024 goto out;
1025 detach_device(domain, devid);
1026 break;
1027 case BUS_NOTIFY_ADD_DEVICE:
1028 /* allocate a protection domain if a device is added */
1029 dma_domain = find_protection_domain(devid);
1030 if (dma_domain)
1031 goto out;
1032 dma_domain = dma_ops_domain_alloc(iommu, order);
1033 if (!dma_domain)
1034 goto out;
1035 dma_domain->target_dev = devid;
1036
1037 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1038 list_add_tail(&dma_domain->list, &iommu_pd_list);
1039 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1040
1041 break;
1042 default:
1043 goto out;
1044 }
1045
1046 iommu_queue_inv_dev_entry(iommu, devid);
1047 iommu_completion_wait(iommu);
1048
1049 out:
1050 return 0;
1051 }
1052
1053 struct notifier_block device_nb = {
1054 .notifier_call = device_change_notifier,
1055 };
1056
1057 /*****************************************************************************
1058 *
1059 * The next functions belong to the dma_ops mapping/unmapping code.
1060 *
1061 *****************************************************************************/
1062
1063 /*
1064 * This function checks if the driver got a valid device from the caller to
1065 * avoid dereferencing invalid pointers.
1066 */
1067 static bool check_device(struct device *dev)
1068 {
1069 if (!dev || !dev->dma_mask)
1070 return false;
1071
1072 return true;
1073 }
1074
1075 /*
1076 * In this function the list of preallocated protection domains is traversed to
1077 * find the domain for a specific device
1078 */
1079 static struct dma_ops_domain *find_protection_domain(u16 devid)
1080 {
1081 struct dma_ops_domain *entry, *ret = NULL;
1082 unsigned long flags;
1083
1084 if (list_empty(&iommu_pd_list))
1085 return NULL;
1086
1087 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1088
1089 list_for_each_entry(entry, &iommu_pd_list, list) {
1090 if (entry->target_dev == devid) {
1091 ret = entry;
1092 break;
1093 }
1094 }
1095
1096 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1097
1098 return ret;
1099 }
1100
1101 /*
1102 * In the dma_ops path we only have the struct device. This function
1103 * finds the corresponding IOMMU, the protection domain and the
1104 * requestor id for a given device.
1105 * If the device is not yet associated with a domain this is also done
1106 * in this function.
1107 */
1108 static int get_device_resources(struct device *dev,
1109 struct amd_iommu **iommu,
1110 struct protection_domain **domain,
1111 u16 *bdf)
1112 {
1113 struct dma_ops_domain *dma_dom;
1114 struct pci_dev *pcidev;
1115 u16 _bdf;
1116
1117 *iommu = NULL;
1118 *domain = NULL;
1119 *bdf = 0xffff;
1120
1121 if (dev->bus != &pci_bus_type)
1122 return 0;
1123
1124 pcidev = to_pci_dev(dev);
1125 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1126
1127 /* device not translated by any IOMMU in the system? */
1128 if (_bdf > amd_iommu_last_bdf)
1129 return 0;
1130
1131 *bdf = amd_iommu_alias_table[_bdf];
1132
1133 *iommu = amd_iommu_rlookup_table[*bdf];
1134 if (*iommu == NULL)
1135 return 0;
1136 *domain = domain_for_device(*bdf);
1137 if (*domain == NULL) {
1138 dma_dom = find_protection_domain(*bdf);
1139 if (!dma_dom)
1140 dma_dom = (*iommu)->default_dom;
1141 *domain = &dma_dom->domain;
1142 attach_device(*iommu, *domain, *bdf);
1143 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1144 "device %s\n", (*domain)->id, dev_name(dev));
1145 }
1146
1147 if (domain_for_device(_bdf) == NULL)
1148 attach_device(*iommu, *domain, _bdf);
1149
1150 return 1;
1151 }
1152
1153 /*
1154 * This is the generic map function. It maps one 4kb page at paddr to
1155 * the given address in the DMA address space for the domain.
1156 */
1157 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1158 struct dma_ops_domain *dom,
1159 unsigned long address,
1160 phys_addr_t paddr,
1161 int direction)
1162 {
1163 u64 *pte, __pte;
1164
1165 WARN_ON(address > dom->aperture_size);
1166
1167 paddr &= PAGE_MASK;
1168
1169 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1170 pte += IOMMU_PTE_L0_INDEX(address);
1171
1172 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1173
1174 if (direction == DMA_TO_DEVICE)
1175 __pte |= IOMMU_PTE_IR;
1176 else if (direction == DMA_FROM_DEVICE)
1177 __pte |= IOMMU_PTE_IW;
1178 else if (direction == DMA_BIDIRECTIONAL)
1179 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1180
1181 WARN_ON(*pte);
1182
1183 *pte = __pte;
1184
1185 return (dma_addr_t)address;
1186 }
1187
1188 /*
1189 * The generic unmapping function for on page in the DMA address space.
1190 */
1191 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1192 struct dma_ops_domain *dom,
1193 unsigned long address)
1194 {
1195 u64 *pte;
1196
1197 if (address >= dom->aperture_size)
1198 return;
1199
1200 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1201
1202 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1203 pte += IOMMU_PTE_L0_INDEX(address);
1204
1205 WARN_ON(!*pte);
1206
1207 *pte = 0ULL;
1208 }
1209
1210 /*
1211 * This function contains common code for mapping of a physically
1212 * contiguous memory region into DMA address space. It is used by all
1213 * mapping functions provided with this IOMMU driver.
1214 * Must be called with the domain lock held.
1215 */
1216 static dma_addr_t __map_single(struct device *dev,
1217 struct amd_iommu *iommu,
1218 struct dma_ops_domain *dma_dom,
1219 phys_addr_t paddr,
1220 size_t size,
1221 int dir,
1222 bool align,
1223 u64 dma_mask)
1224 {
1225 dma_addr_t offset = paddr & ~PAGE_MASK;
1226 dma_addr_t address, start;
1227 unsigned int pages;
1228 unsigned long align_mask = 0;
1229 int i;
1230
1231 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1232 paddr &= PAGE_MASK;
1233
1234 INC_STATS_COUNTER(total_map_requests);
1235
1236 if (pages > 1)
1237 INC_STATS_COUNTER(cross_page);
1238
1239 if (align)
1240 align_mask = (1UL << get_order(size)) - 1;
1241
1242 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1243 dma_mask);
1244 if (unlikely(address == bad_dma_address))
1245 goto out;
1246
1247 start = address;
1248 for (i = 0; i < pages; ++i) {
1249 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1250 paddr += PAGE_SIZE;
1251 start += PAGE_SIZE;
1252 }
1253 address += offset;
1254
1255 ADD_STATS_COUNTER(alloced_io_mem, size);
1256
1257 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1258 iommu_flush_tlb(iommu, dma_dom->domain.id);
1259 dma_dom->need_flush = false;
1260 } else if (unlikely(iommu_has_npcache(iommu)))
1261 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1262
1263 out:
1264 return address;
1265 }
1266
1267 /*
1268 * Does the reverse of the __map_single function. Must be called with
1269 * the domain lock held too
1270 */
1271 static void __unmap_single(struct amd_iommu *iommu,
1272 struct dma_ops_domain *dma_dom,
1273 dma_addr_t dma_addr,
1274 size_t size,
1275 int dir)
1276 {
1277 dma_addr_t i, start;
1278 unsigned int pages;
1279
1280 if ((dma_addr == bad_dma_address) ||
1281 (dma_addr + size > dma_dom->aperture_size))
1282 return;
1283
1284 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1285 dma_addr &= PAGE_MASK;
1286 start = dma_addr;
1287
1288 for (i = 0; i < pages; ++i) {
1289 dma_ops_domain_unmap(iommu, dma_dom, start);
1290 start += PAGE_SIZE;
1291 }
1292
1293 SUB_STATS_COUNTER(alloced_io_mem, size);
1294
1295 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1296
1297 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1298 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1299 dma_dom->need_flush = false;
1300 }
1301 }
1302
1303 /*
1304 * The exported map_single function for dma_ops.
1305 */
1306 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1307 size_t size, int dir)
1308 {
1309 unsigned long flags;
1310 struct amd_iommu *iommu;
1311 struct protection_domain *domain;
1312 u16 devid;
1313 dma_addr_t addr;
1314 u64 dma_mask;
1315
1316 INC_STATS_COUNTER(cnt_map_single);
1317
1318 if (!check_device(dev))
1319 return bad_dma_address;
1320
1321 dma_mask = *dev->dma_mask;
1322
1323 get_device_resources(dev, &iommu, &domain, &devid);
1324
1325 if (iommu == NULL || domain == NULL)
1326 /* device not handled by any AMD IOMMU */
1327 return (dma_addr_t)paddr;
1328
1329 if (!dma_ops_domain(domain))
1330 return bad_dma_address;
1331
1332 spin_lock_irqsave(&domain->lock, flags);
1333 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1334 dma_mask);
1335 if (addr == bad_dma_address)
1336 goto out;
1337
1338 iommu_completion_wait(iommu);
1339
1340 out:
1341 spin_unlock_irqrestore(&domain->lock, flags);
1342
1343 return addr;
1344 }
1345
1346 /*
1347 * The exported unmap_single function for dma_ops.
1348 */
1349 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1350 size_t size, int dir)
1351 {
1352 unsigned long flags;
1353 struct amd_iommu *iommu;
1354 struct protection_domain *domain;
1355 u16 devid;
1356
1357 INC_STATS_COUNTER(cnt_unmap_single);
1358
1359 if (!check_device(dev) ||
1360 !get_device_resources(dev, &iommu, &domain, &devid))
1361 /* device not handled by any AMD IOMMU */
1362 return;
1363
1364 if (!dma_ops_domain(domain))
1365 return;
1366
1367 spin_lock_irqsave(&domain->lock, flags);
1368
1369 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1370
1371 iommu_completion_wait(iommu);
1372
1373 spin_unlock_irqrestore(&domain->lock, flags);
1374 }
1375
1376 /*
1377 * This is a special map_sg function which is used if we should map a
1378 * device which is not handled by an AMD IOMMU in the system.
1379 */
1380 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1381 int nelems, int dir)
1382 {
1383 struct scatterlist *s;
1384 int i;
1385
1386 for_each_sg(sglist, s, nelems, i) {
1387 s->dma_address = (dma_addr_t)sg_phys(s);
1388 s->dma_length = s->length;
1389 }
1390
1391 return nelems;
1392 }
1393
1394 /*
1395 * The exported map_sg function for dma_ops (handles scatter-gather
1396 * lists).
1397 */
1398 static int map_sg(struct device *dev, struct scatterlist *sglist,
1399 int nelems, int dir)
1400 {
1401 unsigned long flags;
1402 struct amd_iommu *iommu;
1403 struct protection_domain *domain;
1404 u16 devid;
1405 int i;
1406 struct scatterlist *s;
1407 phys_addr_t paddr;
1408 int mapped_elems = 0;
1409 u64 dma_mask;
1410
1411 INC_STATS_COUNTER(cnt_map_sg);
1412
1413 if (!check_device(dev))
1414 return 0;
1415
1416 dma_mask = *dev->dma_mask;
1417
1418 get_device_resources(dev, &iommu, &domain, &devid);
1419
1420 if (!iommu || !domain)
1421 return map_sg_no_iommu(dev, sglist, nelems, dir);
1422
1423 if (!dma_ops_domain(domain))
1424 return 0;
1425
1426 spin_lock_irqsave(&domain->lock, flags);
1427
1428 for_each_sg(sglist, s, nelems, i) {
1429 paddr = sg_phys(s);
1430
1431 s->dma_address = __map_single(dev, iommu, domain->priv,
1432 paddr, s->length, dir, false,
1433 dma_mask);
1434
1435 if (s->dma_address) {
1436 s->dma_length = s->length;
1437 mapped_elems++;
1438 } else
1439 goto unmap;
1440 }
1441
1442 iommu_completion_wait(iommu);
1443
1444 out:
1445 spin_unlock_irqrestore(&domain->lock, flags);
1446
1447 return mapped_elems;
1448 unmap:
1449 for_each_sg(sglist, s, mapped_elems, i) {
1450 if (s->dma_address)
1451 __unmap_single(iommu, domain->priv, s->dma_address,
1452 s->dma_length, dir);
1453 s->dma_address = s->dma_length = 0;
1454 }
1455
1456 mapped_elems = 0;
1457
1458 goto out;
1459 }
1460
1461 /*
1462 * The exported map_sg function for dma_ops (handles scatter-gather
1463 * lists).
1464 */
1465 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1466 int nelems, int dir)
1467 {
1468 unsigned long flags;
1469 struct amd_iommu *iommu;
1470 struct protection_domain *domain;
1471 struct scatterlist *s;
1472 u16 devid;
1473 int i;
1474
1475 INC_STATS_COUNTER(cnt_unmap_sg);
1476
1477 if (!check_device(dev) ||
1478 !get_device_resources(dev, &iommu, &domain, &devid))
1479 return;
1480
1481 if (!dma_ops_domain(domain))
1482 return;
1483
1484 spin_lock_irqsave(&domain->lock, flags);
1485
1486 for_each_sg(sglist, s, nelems, i) {
1487 __unmap_single(iommu, domain->priv, s->dma_address,
1488 s->dma_length, dir);
1489 s->dma_address = s->dma_length = 0;
1490 }
1491
1492 iommu_completion_wait(iommu);
1493
1494 spin_unlock_irqrestore(&domain->lock, flags);
1495 }
1496
1497 /*
1498 * The exported alloc_coherent function for dma_ops.
1499 */
1500 static void *alloc_coherent(struct device *dev, size_t size,
1501 dma_addr_t *dma_addr, gfp_t flag)
1502 {
1503 unsigned long flags;
1504 void *virt_addr;
1505 struct amd_iommu *iommu;
1506 struct protection_domain *domain;
1507 u16 devid;
1508 phys_addr_t paddr;
1509 u64 dma_mask = dev->coherent_dma_mask;
1510
1511 INC_STATS_COUNTER(cnt_alloc_coherent);
1512
1513 if (!check_device(dev))
1514 return NULL;
1515
1516 if (!get_device_resources(dev, &iommu, &domain, &devid))
1517 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1518
1519 flag |= __GFP_ZERO;
1520 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1521 if (!virt_addr)
1522 return 0;
1523
1524 paddr = virt_to_phys(virt_addr);
1525
1526 if (!iommu || !domain) {
1527 *dma_addr = (dma_addr_t)paddr;
1528 return virt_addr;
1529 }
1530
1531 if (!dma_ops_domain(domain))
1532 goto out_free;
1533
1534 if (!dma_mask)
1535 dma_mask = *dev->dma_mask;
1536
1537 spin_lock_irqsave(&domain->lock, flags);
1538
1539 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1540 size, DMA_BIDIRECTIONAL, true, dma_mask);
1541
1542 if (*dma_addr == bad_dma_address)
1543 goto out_free;
1544
1545 iommu_completion_wait(iommu);
1546
1547 spin_unlock_irqrestore(&domain->lock, flags);
1548
1549 return virt_addr;
1550
1551 out_free:
1552
1553 free_pages((unsigned long)virt_addr, get_order(size));
1554
1555 return NULL;
1556 }
1557
1558 /*
1559 * The exported free_coherent function for dma_ops.
1560 */
1561 static void free_coherent(struct device *dev, size_t size,
1562 void *virt_addr, dma_addr_t dma_addr)
1563 {
1564 unsigned long flags;
1565 struct amd_iommu *iommu;
1566 struct protection_domain *domain;
1567 u16 devid;
1568
1569 INC_STATS_COUNTER(cnt_free_coherent);
1570
1571 if (!check_device(dev))
1572 return;
1573
1574 get_device_resources(dev, &iommu, &domain, &devid);
1575
1576 if (!iommu || !domain)
1577 goto free_mem;
1578
1579 if (!dma_ops_domain(domain))
1580 goto free_mem;
1581
1582 spin_lock_irqsave(&domain->lock, flags);
1583
1584 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1585
1586 iommu_completion_wait(iommu);
1587
1588 spin_unlock_irqrestore(&domain->lock, flags);
1589
1590 free_mem:
1591 free_pages((unsigned long)virt_addr, get_order(size));
1592 }
1593
1594 /*
1595 * This function is called by the DMA layer to find out if we can handle a
1596 * particular device. It is part of the dma_ops.
1597 */
1598 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1599 {
1600 u16 bdf;
1601 struct pci_dev *pcidev;
1602
1603 /* No device or no PCI device */
1604 if (!dev || dev->bus != &pci_bus_type)
1605 return 0;
1606
1607 pcidev = to_pci_dev(dev);
1608
1609 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1610
1611 /* Out of our scope? */
1612 if (bdf > amd_iommu_last_bdf)
1613 return 0;
1614
1615 return 1;
1616 }
1617
1618 /*
1619 * The function for pre-allocating protection domains.
1620 *
1621 * If the driver core informs the DMA layer if a driver grabs a device
1622 * we don't need to preallocate the protection domains anymore.
1623 * For now we have to.
1624 */
1625 void prealloc_protection_domains(void)
1626 {
1627 struct pci_dev *dev = NULL;
1628 struct dma_ops_domain *dma_dom;
1629 struct amd_iommu *iommu;
1630 int order = amd_iommu_aperture_order;
1631 u16 devid;
1632
1633 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1634 devid = calc_devid(dev->bus->number, dev->devfn);
1635 if (devid > amd_iommu_last_bdf)
1636 continue;
1637 devid = amd_iommu_alias_table[devid];
1638 if (domain_for_device(devid))
1639 continue;
1640 iommu = amd_iommu_rlookup_table[devid];
1641 if (!iommu)
1642 continue;
1643 dma_dom = dma_ops_domain_alloc(iommu, order);
1644 if (!dma_dom)
1645 continue;
1646 init_unity_mappings_for_device(dma_dom, devid);
1647 dma_dom->target_dev = devid;
1648
1649 list_add_tail(&dma_dom->list, &iommu_pd_list);
1650 }
1651 }
1652
1653 static struct dma_mapping_ops amd_iommu_dma_ops = {
1654 .alloc_coherent = alloc_coherent,
1655 .free_coherent = free_coherent,
1656 .map_single = map_single,
1657 .unmap_single = unmap_single,
1658 .map_sg = map_sg,
1659 .unmap_sg = unmap_sg,
1660 .dma_supported = amd_iommu_dma_supported,
1661 };
1662
1663 /*
1664 * The function which clues the AMD IOMMU driver into dma_ops.
1665 */
1666 int __init amd_iommu_init_dma_ops(void)
1667 {
1668 struct amd_iommu *iommu;
1669 int order = amd_iommu_aperture_order;
1670 int ret;
1671
1672 /*
1673 * first allocate a default protection domain for every IOMMU we
1674 * found in the system. Devices not assigned to any other
1675 * protection domain will be assigned to the default one.
1676 */
1677 list_for_each_entry(iommu, &amd_iommu_list, list) {
1678 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1679 if (iommu->default_dom == NULL)
1680 return -ENOMEM;
1681 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1682 ret = iommu_init_unity_mappings(iommu);
1683 if (ret)
1684 goto free_domains;
1685 }
1686
1687 /*
1688 * If device isolation is enabled, pre-allocate the protection
1689 * domains for each device.
1690 */
1691 if (amd_iommu_isolate)
1692 prealloc_protection_domains();
1693
1694 iommu_detected = 1;
1695 force_iommu = 1;
1696 bad_dma_address = 0;
1697 #ifdef CONFIG_GART_IOMMU
1698 gart_iommu_aperture_disabled = 1;
1699 gart_iommu_aperture = 0;
1700 #endif
1701
1702 /* Make the driver finally visible to the drivers */
1703 dma_ops = &amd_iommu_dma_ops;
1704
1705 #ifdef CONFIG_IOMMU_API
1706 register_iommu(&amd_iommu_ops);
1707 #endif
1708
1709 bus_register_notifier(&pci_bus_type, &device_nb);
1710
1711 amd_iommu_stats_init();
1712
1713 return 0;
1714
1715 free_domains:
1716
1717 list_for_each_entry(iommu, &amd_iommu_list, list) {
1718 if (iommu->default_dom)
1719 dma_ops_domain_free(iommu->default_dom);
1720 }
1721
1722 return ret;
1723 }
1724
1725 /*****************************************************************************
1726 *
1727 * The following functions belong to the exported interface of AMD IOMMU
1728 *
1729 * This interface allows access to lower level functions of the IOMMU
1730 * like protection domain handling and assignement of devices to domains
1731 * which is not possible with the dma_ops interface.
1732 *
1733 *****************************************************************************/
1734
1735 #ifdef CONFIG_IOMMU_API
1736
1737 static void cleanup_domain(struct protection_domain *domain)
1738 {
1739 unsigned long flags;
1740 u16 devid;
1741
1742 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1743
1744 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1745 if (amd_iommu_pd_table[devid] == domain)
1746 __detach_device(domain, devid);
1747
1748 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1749 }
1750
1751 static int amd_iommu_domain_init(struct iommu_domain *dom)
1752 {
1753 struct protection_domain *domain;
1754
1755 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1756 if (!domain)
1757 return -ENOMEM;
1758
1759 spin_lock_init(&domain->lock);
1760 domain->mode = PAGE_MODE_3_LEVEL;
1761 domain->id = domain_id_alloc();
1762 if (!domain->id)
1763 goto out_free;
1764 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1765 if (!domain->pt_root)
1766 goto out_free;
1767
1768 dom->priv = domain;
1769
1770 return 0;
1771
1772 out_free:
1773 kfree(domain);
1774
1775 return -ENOMEM;
1776 }
1777
1778 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1779 {
1780 struct protection_domain *domain = dom->priv;
1781
1782 if (!domain)
1783 return;
1784
1785 if (domain->dev_cnt > 0)
1786 cleanup_domain(domain);
1787
1788 BUG_ON(domain->dev_cnt != 0);
1789
1790 free_pagetable(domain);
1791
1792 domain_id_free(domain->id);
1793
1794 kfree(domain);
1795
1796 dom->priv = NULL;
1797 }
1798
1799 static void amd_iommu_detach_device(struct iommu_domain *dom,
1800 struct device *dev)
1801 {
1802 struct protection_domain *domain = dom->priv;
1803 struct amd_iommu *iommu;
1804 struct pci_dev *pdev;
1805 u16 devid;
1806
1807 if (dev->bus != &pci_bus_type)
1808 return;
1809
1810 pdev = to_pci_dev(dev);
1811
1812 devid = calc_devid(pdev->bus->number, pdev->devfn);
1813
1814 if (devid > 0)
1815 detach_device(domain, devid);
1816
1817 iommu = amd_iommu_rlookup_table[devid];
1818 if (!iommu)
1819 return;
1820
1821 iommu_queue_inv_dev_entry(iommu, devid);
1822 iommu_completion_wait(iommu);
1823 }
1824
1825 static int amd_iommu_attach_device(struct iommu_domain *dom,
1826 struct device *dev)
1827 {
1828 struct protection_domain *domain = dom->priv;
1829 struct protection_domain *old_domain;
1830 struct amd_iommu *iommu;
1831 struct pci_dev *pdev;
1832 u16 devid;
1833
1834 if (dev->bus != &pci_bus_type)
1835 return -EINVAL;
1836
1837 pdev = to_pci_dev(dev);
1838
1839 devid = calc_devid(pdev->bus->number, pdev->devfn);
1840
1841 if (devid >= amd_iommu_last_bdf ||
1842 devid != amd_iommu_alias_table[devid])
1843 return -EINVAL;
1844
1845 iommu = amd_iommu_rlookup_table[devid];
1846 if (!iommu)
1847 return -EINVAL;
1848
1849 old_domain = domain_for_device(devid);
1850 if (old_domain)
1851 return -EBUSY;
1852
1853 attach_device(iommu, domain, devid);
1854
1855 iommu_completion_wait(iommu);
1856
1857 return 0;
1858 }
1859
1860 static int amd_iommu_map_range(struct iommu_domain *dom,
1861 unsigned long iova, phys_addr_t paddr,
1862 size_t size, int iommu_prot)
1863 {
1864 struct protection_domain *domain = dom->priv;
1865 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1866 int prot = 0;
1867 int ret;
1868
1869 if (iommu_prot & IOMMU_READ)
1870 prot |= IOMMU_PROT_IR;
1871 if (iommu_prot & IOMMU_WRITE)
1872 prot |= IOMMU_PROT_IW;
1873
1874 iova &= PAGE_MASK;
1875 paddr &= PAGE_MASK;
1876
1877 for (i = 0; i < npages; ++i) {
1878 ret = iommu_map_page(domain, iova, paddr, prot);
1879 if (ret)
1880 return ret;
1881
1882 iova += PAGE_SIZE;
1883 paddr += PAGE_SIZE;
1884 }
1885
1886 return 0;
1887 }
1888
1889 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1890 unsigned long iova, size_t size)
1891 {
1892
1893 struct protection_domain *domain = dom->priv;
1894 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1895
1896 iova &= PAGE_MASK;
1897
1898 for (i = 0; i < npages; ++i) {
1899 iommu_unmap_page(domain, iova);
1900 iova += PAGE_SIZE;
1901 }
1902
1903 iommu_flush_domain(domain->id);
1904 }
1905
1906 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1907 unsigned long iova)
1908 {
1909 struct protection_domain *domain = dom->priv;
1910 unsigned long offset = iova & ~PAGE_MASK;
1911 phys_addr_t paddr;
1912 u64 *pte;
1913
1914 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1915
1916 if (!IOMMU_PTE_PRESENT(*pte))
1917 return 0;
1918
1919 pte = IOMMU_PTE_PAGE(*pte);
1920 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1921
1922 if (!IOMMU_PTE_PRESENT(*pte))
1923 return 0;
1924
1925 pte = IOMMU_PTE_PAGE(*pte);
1926 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1927
1928 if (!IOMMU_PTE_PRESENT(*pte))
1929 return 0;
1930
1931 paddr = *pte & IOMMU_PAGE_MASK;
1932 paddr |= offset;
1933
1934 return paddr;
1935 }
1936
1937 static struct iommu_ops amd_iommu_ops = {
1938 .domain_init = amd_iommu_domain_init,
1939 .domain_destroy = amd_iommu_domain_destroy,
1940 .attach_dev = amd_iommu_attach_device,
1941 .detach_dev = amd_iommu_detach_device,
1942 .map = amd_iommu_map_range,
1943 .unmap = amd_iommu_unmap_range,
1944 .iova_to_phys = amd_iommu_iova_to_phys,
1945 };
1946
1947 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree