2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
33 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
38 static DEFINE_SPINLOCK(hose_spinlock
);
41 /* XXX kill that some day ... */
42 static int global_phb_number
; /* Global phb counter */
44 /* ISA Memory physical address */
45 resource_size_t isa_mem_base
;
47 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
48 unsigned int pci_flags
;
50 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
52 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
54 pci_dma_ops
= dma_ops
;
57 struct dma_map_ops
*get_pci_dma_ops(void)
61 EXPORT_SYMBOL(get_pci_dma_ops
);
63 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
65 struct pci_controller
*phb
;
67 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
70 spin_lock(&hose_spinlock
);
71 phb
->global_number
= global_phb_number
++;
72 list_add_tail(&phb
->list_node
, &hose_list
);
73 spin_unlock(&hose_spinlock
);
75 phb
->is_dynamic
= mem_init_done
;
79 void pcibios_free_controller(struct pci_controller
*phb
)
81 spin_lock(&hose_spinlock
);
82 list_del(&phb
->list_node
);
83 spin_unlock(&hose_spinlock
);
89 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
91 return hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
94 int pcibios_vaddr_is_ioport(void __iomem
*address
)
97 struct pci_controller
*hose
;
100 spin_lock(&hose_spinlock
);
101 list_for_each_entry(hose
, &hose_list
, list_node
) {
102 size
= pcibios_io_size(hose
);
103 if (address
>= hose
->io_base_virt
&&
104 address
< (hose
->io_base_virt
+ size
)) {
109 spin_unlock(&hose_spinlock
);
113 unsigned long pci_address_to_pio(phys_addr_t address
)
115 struct pci_controller
*hose
;
116 resource_size_t size
;
117 unsigned long ret
= ~0;
119 spin_lock(&hose_spinlock
);
120 list_for_each_entry(hose
, &hose_list
, list_node
) {
121 size
= pcibios_io_size(hose
);
122 if (address
>= hose
->io_base_phys
&&
123 address
< (hose
->io_base_phys
+ size
)) {
125 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
126 ret
= base
+ (address
- hose
->io_base_phys
);
130 spin_unlock(&hose_spinlock
);
134 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
137 * Return the domain number for this bus.
139 int pci_domain_nr(struct pci_bus
*bus
)
141 struct pci_controller
*hose
= pci_bus_to_host(bus
);
143 return hose
->global_number
;
145 EXPORT_SYMBOL(pci_domain_nr
);
147 /* This routine is meant to be used early during boot, when the
148 * PCI bus numbers have not yet been assigned, and you need to
149 * issue PCI config cycles to an OF device.
150 * It could also be used to "fix" RTAS config cycles if you want
151 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
154 struct pci_controller
*pci_find_hose_for_OF_device(struct device_node
*node
)
157 struct pci_controller
*hose
, *tmp
;
158 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
159 if (hose
->dn
== node
)
166 static ssize_t
pci_show_devspec(struct device
*dev
,
167 struct device_attribute
*attr
, char *buf
)
169 struct pci_dev
*pdev
;
170 struct device_node
*np
;
172 pdev
= to_pci_dev(dev
);
173 np
= pci_device_to_OF_node(pdev
);
174 if (np
== NULL
|| np
->full_name
== NULL
)
176 return sprintf(buf
, "%s", np
->full_name
);
178 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
180 /* Add sysfs properties */
181 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
183 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
186 char __devinit
*pcibios_setup(char *str
)
192 * Reads the interrupt pin to determine if interrupt is use by card.
193 * If the interrupt is used, then gets the interrupt line from the
194 * openfirmware and sets it in the pci_dev and pci_config line.
196 int pci_read_irq_line(struct pci_dev
*pci_dev
)
201 /* The current device-tree that iSeries generates from the HV
202 * PCI informations doesn't contain proper interrupt routing,
203 * and all the fallback would do is print out crap, so we
204 * don't attempt to resolve the interrupts here at all, some
205 * iSeries specific fixup does it.
207 * In the long run, we will hopefully fix the generated device-tree
210 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
213 memset(&oirq
, 0xff, sizeof(oirq
));
215 /* Try to get a mapping from the device-tree */
216 if (of_irq_map_pci(pci_dev
, &oirq
)) {
219 /* If that fails, lets fallback to what is in the config
220 * space and map that through the default controller. We
221 * also set the type to level low since that's what PCI
222 * interrupts are. If your platform does differently, then
223 * either provide a proper interrupt tree or don't use this
226 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
230 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
231 line
== 0xff || line
== 0) {
234 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
237 virq
= irq_create_mapping(NULL
, line
);
239 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
241 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
242 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
243 oirq
.controller
? oirq
.controller
->full_name
:
246 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
249 if (virq
== NO_IRQ
) {
250 pr_debug(" Failed to map !\n");
254 pr_debug(" Mapped to linux irq %d\n", virq
);
260 EXPORT_SYMBOL(pci_read_irq_line
);
263 * Platform support for /proc/bus/pci/X/Y mmap()s,
264 * modelled on the sparc64 implementation by Dave Miller.
269 * Adjust vm_pgoff of VMA such that it is the physical page offset
270 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
272 * Basically, the user finds the base address for his device which he wishes
273 * to mmap. They read the 32-bit value from the config space base register,
274 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
275 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
277 * Returns negative error code on failure, zero on success.
279 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
280 resource_size_t
*offset
,
281 enum pci_mmap_state mmap_state
)
283 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
284 unsigned long io_offset
= 0;
288 return NULL
; /* should never happen */
290 /* If memory, add on the PCI bridge address offset */
291 if (mmap_state
== pci_mmap_mem
) {
292 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
293 *offset
+= hose
->pci_mem_offset
;
295 res_bit
= IORESOURCE_MEM
;
297 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
298 *offset
+= io_offset
;
299 res_bit
= IORESOURCE_IO
;
303 * Check that the offset requested corresponds to one of the
304 * resources of the device.
306 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
307 struct resource
*rp
= &dev
->resource
[i
];
308 int flags
= rp
->flags
;
310 /* treat ROM as memory (should be already) */
311 if (i
== PCI_ROM_RESOURCE
)
312 flags
|= IORESOURCE_MEM
;
314 /* Active and same type? */
315 if ((flags
& res_bit
) == 0)
318 /* In the range of this resource? */
319 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
322 /* found it! construct the final physical address */
323 if (mmap_state
== pci_mmap_io
)
324 *offset
+= hose
->io_base_phys
- io_offset
;
332 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
335 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
337 enum pci_mmap_state mmap_state
,
340 pgprot_t prot
= protection
;
342 /* Write combine is always 0 on non-memory space mappings. On
343 * memory space, if the user didn't pass 1, we check for a
344 * "prefetchable" resource. This is a bit hackish, but we use
345 * this to workaround the inability of /sysfs to provide a write
348 if (mmap_state
!= pci_mmap_mem
)
350 else if (write_combine
== 0) {
351 if (rp
->flags
& IORESOURCE_PREFETCH
)
355 return pgprot_noncached(prot
);
359 * This one is used by /dev/mem and fbdev who have no clue about the
360 * PCI device, it tries to find the PCI device first and calls the
363 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
368 struct pci_dev
*pdev
= NULL
;
369 struct resource
*found
= NULL
;
370 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
373 if (page_is_ram(pfn
))
376 prot
= pgprot_noncached(prot
);
377 for_each_pci_dev(pdev
) {
378 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
379 struct resource
*rp
= &pdev
->resource
[i
];
380 int flags
= rp
->flags
;
382 /* Active and same type? */
383 if ((flags
& IORESOURCE_MEM
) == 0)
385 /* In the range of this resource? */
386 if (offset
< (rp
->start
& PAGE_MASK
) ||
396 if (found
->flags
& IORESOURCE_PREFETCH
)
397 prot
= pgprot_noncached_wc(prot
);
401 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
402 (unsigned long long)offset
, pgprot_val(prot
));
408 * Perform the actual remap of the pages for a PCI device mapping, as
409 * appropriate for this architecture. The region in the process to map
410 * is described by vm_start and vm_end members of VMA, the base physical
411 * address is found in vm_pgoff.
412 * The pci device structure is provided so that architectures may make mapping
413 * decisions on a per-device or per-bus basis.
415 * Returns a negative error code on failure, zero on success.
417 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
418 enum pci_mmap_state mmap_state
, int write_combine
)
420 resource_size_t offset
=
421 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
425 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
429 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
430 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
432 mmap_state
, write_combine
);
434 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
435 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
440 /* This provides legacy IO read access on a bus */
441 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
443 unsigned long offset
;
444 struct pci_controller
*hose
= pci_bus_to_host(bus
);
445 struct resource
*rp
= &hose
->io_resource
;
448 /* Check if port can be supported by that bus. We only check
449 * the ranges of the PHB though, not the bus itself as the rules
450 * for forwarding legacy cycles down bridges are not our problem
451 * here. So if the host bridge supports it, we do it.
453 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
456 if (!(rp
->flags
& IORESOURCE_IO
))
458 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
460 addr
= hose
->io_base_virt
+ port
;
464 *((u8
*)val
) = in_8(addr
);
469 *((u16
*)val
) = in_le16(addr
);
474 *((u32
*)val
) = in_le32(addr
);
480 /* This provides legacy IO write access on a bus */
481 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
483 unsigned long offset
;
484 struct pci_controller
*hose
= pci_bus_to_host(bus
);
485 struct resource
*rp
= &hose
->io_resource
;
488 /* Check if port can be supported by that bus. We only check
489 * the ranges of the PHB though, not the bus itself as the rules
490 * for forwarding legacy cycles down bridges are not our problem
491 * here. So if the host bridge supports it, we do it.
493 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
496 if (!(rp
->flags
& IORESOURCE_IO
))
498 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
500 addr
= hose
->io_base_virt
+ port
;
502 /* WARNING: The generic code is idiotic. It gets passed a pointer
503 * to what can be a 1, 2 or 4 byte quantity and always reads that
504 * as a u32, which means that we have to correct the location of
505 * the data read within those 32 bits for size 1 and 2
509 out_8(addr
, val
>> 24);
514 out_le16(addr
, val
>> 16);
525 /* This provides legacy IO or memory mmap access on a bus */
526 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
527 struct vm_area_struct
*vma
,
528 enum pci_mmap_state mmap_state
)
530 struct pci_controller
*hose
= pci_bus_to_host(bus
);
531 resource_size_t offset
=
532 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
533 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
536 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
537 pci_domain_nr(bus
), bus
->number
,
538 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
539 (unsigned long long)offset
,
540 (unsigned long long)(offset
+ size
- 1));
542 if (mmap_state
== pci_mmap_mem
) {
545 * Because X is lame and can fail starting if it gets an error
546 * trying to mmap legacy_mem (instead of just moving on without
547 * legacy memory access) we fake it here by giving it anonymous
548 * memory, effectively behaving just like /dev/zero
550 if ((offset
+ size
) > hose
->isa_mem_size
) {
553 "Process %s (pid:%d) mapped non-existing PCI"
554 "legacy memory for 0%04x:%02x\n",
555 current
->comm
, current
->pid
, pci_domain_nr(bus
),
558 if (vma
->vm_flags
& VM_SHARED
)
559 return shmem_zero_setup(vma
);
562 offset
+= hose
->isa_mem_phys
;
564 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- \
566 unsigned long roffset
= offset
+ io_offset
;
567 rp
= &hose
->io_resource
;
568 if (!(rp
->flags
& IORESOURCE_IO
))
570 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
572 offset
+= hose
->io_base_phys
;
574 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
576 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
577 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
578 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
579 vma
->vm_end
- vma
->vm_start
,
583 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
584 const struct resource
*rsrc
,
585 resource_size_t
*start
, resource_size_t
*end
)
587 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
588 resource_size_t offset
= 0;
593 if (rsrc
->flags
& IORESOURCE_IO
)
594 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
596 /* We pass a fully fixed up address to userland for MMIO instead of
597 * a BAR value because X is lame and expects to be able to use that
598 * to pass to /dev/mem !
600 * That means that we'll have potentially 64 bits values where some
601 * userland apps only expect 32 (like X itself since it thinks only
602 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
605 * Hopefully, the sysfs insterface is immune to that gunk. Once X
606 * has been fixed (and the fix spread enough), we can re-enable the
607 * 2 lines below and pass down a BAR value to userland. In that case
608 * we'll also have to re-enable the matching code in
609 * __pci_mmap_make_offset().
614 else if (rsrc
->flags
& IORESOURCE_MEM
)
615 offset
= hose
->pci_mem_offset
;
618 *start
= rsrc
->start
- offset
;
619 *end
= rsrc
->end
- offset
;
623 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
624 * @hose: newly allocated pci_controller to be setup
625 * @dev: device node of the host bridge
626 * @primary: set if primary bus (32 bits only, soon to be deprecated)
628 * This function will parse the "ranges" property of a PCI host bridge device
629 * node and setup the resource mapping of a pci controller based on its
632 * Life would be boring if it wasn't for a few issues that we have to deal
635 * - We can only cope with one IO space range and up to 3 Memory space
636 * ranges. However, some machines (thanks Apple !) tend to split their
637 * space into lots of small contiguous ranges. So we have to coalesce.
639 * - We can only cope with all memory ranges having the same offset
640 * between CPU addresses and PCI addresses. Unfortunately, some bridges
641 * are setup for a large 1:1 mapping along with a small "window" which
642 * maps PCI address 0 to some arbitrary high address of the CPU space in
643 * order to give access to the ISA memory hole.
644 * The way out of here that I've chosen for now is to always set the
645 * offset based on the first resource found, then override it if we
646 * have a different offset and the previous was set by an ISA hole.
648 * - Some busses have IO space not starting at 0, which causes trouble with
649 * the way we do our IO resource renumbering. The code somewhat deals with
650 * it for 64 bits but I would expect problems on 32 bits.
652 * - Some 32 bits platforms such as 4xx can have physical space larger than
653 * 32 bits so we need to use 64 bits values for the parsing
655 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
656 struct device_node
*dev
,
661 int pna
= of_n_addr_cells(dev
);
663 int memno
= 0, isa_hole
= -1;
665 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
666 unsigned long long isa_mb
= 0;
667 struct resource
*res
;
669 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
670 dev
->full_name
, primary
? "(primary)" : "");
672 /* Get ranges property */
673 ranges
= of_get_property(dev
, "ranges", &rlen
);
678 pr_debug("Parsing ranges property...\n");
679 while ((rlen
-= np
* 4) >= 0) {
680 /* Read next ranges element */
681 pci_space
= ranges
[0];
682 pci_addr
= of_read_number(ranges
+ 1, 2);
683 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
684 size
= of_read_number(ranges
+ pna
+ 3, 2);
686 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
687 "cpu_addr:0x%016llx size:0x%016llx\n",
688 pci_space
, pci_addr
, cpu_addr
, size
);
692 /* If we failed translation or got a zero-sized region
693 * (some FW try to feed us with non sensical zero sized regions
694 * such as power3 which look like some kind of attempt
695 * at exposing the VGA memory hole)
697 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
700 /* Now consume following elements while they are contiguous */
701 for (; rlen
>= np
* sizeof(u32
);
702 ranges
+= np
, rlen
-= np
* 4) {
703 if (ranges
[0] != pci_space
)
705 pci_next
= of_read_number(ranges
+ 1, 2);
706 cpu_next
= of_translate_address(dev
, ranges
+ 3);
707 if (pci_next
!= pci_addr
+ size
||
708 cpu_next
!= cpu_addr
+ size
)
710 size
+= of_read_number(ranges
+ pna
+ 3, 2);
713 /* Act based on address space type */
715 switch ((pci_space
>> 24) & 0x3) {
716 case 1: /* PCI IO space */
718 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
719 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
721 /* We support only one IO range */
722 if (hose
->pci_io_size
) {
724 " \\--> Skipped (too many) !\n");
727 /* On 32 bits, limit I/O space to 16MB */
728 if (size
> 0x01000000)
731 /* 32 bits needs to map IOs here */
732 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
734 /* Expect trouble if pci_addr is not 0 */
737 (unsigned long)hose
->io_base_virt
;
738 /* pci_io_size and io_base_phys always represent IO
739 * space starting at 0 so we factor in pci_addr
741 hose
->pci_io_size
= pci_addr
+ size
;
742 hose
->io_base_phys
= cpu_addr
- pci_addr
;
745 res
= &hose
->io_resource
;
746 res
->flags
= IORESOURCE_IO
;
747 res
->start
= pci_addr
;
749 case 2: /* PCI Memory space */
750 case 3: /* PCI 64 bits Memory space */
752 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
753 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
754 (pci_space
& 0x40000000) ? "Prefetch" : "");
756 /* We support only 3 memory ranges */
759 " \\--> Skipped (too many) !\n");
762 /* Handles ISA memory hole space here */
766 if (primary
|| isa_mem_base
== 0)
767 isa_mem_base
= cpu_addr
;
768 hose
->isa_mem_phys
= cpu_addr
;
769 hose
->isa_mem_size
= size
;
772 /* We get the PCI/Mem offset from the first range or
773 * the, current one if the offset came from an ISA
774 * hole. If they don't match, bugger.
777 (isa_hole
>= 0 && pci_addr
!= 0 &&
778 hose
->pci_mem_offset
== isa_mb
))
779 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
780 else if (pci_addr
!= 0 &&
781 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
783 " \\--> Skipped (offset mismatch) !\n");
788 res
= &hose
->mem_resources
[memno
++];
789 res
->flags
= IORESOURCE_MEM
;
790 if (pci_space
& 0x40000000)
791 res
->flags
|= IORESOURCE_PREFETCH
;
792 res
->start
= cpu_addr
;
796 res
->name
= dev
->full_name
;
797 res
->end
= res
->start
+ size
- 1;
804 /* If there's an ISA hole and the pci_mem_offset is -not- matching
805 * the ISA hole offset, then we need to remove the ISA hole from
806 * the resource list for that brige
808 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
809 unsigned int next
= isa_hole
+ 1;
810 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
812 memmove(&hose
->mem_resources
[isa_hole
],
813 &hose
->mem_resources
[next
],
814 sizeof(struct resource
) * (memno
- next
));
815 hose
->mem_resources
[--memno
].flags
= 0;
819 /* Decide whether to display the domain number in /proc */
820 int pci_proc_domain(struct pci_bus
*bus
)
822 struct pci_controller
*hose
= pci_bus_to_host(bus
);
824 if (!(pci_flags
& PCI_ENABLE_PROC_DOMAINS
))
826 if (pci_flags
& PCI_COMPAT_DOMAIN_0
)
827 return hose
->global_number
!= 0;
831 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
832 struct resource
*res
)
834 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
835 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
839 if (res
->flags
& IORESOURCE_IO
) {
840 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
842 } else if (res
->flags
& IORESOURCE_MEM
)
843 offset
= hose
->pci_mem_offset
;
845 region
->start
= (res
->start
- offset
) & mask
;
846 region
->end
= (res
->end
- offset
) & mask
;
848 EXPORT_SYMBOL(pcibios_resource_to_bus
);
850 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
851 struct pci_bus_region
*region
)
853 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
854 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
858 if (res
->flags
& IORESOURCE_IO
) {
859 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
861 } else if (res
->flags
& IORESOURCE_MEM
)
862 offset
= hose
->pci_mem_offset
;
863 res
->start
= (region
->start
+ offset
) & mask
;
864 res
->end
= (region
->end
+ offset
) & mask
;
866 EXPORT_SYMBOL(pcibios_bus_to_resource
);
868 /* Fixup a bus resource into a linux resource */
869 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
871 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
872 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
874 if (res
->flags
& IORESOURCE_IO
) {
875 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
877 } else if (res
->flags
& IORESOURCE_MEM
)
878 offset
= hose
->pci_mem_offset
;
880 res
->start
= (res
->start
+ offset
) & mask
;
881 res
->end
= (res
->end
+ offset
) & mask
;
884 /* This header fixup will do the resource fixup for all devices as they are
885 * probed, but not for bridge ranges
887 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
889 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
893 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
897 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
898 struct resource
*res
= dev
->resource
+ i
;
901 /* On platforms that have PCI_PROBE_ONLY set, we don't
902 * consider 0 as an unassigned BAR value. It's technically
903 * a valid value, but linux doesn't like it... so when we can
904 * re-assign things, we do so, but if we can't, we keep it
905 * around and hope for the best...
907 if (res
->start
== 0 && !(pci_flags
& PCI_PROBE_ONLY
)) {
908 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
911 (unsigned long long)res
->start
,
912 (unsigned long long)res
->end
,
913 (unsigned int)res
->flags
);
914 res
->end
-= res
->start
;
916 res
->flags
|= IORESOURCE_UNSET
;
920 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
922 (unsigned long long)res
->start
,\
923 (unsigned long long)res
->end
,
924 (unsigned int)res
->flags
);
926 fixup_resource(res
, dev
);
928 pr_debug("PCI:%s %016llx-%016llx\n",
930 (unsigned long long)res
->start
,
931 (unsigned long long)res
->end
);
934 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
936 /* This function tries to figure out if a bridge resource has been initialized
937 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
938 * things go more smoothly when it gets it right. It should covers cases such
939 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
941 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
942 struct resource
*res
)
944 struct pci_controller
*hose
= pci_bus_to_host(bus
);
945 struct pci_dev
*dev
= bus
->self
;
946 resource_size_t offset
;
950 /* We don't do anything if PCI_PROBE_ONLY is set */
951 if (pci_flags
& PCI_PROBE_ONLY
)
954 /* Job is a bit different between memory and IO */
955 if (res
->flags
& IORESOURCE_MEM
) {
956 /* If the BAR is non-0 (res != pci_mem_offset) then it's
957 * probably been initialized by somebody
959 if (res
->start
!= hose
->pci_mem_offset
)
962 /* The BAR is 0, let's check if memory decoding is enabled on
963 * the bridge. If not, we consider it unassigned
965 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
966 if ((command
& PCI_COMMAND_MEMORY
) == 0)
969 /* Memory decoding is enabled and the BAR is 0. If any of
970 * the bridge resources covers that starting address (0 then
971 * it's good enough for us for memory
973 for (i
= 0; i
< 3; i
++) {
974 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
975 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
979 /* Well, it starts at 0 and we know it will collide so we may as
980 * well consider it as unassigned. That covers the Apple case.
984 /* If the BAR is non-0, then we consider it assigned */
985 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
986 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
989 /* Here, we are a bit different than memory as typically IO
990 * space starting at low addresses -is- valid. What we do
991 * instead if that we consider as unassigned anything that
992 * doesn't have IO enabled in the PCI command register,
995 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
996 if (command
& PCI_COMMAND_IO
)
999 /* It's starting at 0 and IO is disabled in the bridge, consider
1006 /* Fixup resources of a PCI<->PCI bridge */
1007 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1009 struct resource
*res
;
1012 struct pci_dev
*dev
= bus
->self
;
1014 pci_bus_for_each_resource(bus
, res
, i
) {
1015 res
= bus
->resource
[i
];
1020 if (i
>= 3 && bus
->self
->transparent
)
1023 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1025 (unsigned long long)res
->start
,\
1026 (unsigned long long)res
->end
,
1027 (unsigned int)res
->flags
);
1030 fixup_resource(res
, dev
);
1032 /* Try to detect uninitialized P2P bridge resources,
1033 * and clear them out so they get re-assigned later
1035 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1037 pr_debug("PCI:%s (unassigned)\n",
1040 pr_debug("PCI:%s %016llx-%016llx\n",
1042 (unsigned long long)res
->start
,
1043 (unsigned long long)res
->end
);
1048 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1050 /* Fix up the bus resources for P2P bridges */
1051 if (bus
->self
!= NULL
)
1052 pcibios_fixup_bridge(bus
);
1055 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1057 struct pci_dev
*dev
;
1059 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1060 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1062 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1063 /* Setup OF node pointer in archdata */
1064 dev
->dev
.of_node
= pci_device_to_OF_node(dev
);
1066 /* Fixup NUMA node as it may not be setup yet by the generic
1067 * code and is needed by the DMA init
1069 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1071 /* Hook up default DMA ops */
1072 set_dma_ops(&dev
->dev
, pci_dma_ops
);
1073 dev
->dev
.archdata
.dma_data
= (void *)PCI_DRAM_OFFSET
;
1075 /* Read default IRQs and fixup if necessary */
1076 pci_read_irq_line(dev
);
1080 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1082 /* When called from the generic PCI probe, read PCI<->PCI bridge
1083 * bases. This is -not- called when generating the PCI tree from
1084 * the OF device-tree.
1086 if (bus
->self
!= NULL
)
1087 pci_read_bridge_bases(bus
);
1089 /* Now fixup the bus bus */
1090 pcibios_setup_bus_self(bus
);
1092 /* Now fixup devices on that bus */
1093 pcibios_setup_bus_devices(bus
);
1095 EXPORT_SYMBOL(pcibios_fixup_bus
);
1097 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1099 if ((pci_flags
& PCI_CAN_SKIP_ISA_ALIGN
) &&
1100 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1106 * We need to avoid collisions with `mirrored' VGA ports
1107 * and other strange ISA hardware, so we always want the
1108 * addresses to be allocated in the 0x000-0x0ff region
1111 * Why? Because some silly external IO cards only decode
1112 * the low 10 bits of the IO address. The 0x00-0xff region
1113 * is reserved for motherboard devices that decode all 16
1114 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1115 * but we want to try to avoid allocating at 0x2900-0x2bff
1116 * which might have be mirrored at 0x0100-0x03ff..
1118 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1119 resource_size_t size
, resource_size_t align
)
1121 struct pci_dev
*dev
= data
;
1122 resource_size_t start
= res
->start
;
1124 if (res
->flags
& IORESOURCE_IO
) {
1125 if (skip_isa_ioresource_align(dev
))
1128 start
= (start
+ 0x3ff) & ~0x3ff;
1133 EXPORT_SYMBOL(pcibios_align_resource
);
1136 * Reparent resource children of pr that conflict with res
1137 * under res, and make res replace those children.
1139 static int __init
reparent_resources(struct resource
*parent
,
1140 struct resource
*res
)
1142 struct resource
*p
, **pp
;
1143 struct resource
**firstpp
= NULL
;
1145 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1146 if (p
->end
< res
->start
)
1148 if (res
->end
< p
->start
)
1150 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1151 return -1; /* not completely contained */
1152 if (firstpp
== NULL
)
1155 if (firstpp
== NULL
)
1156 return -1; /* didn't find any conflicting entries? */
1157 res
->parent
= parent
;
1158 res
->child
= *firstpp
;
1162 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1164 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1166 (unsigned long long)p
->start
,
1167 (unsigned long long)p
->end
, res
->name
);
1173 * Handle resources of PCI devices. If the world were perfect, we could
1174 * just allocate all the resource regions and do nothing more. It isn't.
1175 * On the other hand, we cannot just re-allocate all devices, as it would
1176 * require us to know lots of host bridge internals. So we attempt to
1177 * keep as much of the original configuration as possible, but tweak it
1178 * when it's found to be wrong.
1180 * Known BIOS problems we have to work around:
1181 * - I/O or memory regions not configured
1182 * - regions configured, but not enabled in the command register
1183 * - bogus I/O addresses above 64K used
1184 * - expansion ROMs left enabled (this may sound harmless, but given
1185 * the fact the PCI specs explicitly allow address decoders to be
1186 * shared between expansion ROMs and other resource regions, it's
1187 * at least dangerous)
1190 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1191 * This gives us fixed barriers on where we can allocate.
1192 * (2) Allocate resources for all enabled devices. If there is
1193 * a collision, just mark the resource as unallocated. Also
1194 * disable expansion ROMs during this step.
1195 * (3) Try to allocate resources for disabled devices. If the
1196 * resources were assigned correctly, everything goes well,
1197 * if they weren't, they won't disturb allocation of other
1199 * (4) Assign new addresses to resources which were either
1200 * not configured at all or misconfigured. If explicitly
1201 * requested by the user, configure expansion ROM address
1205 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1209 struct resource
*res
, *pr
;
1211 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1212 pci_domain_nr(bus
), bus
->number
);
1214 pci_bus_for_each_resource(bus
, res
, i
) {
1215 res
= bus
->resource
[i
];
1216 if (!res
|| !res
->flags
1217 || res
->start
> res
->end
|| res
->parent
)
1219 if (bus
->parent
== NULL
)
1220 pr
= (res
->flags
& IORESOURCE_IO
) ?
1221 &ioport_resource
: &iomem_resource
;
1223 /* Don't bother with non-root busses when
1224 * re-assigning all resources. We clear the
1225 * resource flags as if they were colliding
1226 * and as such ensure proper re-allocation
1229 if (pci_flags
& PCI_REASSIGN_ALL_RSRC
)
1230 goto clear_resource
;
1231 pr
= pci_find_parent_resource(bus
->self
, res
);
1233 /* this happens when the generic PCI
1234 * code (wrongly) decides that this
1235 * bridge is transparent -- paulus
1241 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1242 "[0x%x], parent %p (%s)\n",
1243 bus
->self
? pci_name(bus
->self
) : "PHB",
1245 (unsigned long long)res
->start
,
1246 (unsigned long long)res
->end
,
1247 (unsigned int)res
->flags
,
1248 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1250 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1251 if (request_resource(pr
, res
) == 0)
1254 * Must be a conflict with an existing entry.
1255 * Move that entry (or entries) under the
1256 * bridge resource and try again.
1258 if (reparent_resources(pr
, res
) == 0)
1261 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1262 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1264 res
->start
= res
->end
= 0;
1268 list_for_each_entry(b
, &bus
->children
, node
)
1269 pcibios_allocate_bus_resources(b
);
1272 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1274 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1276 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1278 (unsigned long long)r
->start
,
1279 (unsigned long long)r
->end
,
1280 (unsigned int)r
->flags
);
1282 pr
= pci_find_parent_resource(dev
, r
);
1283 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1284 request_resource(pr
, r
) < 0) {
1285 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1286 " of device %s, will remap\n", idx
, pci_name(dev
));
1288 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1290 (unsigned long long)pr
->start
,
1291 (unsigned long long)pr
->end
,
1292 (unsigned int)pr
->flags
);
1293 /* We'll assign a new address later */
1294 r
->flags
|= IORESOURCE_UNSET
;
1300 static void __init
pcibios_allocate_resources(int pass
)
1302 struct pci_dev
*dev
= NULL
;
1307 for_each_pci_dev(dev
) {
1308 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1309 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1310 r
= &dev
->resource
[idx
];
1311 if (r
->parent
) /* Already allocated */
1313 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1314 continue; /* Not assigned at all */
1315 /* We only allocate ROMs on pass 1 just in case they
1316 * have been screwed up by firmware
1318 if (idx
== PCI_ROM_RESOURCE
)
1320 if (r
->flags
& IORESOURCE_IO
)
1321 disabled
= !(command
& PCI_COMMAND_IO
);
1323 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1324 if (pass
== disabled
)
1325 alloc_resource(dev
, idx
);
1329 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1331 /* Turn the ROM off, leave the resource region,
1332 * but keep it unregistered.
1335 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1336 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1337 pr_debug("PCI: Switching off ROM of %s\n",
1339 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1340 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1341 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1347 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1349 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1350 resource_size_t offset
;
1351 struct resource
*res
, *pres
;
1354 pr_debug("Reserving legacy ranges for domain %04x\n",
1355 pci_domain_nr(bus
));
1358 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1360 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1361 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1362 BUG_ON(res
== NULL
);
1363 res
->name
= "Legacy IO";
1364 res
->flags
= IORESOURCE_IO
;
1365 res
->start
= offset
;
1366 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1367 pr_debug("Candidate legacy IO: %pR\n", res
);
1368 if (request_resource(&hose
->io_resource
, res
)) {
1370 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1371 pci_domain_nr(bus
), bus
->number
, res
);
1376 /* Check for memory */
1377 offset
= hose
->pci_mem_offset
;
1378 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1379 for (i
= 0; i
< 3; i
++) {
1380 pres
= &hose
->mem_resources
[i
];
1381 if (!(pres
->flags
& IORESOURCE_MEM
))
1383 pr_debug("hose mem res: %pR\n", pres
);
1384 if ((pres
->start
- offset
) <= 0xa0000 &&
1385 (pres
->end
- offset
) >= 0xbffff)
1390 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1391 BUG_ON(res
== NULL
);
1392 res
->name
= "Legacy VGA memory";
1393 res
->flags
= IORESOURCE_MEM
;
1394 res
->start
= 0xa0000 + offset
;
1395 res
->end
= 0xbffff + offset
;
1396 pr_debug("Candidate VGA memory: %pR\n", res
);
1397 if (request_resource(pres
, res
)) {
1399 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1400 pci_domain_nr(bus
), bus
->number
, res
);
1405 void __init
pcibios_resource_survey(void)
1409 /* Allocate and assign resources. If we re-assign everything, then
1410 * we skip the allocate phase
1412 list_for_each_entry(b
, &pci_root_buses
, node
)
1413 pcibios_allocate_bus_resources(b
);
1415 if (!(pci_flags
& PCI_REASSIGN_ALL_RSRC
)) {
1416 pcibios_allocate_resources(0);
1417 pcibios_allocate_resources(1);
1420 /* Before we start assigning unassigned resource, we try to reserve
1421 * the low IO area and the VGA memory area if they intersect the
1422 * bus available resources to avoid allocating things on top of them
1424 if (!(pci_flags
& PCI_PROBE_ONLY
)) {
1425 list_for_each_entry(b
, &pci_root_buses
, node
)
1426 pcibios_reserve_legacy_regions(b
);
1429 /* Now, if the platform didn't decide to blindly trust the firmware,
1430 * we proceed to assigning things that were left unassigned
1432 if (!(pci_flags
& PCI_PROBE_ONLY
)) {
1433 pr_debug("PCI: Assigning unassigned resources...\n");
1434 pci_assign_unassigned_resources();
1438 #ifdef CONFIG_HOTPLUG
1440 /* This is used by the PCI hotplug driver to allocate resource
1441 * of newly plugged busses. We can try to consolidate with the
1442 * rest of the code later, for now, keep it as-is as our main
1443 * resource allocation function doesn't deal with sub-trees yet.
1445 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1447 struct pci_dev
*dev
;
1448 struct pci_bus
*child_bus
;
1450 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1453 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1454 struct resource
*r
= &dev
->resource
[i
];
1456 if (r
->parent
|| !r
->start
|| !r
->flags
)
1459 pr_debug("PCI: Claiming %s: "
1460 "Resource %d: %016llx..%016llx [%x]\n",
1462 (unsigned long long)r
->start
,
1463 (unsigned long long)r
->end
,
1464 (unsigned int)r
->flags
);
1466 pci_claim_resource(dev
, i
);
1470 list_for_each_entry(child_bus
, &bus
->children
, node
)
1471 pcibios_claim_one_bus(child_bus
);
1473 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1476 /* pcibios_finish_adding_to_bus
1478 * This is to be called by the hotplug code after devices have been
1479 * added to a bus, this include calling it for a PHB that is just
1482 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1484 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1485 pci_domain_nr(bus
), bus
->number
);
1487 /* Allocate bus and devices resources */
1488 pcibios_allocate_bus_resources(bus
);
1489 pcibios_claim_one_bus(bus
);
1491 /* Add new devices to global lists. Register in proc, sysfs. */
1492 pci_bus_add_devices(bus
);
1495 /* eeh_add_device_tree_late(bus); */
1497 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1499 #endif /* CONFIG_HOTPLUG */
1501 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1503 return pci_enable_resources(dev
, mask
);
1506 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1508 struct pci_bus
*bus
= hose
->bus
;
1509 struct resource
*res
;
1512 /* Hookup PHB IO resource */
1513 bus
->resource
[0] = res
= &hose
->io_resource
;
1516 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1517 " bridge %s (domain %d)\n",
1518 hose
->dn
->full_name
, hose
->global_number
);
1519 /* Workaround for lack of IO resource only on 32-bit */
1520 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1521 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1522 res
->flags
= IORESOURCE_IO
;
1525 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1526 (unsigned long long)res
->start
,
1527 (unsigned long long)res
->end
,
1528 (unsigned long)res
->flags
);
1530 /* Hookup PHB Memory resources */
1531 for (i
= 0; i
< 3; ++i
) {
1532 res
= &hose
->mem_resources
[i
];
1536 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1537 "host bridge %s (domain %d)\n",
1538 hose
->dn
->full_name
, hose
->global_number
);
1540 /* Workaround for lack of MEM resource only on 32-bit */
1541 res
->start
= hose
->pci_mem_offset
;
1542 res
->end
= (resource_size_t
)-1LL;
1543 res
->flags
= IORESOURCE_MEM
;
1546 bus
->resource
[i
+1] = res
;
1548 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1549 i
, (unsigned long long)res
->start
,
1550 (unsigned long long)res
->end
,
1551 (unsigned long)res
->flags
);
1554 pr_debug("PCI: PHB MEM offset = %016llx\n",
1555 (unsigned long long)hose
->pci_mem_offset
);
1556 pr_debug("PCI: PHB IO offset = %08lx\n",
1557 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1561 * Null PCI config access functions, for the case when we can't
1564 #define NULL_PCI_OP(rw, size, type) \
1566 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1568 return PCIBIOS_DEVICE_NOT_FOUND; \
1572 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1575 return PCIBIOS_DEVICE_NOT_FOUND
;
1579 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1582 return PCIBIOS_DEVICE_NOT_FOUND
;
1585 static struct pci_ops null_pci_ops
= {
1586 .read
= null_read_config
,
1587 .write
= null_write_config
,
1591 * These functions are used early on before PCI scanning is done
1592 * and all of the pci_dev and pci_bus structures have been created.
1594 static struct pci_bus
*
1595 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1597 static struct pci_bus bus
;
1600 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1604 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1608 #define EARLY_PCI_OP(rw, size, type) \
1609 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1610 int devfn, int offset, type value) \
1612 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1613 devfn, offset, value); \
1616 EARLY_PCI_OP(read
, byte
, u8
*)
1617 EARLY_PCI_OP(read
, word
, u16
*)
1618 EARLY_PCI_OP(read
, dword
, u32
*)
1619 EARLY_PCI_OP(write
, byte
, u8
)
1620 EARLY_PCI_OP(write
, word
, u16
)
1621 EARLY_PCI_OP(write
, dword
, u32
)
1623 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1626 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);