ACPI: thinkpad-acpi: preserve radio state across shutdown
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / powerpc / boot / dts / virtex440-ml507.dts
blobdc8e78e2dceb27d791f07e1f9d78c760665dd4b3
1 /*
2  * This file supports the Xilinx ML507 board with the 440 processor.
3  * A reference design for the FPGA is provided at http://git.xilinx.com.
4  *
5  * (C) Copyright 2008 Xilinx, Inc.
6  *
7  * This file is licensed under the terms of the GNU General Public License
8  * version 2. This program is licensed "as is" without any warranty of any
9  * kind, whether express or implied.
10  */
12 /dts-v1/;
14 / {
15         #address-cells = <1>;
16         #size-cells = <1>;
17         compatible = "xlnx,virtex440";
18         dcr-parent = <&ppc440_0>;
19         model = "testing";
20         DDR2_SDRAM: memory@0 {
21                 device_type = "memory";
22                 reg = < 0 0x10000000 >;
23         } ;
24         chosen {
25                 bootargs = "console=ttyS0 ip=on root=/dev/ram";
26                 linux,stdout-path = "/plb@0/serial@83e00000";
27         } ;
28         cpus {
29                 #address-cells = <1>;
30                 #cpus = <1>;
31                 #size-cells = <0>;
32                 ppc440_0: cpu@0 {
33                         clock-frequency = <400000000>;
34                         compatible = "PowerPC,440", "ibm,ppc440";
35                         d-cache-line-size = <0x20>;
36                         d-cache-size = <0x8000>;
37                         dcr-access-method = "native";
38                         dcr-controller ;
39                         device_type = "cpu";
40                         i-cache-line-size = <0x20>;
41                         i-cache-size = <0x8000>;
42                         model = "PowerPC,440";
43                         reg = <0>;
44                         timebase-frequency = <400000000>;
45                         xlnx,apu-control = <1>;
46                         xlnx,apu-udi-0 = <0>;
47                         xlnx,apu-udi-1 = <0>;
48                         xlnx,apu-udi-10 = <0>;
49                         xlnx,apu-udi-11 = <0>;
50                         xlnx,apu-udi-12 = <0>;
51                         xlnx,apu-udi-13 = <0>;
52                         xlnx,apu-udi-14 = <0>;
53                         xlnx,apu-udi-15 = <0>;
54                         xlnx,apu-udi-2 = <0>;
55                         xlnx,apu-udi-3 = <0>;
56                         xlnx,apu-udi-4 = <0>;
57                         xlnx,apu-udi-5 = <0>;
58                         xlnx,apu-udi-6 = <0>;
59                         xlnx,apu-udi-7 = <0>;
60                         xlnx,apu-udi-8 = <0>;
61                         xlnx,apu-udi-9 = <0>;
62                         xlnx,dcr-autolock-enable = <1>;
63                         xlnx,dcu-rd-ld-cache-plb-prio = <0>;
64                         xlnx,dcu-rd-noncache-plb-prio = <0>;
65                         xlnx,dcu-rd-touch-plb-prio = <0>;
66                         xlnx,dcu-rd-urgent-plb-prio = <0>;
67                         xlnx,dcu-wr-flush-plb-prio = <0>;
68                         xlnx,dcu-wr-store-plb-prio = <0>;
69                         xlnx,dcu-wr-urgent-plb-prio = <0>;
70                         xlnx,dma0-control = <0>;
71                         xlnx,dma0-plb-prio = <0>;
72                         xlnx,dma0-rxchannelctrl = <0x1010000>;
73                         xlnx,dma0-rxirqtimer = <0x3ff>;
74                         xlnx,dma0-txchannelctrl = <0x1010000>;
75                         xlnx,dma0-txirqtimer = <0x3ff>;
76                         xlnx,dma1-control = <0>;
77                         xlnx,dma1-plb-prio = <0>;
78                         xlnx,dma1-rxchannelctrl = <0x1010000>;
79                         xlnx,dma1-rxirqtimer = <0x3ff>;
80                         xlnx,dma1-txchannelctrl = <0x1010000>;
81                         xlnx,dma1-txirqtimer = <0x3ff>;
82                         xlnx,dma2-control = <0>;
83                         xlnx,dma2-plb-prio = <0>;
84                         xlnx,dma2-rxchannelctrl = <0x1010000>;
85                         xlnx,dma2-rxirqtimer = <0x3ff>;
86                         xlnx,dma2-txchannelctrl = <0x1010000>;
87                         xlnx,dma2-txirqtimer = <0x3ff>;
88                         xlnx,dma3-control = <0>;
89                         xlnx,dma3-plb-prio = <0>;
90                         xlnx,dma3-rxchannelctrl = <0x1010000>;
91                         xlnx,dma3-rxirqtimer = <0x3ff>;
92                         xlnx,dma3-txchannelctrl = <0x1010000>;
93                         xlnx,dma3-txirqtimer = <0x3ff>;
94                         xlnx,endian-reset = <0>;
95                         xlnx,generate-plb-timespecs = <1>;
96                         xlnx,icu-rd-fetch-plb-prio = <0>;
97                         xlnx,icu-rd-spec-plb-prio = <0>;
98                         xlnx,icu-rd-touch-plb-prio = <0>;
99                         xlnx,interconnect-imask = <0xffffffff>;
100                         xlnx,mplb-allow-lock-xfer = <1>;
101                         xlnx,mplb-arb-mode = <0>;
102                         xlnx,mplb-awidth = <0x20>;
103                         xlnx,mplb-counter = <0x500>;
104                         xlnx,mplb-dwidth = <0x80>;
105                         xlnx,mplb-max-burst = <8>;
106                         xlnx,mplb-native-dwidth = <0x80>;
107                         xlnx,mplb-p2p = <0>;
108                         xlnx,mplb-prio-dcur = <2>;
109                         xlnx,mplb-prio-dcuw = <3>;
110                         xlnx,mplb-prio-icu = <4>;
111                         xlnx,mplb-prio-splb0 = <1>;
112                         xlnx,mplb-prio-splb1 = <0>;
113                         xlnx,mplb-read-pipe-enable = <1>;
114                         xlnx,mplb-sync-tattribute = <0>;
115                         xlnx,mplb-wdog-enable = <1>;
116                         xlnx,mplb-write-pipe-enable = <1>;
117                         xlnx,mplb-write-post-enable = <1>;
118                         xlnx,num-dma = <1>;
119                         xlnx,pir = <0xf>;
120                         xlnx,ppc440mc-addr-base = <0>;
121                         xlnx,ppc440mc-addr-high = <0xfffffff>;
122                         xlnx,ppc440mc-arb-mode = <0>;
123                         xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
124                         xlnx,ppc440mc-control = <0xf810008f>;
125                         xlnx,ppc440mc-max-burst = <8>;
126                         xlnx,ppc440mc-prio-dcur = <2>;
127                         xlnx,ppc440mc-prio-dcuw = <3>;
128                         xlnx,ppc440mc-prio-icu = <4>;
129                         xlnx,ppc440mc-prio-splb0 = <1>;
130                         xlnx,ppc440mc-prio-splb1 = <0>;
131                         xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
132                         xlnx,ppcdm-asyncmode = <0>;
133                         xlnx,ppcds-asyncmode = <0>;
134                         xlnx,user-reset = <0>;
135                         DMA0: sdma@80 {
136                                 compatible = "xlnx,ll-dma-1.00.a";
137                                 dcr-reg = < 0x80 0x11 >;
138                                 interrupt-parent = <&xps_intc_0>;
139                                 interrupts = < 9 2 0xa 2 >;
140                         } ;
141                 } ;
142         } ;
143         plb_v46_0: plb@0 {
144                 #address-cells = <1>;
145                 #size-cells = <1>;
146                 compatible = "xlnx,plb-v46-1.02.a", "simple-bus";
147                 ranges ;
148                 DIP_Switches_8Bit: gpio@81460000 {
149                         compatible = "xlnx,xps-gpio-1.00.a";
150                         interrupt-parent = <&xps_intc_0>;
151                         interrupts = < 6 2 >;
152                         reg = < 0x81460000 0x10000 >;
153                         xlnx,all-inputs = <1>;
154                         xlnx,all-inputs-2 = <0>;
155                         xlnx,dout-default = <0>;
156                         xlnx,dout-default-2 = <0>;
157                         xlnx,family = "virtex5";
158                         xlnx,gpio-width = <8>;
159                         xlnx,interrupt-present = <1>;
160                         xlnx,is-bidir = <1>;
161                         xlnx,is-bidir-2 = <1>;
162                         xlnx,is-dual = <0>;
163                         xlnx,tri-default = <0xffffffff>;
164                         xlnx,tri-default-2 = <0xffffffff>;
165                 } ;
166                 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
167                         #address-cells = <1>;
168                         #size-cells = <1>;
169                         compatible = "xlnx,compound";
170                         ethernet@81c00000 {
171                                 compatible = "xlnx,xps-ll-temac-1.01.b";
172                                 device_type = "network";
173                                 interrupt-parent = <&xps_intc_0>;
174                                 interrupts = < 5 2 >;
175                                 llink-connected = <&DMA0>;
176                                 local-mac-address = [ 02 00 00 00 00 00 ];
177                                 reg = < 0x81c00000 0x40 >;
178                                 xlnx,bus2core-clk-ratio = <1>;
179                                 xlnx,phy-type = <1>;
180                                 xlnx,phyaddr = <1>;
181                                 xlnx,rxcsum = <1>;
182                                 xlnx,rxfifo = <0x1000>;
183                                 xlnx,temac-type = <0>;
184                                 xlnx,txcsum = <1>;
185                                 xlnx,txfifo = <0x1000>;
186                         } ;
187                 } ;
188                 LEDs_8Bit: gpio@81400000 {
189                         compatible = "xlnx,xps-gpio-1.00.a";
190                         reg = < 0x81400000 0x10000 >;
191                         xlnx,all-inputs = <0>;
192                         xlnx,all-inputs-2 = <0>;
193                         xlnx,dout-default = <0>;
194                         xlnx,dout-default-2 = <0>;
195                         xlnx,family = "virtex5";
196                         xlnx,gpio-width = <8>;
197                         xlnx,interrupt-present = <0>;
198                         xlnx,is-bidir = <1>;
199                         xlnx,is-bidir-2 = <1>;
200                         xlnx,is-dual = <0>;
201                         xlnx,tri-default = <0xffffffff>;
202                         xlnx,tri-default-2 = <0xffffffff>;
203                 } ;
204                 LEDs_Positions: gpio@81420000 {
205                         compatible = "xlnx,xps-gpio-1.00.a";
206                         reg = < 0x81420000 0x10000 >;
207                         xlnx,all-inputs = <0>;
208                         xlnx,all-inputs-2 = <0>;
209                         xlnx,dout-default = <0>;
210                         xlnx,dout-default-2 = <0>;
211                         xlnx,family = "virtex5";
212                         xlnx,gpio-width = <5>;
213                         xlnx,interrupt-present = <0>;
214                         xlnx,is-bidir = <1>;
215                         xlnx,is-bidir-2 = <1>;
216                         xlnx,is-dual = <0>;
217                         xlnx,tri-default = <0xffffffff>;
218                         xlnx,tri-default-2 = <0xffffffff>;
219                 } ;
220                 Push_Buttons_5Bit: gpio@81440000 {
221                         compatible = "xlnx,xps-gpio-1.00.a";
222                         interrupt-parent = <&xps_intc_0>;
223                         interrupts = < 7 2 >;
224                         reg = < 0x81440000 0x10000 >;
225                         xlnx,all-inputs = <1>;
226                         xlnx,all-inputs-2 = <0>;
227                         xlnx,dout-default = <0>;
228                         xlnx,dout-default-2 = <0>;
229                         xlnx,family = "virtex5";
230                         xlnx,gpio-width = <5>;
231                         xlnx,interrupt-present = <1>;
232                         xlnx,is-bidir = <1>;
233                         xlnx,is-bidir-2 = <1>;
234                         xlnx,is-dual = <0>;
235                         xlnx,tri-default = <0xffffffff>;
236                         xlnx,tri-default-2 = <0xffffffff>;
237                 } ;
238                 RS232_Uart_1: serial@83e00000 {
239                         clock-frequency = <100000000>;
240                         compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
241                         current-speed = <0x2580>;
242                         device_type = "serial";
243                         interrupt-parent = <&xps_intc_0>;
244                         interrupts = < 8 2 >;
245                         reg = < 0x83e00000 0x10000 >;
246                         reg-offset = <3>;
247                         reg-shift = <2>;
248                         xlnx,family = "virtex5";
249                         xlnx,has-external-rclk = <0>;
250                         xlnx,has-external-xin = <0>;
251                         xlnx,is-a-16550 = <1>;
252                 } ;
253                 SysACE_CompactFlash: sysace@83600000 {
254                         compatible = "xlnx,xps-sysace-1.00.a";
255                         interrupt-parent = <&xps_intc_0>;
256                         interrupts = < 4 2 >;
257                         reg = < 0x83600000 0x10000 >;
258                         xlnx,family = "virtex5";
259                         xlnx,mem-width = <0x10>;
260                 } ;
261                 xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
262                         compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
263                         reg = < 0xffff0000 0x10000 >;
264                         xlnx,family = "virtex5";
265                 } ;
266                 xps_intc_0: interrupt-controller@81800000 {
267                         #interrupt-cells = <2>;
268                         compatible = "xlnx,xps-intc-1.00.a";
269                         interrupt-controller ;
270                         reg = < 0x81800000 0x10000 >;
271                         xlnx,num-intr-inputs = <0xb>;
272                 } ;
273                 xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
274                         compatible = "xlnx,xps-timebase-wdt-1.00.b";
275                         interrupt-parent = <&xps_intc_0>;
276                         interrupts = < 2 0 1 2 >;
277                         reg = < 0x83a00000 0x10000 >;
278                         xlnx,family = "virtex5";
279                         xlnx,wdt-enable-once = <0>;
280                         xlnx,wdt-interval = <0x1e>;
281                 } ;
282                 xps_timer_1: timer@83c00000 {
283                         compatible = "xlnx,xps-timer-1.00.a";
284                         interrupt-parent = <&xps_intc_0>;
285                         interrupts = < 3 2 >;
286                         reg = < 0x83c00000 0x10000 >;
287                         xlnx,count-width = <0x20>;
288                         xlnx,family = "virtex5";
289                         xlnx,gen0-assert = <1>;
290                         xlnx,gen1-assert = <1>;
291                         xlnx,one-timer-only = <1>;
292                         xlnx,trig0-assert = <1>;
293                         xlnx,trig1-assert = <1>;
294                 } ;
295         } ;
296 }  ;