2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
50 unsigned int num_processors
;
52 unsigned disabled_cpus __cpuinitdata
;
54 /* Processor that is doing the boot up */
55 unsigned int boot_cpu_physical_apicid
= -1U;
58 * The highest APIC ID seen during enumeration.
60 * This determines the messaging protocol we can use: if all APIC IDs
61 * are in the 0 ... 7 range, then we can use logical addressing which
62 * has some performance advantages (better broadcasting).
64 * If there's an APIC ID above 8, we use physical addressing.
66 unsigned int max_physical_apicid
;
69 * Bitmask of physically existing CPUs:
71 physid_mask_t phys_cpu_present_map
;
74 * Map cpu index to physical APIC ID
76 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
77 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
83 * Knob to control our willingness to enable the local APIC.
87 static int force_enable_local_apic
;
89 * APIC command line parameters
91 static int __init
parse_lapic(char *arg
)
93 force_enable_local_apic
= 1;
96 early_param("lapic", parse_lapic
);
97 /* Local APIC was disabled by the BIOS and enabled by the kernel */
98 static int enabled_via_apicbase
;
103 static int apic_calibrate_pmtmr __initdata
;
104 static __init
int setup_apicpmtimer(char *s
)
106 apic_calibrate_pmtmr
= 1;
110 __setup("apicpmtimer", setup_apicpmtimer
);
113 #ifdef CONFIG_X86_X2APIC
115 /* x2apic enabled before OS handover */
116 static int x2apic_preenabled
;
117 static int disable_x2apic
;
118 static __init
int setup_nox2apic(char *str
)
121 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
124 early_param("nox2apic", setup_nox2apic
);
127 unsigned long mp_lapic_addr
;
129 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
130 static int disable_apic_timer __cpuinitdata
;
131 /* Local APIC timer works in C2 */
132 int local_apic_timer_c2_ok
;
133 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
135 int first_system_vector
= 0xfe;
138 * Debug level, exported for io_apic.c
140 unsigned int apic_verbosity
;
144 /* Have we found an MP table */
145 int smp_found_config
;
147 static struct resource lapic_resource
= {
148 .name
= "Local APIC",
149 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
152 static unsigned int calibration_result
;
154 static int lapic_next_event(unsigned long delta
,
155 struct clock_event_device
*evt
);
156 static void lapic_timer_setup(enum clock_event_mode mode
,
157 struct clock_event_device
*evt
);
158 static void lapic_timer_broadcast(const struct cpumask
*mask
);
159 static void apic_pm_activate(void);
162 * The local apic timer can be used for any function which is CPU local.
164 static struct clock_event_device lapic_clockevent
= {
166 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
167 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
169 .set_mode
= lapic_timer_setup
,
170 .set_next_event
= lapic_next_event
,
171 .broadcast
= lapic_timer_broadcast
,
175 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
177 static unsigned long apic_phys
;
180 * Get the LAPIC version
182 static inline int lapic_get_version(void)
184 return GET_APIC_VERSION(apic_read(APIC_LVR
));
188 * Check, if the APIC is integrated or a separate chip
190 static inline int lapic_is_integrated(void)
195 return APIC_INTEGRATED(lapic_get_version());
200 * Check, whether this is a modern or a first generation APIC
202 static int modern_apic(void)
204 /* AMD systems use old APIC versions, so check the CPU */
205 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
206 boot_cpu_data
.x86
>= 0xf)
208 return lapic_get_version() >= 0x14;
211 void native_apic_wait_icr_idle(void)
213 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
217 u32
native_safe_apic_wait_icr_idle(void)
224 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
228 } while (timeout
++ < 1000);
233 void native_apic_icr_write(u32 low
, u32 id
)
235 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
236 apic_write(APIC_ICR
, low
);
239 u64
native_apic_icr_read(void)
243 icr2
= apic_read(APIC_ICR2
);
244 icr1
= apic_read(APIC_ICR
);
246 return icr1
| ((u64
)icr2
<< 32);
250 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
252 void __cpuinit
enable_NMI_through_LVT0(void)
256 /* unmask and set to NMI */
259 /* Level triggered for 82489DX (32bit mode) */
260 if (!lapic_is_integrated())
261 v
|= APIC_LVT_LEVEL_TRIGGER
;
263 apic_write(APIC_LVT0
, v
);
268 * get_physical_broadcast - Get number of physical broadcast IDs
270 int get_physical_broadcast(void)
272 return modern_apic() ? 0xff : 0xf;
277 * lapic_get_maxlvt - get the maximum number of local vector table entries
279 int lapic_get_maxlvt(void)
283 v
= apic_read(APIC_LVR
);
285 * - we always have APIC integrated on 64bit mode
286 * - 82489DXs do not report # of LVT entries
288 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
296 #define APIC_DIVISOR 16
299 * This function sets up the local APIC timer, with a timeout of
300 * 'clocks' APIC bus clock. During calibration we actually call
301 * this function twice on the boot CPU, once with a bogus timeout
302 * value, second time for real. The other (noncalibrating) CPUs
303 * call this function only once, with the real, calibrated value.
305 * We do reads before writes even if unnecessary, to get around the
306 * P5 APIC double write bug.
308 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
310 unsigned int lvtt_value
, tmp_value
;
312 lvtt_value
= LOCAL_TIMER_VECTOR
;
314 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
315 if (!lapic_is_integrated())
316 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
319 lvtt_value
|= APIC_LVT_MASKED
;
321 apic_write(APIC_LVTT
, lvtt_value
);
326 tmp_value
= apic_read(APIC_TDCR
);
327 apic_write(APIC_TDCR
,
328 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
332 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
336 * Setup extended LVT, AMD specific (K8, family 10h)
338 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
339 * MCE interrupts are supported. Thus MCE offset must be set to 0.
341 * If mask=1, the LVT entry does not generate interrupts while mask=0
342 * enables the vector. See also the BKDGs.
345 #define APIC_EILVT_LVTOFF_MCE 0
346 #define APIC_EILVT_LVTOFF_IBS 1
348 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
350 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
351 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
356 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
358 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
359 return APIC_EILVT_LVTOFF_MCE
;
362 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
364 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
365 return APIC_EILVT_LVTOFF_IBS
;
367 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
370 * Program the next event, relative to now
372 static int lapic_next_event(unsigned long delta
,
373 struct clock_event_device
*evt
)
375 apic_write(APIC_TMICT
, delta
);
380 * Setup the lapic timer in periodic or oneshot mode
382 static void lapic_timer_setup(enum clock_event_mode mode
,
383 struct clock_event_device
*evt
)
388 /* Lapic used as dummy for broadcast ? */
389 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
392 local_irq_save(flags
);
395 case CLOCK_EVT_MODE_PERIODIC
:
396 case CLOCK_EVT_MODE_ONESHOT
:
397 __setup_APIC_LVTT(calibration_result
,
398 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
400 case CLOCK_EVT_MODE_UNUSED
:
401 case CLOCK_EVT_MODE_SHUTDOWN
:
402 v
= apic_read(APIC_LVTT
);
403 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
404 apic_write(APIC_LVTT
, v
);
405 apic_write(APIC_TMICT
, 0xffffffff);
407 case CLOCK_EVT_MODE_RESUME
:
408 /* Nothing to do here */
412 local_irq_restore(flags
);
416 * Local APIC timer broadcast function
418 static void lapic_timer_broadcast(const struct cpumask
*mask
)
421 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
426 * Setup the local APIC timer for this CPU. Copy the initilized values
427 * of the boot CPU and register the clock event in the framework.
429 static void __cpuinit
setup_APIC_timer(void)
431 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
433 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
434 levt
->cpumask
= cpumask_of(smp_processor_id());
436 clockevents_register_device(levt
);
440 * In this functions we calibrate APIC bus clocks to the external timer.
442 * We want to do the calibration only once since we want to have local timer
443 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
446 * This was previously done by reading the PIT/HPET and waiting for a wrap
447 * around to find out, that a tick has elapsed. I have a box, where the PIT
448 * readout is broken, so it never gets out of the wait loop again. This was
449 * also reported by others.
451 * Monitoring the jiffies value is inaccurate and the clockevents
452 * infrastructure allows us to do a simple substitution of the interrupt
455 * The calibration routine also uses the pm_timer when possible, as the PIT
456 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
457 * back to normal later in the boot process).
460 #define LAPIC_CAL_LOOPS (HZ/10)
462 static __initdata
int lapic_cal_loops
= -1;
463 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
464 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
465 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
466 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
469 * Temporary interrupt handler.
471 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
473 unsigned long long tsc
= 0;
474 long tapic
= apic_read(APIC_TMCCT
);
475 unsigned long pm
= acpi_pm_read_early();
480 switch (lapic_cal_loops
++) {
482 lapic_cal_t1
= tapic
;
483 lapic_cal_tsc1
= tsc
;
485 lapic_cal_j1
= jiffies
;
488 case LAPIC_CAL_LOOPS
:
489 lapic_cal_t2
= tapic
;
490 lapic_cal_tsc2
= tsc
;
491 if (pm
< lapic_cal_pm1
)
492 pm
+= ACPI_PM_OVRRUN
;
494 lapic_cal_j2
= jiffies
;
500 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
502 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
503 const long pm_thresh
= pm_100ms
/ 100;
507 #ifndef CONFIG_X86_PM_TIMER
511 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
513 /* Check, if the PM timer is available */
517 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
519 if (deltapm
> (pm_100ms
- pm_thresh
) &&
520 deltapm
< (pm_100ms
+ pm_thresh
)) {
521 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
525 res
= (((u64
)deltapm
) * mult
) >> 22;
526 do_div(res
, 1000000);
527 pr_warning("APIC calibration not consistent "
528 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
530 /* Correct the lapic counter value */
531 res
= (((u64
)(*delta
)) * pm_100ms
);
532 do_div(res
, deltapm
);
533 pr_info("APIC delta adjusted to PM-Timer: "
534 "%lu (%ld)\n", (unsigned long)res
, *delta
);
537 /* Correct the tsc counter value */
539 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
540 do_div(res
, deltapm
);
541 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
542 "PM-Timer: %lu (%ld) \n",
543 (unsigned long)res
, *deltatsc
);
544 *deltatsc
= (long)res
;
550 static int __init
calibrate_APIC_clock(void)
552 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
553 void (*real_handler
)(struct clock_event_device
*dev
);
554 unsigned long deltaj
;
555 long delta
, deltatsc
;
556 int pm_referenced
= 0;
560 /* Replace the global interrupt handler */
561 real_handler
= global_clock_event
->event_handler
;
562 global_clock_event
->event_handler
= lapic_cal_handler
;
565 * Setup the APIC counter to maximum. There is no way the lapic
566 * can underflow in the 100ms detection time frame
568 __setup_APIC_LVTT(0xffffffff, 0, 0);
570 /* Let the interrupts run */
573 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
578 /* Restore the real event handler */
579 global_clock_event
->event_handler
= real_handler
;
581 /* Build delta t1-t2 as apic timer counts down */
582 delta
= lapic_cal_t1
- lapic_cal_t2
;
583 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
585 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
587 /* we trust the PM based calibration if possible */
588 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
591 /* Calculate the scaled math multiplication factor */
592 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
593 lapic_clockevent
.shift
);
594 lapic_clockevent
.max_delta_ns
=
595 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
596 lapic_clockevent
.min_delta_ns
=
597 clockevent_delta2ns(0xF, &lapic_clockevent
);
599 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
601 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
602 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
603 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
607 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
609 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
610 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
613 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
615 calibration_result
/ (1000000 / HZ
),
616 calibration_result
% (1000000 / HZ
));
619 * Do a sanity check on the APIC calibration result
621 if (calibration_result
< (1000000 / HZ
)) {
623 pr_warning("APIC frequency too slow, disabling apic timer\n");
627 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
630 * PM timer calibration failed or not turned on
631 * so lets try APIC timer based calibration
633 if (!pm_referenced
) {
634 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
637 * Setup the apic timer manually
639 levt
->event_handler
= lapic_cal_handler
;
640 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
641 lapic_cal_loops
= -1;
643 /* Let the interrupts run */
646 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
649 /* Stop the lapic timer */
650 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
653 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
654 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
656 /* Check, if the jiffies result is consistent */
657 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
658 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
660 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
664 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
665 pr_warning("APIC timer disabled due to verification failure\n");
673 * Setup the boot APIC
675 * Calibrate and verify the result.
677 void __init
setup_boot_APIC_clock(void)
680 * The local apic timer can be disabled via the kernel
681 * commandline or from the CPU detection code. Register the lapic
682 * timer as a dummy clock event source on SMP systems, so the
683 * broadcast mechanism is used. On UP systems simply ignore it.
685 if (disable_apic_timer
) {
686 pr_info("Disabling APIC timer\n");
687 /* No broadcast on UP ! */
688 if (num_possible_cpus() > 1) {
689 lapic_clockevent
.mult
= 1;
695 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
696 "calibrating APIC timer ...\n");
698 if (calibrate_APIC_clock()) {
699 /* No broadcast on UP ! */
700 if (num_possible_cpus() > 1)
706 * If nmi_watchdog is set to IO_APIC, we need the
707 * PIT/HPET going. Otherwise register lapic as a dummy
710 if (nmi_watchdog
!= NMI_IO_APIC
)
711 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
713 pr_warning("APIC timer registered as dummy,"
714 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
716 /* Setup the lapic or request the broadcast */
720 void __cpuinit
setup_secondary_APIC_clock(void)
726 * The guts of the apic timer interrupt
728 static void local_apic_timer_interrupt(void)
730 int cpu
= smp_processor_id();
731 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
734 * Normally we should not be here till LAPIC has been initialized but
735 * in some cases like kdump, its possible that there is a pending LAPIC
736 * timer interrupt from previous kernel's context and is delivered in
737 * new kernel the moment interrupts are enabled.
739 * Interrupts are enabled early and LAPIC is setup much later, hence
740 * its possible that when we get here evt->event_handler is NULL.
741 * Check for event_handler being NULL and discard the interrupt as
744 if (!evt
->event_handler
) {
745 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
747 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
752 * the NMI deadlock-detector uses this.
754 inc_irq_stat(apic_timer_irqs
);
756 evt
->event_handler(evt
);
760 * Local APIC timer interrupt. This is the most natural way for doing
761 * local interrupts, but local timer interrupts can be emulated by
762 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
764 * [ if a single-CPU system runs an SMP kernel then we call the local
765 * interrupt as well. Thus we cannot inline the local irq ... ]
767 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
769 struct pt_regs
*old_regs
= set_irq_regs(regs
);
772 * NOTE! We'd better ACK the irq immediately,
773 * because timer handling can be slow.
777 * update_process_times() expects us to have done irq_enter().
778 * Besides, if we don't timer interrupts ignore the global
779 * interrupt lock, which is the WrongThing (tm) to do.
783 local_apic_timer_interrupt();
786 set_irq_regs(old_regs
);
789 int setup_profiling_timer(unsigned int multiplier
)
795 * Local APIC start and shutdown
799 * clear_local_APIC - shutdown the local APIC
801 * This is called, when a CPU is disabled and before rebooting, so the state of
802 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
803 * leftovers during boot.
805 void clear_local_APIC(void)
810 /* APIC hasn't been mapped yet */
814 maxlvt
= lapic_get_maxlvt();
816 * Masking an LVT entry can trigger a local APIC error
817 * if the vector is zero. Mask LVTERR first to prevent this.
820 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
821 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
824 * Careful: we have to set masks only first to deassert
825 * any level-triggered sources.
827 v
= apic_read(APIC_LVTT
);
828 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
829 v
= apic_read(APIC_LVT0
);
830 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
831 v
= apic_read(APIC_LVT1
);
832 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
834 v
= apic_read(APIC_LVTPC
);
835 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
838 /* lets not touch this if we didn't frob it */
839 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
841 v
= apic_read(APIC_LVTTHMR
);
842 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
846 * Clean APIC state for other OSs:
848 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
849 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
850 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
852 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
854 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
856 /* Integrated APIC (!82489DX) ? */
857 if (lapic_is_integrated()) {
859 /* Clear ESR due to Pentium errata 3AP and 11AP */
860 apic_write(APIC_ESR
, 0);
866 * disable_local_APIC - clear and disable the local APIC
868 void disable_local_APIC(void)
872 /* APIC hasn't been mapped yet */
879 * Disable APIC (implies clearing of registers
882 value
= apic_read(APIC_SPIV
);
883 value
&= ~APIC_SPIV_APIC_ENABLED
;
884 apic_write(APIC_SPIV
, value
);
888 * When LAPIC was disabled by the BIOS and enabled by the kernel,
889 * restore the disabled state.
891 if (enabled_via_apicbase
) {
894 rdmsr(MSR_IA32_APICBASE
, l
, h
);
895 l
&= ~MSR_IA32_APICBASE_ENABLE
;
896 wrmsr(MSR_IA32_APICBASE
, l
, h
);
902 * If Linux enabled the LAPIC against the BIOS default disable it down before
903 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
904 * not power-off. Additionally clear all LVT entries before disable_local_APIC
905 * for the case where Linux didn't enable the LAPIC.
907 void lapic_shutdown(void)
914 local_irq_save(flags
);
917 if (!enabled_via_apicbase
)
921 disable_local_APIC();
924 local_irq_restore(flags
);
928 * This is to verify that we're looking at a real local APIC.
929 * Check these against your board if the CPUs aren't getting
930 * started for no apparent reason.
932 int __init
verify_local_APIC(void)
934 unsigned int reg0
, reg1
;
937 * The version register is read-only in a real APIC.
939 reg0
= apic_read(APIC_LVR
);
940 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
941 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
942 reg1
= apic_read(APIC_LVR
);
943 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
946 * The two version reads above should print the same
947 * numbers. If the second one is different, then we
948 * poke at a non-APIC.
954 * Check if the version looks reasonably.
956 reg1
= GET_APIC_VERSION(reg0
);
957 if (reg1
== 0x00 || reg1
== 0xff)
959 reg1
= lapic_get_maxlvt();
960 if (reg1
< 0x02 || reg1
== 0xff)
964 * The ID register is read/write in a real APIC.
966 reg0
= apic_read(APIC_ID
);
967 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
968 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
969 reg1
= apic_read(APIC_ID
);
970 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
971 apic_write(APIC_ID
, reg0
);
972 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
976 * The next two are just to see if we have sane values.
977 * They're only really relevant if we're in Virtual Wire
978 * compatibility mode, but most boxes are anymore.
980 reg0
= apic_read(APIC_LVT0
);
981 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
982 reg1
= apic_read(APIC_LVT1
);
983 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
989 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
991 void __init
sync_Arb_IDs(void)
994 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
997 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1003 apic_wait_icr_idle();
1005 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1006 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1007 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1011 * An initial setup of the virtual wire mode.
1013 void __init
init_bsp_APIC(void)
1018 * Don't do the setup now if we have a SMP BIOS as the
1019 * through-I/O-APIC virtual wire mode might be active.
1021 if (smp_found_config
|| !cpu_has_apic
)
1025 * Do not trust the local APIC being empty at bootup.
1032 value
= apic_read(APIC_SPIV
);
1033 value
&= ~APIC_VECTOR_MASK
;
1034 value
|= APIC_SPIV_APIC_ENABLED
;
1036 #ifdef CONFIG_X86_32
1037 /* This bit is reserved on P4/Xeon and should be cleared */
1038 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1039 (boot_cpu_data
.x86
== 15))
1040 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1043 value
|= APIC_SPIV_FOCUS_DISABLED
;
1044 value
|= SPURIOUS_APIC_VECTOR
;
1045 apic_write(APIC_SPIV
, value
);
1048 * Set up the virtual wire mode.
1050 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1051 value
= APIC_DM_NMI
;
1052 if (!lapic_is_integrated()) /* 82489DX */
1053 value
|= APIC_LVT_LEVEL_TRIGGER
;
1054 apic_write(APIC_LVT1
, value
);
1057 static void __cpuinit
lapic_setup_esr(void)
1059 unsigned int oldvalue
, value
, maxlvt
;
1061 if (!lapic_is_integrated()) {
1062 pr_info("No ESR for 82489DX.\n");
1066 if (apic
->disable_esr
) {
1068 * Something untraceable is creating bad interrupts on
1069 * secondary quads ... for the moment, just leave the
1070 * ESR disabled - we can't do anything useful with the
1071 * errors anyway - mbligh
1073 pr_info("Leaving ESR disabled.\n");
1077 maxlvt
= lapic_get_maxlvt();
1078 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1079 apic_write(APIC_ESR
, 0);
1080 oldvalue
= apic_read(APIC_ESR
);
1082 /* enables sending errors */
1083 value
= ERROR_APIC_VECTOR
;
1084 apic_write(APIC_LVTERR
, value
);
1087 * spec says clear errors after enabling vector.
1090 apic_write(APIC_ESR
, 0);
1091 value
= apic_read(APIC_ESR
);
1092 if (value
!= oldvalue
)
1093 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1094 "vector: 0x%08x after: 0x%08x\n",
1100 * setup_local_APIC - setup the local APIC
1102 void __cpuinit
setup_local_APIC(void)
1108 arch_disable_smp_support();
1112 #ifdef CONFIG_X86_32
1113 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1114 if (lapic_is_integrated() && apic
->disable_esr
) {
1115 apic_write(APIC_ESR
, 0);
1116 apic_write(APIC_ESR
, 0);
1117 apic_write(APIC_ESR
, 0);
1118 apic_write(APIC_ESR
, 0);
1125 * Double-check whether this APIC is really registered.
1126 * This is meaningless in clustered apic mode, so we skip it.
1128 if (!apic
->apic_id_registered())
1132 * Intel recommends to set DFR, LDR and TPR before enabling
1133 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1134 * document number 292116). So here it goes...
1136 apic
->init_apic_ldr();
1139 * Set Task Priority to 'accept all'. We never change this
1142 value
= apic_read(APIC_TASKPRI
);
1143 value
&= ~APIC_TPRI_MASK
;
1144 apic_write(APIC_TASKPRI
, value
);
1147 * After a crash, we no longer service the interrupts and a pending
1148 * interrupt from previous kernel might still have ISR bit set.
1150 * Most probably by now CPU has serviced that pending interrupt and
1151 * it might not have done the ack_APIC_irq() because it thought,
1152 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1153 * does not clear the ISR bit and cpu thinks it has already serivced
1154 * the interrupt. Hence a vector might get locked. It was noticed
1155 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1157 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1158 value
= apic_read(APIC_ISR
+ i
*0x10);
1159 for (j
= 31; j
>= 0; j
--) {
1166 * Now that we are all set up, enable the APIC
1168 value
= apic_read(APIC_SPIV
);
1169 value
&= ~APIC_VECTOR_MASK
;
1173 value
|= APIC_SPIV_APIC_ENABLED
;
1175 #ifdef CONFIG_X86_32
1177 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1178 * certain networking cards. If high frequency interrupts are
1179 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1180 * entry is masked/unmasked at a high rate as well then sooner or
1181 * later IOAPIC line gets 'stuck', no more interrupts are received
1182 * from the device. If focus CPU is disabled then the hang goes
1185 * [ This bug can be reproduced easily with a level-triggered
1186 * PCI Ne2000 networking cards and PII/PIII processors, dual
1190 * Actually disabling the focus CPU check just makes the hang less
1191 * frequent as it makes the interrupt distributon model be more
1192 * like LRU than MRU (the short-term load is more even across CPUs).
1193 * See also the comment in end_level_ioapic_irq(). --macro
1197 * - enable focus processor (bit==0)
1198 * - 64bit mode always use processor focus
1199 * so no need to set it
1201 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1205 * Set spurious IRQ vector
1207 value
|= SPURIOUS_APIC_VECTOR
;
1208 apic_write(APIC_SPIV
, value
);
1211 * Set up LVT0, LVT1:
1213 * set up through-local-APIC on the BP's LINT0. This is not
1214 * strictly necessary in pure symmetric-IO mode, but sometimes
1215 * we delegate interrupts to the 8259A.
1218 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1220 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1221 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1222 value
= APIC_DM_EXTINT
;
1223 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1224 smp_processor_id());
1226 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1227 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1228 smp_processor_id());
1230 apic_write(APIC_LVT0
, value
);
1233 * only the BP should see the LINT1 NMI signal, obviously.
1235 if (!smp_processor_id())
1236 value
= APIC_DM_NMI
;
1238 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1239 if (!lapic_is_integrated()) /* 82489DX */
1240 value
|= APIC_LVT_LEVEL_TRIGGER
;
1241 apic_write(APIC_LVT1
, value
);
1246 void __cpuinit
end_local_APIC_setup(void)
1250 #ifdef CONFIG_X86_32
1253 /* Disable the local apic timer */
1254 value
= apic_read(APIC_LVTT
);
1255 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1256 apic_write(APIC_LVTT
, value
);
1260 setup_apic_nmi_watchdog(NULL
);
1264 #ifdef CONFIG_X86_X2APIC
1265 void check_x2apic(void)
1267 if (x2apic_enabled()) {
1268 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1269 x2apic_preenabled
= x2apic
= 1;
1273 void enable_x2apic(void)
1280 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1281 if (!(msr
& X2APIC_ENABLE
)) {
1282 pr_info("Enabling x2apic\n");
1283 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1287 void __init
enable_IR_x2apic(void)
1289 #ifdef CONFIG_INTR_REMAP
1291 unsigned long flags
;
1293 if (!cpu_has_x2apic
)
1296 if (!x2apic_preenabled
&& disable_x2apic
) {
1297 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1298 "because of nox2apic\n");
1302 if (x2apic_preenabled
&& disable_x2apic
)
1303 panic("Bios already enabled x2apic, can't enforce nox2apic");
1305 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1306 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1307 "because of skipping io-apic setup\n");
1311 ret
= dmar_table_init();
1313 pr_info("dmar_table_init() failed with %d:\n", ret
);
1315 if (x2apic_preenabled
)
1316 panic("x2apic enabled by bios. But IR enabling failed");
1318 pr_info("Not enabling x2apic,Intr-remapping\n");
1322 local_irq_save(flags
);
1325 ret
= save_mask_IO_APIC_setup();
1327 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1331 ret
= enable_intr_remapping(1);
1333 if (ret
&& x2apic_preenabled
) {
1334 local_irq_restore(flags
);
1335 panic("x2apic enabled by bios. But IR enabling failed");
1349 * IR enabling failed
1351 restore_IO_APIC_setup();
1353 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1357 local_irq_restore(flags
);
1360 if (!x2apic_preenabled
)
1361 pr_info("Enabled x2apic and interrupt-remapping\n");
1363 pr_info("Enabled Interrupt-remapping\n");
1365 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1367 if (!cpu_has_x2apic
)
1370 if (x2apic_preenabled
)
1371 panic("x2apic enabled prior OS handover,"
1372 " enable CONFIG_INTR_REMAP");
1374 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1380 #endif /* CONFIG_X86_X2APIC */
1382 #ifdef CONFIG_X86_64
1384 * Detect and enable local APICs on non-SMP boards.
1385 * Original code written by Keir Fraser.
1386 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1387 * not correctly set up (usually the APIC timer won't work etc.)
1389 static int __init
detect_init_APIC(void)
1391 if (!cpu_has_apic
) {
1392 pr_info("No local APIC present\n");
1396 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1397 boot_cpu_physical_apicid
= 0;
1402 * Detect and initialize APIC
1404 static int __init
detect_init_APIC(void)
1408 /* Disabled by kernel option? */
1412 switch (boot_cpu_data
.x86_vendor
) {
1413 case X86_VENDOR_AMD
:
1414 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1415 (boot_cpu_data
.x86
>= 15))
1418 case X86_VENDOR_INTEL
:
1419 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1420 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1427 if (!cpu_has_apic
) {
1429 * Over-ride BIOS and try to enable the local APIC only if
1430 * "lapic" specified.
1432 if (!force_enable_local_apic
) {
1433 pr_info("Local APIC disabled by BIOS -- "
1434 "you can enable it with \"lapic\"\n");
1438 * Some BIOSes disable the local APIC in the APIC_BASE
1439 * MSR. This can only be done in software for Intel P6 or later
1440 * and AMD K7 (Model > 1) or later.
1442 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1443 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1444 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1445 l
&= ~MSR_IA32_APICBASE_BASE
;
1446 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1447 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1448 enabled_via_apicbase
= 1;
1452 * The APIC feature bit should now be enabled
1455 features
= cpuid_edx(1);
1456 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1457 pr_warning("Could not enable APIC!\n");
1460 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1461 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1463 /* The BIOS may have set up the APIC at some other address */
1464 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1465 if (l
& MSR_IA32_APICBASE_ENABLE
)
1466 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1468 pr_info("Found and enabled local APIC!\n");
1475 pr_info("No local APIC present or hardware disabled\n");
1480 #ifdef CONFIG_X86_64
1481 void __init
early_init_lapic_mapping(void)
1483 unsigned long phys_addr
;
1486 * If no local APIC can be found then go out
1487 * : it means there is no mpatable and MADT
1489 if (!smp_found_config
)
1492 phys_addr
= mp_lapic_addr
;
1494 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1495 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1496 APIC_BASE
, phys_addr
);
1499 * Fetch the APIC ID of the BSP in case we have a
1500 * default configuration (or the MP table is broken).
1502 boot_cpu_physical_apicid
= read_apic_id();
1507 * init_apic_mappings - initialize APIC mappings
1509 void __init
init_apic_mappings(void)
1511 #ifdef CONFIG_X86_X2APIC
1513 boot_cpu_physical_apicid
= read_apic_id();
1519 * If no local APIC can be found then set up a fake all
1520 * zeroes page to simulate the local APIC and another
1521 * one for the IO-APIC.
1523 if (!smp_found_config
&& detect_init_APIC()) {
1524 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1525 apic_phys
= __pa(apic_phys
);
1527 apic_phys
= mp_lapic_addr
;
1529 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1530 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1531 APIC_BASE
, apic_phys
);
1534 * Fetch the APIC ID of the BSP in case we have a
1535 * default configuration (or the MP table is broken).
1537 if (boot_cpu_physical_apicid
== -1U)
1538 boot_cpu_physical_apicid
= read_apic_id();
1542 * This initializes the IO-APIC and APIC hardware if this is
1545 int apic_version
[MAX_APICS
];
1547 int __init
APIC_init_uniprocessor(void)
1550 pr_info("Apic disabled\n");
1553 #ifdef CONFIG_X86_64
1554 if (!cpu_has_apic
) {
1556 pr_info("Apic disabled by BIOS\n");
1560 if (!smp_found_config
&& !cpu_has_apic
)
1564 * Complain if the BIOS pretends there is one.
1566 if (!cpu_has_apic
&&
1567 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1568 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1569 boot_cpu_physical_apicid
);
1570 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1576 #ifdef CONFIG_X86_64
1577 default_setup_apic_routing();
1580 verify_local_APIC();
1583 #ifdef CONFIG_X86_64
1584 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1587 * Hack: In case of kdump, after a crash, kernel might be booting
1588 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1589 * might be zero if read from MP tables. Get it from LAPIC.
1591 # ifdef CONFIG_CRASH_DUMP
1592 boot_cpu_physical_apicid
= read_apic_id();
1595 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1598 #ifdef CONFIG_X86_IO_APIC
1600 * Now enable IO-APICs, actually call clear_IO_APIC
1601 * We need clear_IO_APIC before enabling error vector
1603 if (!skip_ioapic_setup
&& nr_ioapics
)
1607 end_local_APIC_setup();
1609 #ifdef CONFIG_X86_IO_APIC
1610 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1614 localise_nmi_watchdog();
1617 localise_nmi_watchdog();
1621 #ifdef CONFIG_X86_64
1622 check_nmi_watchdog();
1629 * Local APIC interrupts
1633 * This interrupt should _never_ happen with our APIC/SMP architecture
1635 void smp_spurious_interrupt(struct pt_regs
*regs
)
1642 * Check if this really is a spurious interrupt and ACK it
1643 * if it is a vectored one. Just in case...
1644 * Spurious interrupts should not be ACKed.
1646 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1647 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1650 inc_irq_stat(irq_spurious_count
);
1652 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1653 pr_info("spurious APIC interrupt on CPU#%d, "
1654 "should never happen.\n", smp_processor_id());
1659 * This interrupt should never happen with our APIC/SMP architecture
1661 void smp_error_interrupt(struct pt_regs
*regs
)
1667 /* First tickle the hardware, only then report what went on. -- REW */
1668 v
= apic_read(APIC_ESR
);
1669 apic_write(APIC_ESR
, 0);
1670 v1
= apic_read(APIC_ESR
);
1672 atomic_inc(&irq_err_count
);
1675 * Here is what the APIC error bits mean:
1677 * 1: Receive CS error
1678 * 2: Send accept error
1679 * 3: Receive accept error
1681 * 5: Send illegal vector
1682 * 6: Received illegal vector
1683 * 7: Illegal register address
1685 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1686 smp_processor_id(), v
, v1
);
1691 * connect_bsp_APIC - attach the APIC to the interrupt system
1693 void __init
connect_bsp_APIC(void)
1695 #ifdef CONFIG_X86_32
1698 * Do not trust the local APIC being empty at bootup.
1702 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1703 * local APIC to INT and NMI lines.
1705 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1706 "enabling APIC mode.\n");
1711 if (apic
->enable_apic_mode
)
1712 apic
->enable_apic_mode();
1716 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1717 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1719 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1722 void disconnect_bsp_APIC(int virt_wire_setup
)
1726 #ifdef CONFIG_X86_32
1729 * Put the board back into PIC mode (has an effect only on
1730 * certain older boards). Note that APIC interrupts, including
1731 * IPIs, won't work beyond this point! The only exception are
1734 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1735 "entering PIC mode.\n");
1742 /* Go back to Virtual Wire compatibility mode */
1744 /* For the spurious interrupt use vector F, and enable it */
1745 value
= apic_read(APIC_SPIV
);
1746 value
&= ~APIC_VECTOR_MASK
;
1747 value
|= APIC_SPIV_APIC_ENABLED
;
1749 apic_write(APIC_SPIV
, value
);
1751 if (!virt_wire_setup
) {
1753 * For LVT0 make it edge triggered, active high,
1754 * external and enabled
1756 value
= apic_read(APIC_LVT0
);
1757 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1758 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1759 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1760 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1761 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1762 apic_write(APIC_LVT0
, value
);
1765 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1769 * For LVT1 make it edge triggered, active high,
1772 value
= apic_read(APIC_LVT1
);
1773 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1774 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1775 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1776 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1777 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1778 apic_write(APIC_LVT1
, value
);
1781 void __cpuinit
generic_processor_info(int apicid
, int version
)
1788 if (version
== 0x0) {
1789 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1790 "fixing up to 0x10. (tell your hw vendor)\n",
1794 apic_version
[apicid
] = version
;
1796 if (num_processors
>= nr_cpu_ids
) {
1797 int max
= nr_cpu_ids
;
1798 int thiscpu
= max
+ disabled_cpus
;
1801 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1802 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1809 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1811 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1813 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1814 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1816 physid_set(apicid
, phys_cpu_present_map
);
1817 if (apicid
== boot_cpu_physical_apicid
) {
1819 * x86_bios_cpu_apicid is required to have processors listed
1820 * in same order as logical cpu numbers. Hence the first
1821 * entry is BSP, and so on.
1825 if (apicid
> max_physical_apicid
)
1826 max_physical_apicid
= apicid
;
1828 #ifdef CONFIG_X86_32
1830 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1831 * but we need to work other dependencies like SMP_SUSPEND etc
1832 * before this can be done without some confusion.
1833 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1834 * - Ashok Raj <ashok.raj@intel.com>
1836 if (max_physical_apicid
>= 8) {
1837 switch (boot_cpu_data
.x86_vendor
) {
1838 case X86_VENDOR_INTEL
:
1839 if (!APIC_XAPIC(version
)) {
1843 /* If P4 and above fall through */
1844 case X86_VENDOR_AMD
:
1850 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1851 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1852 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1855 set_cpu_possible(cpu
, true);
1856 set_cpu_present(cpu
, true);
1859 int hard_smp_processor_id(void)
1861 return read_apic_id();
1864 void default_init_apic_ldr(void)
1868 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1869 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1870 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1871 apic_write(APIC_LDR
, val
);
1874 #ifdef CONFIG_X86_32
1875 int default_apicid_to_node(int logical_apicid
)
1878 return apicid_2_node
[hard_smp_processor_id()];
1892 * 'active' is true if the local APIC was enabled by us and
1893 * not the BIOS; this signifies that we are also responsible
1894 * for disabling it before entering apm/acpi suspend
1897 /* r/w apic fields */
1898 unsigned int apic_id
;
1899 unsigned int apic_taskpri
;
1900 unsigned int apic_ldr
;
1901 unsigned int apic_dfr
;
1902 unsigned int apic_spiv
;
1903 unsigned int apic_lvtt
;
1904 unsigned int apic_lvtpc
;
1905 unsigned int apic_lvt0
;
1906 unsigned int apic_lvt1
;
1907 unsigned int apic_lvterr
;
1908 unsigned int apic_tmict
;
1909 unsigned int apic_tdcr
;
1910 unsigned int apic_thmr
;
1913 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1915 unsigned long flags
;
1918 if (!apic_pm_state
.active
)
1921 maxlvt
= lapic_get_maxlvt();
1923 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1924 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1925 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1926 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1927 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1928 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1930 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1931 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1932 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1933 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1934 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1935 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1936 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1938 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1941 local_irq_save(flags
);
1942 disable_local_APIC();
1943 local_irq_restore(flags
);
1947 static int lapic_resume(struct sys_device
*dev
)
1950 unsigned long flags
;
1953 if (!apic_pm_state
.active
)
1956 maxlvt
= lapic_get_maxlvt();
1958 local_irq_save(flags
);
1960 #ifdef CONFIG_X86_X2APIC
1967 * Make sure the APICBASE points to the right address
1969 * FIXME! This will be wrong if we ever support suspend on
1970 * SMP! We'll need to do this as part of the CPU restore!
1972 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1973 l
&= ~MSR_IA32_APICBASE_BASE
;
1974 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1975 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1978 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1979 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1980 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1981 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1982 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1983 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1984 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1985 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1986 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1988 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1991 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1992 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1993 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1994 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1995 apic_write(APIC_ESR
, 0);
1996 apic_read(APIC_ESR
);
1997 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1998 apic_write(APIC_ESR
, 0);
1999 apic_read(APIC_ESR
);
2001 local_irq_restore(flags
);
2007 * This device has no shutdown method - fully functioning local APICs
2008 * are needed on every CPU up until machine_halt/restart/poweroff.
2011 static struct sysdev_class lapic_sysclass
= {
2013 .resume
= lapic_resume
,
2014 .suspend
= lapic_suspend
,
2017 static struct sys_device device_lapic
= {
2019 .cls
= &lapic_sysclass
,
2022 static void __cpuinit
apic_pm_activate(void)
2024 apic_pm_state
.active
= 1;
2027 static int __init
init_lapic_sysfs(void)
2033 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2035 error
= sysdev_class_register(&lapic_sysclass
);
2037 error
= sysdev_register(&device_lapic
);
2040 device_initcall(init_lapic_sysfs
);
2042 #else /* CONFIG_PM */
2044 static void apic_pm_activate(void) { }
2046 #endif /* CONFIG_PM */
2048 #ifdef CONFIG_X86_64
2050 * apic_is_clustered_box() -- Check if we can expect good TSC
2052 * Thus far, the major user of this is IBM's Summit2 series:
2054 * Clustered boxes may have unsynced TSC problems if they are
2055 * multi-chassis. Use available data to take a good guess.
2056 * If in doubt, go HPET.
2058 __cpuinit
int apic_is_clustered_box(void)
2060 int i
, clusters
, zeros
;
2062 u16
*bios_cpu_apicid
;
2063 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2066 * there is not this kind of box with AMD CPU yet.
2067 * Some AMD box with quadcore cpu and 8 sockets apicid
2068 * will be [4, 0x23] or [8, 0x27] could be thought to
2069 * vsmp box still need checking...
2071 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2074 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2075 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2077 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2078 /* are we being called early in kernel startup? */
2079 if (bios_cpu_apicid
) {
2080 id
= bios_cpu_apicid
[i
];
2081 } else if (i
< nr_cpu_ids
) {
2083 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2089 if (id
!= BAD_APICID
)
2090 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2093 /* Problem: Partially populated chassis may not have CPUs in some of
2094 * the APIC clusters they have been allocated. Only present CPUs have
2095 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2096 * Since clusters are allocated sequentially, count zeros only if
2097 * they are bounded by ones.
2101 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2102 if (test_bit(i
, clustermap
)) {
2103 clusters
+= 1 + zeros
;
2109 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2110 * not guaranteed to be synced between boards
2112 if (is_vsmp_box() && clusters
> 1)
2116 * If clusters > 2, then should be multi-chassis.
2117 * May have to revisit this when multi-core + hyperthreaded CPUs come
2118 * out, but AFAIK this will work even for them.
2120 return (clusters
> 2);
2125 * APIC command line parameters
2127 static int __init
setup_disableapic(char *arg
)
2130 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2133 early_param("disableapic", setup_disableapic
);
2135 /* same as disableapic, for compatibility */
2136 static int __init
setup_nolapic(char *arg
)
2138 return setup_disableapic(arg
);
2140 early_param("nolapic", setup_nolapic
);
2142 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2144 local_apic_timer_c2_ok
= 1;
2147 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2149 static int __init
parse_disable_apic_timer(char *arg
)
2151 disable_apic_timer
= 1;
2154 early_param("noapictimer", parse_disable_apic_timer
);
2156 static int __init
parse_nolapic_timer(char *arg
)
2158 disable_apic_timer
= 1;
2161 early_param("nolapic_timer", parse_nolapic_timer
);
2163 static int __init
apic_set_verbosity(char *arg
)
2166 #ifdef CONFIG_X86_64
2167 skip_ioapic_setup
= 0;
2173 if (strcmp("debug", arg
) == 0)
2174 apic_verbosity
= APIC_DEBUG
;
2175 else if (strcmp("verbose", arg
) == 0)
2176 apic_verbosity
= APIC_VERBOSE
;
2178 pr_warning("APIC Verbosity level %s not recognised"
2179 " use apic=verbose or apic=debug\n", arg
);
2185 early_param("apic", apic_set_verbosity
);
2187 static int __init
lapic_insert_resource(void)
2192 /* Put local APIC into the resource map. */
2193 lapic_resource
.start
= apic_phys
;
2194 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2195 insert_resource(&iomem_resource
, &lapic_resource
);
2201 * need call insert after e820_reserve_resources()
2202 * that is using request_resource
2204 late_initcall(lapic_insert_resource
);