2 * Copyright (c) 1996-2004 Russell King.
4 * Please note that this platform does not support 32-bit IDE IO.
7 #include <linux/string.h>
8 #include <linux/module.h>
9 #include <linux/ioport.h>
10 #include <linux/slab.h>
11 #include <linux/blkdev.h>
12 #include <linux/errno.h>
13 #include <linux/hdreg.h>
14 #include <linux/ide.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/device.h>
17 #include <linux/init.h>
18 #include <linux/scatterlist.h>
22 #include <asm/ecard.h>
24 #define DRV_NAME "icside"
26 #define ICS_IDENT_OFFSET 0x2280
28 #define ICS_ARCIN_V5_INTRSTAT 0x0000
29 #define ICS_ARCIN_V5_INTROFFSET 0x0004
30 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
31 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
32 #define ICS_ARCIN_V5_IDESTEPPING 6
34 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
35 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
36 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
37 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
38 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
39 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
40 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
41 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
42 #define ICS_ARCIN_V6_IDESTEPPING 6
45 unsigned int dataoffset
;
46 unsigned int ctrloffset
;
47 unsigned int stepping
;
50 static struct cardinfo icside_cardinfo_v5
= {
51 .dataoffset
= ICS_ARCIN_V5_IDEOFFSET
,
52 .ctrloffset
= ICS_ARCIN_V5_IDEALTOFFSET
,
53 .stepping
= ICS_ARCIN_V5_IDESTEPPING
,
56 static struct cardinfo icside_cardinfo_v6_1
= {
57 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_1
,
58 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_1
,
59 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
62 static struct cardinfo icside_cardinfo_v6_2
= {
63 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_2
,
64 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_2
,
65 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
71 void __iomem
*irq_port
;
72 void __iomem
*ioc_base
;
75 struct ide_host
*host
;
78 #define ICS_TYPE_A3IN 0
79 #define ICS_TYPE_A3USER 1
81 #define ICS_TYPE_V5 15
82 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
84 /* ---------------- Version 5 PCB Support Functions --------------------- */
85 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
86 * Purpose : enable interrupts from card
88 static void icside_irqenable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
90 struct icside_state
*state
= ec
->irq_data
;
92 writeb(0, state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
95 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
96 * Purpose : disable interrupts from card
98 static void icside_irqdisable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
100 struct icside_state
*state
= ec
->irq_data
;
102 readb(state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
105 static const expansioncard_ops_t icside_ops_arcin_v5
= {
106 .irqenable
= icside_irqenable_arcin_v5
,
107 .irqdisable
= icside_irqdisable_arcin_v5
,
111 /* ---------------- Version 6 PCB Support Functions --------------------- */
112 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
113 * Purpose : enable interrupts from card
115 static void icside_irqenable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
117 struct icside_state
*state
= ec
->irq_data
;
118 void __iomem
*base
= state
->irq_port
;
122 switch (state
->channel
) {
124 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_1
);
125 readb(base
+ ICS_ARCIN_V6_INTROFFSET_2
);
128 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_2
);
129 readb(base
+ ICS_ARCIN_V6_INTROFFSET_1
);
134 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
135 * Purpose : disable interrupts from card
137 static void icside_irqdisable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
139 struct icside_state
*state
= ec
->irq_data
;
143 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
144 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
147 /* Prototype: icside_irqprobe(struct expansion_card *ec)
148 * Purpose : detect an active interrupt from card
150 static int icside_irqpending_arcin_v6(struct expansion_card
*ec
)
152 struct icside_state
*state
= ec
->irq_data
;
154 return readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_1
) & 1 ||
155 readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_2
) & 1;
158 static const expansioncard_ops_t icside_ops_arcin_v6
= {
159 .irqenable
= icside_irqenable_arcin_v6
,
160 .irqdisable
= icside_irqdisable_arcin_v6
,
161 .irqpending
= icside_irqpending_arcin_v6
,
165 * Handle routing of interrupts. This is called before
166 * we write the command to the drive.
168 static void icside_maskproc(ide_drive_t
*drive
, int mask
)
170 ide_hwif_t
*hwif
= HWIF(drive
);
171 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
172 struct icside_state
*state
= ecard_get_drvdata(ec
);
175 local_irq_save(flags
);
177 state
->channel
= hwif
->channel
;
179 if (state
->enabled
&& !mask
) {
180 switch (hwif
->channel
) {
182 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
183 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
186 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
187 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
191 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
192 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
195 local_irq_restore(flags
);
198 static const struct ide_port_ops icside_v6_no_dma_port_ops
= {
199 .maskproc
= icside_maskproc
,
202 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
206 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
207 * There is only one DMA controller per card, which means that only
208 * one drive can be accessed at one time. NOTE! We do not enforce that
209 * here, but we rely on the main IDE driver spotting that both
210 * interfaces use the same IRQ, which should guarantee this.
214 * Configure the IOMD to give the appropriate timings for the transfer
215 * mode being requested. We take the advice of the ATA standards, and
216 * calculate the cycle time based on the transfer mode, and the EIDE
217 * MW DMA specs that the drive provides in the IDENTIFY command.
219 * We have the following IOMD DMA modes to choose from:
221 * Type Active Recovery Cycle
222 * A 250 (250) 312 (550) 562 (800)
224 * C 125 (125) 125 (375) 250 (500)
227 * (figures in brackets are actual measured timings)
229 * However, we also need to take care of the read/write active and
233 * Mode Active -- Recovery -- Cycle IOMD type
234 * MW0 215 50 215 480 A
238 static void icside_set_dma_mode(ide_drive_t
*drive
, const u8 xfer_mode
)
240 int cycle_time
, use_dma_info
= 0;
265 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
266 * take care to note the values in the ID...
268 if (use_dma_info
&& drive
->id
->eide_dma_time
> cycle_time
)
269 cycle_time
= drive
->id
->eide_dma_time
;
271 drive
->drive_data
= cycle_time
;
273 printk("%s: %s selected (peak %dMB/s)\n", drive
->name
,
274 ide_xfer_verbose(xfer_mode
), 2000 / drive
->drive_data
);
277 static const struct ide_port_ops icside_v6_port_ops
= {
278 .set_dma_mode
= icside_set_dma_mode
,
279 .maskproc
= icside_maskproc
,
282 static void icside_dma_host_set(ide_drive_t
*drive
, int on
)
286 static int icside_dma_end(ide_drive_t
*drive
)
288 ide_hwif_t
*hwif
= HWIF(drive
);
289 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
291 drive
->waiting_for_dma
= 0;
293 disable_dma(ec
->dma
);
295 /* Teardown mappings after DMA has completed. */
296 ide_destroy_dmatable(drive
);
298 return get_dma_residue(ec
->dma
) != 0;
301 static void icside_dma_start(ide_drive_t
*drive
)
303 ide_hwif_t
*hwif
= HWIF(drive
);
304 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
306 /* We can not enable DMA on both channels simultaneously. */
307 BUG_ON(dma_channel_active(ec
->dma
));
311 static int icside_dma_setup(ide_drive_t
*drive
)
313 ide_hwif_t
*hwif
= HWIF(drive
);
314 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
315 struct icside_state
*state
= ecard_get_drvdata(ec
);
316 struct request
*rq
= hwif
->hwgroup
->rq
;
317 unsigned int dma_mode
;
320 dma_mode
= DMA_MODE_WRITE
;
322 dma_mode
= DMA_MODE_READ
;
325 * We can not enable DMA on both channels.
327 BUG_ON(dma_channel_active(ec
->dma
));
329 hwif
->sg_nents
= ide_build_sglist(drive
, rq
);
332 * Ensure that we have the right interrupt routed.
334 icside_maskproc(drive
, 0);
337 * Route the DMA signals to the correct interface.
339 writeb(state
->sel
| hwif
->channel
, state
->ioc_base
);
342 * Select the correct timing for this drive.
344 set_dma_speed(ec
->dma
, drive
->drive_data
);
347 * Tell the DMA engine about the SG table and
350 set_dma_sg(ec
->dma
, hwif
->sg_table
, hwif
->sg_nents
);
351 set_dma_mode(ec
->dma
, dma_mode
);
353 drive
->waiting_for_dma
= 1;
358 static void icside_dma_exec_cmd(ide_drive_t
*drive
, u8 cmd
)
360 /* issue cmd to drive */
361 ide_execute_command(drive
, cmd
, ide_dma_intr
, 2 * WAIT_CMD
, NULL
);
364 static int icside_dma_test_irq(ide_drive_t
*drive
)
366 ide_hwif_t
*hwif
= HWIF(drive
);
367 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
368 struct icside_state
*state
= ecard_get_drvdata(ec
);
370 return readb(state
->irq_port
+
372 ICS_ARCIN_V6_INTRSTAT_2
:
373 ICS_ARCIN_V6_INTRSTAT_1
)) & 1;
376 static void icside_dma_timeout(ide_drive_t
*drive
)
378 ide_hwif_t
*hwif
= drive
->hwif
;
380 printk(KERN_ERR
"%s: DMA timeout occurred: ", drive
->name
);
382 if (icside_dma_test_irq(drive
))
385 ide_dump_status(drive
, "DMA timeout", hwif
->tp_ops
->read_status(hwif
));
387 icside_dma_end(drive
);
390 static void icside_dma_lost_irq(ide_drive_t
*drive
)
392 printk(KERN_ERR
"%s: IRQ lost\n", drive
->name
);
395 static int icside_dma_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
397 hwif
->dmatable_cpu
= NULL
;
398 hwif
->dmatable_dma
= 0;
403 static const struct ide_dma_ops icside_v6_dma_ops
= {
404 .dma_host_set
= icside_dma_host_set
,
405 .dma_setup
= icside_dma_setup
,
406 .dma_exec_cmd
= icside_dma_exec_cmd
,
407 .dma_start
= icside_dma_start
,
408 .dma_end
= icside_dma_end
,
409 .dma_test_irq
= icside_dma_test_irq
,
410 .dma_timeout
= icside_dma_timeout
,
411 .dma_lost_irq
= icside_dma_lost_irq
,
414 #define icside_v6_dma_ops NULL
417 static int icside_dma_off_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
422 static void icside_setup_ports(hw_regs_t
*hw
, void __iomem
*base
,
423 struct cardinfo
*info
, struct expansion_card
*ec
)
425 unsigned long port
= (unsigned long)base
+ info
->dataoffset
;
427 hw
->io_ports
.data_addr
= port
;
428 hw
->io_ports
.error_addr
= port
+ (1 << info
->stepping
);
429 hw
->io_ports
.nsect_addr
= port
+ (2 << info
->stepping
);
430 hw
->io_ports
.lbal_addr
= port
+ (3 << info
->stepping
);
431 hw
->io_ports
.lbam_addr
= port
+ (4 << info
->stepping
);
432 hw
->io_ports
.lbah_addr
= port
+ (5 << info
->stepping
);
433 hw
->io_ports
.device_addr
= port
+ (6 << info
->stepping
);
434 hw
->io_ports
.status_addr
= port
+ (7 << info
->stepping
);
435 hw
->io_ports
.ctl_addr
= (unsigned long)base
+ info
->ctrloffset
;
439 hw
->chipset
= ide_acorn
;
443 icside_register_v5(struct icside_state
*state
, struct expansion_card
*ec
)
446 struct ide_host
*host
;
447 hw_regs_t hw
, *hws
[] = { &hw
, NULL
, NULL
, NULL
};
450 base
= ecardm_iomap(ec
, ECARD_RES_MEMC
, 0, 0);
454 state
->irq_port
= base
;
456 ec
->irqaddr
= base
+ ICS_ARCIN_V5_INTRSTAT
;
459 ecard_setirq(ec
, &icside_ops_arcin_v5
, state
);
462 * Be on the safe side - disable interrupts
464 icside_irqdisable_arcin_v5(ec
, 0);
466 icside_setup_ports(&hw
, base
, &icside_cardinfo_v5
, ec
);
468 host
= ide_host_alloc(NULL
, hws
);
474 ecard_set_drvdata(ec
, state
);
476 ret
= ide_host_register(host
, NULL
, hws
);
483 ecard_set_drvdata(ec
, NULL
);
487 static const struct ide_port_info icside_v6_port_info __initdata
= {
488 .init_dma
= icside_dma_off_init
,
489 .port_ops
= &icside_v6_no_dma_port_ops
,
490 .dma_ops
= &icside_v6_dma_ops
,
491 .host_flags
= IDE_HFLAG_SERIALIZE
| IDE_HFLAG_MMIO
,
492 .mwdma_mask
= ATA_MWDMA2
,
493 .swdma_mask
= ATA_SWDMA2
,
497 icside_register_v6(struct icside_state
*state
, struct expansion_card
*ec
)
499 void __iomem
*ioc_base
, *easi_base
;
500 struct ide_host
*host
;
501 unsigned int sel
= 0;
503 hw_regs_t hw
[2], *hws
[] = { &hw
[0], NULL
, NULL
, NULL
};
504 struct ide_port_info d
= icside_v6_port_info
;
506 ioc_base
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
512 easi_base
= ioc_base
;
514 if (ecard_resource_flags(ec
, ECARD_RES_EASI
)) {
515 easi_base
= ecardm_iomap(ec
, ECARD_RES_EASI
, 0, 0);
522 * Enable access to the EASI region.
527 writeb(sel
, ioc_base
);
529 ecard_setirq(ec
, &icside_ops_arcin_v6
, state
);
531 state
->irq_port
= easi_base
;
532 state
->ioc_base
= ioc_base
;
536 * Be on the safe side - disable interrupts
538 icside_irqdisable_arcin_v6(ec
, 0);
540 icside_setup_ports(&hw
[0], easi_base
, &icside_cardinfo_v6_1
, ec
);
541 icside_setup_ports(&hw
[1], easi_base
, &icside_cardinfo_v6_2
, ec
);
543 host
= ide_host_alloc(&d
, hws
);
549 ecard_set_drvdata(ec
, state
);
551 if (ec
->dma
!= NO_DMA
&& !request_dma(ec
->dma
, DRV_NAME
)) {
552 d
.init_dma
= icside_dma_init
;
553 d
.port_ops
= &icside_v6_port_ops
;
557 ret
= ide_host_register(host
, NULL
, hws
);
566 ecard_set_drvdata(ec
, NULL
);
572 icside_probe(struct expansion_card
*ec
, const struct ecard_id
*id
)
574 struct icside_state
*state
;
578 ret
= ecard_request_resources(ec
);
582 state
= kzalloc(sizeof(struct icside_state
), GFP_KERNEL
);
588 state
->type
= ICS_TYPE_NOTYPE
;
590 idmem
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
594 type
= readb(idmem
+ ICS_IDENT_OFFSET
) & 1;
595 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 4) & 1) << 1;
596 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 8) & 1) << 2;
597 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 12) & 1) << 3;
598 ecardm_iounmap(ec
, idmem
);
603 switch (state
->type
) {
605 dev_warn(&ec
->dev
, "A3IN unsupported\n");
609 case ICS_TYPE_A3USER
:
610 dev_warn(&ec
->dev
, "A3USER unsupported\n");
615 ret
= icside_register_v5(state
, ec
);
619 ret
= icside_register_v6(state
, ec
);
623 dev_warn(&ec
->dev
, "unknown interface type\n");
633 ecard_release_resources(ec
);
638 static void __devexit
icside_remove(struct expansion_card
*ec
)
640 struct icside_state
*state
= ecard_get_drvdata(ec
);
642 switch (state
->type
) {
644 /* FIXME: tell IDE to stop using the interface */
646 /* Disable interrupts */
647 icside_irqdisable_arcin_v5(ec
, 0);
651 /* FIXME: tell IDE to stop using the interface */
652 if (ec
->dma
!= NO_DMA
)
655 /* Disable interrupts */
656 icside_irqdisable_arcin_v6(ec
, 0);
658 /* Reset the ROM pointer/EASI selection */
659 writeb(0, state
->ioc_base
);
663 ecard_set_drvdata(ec
, NULL
);
666 ecard_release_resources(ec
);
669 static void icside_shutdown(struct expansion_card
*ec
)
671 struct icside_state
*state
= ecard_get_drvdata(ec
);
675 * Disable interrupts from this card. We need to do
676 * this before disabling EASI since we may be accessing
677 * this register via that region.
679 local_irq_save(flags
);
680 ec
->ops
->irqdisable(ec
, 0);
681 local_irq_restore(flags
);
684 * Reset the ROM pointer so that we can read the ROM
685 * after a soft reboot. This also disables access to
686 * the IDE taskfile via the EASI region.
689 writeb(0, state
->ioc_base
);
692 static const struct ecard_id icside_ids
[] = {
693 { MANU_ICS
, PROD_ICS_IDE
},
694 { MANU_ICS2
, PROD_ICS2_IDE
},
698 static struct ecard_driver icside_driver
= {
699 .probe
= icside_probe
,
700 .remove
= __devexit_p(icside_remove
),
701 .shutdown
= icside_shutdown
,
702 .id_table
= icside_ids
,
708 static int __init
icside_init(void)
710 return ecard_register_driver(&icside_driver
);
713 static void __exit
icside_exit(void);
715 ecard_unregister_driver(&icside_driver
);
718 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
719 MODULE_LICENSE("GPL");
720 MODULE_DESCRIPTION("ICS IDE driver");
722 module_init(icside_init
);
723 module_exit(icside_exit
);