?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] hrtimer comment tweak
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / cassini.c
blob1f7ca453bb4a28c48a5e44da3024df4b8facdb5c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2 *
3 * Copyright (C) 2004 Sun Microsystems Inc.
4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19 * 02111-1307, USA.
20 *
21 * This driver uses the sungem driver (c) David Miller
22 * (davem@redhat.com) as its basis.
23 *
24 * The cassini chip has a number of features that distinguish it from
25 * the gem chip:
26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
27 * load balancing (non-VLAN mode)
28 * batching of multiple packets
29 * multiple CPU dispatching
30 * page-based RX descriptor engine with separate completion rings
31 * Gigabit support (GMII and PCS interface)
32 * MIF link up/down detection works
33 *
34 * RX is handled by page sized buffers that are attached as fragments to
35 * the skb. here's what's done:
36 * -- driver allocates pages at a time and keeps reference counts
37 * on them.
38 * -- the upper protocol layers assume that the header is in the skb
39 * itself. as a result, cassini will copy a small amount (64 bytes)
40 * to make them happy.
41 * -- driver appends the rest of the data pages as frags to skbuffs
42 * and increments the reference count
43 * -- on page reclamation, the driver swaps the page with a spare page.
44 * if that page is still in use, it frees its reference to that page,
45 * and allocates a new page for use. otherwise, it just recycles the
46 * the page.
47 *
48 * NOTE: cassini can parse the header. however, it's not worth it
49 * as long as the network stack requires a header copy.
50 *
51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targetted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose
56 * ioctl.
57 *
58 * RX DATA: the rx completion ring has all the info, but the rx desc
59 * ring has all of the data. RX can conceivably come in under multiple
60 * interrupts, but the INT# assignment needs to be set up properly by
61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62 * that. also, the two descriptor rings are designed to distinguish between
63 * encrypted and non-encrypted packets, but we use them for buffering
64 * instead.
65 *
66 * by default, the selective clear mask is set up to process rx packets.
67 */
68
69 #include <linux/config.h>
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74 #include <linux/compiler.h>
75 #include <linux/slab.h>
76 #include <linux/delay.h>
77 #include <linux/init.h>
78 #include <linux/ioport.h>
79 #include <linux/pci.h>
80 #include <linux/mm.h>
81 #include <linux/highmem.h>
82 #include <linux/list.h>
83 #include <linux/dma-mapping.h>
84
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/crc32.h>
90 #include <linux/random.h>
91 #include <linux/mii.h>
92 #include <linux/ip.h>
93 #include <linux/tcp.h>
94
95 #include <net/checksum.h>
96
97 #include <asm/atomic.h>
98 #include <asm/system.h>
99 #include <asm/io.h>
100 #include <asm/byteorder.h>
101 #include <asm/uaccess.h>
102
103 #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
104 #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define CAS_NCPUS num_online_cpus()
106
107 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
108 #define USE_NAPI
109 #define cas_skb_release(x) netif_receive_skb(x)
110 #else
111 #define cas_skb_release(x) netif_rx(x)
112 #endif
113
114 /* select which firmware to use */
115 #define USE_HP_WORKAROUND
116 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
117 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
118
119 #include "cassini.h"
120
121 #define USE_TX_COMPWB /* use completion writeback registers */
122 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
123 #define USE_RX_BLANK /* hw interrupt mitigation */
124 #undef USE_ENTROPY_DEV /* don't test for entropy device */
125
126 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
127 * also, we need to make cp->lock finer-grained.
128 */
129 #undef USE_PCI_INTB
130 #undef USE_PCI_INTC
131 #undef USE_PCI_INTD
132 #undef USE_QOS
133
134 #undef USE_VPD_DEBUG /* debug vpd information if defined */
135
136 /* rx processing options */
137 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
138 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
139 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
140 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
141 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
142
143 #define DRV_MODULE_NAME "cassini"
144 #define PFX DRV_MODULE_NAME ": "
145 #define DRV_MODULE_VERSION "1.4"
146 #define DRV_MODULE_RELDATE "1 July 2004"
147
148 #define CAS_DEF_MSG_ENABLE \
149 (NETIF_MSG_DRV | \
150 NETIF_MSG_PROBE | \
151 NETIF_MSG_LINK | \
152 NETIF_MSG_TIMER | \
153 NETIF_MSG_IFDOWN | \
154 NETIF_MSG_IFUP | \
155 NETIF_MSG_RX_ERR | \
156 NETIF_MSG_TX_ERR)
157
158 /* length of time before we decide the hardware is borked,
159 * and dev->tx_timeout() should be called to fix the problem
160 */
161 #define CAS_TX_TIMEOUT (HZ)
162 #define CAS_LINK_TIMEOUT (22*HZ/10)
163 #define CAS_LINK_FAST_TIMEOUT (1)
164
165 /* timeout values for state changing. these specify the number
166 * of 10us delays to be used before giving up.
167 */
168 #define STOP_TRIES_PHY 1000
169 #define STOP_TRIES 5000
170
171 /* specify a minimum frame size to deal with some fifo issues
172 * max mtu == 2 * page size - ethernet header - 64 - swivel =
173 * 2 * page_size - 0x50
174 */
175 #define CAS_MIN_FRAME 97
176 #define CAS_1000MB_MIN_FRAME 255
177 #define CAS_MIN_MTU 60
178 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
179
180 #if 1
181 /*
182 * Eliminate these and use separate atomic counters for each, to
183 * avoid a race condition.
184 */
185 #else
186 #define CAS_RESET_MTU 1
187 #define CAS_RESET_ALL 2
188 #define CAS_RESET_SPARE 3
189 #endif
190
191 static char version[] __devinitdata =
192 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
193
194 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
195 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
196 MODULE_LICENSE("GPL");
197 MODULE_PARM(cassini_debug, "i");
198 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
199 MODULE_PARM(link_mode, "i");
200 MODULE_PARM_DESC(link_mode, "default link mode");
201
202 /*
203 * Work around for a PCS bug in which the link goes down due to the chip
204 * being confused and never showing a link status of "up."
205 */
206 #define DEFAULT_LINKDOWN_TIMEOUT 5
207 /*
208 * Value in seconds, for user input.
209 */
210 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
211 MODULE_PARM(linkdown_timeout, "i");
212 MODULE_PARM_DESC(linkdown_timeout,
213 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
214
215 /*
216 * value in 'ticks' (units used by jiffies). Set when we init the
217 * module because 'HZ' in actually a function call on some flavors of
218 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
219 */
220 static int link_transition_timeout;
221
222
223 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
224 static int link_mode;
225
226 static u16 link_modes[] __devinitdata = {
227 BMCR_ANENABLE, /* 0 : autoneg */
228 0, /* 1 : 10bt half duplex */
229 BMCR_SPEED100, /* 2 : 100bt half duplex */
230 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
231 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
232 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
233 };
234
235 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
236 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { 0, }
241 };
242
243 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
244
245 static void cas_set_link_modes(struct cas *cp);
246
247 static inline void cas_lock_tx(struct cas *cp)
248 {
249 int i;
250
251 for (i = 0; i < N_TX_RINGS; i++)
252 spin_lock(&cp->tx_lock[i]);
253 }
254
255 static inline void cas_lock_all(struct cas *cp)
256 {
257 spin_lock_irq(&cp->lock);
258 cas_lock_tx(cp);
259 }
260
261 /* WTZ: QA was finding deadlock problems with the previous
262 * versions after long test runs with multiple cards per machine.
263 * See if replacing cas_lock_all with safer versions helps. The
264 * symptoms QA is reporting match those we'd expect if interrupts
265 * aren't being properly restored, and we fixed a previous deadlock
266 * with similar symptoms by using save/restore versions in other
267 * places.
268 */
269 #define cas_lock_all_save(cp, flags) \
270 do { \
271 struct cas *xxxcp = (cp); \
272 spin_lock_irqsave(&xxxcp->lock, flags); \
273 cas_lock_tx(xxxcp); \
274 } while (0)
275
276 static inline void cas_unlock_tx(struct cas *cp)
277 {
278 int i;
279
280 for (i = N_TX_RINGS; i > 0; i--)
281 spin_unlock(&cp->tx_lock[i - 1]);
282 }
283
284 static inline void cas_unlock_all(struct cas *cp)
285 {
286 cas_unlock_tx(cp);
287 spin_unlock_irq(&cp->lock);
288 }
289
290 #define cas_unlock_all_restore(cp, flags) \
291 do { \
292 struct cas *xxxcp = (cp); \
293 cas_unlock_tx(xxxcp); \
294 spin_unlock_irqrestore(&xxxcp->lock, flags); \
295 } while (0)
296
297 static void cas_disable_irq(struct cas *cp, const int ring)
298 {
299 /* Make sure we won't get any more interrupts */
300 if (ring == 0) {
301 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
302 return;
303 }
304
305 /* disable completion interrupts and selectively mask */
306 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
307 switch (ring) {
308 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
309 #ifdef USE_PCI_INTB
310 case 1:
311 #endif
312 #ifdef USE_PCI_INTC
313 case 2:
314 #endif
315 #ifdef USE_PCI_INTD
316 case 3:
317 #endif
318 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
319 cp->regs + REG_PLUS_INTRN_MASK(ring));
320 break;
321 #endif
322 default:
323 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
324 REG_PLUS_INTRN_MASK(ring));
325 break;
326 }
327 }
328 }
329
330 static inline void cas_mask_intr(struct cas *cp)
331 {
332 int i;
333
334 for (i = 0; i < N_RX_COMP_RINGS; i++)
335 cas_disable_irq(cp, i);
336 }
337
338 static void cas_enable_irq(struct cas *cp, const int ring)
339 {
340 if (ring == 0) { /* all but TX_DONE */
341 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
342 return;
343 }
344
345 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
346 switch (ring) {
347 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
348 #ifdef USE_PCI_INTB
349 case 1:
350 #endif
351 #ifdef USE_PCI_INTC
352 case 2:
353 #endif
354 #ifdef USE_PCI_INTD
355 case 3:
356 #endif
357 writel(INTRN_MASK_RX_EN, cp->regs +
358 REG_PLUS_INTRN_MASK(ring));
359 break;
360 #endif
361 default:
362 break;
363 }
364 }
365 }
366
367 static inline void cas_unmask_intr(struct cas *cp)
368 {
369 int i;
370
371 for (i = 0; i < N_RX_COMP_RINGS; i++)
372 cas_enable_irq(cp, i);
373 }
374
375 static inline void cas_entropy_gather(struct cas *cp)
376 {
377 #ifdef USE_ENTROPY_DEV
378 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
379 return;
380
381 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
382 readl(cp->regs + REG_ENTROPY_IV),
383 sizeof(uint64_t)*8);
384 #endif
385 }
386
387 static inline void cas_entropy_reset(struct cas *cp)
388 {
389 #ifdef USE_ENTROPY_DEV
390 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
391 return;
392
393 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
394 cp->regs + REG_BIM_LOCAL_DEV_EN);
395 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
396 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
397
398 /* if we read back 0x0, we don't have an entropy device */
399 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
400 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
401 #endif
402 }
403
404 /* access to the phy. the following assumes that we've initialized the MIF to
405 * be in frame rather than bit-bang mode
406 */
407 static u16 cas_phy_read(struct cas *cp, int reg)
408 {
409 u32 cmd;
410 int limit = STOP_TRIES_PHY;
411
412 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
413 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
414 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
415 cmd |= MIF_FRAME_TURN_AROUND_MSB;
416 writel(cmd, cp->regs + REG_MIF_FRAME);
417
418 /* poll for completion */
419 while (limit-- > 0) {
420 udelay(10);
421 cmd = readl(cp->regs + REG_MIF_FRAME);
422 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
423 return (cmd & MIF_FRAME_DATA_MASK);
424 }
425 return 0xFFFF; /* -1 */
426 }
427
428 static int cas_phy_write(struct cas *cp, int reg, u16 val)
429 {
430 int limit = STOP_TRIES_PHY;
431 u32 cmd;
432
433 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
434 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
435 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
436 cmd |= MIF_FRAME_TURN_AROUND_MSB;
437 cmd |= val & MIF_FRAME_DATA_MASK;
438 writel(cmd, cp->regs + REG_MIF_FRAME);
439
440 /* poll for completion */
441 while (limit-- > 0) {
442 udelay(10);
443 cmd = readl(cp->regs + REG_MIF_FRAME);
444 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
445 return 0;
446 }
447 return -1;
448 }
449
450 static void cas_phy_powerup(struct cas *cp)
451 {
452 u16 ctl = cas_phy_read(cp, MII_BMCR);
453
454 if ((ctl & BMCR_PDOWN) == 0)
455 return;
456 ctl &= ~BMCR_PDOWN;
457 cas_phy_write(cp, MII_BMCR, ctl);
458 }
459
460 static void cas_phy_powerdown(struct cas *cp)
461 {
462 u16 ctl = cas_phy_read(cp, MII_BMCR);
463
464 if (ctl & BMCR_PDOWN)
465 return;
466 ctl |= BMCR_PDOWN;
467 cas_phy_write(cp, MII_BMCR, ctl);
468 }
469
470 /* cp->lock held. note: the last put_page will free the buffer */
471 static int cas_page_free(struct cas *cp, cas_page_t *page)
472 {
473 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
474 PCI_DMA_FROMDEVICE);
475 __free_pages(page->buffer, cp->page_order);
476 kfree(page);
477 return 0;
478 }
479
480 #ifdef RX_COUNT_BUFFERS
481 #define RX_USED_ADD(x, y) ((x)->used += (y))
482 #define RX_USED_SET(x, y) ((x)->used = (y))
483 #else
484 #define RX_USED_ADD(x, y)
485 #define RX_USED_SET(x, y)
486 #endif
487
488 /* local page allocation routines for the receive buffers. jumbo pages
489 * require at least 8K contiguous and 8K aligned buffers.
490 */
491 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
492 {
493 cas_page_t *page;
494
495 page = kmalloc(sizeof(cas_page_t), flags);
496 if (!page)
497 return NULL;
498
499 INIT_LIST_HEAD(&page->list);
500 RX_USED_SET(page, 0);
501 page->buffer = alloc_pages(flags, cp->page_order);
502 if (!page->buffer)
503 goto page_err;
504 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
505 cp->page_size, PCI_DMA_FROMDEVICE);
506 return page;
507
508 page_err:
509 kfree(page);
510 return NULL;
511 }
512
513 /* initialize spare pool of rx buffers, but allocate during the open */
514 static void cas_spare_init(struct cas *cp)
515 {
516 spin_lock(&cp->rx_inuse_lock);
517 INIT_LIST_HEAD(&cp->rx_inuse_list);
518 spin_unlock(&cp->rx_inuse_lock);
519
520 spin_lock(&cp->rx_spare_lock);
521 INIT_LIST_HEAD(&cp->rx_spare_list);
522 cp->rx_spares_needed = RX_SPARE_COUNT;
523 spin_unlock(&cp->rx_spare_lock);
524 }
525
526 /* used on close. free all the spare buffers. */
527 static void cas_spare_free(struct cas *cp)
528 {
529 struct list_head list, *elem, *tmp;
530
531 /* free spare buffers */
532 INIT_LIST_HEAD(&list);
533 spin_lock(&cp->rx_spare_lock);
534 list_splice(&cp->rx_spare_list, &list);
535 INIT_LIST_HEAD(&cp->rx_spare_list);
536 spin_unlock(&cp->rx_spare_lock);
537 list_for_each_safe(elem, tmp, &list) {
538 cas_page_free(cp, list_entry(elem, cas_page_t, list));
539 }
540
541 INIT_LIST_HEAD(&list);
542 #if 1
543 /*
544 * Looks like Adrian had protected this with a different
545 * lock than used everywhere else to manipulate this list.
546 */
547 spin_lock(&cp->rx_inuse_lock);
548 list_splice(&cp->rx_inuse_list, &list);
549 INIT_LIST_HEAD(&cp->rx_inuse_list);
550 spin_unlock(&cp->rx_inuse_lock);
551 #else
552 spin_lock(&cp->rx_spare_lock);
553 list_splice(&cp->rx_inuse_list, &list);
554 INIT_LIST_HEAD(&cp->rx_inuse_list);
555 spin_unlock(&cp->rx_spare_lock);
556 #endif
557 list_for_each_safe(elem, tmp, &list) {
558 cas_page_free(cp, list_entry(elem, cas_page_t, list));
559 }
560 }
561
562 /* replenish spares if needed */
563 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
564 {
565 struct list_head list, *elem, *tmp;
566 int needed, i;
567
568 /* check inuse list. if we don't need any more free buffers,
569 * just free it
570 */
571
572 /* make a local copy of the list */
573 INIT_LIST_HEAD(&list);
574 spin_lock(&cp->rx_inuse_lock);
575 list_splice(&cp->rx_inuse_list, &list);
576 INIT_LIST_HEAD(&cp->rx_inuse_list);
577 spin_unlock(&cp->rx_inuse_lock);
578
579 list_for_each_safe(elem, tmp, &list) {
580 cas_page_t *page = list_entry(elem, cas_page_t, list);
581
582 if (page_count(page->buffer) > 1)
583 continue;
584
585 list_del(elem);
586 spin_lock(&cp->rx_spare_lock);
587 if (cp->rx_spares_needed > 0) {
588 list_add(elem, &cp->rx_spare_list);
589 cp->rx_spares_needed--;
590 spin_unlock(&cp->rx_spare_lock);
591 } else {
592 spin_unlock(&cp->rx_spare_lock);
593 cas_page_free(cp, page);
594 }
595 }
596
597 /* put any inuse buffers back on the list */
598 if (!list_empty(&list)) {
599 spin_lock(&cp->rx_inuse_lock);
600 list_splice(&list, &cp->rx_inuse_list);
601 spin_unlock(&cp->rx_inuse_lock);
602 }
603
604 spin_lock(&cp->rx_spare_lock);
605 needed = cp->rx_spares_needed;
606 spin_unlock(&cp->rx_spare_lock);
607 if (!needed)
608 return;
609
610 /* we still need spares, so try to allocate some */
611 INIT_LIST_HEAD(&list);
612 i = 0;
613 while (i < needed) {
614 cas_page_t *spare = cas_page_alloc(cp, flags);
615 if (!spare)
616 break;
617 list_add(&spare->list, &list);
618 i++;
619 }
620
621 spin_lock(&cp->rx_spare_lock);
622 list_splice(&list, &cp->rx_spare_list);
623 cp->rx_spares_needed -= i;
624 spin_unlock(&cp->rx_spare_lock);
625 }
626
627 /* pull a page from the list. */
628 static cas_page_t *cas_page_dequeue(struct cas *cp)
629 {
630 struct list_head *entry;
631 int recover;
632
633 spin_lock(&cp->rx_spare_lock);
634 if (list_empty(&cp->rx_spare_list)) {
635 /* try to do a quick recovery */
636 spin_unlock(&cp->rx_spare_lock);
637 cas_spare_recover(cp, GFP_ATOMIC);
638 spin_lock(&cp->rx_spare_lock);
639 if (list_empty(&cp->rx_spare_list)) {
640 if (netif_msg_rx_err(cp))
641 printk(KERN_ERR "%s: no spare buffers "
642 "available.\n", cp->dev->name);
643 spin_unlock(&cp->rx_spare_lock);
644 return NULL;
645 }
646 }
647
648 entry = cp->rx_spare_list.next;
649 list_del(entry);
650 recover = ++cp->rx_spares_needed;
651 spin_unlock(&cp->rx_spare_lock);
652
653 /* trigger the timer to do the recovery */
654 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
655 #if 1
656 atomic_inc(&cp->reset_task_pending);
657 atomic_inc(&cp->reset_task_pending_spare);
658 schedule_work(&cp->reset_task);
659 #else
660 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
661 schedule_work(&cp->reset_task);
662 #endif
663 }
664 return list_entry(entry, cas_page_t, list);
665 }
666
667
668 static void cas_mif_poll(struct cas *cp, const int enable)
669 {
670 u32 cfg;
671
672 cfg = readl(cp->regs + REG_MIF_CFG);
673 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
674
675 if (cp->phy_type & CAS_PHY_MII_MDIO1)
676 cfg |= MIF_CFG_PHY_SELECT;
677
678 /* poll and interrupt on link status change. */
679 if (enable) {
680 cfg |= MIF_CFG_POLL_EN;
681 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
682 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
683 }
684 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
685 cp->regs + REG_MIF_MASK);
686 writel(cfg, cp->regs + REG_MIF_CFG);
687 }
688
689 /* Must be invoked under cp->lock */
690 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
691 {
692 u16 ctl;
693 #if 1
694 int lcntl;
695 int changed = 0;
696 int oldstate = cp->lstate;
697 int link_was_not_down = !(oldstate == link_down);
698 #endif
699 /* Setup link parameters */
700 if (!ep)
701 goto start_aneg;
702 lcntl = cp->link_cntl;
703 if (ep->autoneg == AUTONEG_ENABLE)
704 cp->link_cntl = BMCR_ANENABLE;
705 else {
706 cp->link_cntl = 0;
707 if (ep->speed == SPEED_100)
708 cp->link_cntl |= BMCR_SPEED100;
709 else if (ep->speed == SPEED_1000)
710 cp->link_cntl |= CAS_BMCR_SPEED1000;
711 if (ep->duplex == DUPLEX_FULL)
712 cp->link_cntl |= BMCR_FULLDPLX;
713 }
714 #if 1
715 changed = (lcntl != cp->link_cntl);
716 #endif
717 start_aneg:
718 if (cp->lstate == link_up) {
719 printk(KERN_INFO "%s: PCS link down.\n",
720 cp->dev->name);
721 } else {
722 if (changed) {
723 printk(KERN_INFO "%s: link configuration changed\n",
724 cp->dev->name);
725 }
726 }
727 cp->lstate = link_down;
728 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
729 if (!cp->hw_running)
730 return;
731 #if 1
732 /*
733 * WTZ: If the old state was link_up, we turn off the carrier
734 * to replicate everything we do elsewhere on a link-down
735 * event when we were already in a link-up state..
736 */
737 if (oldstate == link_up)
738 netif_carrier_off(cp->dev);
739 if (changed && link_was_not_down) {
740 /*
741 * WTZ: This branch will simply schedule a full reset after
742 * we explicitly changed link modes in an ioctl. See if this
743 * fixes the link-problems we were having for forced mode.
744 */
745 atomic_inc(&cp->reset_task_pending);
746 atomic_inc(&cp->reset_task_pending_all);
747 schedule_work(&cp->reset_task);
748 cp->timer_ticks = 0;
749 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
750 return;
751 }
752 #endif
753 if (cp->phy_type & CAS_PHY_SERDES) {
754 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
755
756 if (cp->link_cntl & BMCR_ANENABLE) {
757 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
758 cp->lstate = link_aneg;
759 } else {
760 if (cp->link_cntl & BMCR_FULLDPLX)
761 val |= PCS_MII_CTRL_DUPLEX;
762 val &= ~PCS_MII_AUTONEG_EN;
763 cp->lstate = link_force_ok;
764 }
765 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
766 writel(val, cp->regs + REG_PCS_MII_CTRL);
767
768 } else {
769 cas_mif_poll(cp, 0);
770 ctl = cas_phy_read(cp, MII_BMCR);
771 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
772 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
773 ctl |= cp->link_cntl;
774 if (ctl & BMCR_ANENABLE) {
775 ctl |= BMCR_ANRESTART;
776 cp->lstate = link_aneg;
777 } else {
778 cp->lstate = link_force_ok;
779 }
780 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
781 cas_phy_write(cp, MII_BMCR, ctl);
782 cas_mif_poll(cp, 1);
783 }
784
785 cp->timer_ticks = 0;
786 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
787 }
788
789 /* Must be invoked under cp->lock. */
790 static int cas_reset_mii_phy(struct cas *cp)
791 {
792 int limit = STOP_TRIES_PHY;
793 u16 val;
794
795 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
796 udelay(100);
797 while (limit--) {
798 val = cas_phy_read(cp, MII_BMCR);
799 if ((val & BMCR_RESET) == 0)
800 break;
801 udelay(10);
802 }
803 return (limit <= 0);
804 }
805
806 static void cas_saturn_firmware_load(struct cas *cp)
807 {
808 cas_saturn_patch_t *patch = cas_saturn_patch;
809
810 cas_phy_powerdown(cp);
811
812 /* expanded memory access mode */
813 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
814
815 /* pointer configuration for new firmware */
816 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
817 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
818 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
819 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
820 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
821 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
822 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
823 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
824
825 /* download new firmware */
826 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
827 cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
828 while (patch->addr) {
829 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
830 patch++;
831 }
832
833 /* enable firmware */
834 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
835 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
836 }
837
838
839 /* phy initialization */
840 static void cas_phy_init(struct cas *cp)
841 {
842 u16 val;
843
844 /* if we're in MII/GMII mode, set up phy */
845 if (CAS_PHY_MII(cp->phy_type)) {
846 writel(PCS_DATAPATH_MODE_MII,
847 cp->regs + REG_PCS_DATAPATH_MODE);
848
849 cas_mif_poll(cp, 0);
850 cas_reset_mii_phy(cp); /* take out of isolate mode */
851
852 if (PHY_LUCENT_B0 == cp->phy_id) {
853 /* workaround link up/down issue with lucent */
854 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
855 cas_phy_write(cp, MII_BMCR, 0x00f1);
856 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
857
858 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
859 /* workarounds for broadcom phy */
860 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
861 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
862 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
863 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
864 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
865 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
866 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
867 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
868 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
869 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
870 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
871
872 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
873 val = cas_phy_read(cp, BROADCOM_MII_REG4);
874 val = cas_phy_read(cp, BROADCOM_MII_REG4);
875 if (val & 0x0080) {
876 /* link workaround */
877 cas_phy_write(cp, BROADCOM_MII_REG4,
878 val & ~0x0080);
879 }
880
881 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
882 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
883 SATURN_PCFG_FSI : 0x0,
884 cp->regs + REG_SATURN_PCFG);
885
886 /* load firmware to address 10Mbps auto-negotiation
887 * issue. NOTE: this will need to be changed if the
888 * default firmware gets fixed.
889 */
890 if (PHY_NS_DP83065 == cp->phy_id) {
891 cas_saturn_firmware_load(cp);
892 }
893 cas_phy_powerup(cp);
894 }
895
896 /* advertise capabilities */
897 val = cas_phy_read(cp, MII_BMCR);
898 val &= ~BMCR_ANENABLE;
899 cas_phy_write(cp, MII_BMCR, val);
900 udelay(10);
901
902 cas_phy_write(cp, MII_ADVERTISE,
903 cas_phy_read(cp, MII_ADVERTISE) |
904 (ADVERTISE_10HALF | ADVERTISE_10FULL |
905 ADVERTISE_100HALF | ADVERTISE_100FULL |
906 CAS_ADVERTISE_PAUSE |
907 CAS_ADVERTISE_ASYM_PAUSE));
908
909 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
910 /* make sure that we don't advertise half
911 * duplex to avoid a chip issue
912 */
913 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
914 val &= ~CAS_ADVERTISE_1000HALF;
915 val |= CAS_ADVERTISE_1000FULL;
916 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
917 }
918
919 } else {
920 /* reset pcs for serdes */
921 u32 val;
922 int limit;
923
924 writel(PCS_DATAPATH_MODE_SERDES,
925 cp->regs + REG_PCS_DATAPATH_MODE);
926
927 /* enable serdes pins on saturn */
928 if (cp->cas_flags & CAS_FLAG_SATURN)
929 writel(0, cp->regs + REG_SATURN_PCFG);
930
931 /* Reset PCS unit. */
932 val = readl(cp->regs + REG_PCS_MII_CTRL);
933 val |= PCS_MII_RESET;
934 writel(val, cp->regs + REG_PCS_MII_CTRL);
935
936 limit = STOP_TRIES;
937 while (limit-- > 0) {
938 udelay(10);
939 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
940 PCS_MII_RESET) == 0)
941 break;
942 }
943 if (limit <= 0)
944 printk(KERN_WARNING "%s: PCS reset bit would not "
945 "clear [%08x].\n", cp->dev->name,
946 readl(cp->regs + REG_PCS_STATE_MACHINE));
947
948 /* Make sure PCS is disabled while changing advertisement
949 * configuration.
950 */
951 writel(0x0, cp->regs + REG_PCS_CFG);
952
953 /* Advertise all capabilities except half-duplex. */
954 val = readl(cp->regs + REG_PCS_MII_ADVERT);
955 val &= ~PCS_MII_ADVERT_HD;
956 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
957 PCS_MII_ADVERT_ASYM_PAUSE);
958 writel(val, cp->regs + REG_PCS_MII_ADVERT);
959
960 /* enable PCS */
961 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
962
963 /* pcs workaround: enable sync detect */
964 writel(PCS_SERDES_CTRL_SYNCD_EN,
965 cp->regs + REG_PCS_SERDES_CTRL);
966 }
967 }
968
969
970 static int cas_pcs_link_check(struct cas *cp)
971 {
972 u32 stat, state_machine;
973 int retval = 0;
974
975 /* The link status bit latches on zero, so you must
976 * read it twice in such a case to see a transition
977 * to the link being up.
978 */
979 stat = readl(cp->regs + REG_PCS_MII_STATUS);
980 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
981 stat = readl(cp->regs + REG_PCS_MII_STATUS);
982
983 /* The remote-fault indication is only valid
984 * when autoneg has completed.
985 */
986 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
987 PCS_MII_STATUS_REMOTE_FAULT)) ==
988 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
989 if (netif_msg_link(cp))
990 printk(KERN_INFO "%s: PCS RemoteFault\n",
991 cp->dev->name);
992 }
993
994 /* work around link detection issue by querying the PCS state
995 * machine directly.
996 */
997 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
998 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
999 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1000 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1001 stat |= PCS_MII_STATUS_LINK_STATUS;
1002 }
1003
1004 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1005 if (cp->lstate != link_up) {
1006 if (cp->opened) {
1007 cp->lstate = link_up;
1008 cp->link_transition = LINK_TRANSITION_LINK_UP;
1009
1010 cas_set_link_modes(cp);
1011 netif_carrier_on(cp->dev);
1012 }
1013 }
1014 } else if (cp->lstate == link_up) {
1015 cp->lstate = link_down;
1016 if (link_transition_timeout != 0 &&
1017 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1018 !cp->link_transition_jiffies_valid) {
1019 /*
1020 * force a reset, as a workaround for the
1021 * link-failure problem. May want to move this to a
1022 * point a bit earlier in the sequence. If we had
1023 * generated a reset a short time ago, we'll wait for
1024 * the link timer to check the status until a
1025 * timer expires (link_transistion_jiffies_valid is
1026 * true when the timer is running.) Instead of using
1027 * a system timer, we just do a check whenever the
1028 * link timer is running - this clears the flag after
1029 * a suitable delay.
1030 */
1031 retval = 1;
1032 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1033 cp->link_transition_jiffies = jiffies;
1034 cp->link_transition_jiffies_valid = 1;
1035 } else {
1036 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1037 }
1038 netif_carrier_off(cp->dev);
1039 if (cp->opened && netif_msg_link(cp)) {
1040 printk(KERN_INFO "%s: PCS link down.\n",
1041 cp->dev->name);
1042 }
1043
1044 /* Cassini only: if you force a mode, there can be
1045 * sync problems on link down. to fix that, the following
1046 * things need to be checked:
1047 * 1) read serialink state register
1048 * 2) read pcs status register to verify link down.
1049 * 3) if link down and serial link == 0x03, then you need
1050 * to global reset the chip.
1051 */
1052 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1053 /* should check to see if we're in a forced mode */
1054 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1055 if (stat == 0x03)
1056 return 1;
1057 }
1058 } else if (cp->lstate == link_down) {
1059 if (link_transition_timeout != 0 &&
1060 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1061 !cp->link_transition_jiffies_valid) {
1062 /* force a reset, as a workaround for the
1063 * link-failure problem. May want to move
1064 * this to a point a bit earlier in the
1065 * sequence.
1066 */
1067 retval = 1;
1068 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1069 cp->link_transition_jiffies = jiffies;
1070 cp->link_transition_jiffies_valid = 1;
1071 } else {
1072 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1073 }
1074 }
1075
1076 return retval;
1077 }
1078
1079 static int cas_pcs_interrupt(struct net_device *dev,
1080 struct cas *cp, u32 status)
1081 {
1082 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1083
1084 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1085 return 0;
1086 return cas_pcs_link_check(cp);
1087 }
1088
1089 static int cas_txmac_interrupt(struct net_device *dev,
1090 struct cas *cp, u32 status)
1091 {
1092 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1093
1094 if (!txmac_stat)
1095 return 0;
1096
1097 if (netif_msg_intr(cp))
1098 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1099 cp->dev->name, txmac_stat);
1100
1101 /* Defer timer expiration is quite normal,
1102 * don't even log the event.
1103 */
1104 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1105 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1106 return 0;
1107
1108 spin_lock(&cp->stat_lock[0]);
1109 if (txmac_stat & MAC_TX_UNDERRUN) {
1110 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1111 dev->name);
1112 cp->net_stats[0].tx_fifo_errors++;
1113 }
1114
1115 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1116 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1117 dev->name);
1118 cp->net_stats[0].tx_errors++;
1119 }
1120
1121 /* The rest are all cases of one of the 16-bit TX
1122 * counters expiring.
1123 */
1124 if (txmac_stat & MAC_TX_COLL_NORMAL)
1125 cp->net_stats[0].collisions += 0x10000;
1126
1127 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1128 cp->net_stats[0].tx_aborted_errors += 0x10000;
1129 cp->net_stats[0].collisions += 0x10000;
1130 }
1131
1132 if (txmac_stat & MAC_TX_COLL_LATE) {
1133 cp->net_stats[0].tx_aborted_errors += 0x10000;
1134 cp->net_stats[0].collisions += 0x10000;
1135 }
1136 spin_unlock(&cp->stat_lock[0]);
1137
1138 /* We do not keep track of MAC_TX_COLL_FIRST and
1139 * MAC_TX_PEAK_ATTEMPTS events.
1140 */
1141 return 0;
1142 }
1143
1144 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1145 {
1146 cas_hp_inst_t *inst;
1147 u32 val;
1148 int i;
1149
1150 i = 0;
1151 while ((inst = firmware) && inst->note) {
1152 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1153
1154 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1155 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1156 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1157
1158 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1159 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1160 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1161 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1162 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1163 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1164 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1165 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1166
1167 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1168 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1169 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1170 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1171 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1172 ++firmware;
1173 ++i;
1174 }
1175 }
1176
1177 static void cas_init_rx_dma(struct cas *cp)
1178 {
1179 u64 desc_dma = cp->block_dvma;
1180 u32 val;
1181 int i, size;
1182
1183 /* rx free descriptors */
1184 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1185 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1186 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1187 if ((N_RX_DESC_RINGS > 1) &&
1188 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1189 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1190 writel(val, cp->regs + REG_RX_CFG);
1191
1192 val = (unsigned long) cp->init_rxds[0] -
1193 (unsigned long) cp->init_block;
1194 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1195 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1196 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1197
1198 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1199 /* rx desc 2 is for IPSEC packets. however,
1200 * we don't it that for that purpose.
1201 */
1202 val = (unsigned long) cp->init_rxds[1] -
1203 (unsigned long) cp->init_block;
1204 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1205 writel((desc_dma + val) & 0xffffffff, cp->regs +
1206 REG_PLUS_RX_DB1_LOW);
1207 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1208 REG_PLUS_RX_KICK1);
1209 }
1210
1211 /* rx completion registers */
1212 val = (unsigned long) cp->init_rxcs[0] -
1213 (unsigned long) cp->init_block;
1214 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1215 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1216
1217 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1218 /* rx comp 2-4 */
1219 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1220 val = (unsigned long) cp->init_rxcs[i] -
1221 (unsigned long) cp->init_block;
1222 writel((desc_dma + val) >> 32, cp->regs +
1223 REG_PLUS_RX_CBN_HI(i));
1224 writel((desc_dma + val) & 0xffffffff, cp->regs +
1225 REG_PLUS_RX_CBN_LOW(i));
1226 }
1227 }
1228
1229 /* read selective clear regs to prevent spurious interrupts
1230 * on reset because complete == kick.
1231 * selective clear set up to prevent interrupts on resets
1232 */
1233 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1234 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1235 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1236 for (i = 1; i < N_RX_COMP_RINGS; i++)
1237 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1238
1239 /* 2 is different from 3 and 4 */
1240 if (N_RX_COMP_RINGS > 1)
1241 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1242 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1243
1244 for (i = 2; i < N_RX_COMP_RINGS; i++)
1245 writel(INTR_RX_DONE_ALT,
1246 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1247 }
1248
1249 /* set up pause thresholds */
1250 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1251 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1252 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1253 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1254 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1255
1256 /* zero out dma reassembly buffers */
1257 for (i = 0; i < 64; i++) {
1258 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1259 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1260 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1261 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1262 }
1263
1264 /* make sure address register is 0 for normal operation */
1265 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1266 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1267
1268 /* interrupt mitigation */
1269 #ifdef USE_RX_BLANK
1270 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1271 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1272 writel(val, cp->regs + REG_RX_BLANK);
1273 #else
1274 writel(0x0, cp->regs + REG_RX_BLANK);
1275 #endif
1276
1277 /* interrupt generation as a function of low water marks for
1278 * free desc and completion entries. these are used to trigger
1279 * housekeeping for rx descs. we don't use the free interrupt
1280 * as it's not very useful
1281 */
1282 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1283 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1284 writel(val, cp->regs + REG_RX_AE_THRESH);
1285 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1286 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1287 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1288 }
1289
1290 /* Random early detect registers. useful for congestion avoidance.
1291 * this should be tunable.
1292 */
1293 writel(0x0, cp->regs + REG_RX_RED);
1294
1295 /* receive page sizes. default == 2K (0x800) */
1296 val = 0;
1297 if (cp->page_size == 0x1000)
1298 val = 0x1;
1299 else if (cp->page_size == 0x2000)
1300 val = 0x2;
1301 else if (cp->page_size == 0x4000)
1302 val = 0x3;
1303
1304 /* round mtu + offset. constrain to page size. */
1305 size = cp->dev->mtu + 64;
1306 if (size > cp->page_size)
1307 size = cp->page_size;
1308
1309 if (size <= 0x400)
1310 i = 0x0;
1311 else if (size <= 0x800)
1312 i = 0x1;
1313 else if (size <= 0x1000)
1314 i = 0x2;
1315 else
1316 i = 0x3;
1317
1318 cp->mtu_stride = 1 << (i + 10);
1319 val = CAS_BASE(RX_PAGE_SIZE, val);
1320 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1321 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1322 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1323 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1324
1325 /* enable the header parser if desired */
1326 if (CAS_HP_FIRMWARE == cas_prog_null)
1327 return;
1328
1329 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1330 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1331 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1332 writel(val, cp->regs + REG_HP_CFG);
1333 }
1334
1335 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1336 {
1337 memset(rxc, 0, sizeof(*rxc));
1338 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1339 }
1340
1341 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1342 * flipping is protected by the fact that the chip will not
1343 * hand back the same page index while it's being processed.
1344 */
1345 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1346 {
1347 cas_page_t *page = cp->rx_pages[1][index];
1348 cas_page_t *new;
1349
1350 if (page_count(page->buffer) == 1)
1351 return page;
1352
1353 new = cas_page_dequeue(cp);
1354 if (new) {
1355 spin_lock(&cp->rx_inuse_lock);
1356 list_add(&page->list, &cp->rx_inuse_list);
1357 spin_unlock(&cp->rx_inuse_lock);
1358 }
1359 return new;
1360 }
1361
1362 /* this needs to be changed if we actually use the ENC RX DESC ring */
1363 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1364 const int index)
1365 {
1366 cas_page_t **page0 = cp->rx_pages[0];
1367 cas_page_t **page1 = cp->rx_pages[1];
1368
1369 /* swap if buffer is in use */
1370 if (page_count(page0[index]->buffer) > 1) {
1371 cas_page_t *new = cas_page_spare(cp, index);
1372 if (new) {
1373 page1[index] = page0[index];
1374 page0[index] = new;
1375 }
1376 }
1377 RX_USED_SET(page0[index], 0);
1378 return page0[index];
1379 }
1380
1381 static void cas_clean_rxds(struct cas *cp)
1382 {
1383 /* only clean ring 0 as ring 1 is used for spare buffers */
1384 struct cas_rx_desc *rxd = cp->init_rxds[0];
1385 int i, size;
1386
1387 /* release all rx flows */
1388 for (i = 0; i < N_RX_FLOWS; i++) {
1389 struct sk_buff *skb;
1390 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1391 cas_skb_release(skb);
1392 }
1393 }
1394
1395 /* initialize descriptors */
1396 size = RX_DESC_RINGN_SIZE(0);
1397 for (i = 0; i < size; i++) {
1398 cas_page_t *page = cas_page_swap(cp, 0, i);
1399 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1400 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1401 CAS_BASE(RX_INDEX_RING, 0));
1402 }
1403
1404 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1405 cp->rx_last[0] = 0;
1406 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1407 }
1408
1409 static void cas_clean_rxcs(struct cas *cp)
1410 {
1411 int i, j;
1412
1413 /* take ownership of rx comp descriptors */
1414 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1415 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1416 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1417 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1418 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1419 cas_rxc_init(rxc + j);
1420 }
1421 }
1422 }
1423
1424 #if 0
1425 /* When we get a RX fifo overflow, the RX unit is probably hung
1426 * so we do the following.
1427 *
1428 * If any part of the reset goes wrong, we return 1 and that causes the
1429 * whole chip to be reset.
1430 */
1431 static int cas_rxmac_reset(struct cas *cp)
1432 {
1433 struct net_device *dev = cp->dev;
1434 int limit;
1435 u32 val;
1436
1437 /* First, reset MAC RX. */
1438 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1439 for (limit = 0; limit < STOP_TRIES; limit++) {
1440 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1441 break;
1442 udelay(10);
1443 }
1444 if (limit == STOP_TRIES) {
1445 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1446 "chip.\n", dev->name);
1447 return 1;
1448 }
1449
1450 /* Second, disable RX DMA. */
1451 writel(0, cp->regs + REG_RX_CFG);
1452 for (limit = 0; limit < STOP_TRIES; limit++) {
1453 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1454 break;
1455 udelay(10);
1456 }
1457 if (limit == STOP_TRIES) {
1458 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1459 "chip.\n", dev->name);
1460 return 1;
1461 }
1462
1463 mdelay(5);
1464
1465 /* Execute RX reset command. */
1466 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1467 for (limit = 0; limit < STOP_TRIES; limit++) {
1468 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1469 break;
1470 udelay(10);
1471 }
1472 if (limit == STOP_TRIES) {
1473 printk(KERN_ERR "%s: RX reset command will not execute, "
1474 "resetting whole chip.\n", dev->name);
1475 return 1;
1476 }
1477
1478 /* reset driver rx state */
1479 cas_clean_rxds(cp);
1480 cas_clean_rxcs(cp);
1481
1482 /* Now, reprogram the rest of RX unit. */
1483 cas_init_rx_dma(cp);
1484
1485 /* re-enable */
1486 val = readl(cp->regs + REG_RX_CFG);
1487 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1488 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1489 val = readl(cp->regs + REG_MAC_RX_CFG);
1490 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1491 return 0;
1492 }
1493 #endif
1494
1495 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1496 u32 status)
1497 {
1498 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1499
1500 if (!stat)
1501 return 0;
1502
1503 if (netif_msg_intr(cp))
1504 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1505 cp->dev->name, stat);
1506
1507 /* these are all rollovers */
1508 spin_lock(&cp->stat_lock[0]);
1509 if (stat & MAC_RX_ALIGN_ERR)
1510 cp->net_stats[0].rx_frame_errors += 0x10000;
1511
1512 if (stat & MAC_RX_CRC_ERR)
1513 cp->net_stats[0].rx_crc_errors += 0x10000;
1514
1515 if (stat & MAC_RX_LEN_ERR)
1516 cp->net_stats[0].rx_length_errors += 0x10000;
1517
1518 if (stat & MAC_RX_OVERFLOW) {
1519 cp->net_stats[0].rx_over_errors++;
1520 cp->net_stats[0].rx_fifo_errors++;
1521 }
1522
1523 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1524 * events.
1525 */
1526 spin_unlock(&cp->stat_lock[0]);
1527 return 0;
1528 }
1529
1530 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1531 u32 status)
1532 {
1533 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1534
1535 if (!stat)
1536 return 0;
1537
1538 if (netif_msg_intr(cp))
1539 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1540 cp->dev->name, stat);
1541
1542 /* This interrupt is just for pause frame and pause
1543 * tracking. It is useful for diagnostics and debug
1544 * but probably by default we will mask these events.
1545 */
1546 if (stat & MAC_CTRL_PAUSE_STATE)
1547 cp->pause_entered++;
1548
1549 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1550 cp->pause_last_time_recvd = (stat >> 16);
1551
1552 return 0;
1553 }
1554
1555
1556 /* Must be invoked under cp->lock. */
1557 static inline int cas_mdio_link_not_up(struct cas *cp)
1558 {
1559 u16 val;
1560
1561 switch (cp->lstate) {
1562 case link_force_ret:
1563 if (netif_msg_link(cp))
1564 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1565 " forced mode\n", cp->dev->name);
1566 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1567 cp->timer_ticks = 5;
1568 cp->lstate = link_force_ok;
1569 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1570 break;
1571
1572 case link_aneg:
1573 val = cas_phy_read(cp, MII_BMCR);
1574
1575 /* Try forced modes. we try things in the following order:
1576 * 1000 full -> 100 full/half -> 10 half
1577 */
1578 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1579 val |= BMCR_FULLDPLX;
1580 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1581 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1582 cas_phy_write(cp, MII_BMCR, val);
1583 cp->timer_ticks = 5;
1584 cp->lstate = link_force_try;
1585 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1586 break;
1587
1588 case link_force_try:
1589 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1590 val = cas_phy_read(cp, MII_BMCR);
1591 cp->timer_ticks = 5;
1592 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1593 val &= ~CAS_BMCR_SPEED1000;
1594 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1595 cas_phy_write(cp, MII_BMCR, val);
1596 break;
1597 }
1598
1599 if (val & BMCR_SPEED100) {
1600 if (val & BMCR_FULLDPLX) /* fd failed */
1601 val &= ~BMCR_FULLDPLX;
1602 else { /* 100Mbps failed */
1603 val &= ~BMCR_SPEED100;
1604 }
1605 cas_phy_write(cp, MII_BMCR, val);
1606 break;
1607 }
1608 default:
1609 break;
1610 }
1611 return 0;
1612 }
1613
1614
1615 /* must be invoked with cp->lock held */
1616 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1617 {
1618 int restart;
1619
1620 if (bmsr & BMSR_LSTATUS) {
1621 /* Ok, here we got a link. If we had it due to a forced
1622 * fallback, and we were configured for autoneg, we
1623 * retry a short autoneg pass. If you know your hub is
1624 * broken, use ethtool ;)
1625 */
1626 if ((cp->lstate == link_force_try) &&
1627 (cp->link_cntl & BMCR_ANENABLE)) {
1628 cp->lstate = link_force_ret;
1629 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1630 cas_mif_poll(cp, 0);
1631 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1632 cp->timer_ticks = 5;
1633 if (cp->opened && netif_msg_link(cp))
1634 printk(KERN_INFO "%s: Got link after fallback, retrying"
1635 " autoneg once...\n", cp->dev->name);
1636 cas_phy_write(cp, MII_BMCR,
1637 cp->link_fcntl | BMCR_ANENABLE |
1638 BMCR_ANRESTART);
1639 cas_mif_poll(cp, 1);
1640
1641 } else if (cp->lstate != link_up) {
1642 cp->lstate = link_up;
1643 cp->link_transition = LINK_TRANSITION_LINK_UP;
1644
1645 if (cp->opened) {
1646 cas_set_link_modes(cp);
1647 netif_carrier_on(cp->dev);
1648 }
1649 }
1650 return 0;
1651 }
1652
1653 /* link not up. if the link was previously up, we restart the
1654 * whole process
1655 */
1656 restart = 0;
1657 if (cp->lstate == link_up) {
1658 cp->lstate = link_down;
1659 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1660
1661 netif_carrier_off(cp->dev);
1662 if (cp->opened && netif_msg_link(cp))
1663 printk(KERN_INFO "%s: Link down\n",
1664 cp->dev->name);
1665 restart = 1;
1666
1667 } else if (++cp->timer_ticks > 10)
1668 cas_mdio_link_not_up(cp);
1669
1670 return restart;
1671 }
1672
1673 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1674 u32 status)
1675 {
1676 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1677 u16 bmsr;
1678
1679 /* check for a link change */
1680 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1681 return 0;
1682
1683 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1684 return cas_mii_link_check(cp, bmsr);
1685 }
1686
1687 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1688 u32 status)
1689 {
1690 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1691
1692 if (!stat)
1693 return 0;
1694
1695 printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1696 readl(cp->regs + REG_BIM_DIAG));
1697
1698 /* cassini+ has this reserved */
1699 if ((stat & PCI_ERR_BADACK) &&
1700 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1701 printk("<No ACK64# during ABS64 cycle> ");
1702
1703 if (stat & PCI_ERR_DTRTO)
1704 printk("<Delayed transaction timeout> ");
1705 if (stat & PCI_ERR_OTHER)
1706 printk("<other> ");
1707 if (stat & PCI_ERR_BIM_DMA_WRITE)
1708 printk("<BIM DMA 0 write req> ");
1709 if (stat & PCI_ERR_BIM_DMA_READ)
1710 printk("<BIM DMA 0 read req> ");
1711 printk("\n");
1712
1713 if (stat & PCI_ERR_OTHER) {
1714 u16 cfg;
1715
1716 /* Interrogate PCI config space for the
1717 * true cause.
1718 */
1719 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1720 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1721 dev->name, cfg);
1722 if (cfg & PCI_STATUS_PARITY)
1723 printk(KERN_ERR "%s: PCI parity error detected.\n",
1724 dev->name);
1725 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1726 printk(KERN_ERR "%s: PCI target abort.\n",
1727 dev->name);
1728 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1729 printk(KERN_ERR "%s: PCI master acks target abort.\n",
1730 dev->name);
1731 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1732 printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1733 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1734 printk(KERN_ERR "%s: PCI system error SERR#.\n",
1735 dev->name);
1736 if (cfg & PCI_STATUS_DETECTED_PARITY)
1737 printk(KERN_ERR "%s: PCI parity error.\n",
1738 dev->name);
1739
1740 /* Write the error bits back to clear them. */
1741 cfg &= (PCI_STATUS_PARITY |
1742 PCI_STATUS_SIG_TARGET_ABORT |
1743 PCI_STATUS_REC_TARGET_ABORT |
1744 PCI_STATUS_REC_MASTER_ABORT |
1745 PCI_STATUS_SIG_SYSTEM_ERROR |
1746 PCI_STATUS_DETECTED_PARITY);
1747 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1748 }
1749
1750 /* For all PCI errors, we should reset the chip. */
1751 return 1;
1752 }
1753
1754 /* All non-normal interrupt conditions get serviced here.
1755 * Returns non-zero if we should just exit the interrupt
1756 * handler right now (ie. if we reset the card which invalidates
1757 * all of the other original irq status bits).
1758 */
1759 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1760 u32 status)
1761 {
1762 if (status & INTR_RX_TAG_ERROR) {
1763 /* corrupt RX tag framing */
1764 if (netif_msg_rx_err(cp))
1765 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1766 cp->dev->name);
1767 spin_lock(&cp->stat_lock[0]);
1768 cp->net_stats[0].rx_errors++;
1769 spin_unlock(&cp->stat_lock[0]);
1770 goto do_reset;
1771 }
1772
1773 if (status & INTR_RX_LEN_MISMATCH) {
1774 /* length mismatch. */
1775 if (netif_msg_rx_err(cp))
1776 printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1777 cp->dev->name);
1778 spin_lock(&cp->stat_lock[0]);
1779 cp->net_stats[0].rx_errors++;
1780 spin_unlock(&cp->stat_lock[0]);
1781 goto do_reset;
1782 }
1783
1784 if (status & INTR_PCS_STATUS) {
1785 if (cas_pcs_interrupt(dev, cp, status))
1786 goto do_reset;
1787 }
1788
1789 if (status & INTR_TX_MAC_STATUS) {
1790 if (cas_txmac_interrupt(dev, cp, status))
1791 goto do_reset;
1792 }
1793
1794 if (status & INTR_RX_MAC_STATUS) {
1795 if (cas_rxmac_interrupt(dev, cp, status))
1796 goto do_reset;
1797 }
1798
1799 if (status & INTR_MAC_CTRL_STATUS) {
1800 if (cas_mac_interrupt(dev, cp, status))
1801 goto do_reset;
1802 }
1803
1804 if (status & INTR_MIF_STATUS) {
1805 if (cas_mif_interrupt(dev, cp, status))
1806 goto do_reset;
1807 }
1808
1809 if (status & INTR_PCI_ERROR_STATUS) {
1810 if (cas_pci_interrupt(dev, cp, status))
1811 goto do_reset;
1812 }
1813 return 0;
1814
1815 do_reset:
1816 #if 1
1817 atomic_inc(&cp->reset_task_pending);
1818 atomic_inc(&cp->reset_task_pending_all);
1819 printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1820 dev->name, status);
1821 schedule_work(&cp->reset_task);
1822 #else
1823 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1824 printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1825 schedule_work(&cp->reset_task);
1826 #endif
1827 return 1;
1828 }
1829
1830 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1831 * determining whether to do a netif_stop/wakeup
1832 */
1833 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1834 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1835 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1836 const int len)
1837 {
1838 unsigned long off = addr + len;
1839
1840 if (CAS_TABORT(cp) == 1)
1841 return 0;
1842 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1843 return 0;
1844 return TX_TARGET_ABORT_LEN;
1845 }
1846
1847 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1848 {
1849 struct cas_tx_desc *txds;
1850 struct sk_buff **skbs;
1851 struct net_device *dev = cp->dev;
1852 int entry, count;
1853
1854 spin_lock(&cp->tx_lock[ring]);
1855 txds = cp->init_txds[ring];
1856 skbs = cp->tx_skbs[ring];
1857 entry = cp->tx_old[ring];
1858
1859 count = TX_BUFF_COUNT(ring, entry, limit);
1860 while (entry != limit) {
1861 struct sk_buff *skb = skbs[entry];
1862 dma_addr_t daddr;
1863 u32 dlen;
1864 int frag;
1865
1866 if (!skb) {
1867 /* this should never occur */
1868 entry = TX_DESC_NEXT(ring, entry);
1869 continue;
1870 }
1871
1872 /* however, we might get only a partial skb release. */
1873 count -= skb_shinfo(skb)->nr_frags +
1874 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1875 if (count < 0)
1876 break;
1877
1878 if (netif_msg_tx_done(cp))
1879 printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1880 cp->dev->name, ring, entry);
1881
1882 skbs[entry] = NULL;
1883 cp->tx_tiny_use[ring][entry].nbufs = 0;
1884
1885 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1886 struct cas_tx_desc *txd = txds + entry;
1887
1888 daddr = le64_to_cpu(txd->buffer);
1889 dlen = CAS_VAL(TX_DESC_BUFLEN,
1890 le64_to_cpu(txd->control));
1891 pci_unmap_page(cp->pdev, daddr, dlen,
1892 PCI_DMA_TODEVICE);
1893 entry = TX_DESC_NEXT(ring, entry);
1894
1895 /* tiny buffer may follow */
1896 if (cp->tx_tiny_use[ring][entry].used) {
1897 cp->tx_tiny_use[ring][entry].used = 0;
1898 entry = TX_DESC_NEXT(ring, entry);
1899 }
1900 }
1901
1902 spin_lock(&cp->stat_lock[ring]);
1903 cp->net_stats[ring].tx_packets++;
1904 cp->net_stats[ring].tx_bytes += skb->len;
1905 spin_unlock(&cp->stat_lock[ring]);
1906 dev_kfree_skb_irq(skb);
1907 }
1908 cp->tx_old[ring] = entry;
1909
1910 /* this is wrong for multiple tx rings. the net device needs
1911 * multiple queues for this to do the right thing. we wait
1912 * for 2*packets to be available when using tiny buffers
1913 */
1914 if (netif_queue_stopped(dev) &&
1915 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1916 netif_wake_queue(dev);
1917 spin_unlock(&cp->tx_lock[ring]);
1918 }
1919
1920 static void cas_tx(struct net_device *dev, struct cas *cp,
1921 u32 status)
1922 {
1923 int limit, ring;
1924 #ifdef USE_TX_COMPWB
1925 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1926 #endif
1927 if (netif_msg_intr(cp))
1928 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %lx\n",
1929 cp->dev->name, status, compwb);
1930 /* process all the rings */
1931 for (ring = 0; ring < N_TX_RINGS; ring++) {
1932 #ifdef USE_TX_COMPWB
1933 /* use the completion writeback registers */
1934 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1935 CAS_VAL(TX_COMPWB_LSB, compwb);
1936 compwb = TX_COMPWB_NEXT(compwb);
1937 #else
1938 limit = readl(cp->regs + REG_TX_COMPN(ring));
1939 #endif
1940 if (cp->tx_old[ring] != limit)
1941 cas_tx_ringN(cp, ring, limit);
1942 }
1943 }
1944
1945
1946 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1947 int entry, const u64 *words,
1948 struct sk_buff **skbref)
1949 {
1950 int dlen, hlen, len, i, alloclen;
1951 int off, swivel = RX_SWIVEL_OFF_VAL;
1952 struct cas_page *page;
1953 struct sk_buff *skb;
1954 void *addr, *crcaddr;
1955 char *p;
1956
1957 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1958 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1959 len = hlen + dlen;
1960
1961 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1962 alloclen = len;
1963 else
1964 alloclen = max(hlen, RX_COPY_MIN);
1965
1966 skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1967 if (skb == NULL)
1968 return -1;
1969
1970 *skbref = skb;
1971 skb->dev = cp->dev;
1972 skb_reserve(skb, swivel);
1973
1974 p = skb->data;
1975 addr = crcaddr = NULL;
1976 if (hlen) { /* always copy header pages */
1977 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1978 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1979 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1980 swivel;
1981
1982 i = hlen;
1983 if (!dlen) /* attach FCS */
1984 i += cp->crc_size;
1985 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1986 PCI_DMA_FROMDEVICE);
1987 addr = cas_page_map(page->buffer);
1988 memcpy(p, addr + off, i);
1989 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1990 PCI_DMA_FROMDEVICE);
1991 cas_page_unmap(addr);
1992 RX_USED_ADD(page, 0x100);
1993 p += hlen;
1994 swivel = 0;
1995 }
1996
1997
1998 if (alloclen < (hlen + dlen)) {
1999 skb_frag_t *frag = skb_shinfo(skb)->frags;
2000
2001 /* normal or jumbo packets. we use frags */
2002 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2003 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2004 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2005
2006 hlen = min(cp->page_size - off, dlen);
2007 if (hlen < 0) {
2008 if (netif_msg_rx_err(cp)) {
2009 printk(KERN_DEBUG "%s: rx page overflow: "
2010 "%d\n", cp->dev->name, hlen);
2011 }
2012 dev_kfree_skb_irq(skb);
2013 return -1;
2014 }
2015 i = hlen;
2016 if (i == dlen) /* attach FCS */
2017 i += cp->crc_size;
2018 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2019 PCI_DMA_FROMDEVICE);
2020
2021 /* make sure we always copy a header */
2022 swivel = 0;
2023 if (p == (char *) skb->data) { /* not split */
2024 addr = cas_page_map(page->buffer);
2025 memcpy(p, addr + off, RX_COPY_MIN);
2026 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2027 PCI_DMA_FROMDEVICE);
2028 cas_page_unmap(addr);
2029 off += RX_COPY_MIN;
2030 swivel = RX_COPY_MIN;
2031 RX_USED_ADD(page, cp->mtu_stride);
2032 } else {
2033 RX_USED_ADD(page, hlen);
2034 }
2035 skb_put(skb, alloclen);
2036
2037 skb_shinfo(skb)->nr_frags++;
2038 skb->data_len += hlen - swivel;
2039 skb->len += hlen - swivel;
2040
2041 get_page(page->buffer);
2042 frag->page = page->buffer;
2043 frag->page_offset = off;
2044 frag->size = hlen - swivel;
2045
2046 /* any more data? */
2047 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2048 hlen = dlen;
2049 off = 0;
2050
2051 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2052 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2053 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2054 hlen + cp->crc_size,
2055 PCI_DMA_FROMDEVICE);
2056 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2057 hlen + cp->crc_size,
2058 PCI_DMA_FROMDEVICE);
2059
2060 skb_shinfo(skb)->nr_frags++;
2061 skb->data_len += hlen;
2062 skb->len += hlen;
2063 frag++;
2064
2065 get_page(page->buffer);
2066 frag->page = page->buffer;
2067 frag->page_offset = 0;
2068 frag->size = hlen;
2069 RX_USED_ADD(page, hlen + cp->crc_size);
2070 }
2071
2072 if (cp->crc_size) {
2073 addr = cas_page_map(page->buffer);
2074 crcaddr = addr + off + hlen;
2075 }
2076
2077 } else {
2078 /* copying packet */
2079 if (!dlen)
2080 goto end_copy_pkt;
2081
2082 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2083 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2084 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2085 hlen = min(cp->page_size - off, dlen);
2086 if (hlen < 0) {
2087 if (netif_msg_rx_err(cp)) {
2088 printk(KERN_DEBUG "%s: rx page overflow: "
2089 "%d\n", cp->dev->name, hlen);
2090 }
2091 dev_kfree_skb_irq(skb);
2092 return -1;
2093 }
2094 i = hlen;
2095 if (i == dlen) /* attach FCS */
2096 i += cp->crc_size;
2097 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2098 PCI_DMA_FROMDEVICE);
2099 addr = cas_page_map(page->buffer);
2100 memcpy(p, addr + off, i);
2101 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2102 PCI_DMA_FROMDEVICE);
2103 cas_page_unmap(addr);
2104 if (p == (char *) skb->data) /* not split */
2105 RX_USED_ADD(page, cp->mtu_stride);
2106 else
2107 RX_USED_ADD(page, i);
2108
2109 /* any more data? */
2110 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2111 p += hlen;
2112 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2113 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2114 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2115 dlen + cp->crc_size,
2116 PCI_DMA_FROMDEVICE);
2117 addr = cas_page_map(page->buffer);
2118 memcpy(p, addr, dlen + cp->crc_size);
2119 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2120 dlen + cp->crc_size,
2121 PCI_DMA_FROMDEVICE);
2122 cas_page_unmap(addr);
2123 RX_USED_ADD(page, dlen + cp->crc_size);
2124 }
2125 end_copy_pkt:
2126 if (cp->crc_size) {
2127 addr = NULL;
2128 crcaddr = skb->data + alloclen;
2129 }
2130 skb_put(skb, alloclen);
2131 }
2132
2133 i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
2134 if (cp->crc_size) {
2135 /* checksum includes FCS. strip it out. */
2136 i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
2137 if (addr)
2138 cas_page_unmap(addr);
2139 }
2140 skb->csum = ntohs(i ^ 0xffff);
2141 skb->ip_summed = CHECKSUM_HW;
2142 skb->protocol = eth_type_trans(skb, cp->dev);
2143 return len;
2144 }
2145
2146
2147 /* we can handle up to 64 rx flows at a time. we do the same thing
2148 * as nonreassm except that we batch up the buffers.
2149 * NOTE: we currently just treat each flow as a bunch of packets that
2150 * we pass up. a better way would be to coalesce the packets
2151 * into a jumbo packet. to do that, we need to do the following:
2152 * 1) the first packet will have a clean split between header and
2153 * data. save both.
2154 * 2) each time the next flow packet comes in, extend the
2155 * data length and merge the checksums.
2156 * 3) on flow release, fix up the header.
2157 * 4) make sure the higher layer doesn't care.
2158 * because packets get coalesced, we shouldn't run into fragment count
2159 * issues.
2160 */
2161 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2162 struct sk_buff *skb)
2163 {
2164 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2165 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2166
2167 /* this is protected at a higher layer, so no need to
2168 * do any additional locking here. stick the buffer
2169 * at the end.
2170 */
2171 __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2172 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2173 while ((skb = __skb_dequeue(flow))) {
2174 cas_skb_release(skb);
2175 }
2176 }
2177 }
2178
2179 /* put rx descriptor back on ring. if a buffer is in use by a higher
2180 * layer, this will need to put in a replacement.
2181 */
2182 static void cas_post_page(struct cas *cp, const int ring, const int index)
2183 {
2184 cas_page_t *new;
2185 int entry;
2186
2187 entry = cp->rx_old[ring];
2188
2189 new = cas_page_swap(cp, ring, index);
2190 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2191 cp->init_rxds[ring][entry].index =
2192 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2193 CAS_BASE(RX_INDEX_RING, ring));
2194
2195 entry = RX_DESC_ENTRY(ring, entry + 1);
2196 cp->rx_old[ring] = entry;
2197
2198 if (entry % 4)
2199 return;
2200
2201 if (ring == 0)
2202 writel(entry, cp->regs + REG_RX_KICK);
2203 else if ((N_RX_DESC_RINGS > 1) &&
2204 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2205 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2206 }
2207
2208
2209 /* only when things are bad */
2210 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2211 {
2212 unsigned int entry, last, count, released;
2213 int cluster;
2214 cas_page_t **page = cp->rx_pages[ring];
2215
2216 entry = cp->rx_old[ring];
2217
2218 if (netif_msg_intr(cp))
2219 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2220 cp->dev->name, ring, entry);
2221
2222 cluster = -1;
2223 count = entry & 0x3;
2224 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2225 released = 0;
2226 while (entry != last) {
2227 /* make a new buffer if it's still in use */
2228 if (page_count(page[entry]->buffer) > 1) {
2229 cas_page_t *new = cas_page_dequeue(cp);
2230 if (!new) {
2231 /* let the timer know that we need to
2232 * do this again
2233 */
2234 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2235 if (!timer_pending(&cp->link_timer))
2236 mod_timer(&cp->link_timer, jiffies +
2237 CAS_LINK_FAST_TIMEOUT);
2238 cp->rx_old[ring] = entry;
2239 cp->rx_last[ring] = num ? num - released : 0;
2240 return -ENOMEM;
2241 }
2242 spin_lock(&cp->rx_inuse_lock);
2243 list_add(&page[entry]->list, &cp->rx_inuse_list);
2244 spin_unlock(&cp->rx_inuse_lock);
2245 cp->init_rxds[ring][entry].buffer =
2246 cpu_to_le64(new->dma_addr);
2247 page[entry] = new;
2248
2249 }
2250
2251 if (++count == 4) {
2252 cluster = entry;
2253 count = 0;
2254 }
2255 released++;
2256 entry = RX_DESC_ENTRY(ring, entry + 1);
2257 }
2258 cp->rx_old[ring] = entry;
2259
2260 if (cluster < 0)
2261 return 0;
2262
2263 if (ring == 0)
2264 writel(cluster, cp->regs + REG_RX_KICK);
2265 else if ((N_RX_DESC_RINGS > 1) &&
2266 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2267 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2268 return 0;
2269 }
2270
2271
2272 /* process a completion ring. packets are set up in three basic ways:
2273 * small packets: should be copied header + data in single buffer.
2274 * large packets: header and data in a single buffer.
2275 * split packets: header in a separate buffer from data.
2276 * data may be in multiple pages. data may be > 256
2277 * bytes but in a single page.
2278 *
2279 * NOTE: RX page posting is done in this routine as well. while there's
2280 * the capability of using multiple RX completion rings, it isn't
2281 * really worthwhile due to the fact that the page posting will
2282 * force serialization on the single descriptor ring.
2283 */
2284 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2285 {
2286 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2287 int entry, drops;
2288 int npackets = 0;
2289
2290 if (netif_msg_intr(cp))
2291 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2292 cp->dev->name, ring,
2293 readl(cp->regs + REG_RX_COMP_HEAD),
2294 cp->rx_new[ring]);
2295
2296 entry = cp->rx_new[ring];
2297 drops = 0;
2298 while (1) {
2299 struct cas_rx_comp *rxc = rxcs + entry;
2300 struct sk_buff *skb;
2301 int type, len;
2302 u64 words[4];
2303 int i, dring;
2304
2305 words[0] = le64_to_cpu(rxc->word1);
2306 words[1] = le64_to_cpu(rxc->word2);
2307 words[2] = le64_to_cpu(rxc->word3);
2308 words[3] = le64_to_cpu(rxc->word4);
2309
2310 /* don't touch if still owned by hw */
2311 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2312 if (type == 0)
2313 break;
2314
2315 /* hw hasn't cleared the zero bit yet */
2316 if (words[3] & RX_COMP4_ZERO) {
2317 break;
2318 }
2319
2320 /* get info on the packet */
2321 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2322 spin_lock(&cp->stat_lock[ring]);
2323 cp->net_stats[ring].rx_errors++;
2324 if (words[3] & RX_COMP4_LEN_MISMATCH)
2325 cp->net_stats[ring].rx_length_errors++;
2326 if (words[3] & RX_COMP4_BAD)
2327 cp->net_stats[ring].rx_crc_errors++;
2328 spin_unlock(&cp->stat_lock[ring]);
2329
2330 /* We'll just return it to Cassini. */
2331 drop_it:
2332 spin_lock(&cp->stat_lock[ring]);
2333 ++cp->net_stats[ring].rx_dropped;
2334 spin_unlock(&cp->stat_lock[ring]);
2335 goto next;
2336 }
2337
2338 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2339 if (len < 0) {
2340 ++drops;
2341 goto drop_it;
2342 }
2343
2344 /* see if it's a flow re-assembly or not. the driver
2345 * itself handles release back up.
2346 */
2347 if (RX_DONT_BATCH || (type == 0x2)) {
2348 /* non-reassm: these always get released */
2349 cas_skb_release(skb);
2350 } else {
2351 cas_rx_flow_pkt(cp, words, skb);
2352 }
2353
2354 spin_lock(&cp->stat_lock[ring]);
2355 cp->net_stats[ring].rx_packets++;
2356 cp->net_stats[ring].rx_bytes += len;
2357 spin_unlock(&cp->stat_lock[ring]);
2358 cp->dev->last_rx = jiffies;
2359
2360 next:
2361 npackets++;
2362
2363 /* should it be released? */
2364 if (words[0] & RX_COMP1_RELEASE_HDR) {
2365 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2366 dring = CAS_VAL(RX_INDEX_RING, i);
2367 i = CAS_VAL(RX_INDEX_NUM, i);
2368 cas_post_page(cp, dring, i);
2369 }
2370
2371 if (words[0] & RX_COMP1_RELEASE_DATA) {
2372 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2373 dring = CAS_VAL(RX_INDEX_RING, i);
2374 i = CAS_VAL(RX_INDEX_NUM, i);
2375 cas_post_page(cp, dring, i);
2376 }
2377
2378 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2379 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2380 dring = CAS_VAL(RX_INDEX_RING, i);
2381 i = CAS_VAL(RX_INDEX_NUM, i);
2382 cas_post_page(cp, dring, i);
2383 }
2384
2385 /* skip to the next entry */
2386 entry = RX_COMP_ENTRY(ring, entry + 1 +
2387 CAS_VAL(RX_COMP1_SKIP, words[0]));
2388 #ifdef USE_NAPI
2389 if (budget && (npackets >= budget))
2390 break;
2391 #endif
2392 }
2393 cp->rx_new[ring] = entry;
2394
2395 if (drops)
2396 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2397 cp->dev->name);
2398 return npackets;
2399 }
2400
2401
2402 /* put completion entries back on the ring */
2403 static void cas_post_rxcs_ringN(struct net_device *dev,
2404 struct cas *cp, int ring)
2405 {
2406 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2407 int last, entry;
2408
2409 last = cp->rx_cur[ring];
2410 entry = cp->rx_new[ring];
2411 if (netif_msg_intr(cp))
2412 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2413 dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2414 entry);
2415
2416 /* zero and re-mark descriptors */
2417 while (last != entry) {
2418 cas_rxc_init(rxc + last);
2419 last = RX_COMP_ENTRY(ring, last + 1);
2420 }
2421 cp->rx_cur[ring] = last;
2422
2423 if (ring == 0)
2424 writel(last, cp->regs + REG_RX_COMP_TAIL);
2425 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2426 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2427 }
2428
2429
2430
2431 /* cassini can use all four PCI interrupts for the completion ring.
2432 * rings 3 and 4 are identical
2433 */
2434 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2435 static inline void cas_handle_irqN(struct net_device *dev,
2436 struct cas *cp, const u32 status,
2437 const int ring)
2438 {
2439 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2440 cas_post_rxcs_ringN(dev, cp, ring);
2441 }
2442
2443 static irqreturn_t cas_interruptN(int irq, void *dev_id, struct pt_regs *regs)
2444 {
2445 struct net_device *dev = dev_id;
2446 struct cas *cp = netdev_priv(dev);
2447 unsigned long flags;
2448 int ring;
2449 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2450
2451 /* check for shared irq */
2452 if (status == 0)
2453 return IRQ_NONE;
2454
2455 ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2456 spin_lock_irqsave(&cp->lock, flags);
2457 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2458 #ifdef USE_NAPI
2459 cas_mask_intr(cp);
2460 netif_rx_schedule(dev);
2461 #else
2462 cas_rx_ringN(cp, ring, 0);
2463 #endif
2464 status &= ~INTR_RX_DONE_ALT;
2465 }
2466
2467 if (status)
2468 cas_handle_irqN(dev, cp, status, ring);
2469 spin_unlock_irqrestore(&cp->lock, flags);
2470 return IRQ_HANDLED;
2471 }
2472 #endif
2473
2474 #ifdef USE_PCI_INTB
2475 /* everything but rx packets */
2476 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2477 {
2478 if (status & INTR_RX_BUF_UNAVAIL_1) {
2479 /* Frame arrived, no free RX buffers available.
2480 * NOTE: we can get this on a link transition. */
2481 cas_post_rxds_ringN(cp, 1, 0);
2482 spin_lock(&cp->stat_lock[1]);
2483 cp->net_stats[1].rx_dropped++;
2484 spin_unlock(&cp->stat_lock[1]);
2485 }
2486
2487 if (status & INTR_RX_BUF_AE_1)
2488 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2489 RX_AE_FREEN_VAL(1));
2490
2491 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2492 cas_post_rxcs_ringN(cp, 1);
2493 }
2494
2495 /* ring 2 handles a few more events than 3 and 4 */
2496 static irqreturn_t cas_interrupt1(int irq, void *dev_id, struct pt_regs *regs)
2497 {
2498 struct net_device *dev = dev_id;
2499 struct cas *cp = netdev_priv(dev);
2500 unsigned long flags;
2501 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2502
2503 /* check for shared interrupt */
2504 if (status == 0)
2505 return IRQ_NONE;
2506
2507 spin_lock_irqsave(&cp->lock, flags);
2508 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2509 #ifdef USE_NAPI
2510 cas_mask_intr(cp);
2511 netif_rx_schedule(dev);
2512 #else
2513 cas_rx_ringN(cp, 1, 0);
2514 #endif
2515 status &= ~INTR_RX_DONE_ALT;
2516 }
2517 if (status)
2518 cas_handle_irq1(cp, status);
2519 spin_unlock_irqrestore(&cp->lock, flags);
2520 return IRQ_HANDLED;
2521 }
2522 #endif
2523
2524 static inline void cas_handle_irq(struct net_device *dev,
2525 struct cas *cp, const u32 status)
2526 {
2527 /* housekeeping interrupts */
2528 if (status & INTR_ERROR_MASK)
2529 cas_abnormal_irq(dev, cp, status);
2530
2531 if (status & INTR_RX_BUF_UNAVAIL) {
2532 /* Frame arrived, no free RX buffers available.
2533 * NOTE: we can get this on a link transition.
2534 */
2535 cas_post_rxds_ringN(cp, 0, 0);
2536 spin_lock(&cp->stat_lock[0]);
2537 cp->net_stats[0].rx_dropped++;
2538 spin_unlock(&cp->stat_lock[0]);
2539 } else if (status & INTR_RX_BUF_AE) {
2540 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2541 RX_AE_FREEN_VAL(0));
2542 }
2543
2544 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2545 cas_post_rxcs_ringN(dev, cp, 0);
2546 }
2547
2548 static irqreturn_t cas_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2549 {
2550 struct net_device *dev = dev_id;
2551 struct cas *cp = netdev_priv(dev);
2552 unsigned long flags;
2553 u32 status = readl(cp->regs + REG_INTR_STATUS);
2554
2555 if (status == 0)
2556 return IRQ_NONE;
2557
2558 spin_lock_irqsave(&cp->lock, flags);
2559 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2560 cas_tx(dev, cp, status);
2561 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2562 }
2563
2564 if (status & INTR_RX_DONE) {
2565 #ifdef USE_NAPI
2566 cas_mask_intr(cp);
2567 netif_rx_schedule(dev);
2568 #else
2569 cas_rx_ringN(cp, 0, 0);
2570 #endif
2571 status &= ~INTR_RX_DONE;
2572 }
2573
2574 if (status)
2575 cas_handle_irq(dev, cp, status);
2576 spin_unlock_irqrestore(&cp->lock, flags);
2577 return IRQ_HANDLED;
2578 }
2579
2580
2581 #ifdef USE_NAPI
2582 static int cas_poll(struct net_device *dev, int *budget)
2583 {
2584 struct cas *cp = netdev_priv(dev);
2585 int i, enable_intr, todo, credits;
2586 u32 status = readl(cp->regs + REG_INTR_STATUS);
2587 unsigned long flags;
2588
2589 spin_lock_irqsave(&cp->lock, flags);
2590 cas_tx(dev, cp, status);
2591 spin_unlock_irqrestore(&cp->lock, flags);
2592
2593 /* NAPI rx packets. we spread the credits across all of the
2594 * rxc rings
2595 */
2596 todo = min(*budget, dev->quota);
2597
2598 /* to make sure we're fair with the work we loop through each
2599 * ring N_RX_COMP_RING times with a request of
2600 * todo / N_RX_COMP_RINGS
2601 */
2602 enable_intr = 1;
2603 credits = 0;
2604 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2605 int j;
2606 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2607 credits += cas_rx_ringN(cp, j, todo / N_RX_COMP_RINGS);
2608 if (credits >= todo) {
2609 enable_intr = 0;
2610 goto rx_comp;
2611 }
2612 }
2613 }
2614
2615 rx_comp:
2616 *budget -= credits;
2617 dev->quota -= credits;
2618
2619 /* final rx completion */
2620 spin_lock_irqsave(&cp->lock, flags);
2621 if (status)
2622 cas_handle_irq(dev, cp, status);
2623
2624 #ifdef USE_PCI_INTB
2625 if (N_RX_COMP_RINGS > 1) {
2626 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2627 if (status)
2628 cas_handle_irq1(dev, cp, status);
2629 }
2630 #endif
2631
2632 #ifdef USE_PCI_INTC
2633 if (N_RX_COMP_RINGS > 2) {
2634 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2635 if (status)
2636 cas_handle_irqN(dev, cp, status, 2);
2637 }
2638 #endif
2639
2640 #ifdef USE_PCI_INTD
2641 if (N_RX_COMP_RINGS > 3) {
2642 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2643 if (status)
2644 cas_handle_irqN(dev, cp, status, 3);
2645 }
2646 #endif
2647 spin_unlock_irqrestore(&cp->lock, flags);
2648 if (enable_intr) {
2649 netif_rx_complete(dev);
2650 cas_unmask_intr(cp);
2651 return 0;
2652 }
2653 return 1;
2654 }
2655 #endif
2656
2657 #ifdef CONFIG_NET_POLL_CONTROLLER
2658 static void cas_netpoll(struct net_device *dev)
2659 {
2660 struct cas *cp = netdev_priv(dev);
2661
2662 cas_disable_irq(cp, 0);
2663 cas_interrupt(cp->pdev->irq, dev, NULL);
2664 cas_enable_irq(cp, 0);
2665
2666 #ifdef USE_PCI_INTB
2667 if (N_RX_COMP_RINGS > 1) {
2668 /* cas_interrupt1(); */
2669 }
2670 #endif
2671 #ifdef USE_PCI_INTC
2672 if (N_RX_COMP_RINGS > 2) {
2673 /* cas_interruptN(); */
2674 }
2675 #endif
2676 #ifdef USE_PCI_INTD
2677 if (N_RX_COMP_RINGS > 3) {
2678 /* cas_interruptN(); */
2679 }
2680 #endif
2681 }
2682 #endif
2683
2684 static void cas_tx_timeout(struct net_device *dev)
2685 {
2686 struct cas *cp = netdev_priv(dev);
2687
2688 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2689 if (!cp->hw_running) {
2690 printk("%s: hrm.. hw not running!\n", dev->name);
2691 return;
2692 }
2693
2694 printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2695 dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2696
2697 printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2698 dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2699
2700 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2701 "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2702 dev->name,
2703 readl(cp->regs + REG_TX_CFG),
2704 readl(cp->regs + REG_MAC_TX_STATUS),
2705 readl(cp->regs + REG_MAC_TX_CFG),
2706 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2707 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2708 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2709 readl(cp->regs + REG_TX_SM_1),
2710 readl(cp->regs + REG_TX_SM_2));
2711
2712 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2713 dev->name,
2714 readl(cp->regs + REG_RX_CFG),
2715 readl(cp->regs + REG_MAC_RX_STATUS),
2716 readl(cp->regs + REG_MAC_RX_CFG));
2717
2718 printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2719 dev->name,
2720 readl(cp->regs + REG_HP_STATE_MACHINE),
2721 readl(cp->regs + REG_HP_STATUS0),
2722 readl(cp->regs + REG_HP_STATUS1),
2723 readl(cp->regs + REG_HP_STATUS2));
2724
2725 #if 1
2726 atomic_inc(&cp->reset_task_pending);
2727 atomic_inc(&cp->reset_task_pending_all);
2728 schedule_work(&cp->reset_task);
2729 #else
2730 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2731 schedule_work(&cp->reset_task);
2732 #endif
2733 }
2734
2735 static inline int cas_intme(int ring, int entry)
2736 {
2737 /* Algorithm: IRQ every 1/2 of descriptors. */
2738 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2739 return 1;
2740 return 0;
2741 }
2742
2743
2744 static void cas_write_txd(struct cas *cp, int ring, int entry,
2745 dma_addr_t mapping, int len, u64 ctrl, int last)
2746 {
2747 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2748
2749 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2750 if (cas_intme(ring, entry))
2751 ctrl |= TX_DESC_INTME;
2752 if (last)
2753 ctrl |= TX_DESC_EOF;
2754 txd->control = cpu_to_le64(ctrl);
2755 txd->buffer = cpu_to_le64(mapping);
2756 }
2757
2758 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2759 const int entry)
2760 {
2761 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2762 }
2763
2764 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2765 const int entry, const int tentry)
2766 {
2767 cp->tx_tiny_use[ring][tentry].nbufs++;
2768 cp->tx_tiny_use[ring][entry].used = 1;
2769 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2770 }
2771
2772 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2773 struct sk_buff *skb)
2774 {
2775 struct net_device *dev = cp->dev;
2776 int entry, nr_frags, frag, tabort, tentry;
2777 dma_addr_t mapping;
2778 unsigned long flags;
2779 u64 ctrl;
2780 u32 len;
2781
2782 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2783
2784 /* This is a hard error, log it. */
2785 if (TX_BUFFS_AVAIL(cp, ring) <=
2786 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2787 netif_stop_queue(dev);
2788 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2789 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2790 "queue awake!\n", dev->name);
2791 return 1;
2792 }
2793
2794 ctrl = 0;
2795 if (skb->ip_summed == CHECKSUM_HW) {
2796 u64 csum_start_off, csum_stuff_off;
2797
2798 csum_start_off = (u64) (skb->h.raw - skb->data);
2799 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
2800
2801 ctrl = TX_DESC_CSUM_EN |
2802 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2803 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2804 }
2805
2806 entry = cp->tx_new[ring];
2807 cp->tx_skbs[ring][entry] = skb;
2808
2809 nr_frags = skb_shinfo(skb)->nr_frags;
2810 len = skb_headlen(skb);
2811 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2812 offset_in_page(skb->data), len,
2813 PCI_DMA_TODEVICE);
2814
2815 tentry = entry;
2816 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2817 if (unlikely(tabort)) {
2818 /* NOTE: len is always > tabort */
2819 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2820 ctrl | TX_DESC_SOF, 0);
2821 entry = TX_DESC_NEXT(ring, entry);
2822
2823 memcpy(tx_tiny_buf(cp, ring, entry), skb->data +
2824 len - tabort, tabort);
2825 mapping = tx_tiny_map(cp, ring, entry, tentry);
2826 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2827 (nr_frags == 0));
2828 } else {
2829 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2830 TX_DESC_SOF, (nr_frags == 0));
2831 }
2832 entry = TX_DESC_NEXT(ring, entry);
2833
2834 for (frag = 0; frag < nr_frags; frag++) {
2835 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2836
2837 len = fragp->size;
2838 mapping = pci_map_page(cp->pdev, fragp->page,
2839 fragp->page_offset, len,
2840 PCI_DMA_TODEVICE);
2841
2842 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2843 if (unlikely(tabort)) {
2844 void *addr;
2845
2846 /* NOTE: len is always > tabort */
2847 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2848 ctrl, 0);
2849 entry = TX_DESC_NEXT(ring, entry);
2850
2851 addr = cas_page_map(fragp->page);
2852 memcpy(tx_tiny_buf(cp, ring, entry),
2853 addr + fragp->page_offset + len - tabort,
2854 tabort);
2855 cas_page_unmap(addr);
2856 mapping = tx_tiny_map(cp, ring, entry, tentry);
2857 len = tabort;
2858 }
2859
2860 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2861 (frag + 1 == nr_frags));
2862 entry = TX_DESC_NEXT(ring, entry);
2863 }
2864
2865 cp->tx_new[ring] = entry;
2866 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2867 netif_stop_queue(dev);
2868
2869 if (netif_msg_tx_queued(cp))
2870 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2871 "avail %d\n",
2872 dev->name, ring, entry, skb->len,
2873 TX_BUFFS_AVAIL(cp, ring));
2874 writel(entry, cp->regs + REG_TX_KICKN(ring));
2875 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2876 return 0;
2877 }
2878
2879 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2880 {
2881 struct cas *cp = netdev_priv(dev);
2882
2883 /* this is only used as a load-balancing hint, so it doesn't
2884 * need to be SMP safe
2885 */
2886 static int ring;
2887
2888 skb = skb_padto(skb, cp->min_frame_size);
2889 if (!skb)
2890 return 0;
2891
2892 /* XXX: we need some higher-level QoS hooks to steer packets to
2893 * individual queues.
2894 */
2895 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2896 return 1;
2897 dev->trans_start = jiffies;
2898 return 0;
2899 }
2900
2901 static void cas_init_tx_dma(struct cas *cp)
2902 {
2903 u64 desc_dma = cp->block_dvma;
2904 unsigned long off;
2905 u32 val;
2906 int i;
2907
2908 /* set up tx completion writeback registers. must be 8-byte aligned */
2909 #ifdef USE_TX_COMPWB
2910 off = offsetof(struct cas_init_block, tx_compwb);
2911 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2912 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2913 #endif
2914
2915 /* enable completion writebacks, enable paced mode,
2916 * disable read pipe, and disable pre-interrupt compwbs
2917 */
2918 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2919 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2920 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2921 TX_CFG_INTR_COMPWB_DIS;
2922
2923 /* write out tx ring info and tx desc bases */
2924 for (i = 0; i < MAX_TX_RINGS; i++) {
2925 off = (unsigned long) cp->init_txds[i] -
2926 (unsigned long) cp->init_block;
2927
2928 val |= CAS_TX_RINGN_BASE(i);
2929 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2930 writel((desc_dma + off) & 0xffffffff, cp->regs +
2931 REG_TX_DBN_LOW(i));
2932 /* don't zero out the kick register here as the system
2933 * will wedge
2934 */
2935 }
2936 writel(val, cp->regs + REG_TX_CFG);
2937
2938 /* program max burst sizes. these numbers should be different
2939 * if doing QoS.
2940 */
2941 #ifdef USE_QOS
2942 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2943 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2944 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2945 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2946 #else
2947 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2948 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2949 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2950 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2951 #endif
2952 }
2953
2954 /* Must be invoked under cp->lock. */
2955 static inline void cas_init_dma(struct cas *cp)
2956 {
2957 cas_init_tx_dma(cp);
2958 cas_init_rx_dma(cp);
2959 }
2960
2961 /* Must be invoked under cp->lock. */
2962 static u32 cas_setup_multicast(struct cas *cp)
2963 {
2964 u32 rxcfg = 0;
2965 int i;
2966
2967 if (cp->dev->flags & IFF_PROMISC) {
2968 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2969
2970 } else if (cp->dev->flags & IFF_ALLMULTI) {
2971 for (i=0; i < 16; i++)
2972 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2973 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2974
2975 } else {
2976 u16 hash_table[16];
2977 u32 crc;
2978 struct dev_mc_list *dmi = cp->dev->mc_list;
2979 int i;
2980
2981 /* use the alternate mac address registers for the
2982 * first 15 multicast addresses
2983 */
2984 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
2985 if (!dmi) {
2986 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
2987 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
2988 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
2989 continue;
2990 }
2991 writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
2992 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2993 writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
2994 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2995 writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
2996 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2997 dmi = dmi->next;
2998 }
2999
3000 /* use hw hash table for the next series of
3001 * multicast addresses
3002 */
3003 memset(hash_table, 0, sizeof(hash_table));
3004 while (dmi) {
3005 crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3006 crc >>= 24;
3007 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3008 dmi = dmi->next;
3009 }
3010 for (i=0; i < 16; i++)
3011 writel(hash_table[i], cp->regs +
3012 REG_MAC_HASH_TABLEN(i));
3013 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3014 }
3015
3016 return rxcfg;
3017 }
3018
3019 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3020 static void cas_clear_mac_err(struct cas *cp)
3021 {
3022 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3023 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3024 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3025 writel(0, cp->regs + REG_MAC_COLL_LATE);
3026 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3027 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3028 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3029 writel(0, cp->regs + REG_MAC_LEN_ERR);
3030 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3031 writel(0, cp->regs + REG_MAC_FCS_ERR);
3032 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3033 }
3034
3035
3036 static void cas_mac_reset(struct cas *cp)
3037 {
3038 int i;
3039
3040 /* do both TX and RX reset */
3041 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3042 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3043
3044 /* wait for TX */
3045 i = STOP_TRIES;
3046 while (i-- > 0) {
3047 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3048 break;
3049 udelay(10);
3050 }
3051
3052 /* wait for RX */
3053 i = STOP_TRIES;
3054 while (i-- > 0) {
3055 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3056 break;
3057 udelay(10);
3058 }
3059
3060 if (readl(cp->regs + REG_MAC_TX_RESET) |
3061 readl(cp->regs + REG_MAC_RX_RESET))
3062 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3063 cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3064 readl(cp->regs + REG_MAC_RX_RESET),
3065 readl(cp->regs + REG_MAC_STATE_MACHINE));
3066 }
3067
3068
3069 /* Must be invoked under cp->lock. */
3070 static void cas_init_mac(struct cas *cp)
3071 {
3072 unsigned char *e = &cp->dev->dev_addr[0];
3073 int i;
3074 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3075 u32 rxcfg;
3076 #endif
3077 cas_mac_reset(cp);
3078
3079 /* setup core arbitration weight register */
3080 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3081
3082 /* XXX Use pci_dma_burst_advice() */
3083 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3084 /* set the infinite burst register for chips that don't have
3085 * pci issues.
3086 */
3087 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3088 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3089 #endif
3090
3091 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3092
3093 writel(0x00, cp->regs + REG_MAC_IPG0);
3094 writel(0x08, cp->regs + REG_MAC_IPG1);
3095 writel(0x04, cp->regs + REG_MAC_IPG2);
3096
3097 /* change later for 802.3z */
3098 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3099
3100 /* min frame + FCS */
3101 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3102
3103 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3104 * specify the maximum frame size to prevent RX tag errors on
3105 * oversized frames.
3106 */
3107 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3108 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3109 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3110 cp->regs + REG_MAC_FRAMESIZE_MAX);
3111
3112 /* NOTE: crc_size is used as a surrogate for half-duplex.
3113 * workaround saturn half-duplex issue by increasing preamble
3114 * size to 65 bytes.
3115 */
3116 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3117 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3118 else
3119 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3120 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3121 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3122 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3123
3124 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3125
3126 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3127 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3128 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3129 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3130 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3131
3132 /* setup mac address in perfect filter array */
3133 for (i = 0; i < 45; i++)
3134 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3135
3136 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3137 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3138 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3139
3140 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3141 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3142 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3143
3144 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3145 cp->mac_rx_cfg = cas_setup_multicast(cp);
3146 #else
3147 /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3148 * a writel does not seem to be necessary because Cassini
3149 * seems to preserve the configuration when we do the reset.
3150 * If the chip is in trouble, though, it is not clear if we
3151 * can really count on this behavior. cas_set_multicast uses
3152 * spin_lock_irqsave, but we are called only in cas_init_hw and
3153 * cas_init_hw is protected by cas_lock_all, which calls
3154 * spin_lock_irq (so it doesn't need to save the flags, and
3155 * we should be OK for the writel, as that is the only
3156 * difference).
3157 */
3158 cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3159 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3160 #endif
3161 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3162 cas_clear_mac_err(cp);
3163 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3164
3165 /* Setup MAC interrupts. We want to get all of the interesting
3166 * counter expiration events, but we do not want to hear about
3167 * normal rx/tx as the DMA engine tells us that.
3168 */
3169 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3170 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3171
3172 /* Don't enable even the PAUSE interrupts for now, we
3173 * make no use of those events other than to record them.
3174 */
3175 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3176 }
3177
3178 /* Must be invoked under cp->lock. */
3179 static void cas_init_pause_thresholds(struct cas *cp)
3180 {
3181 /* Calculate pause thresholds. Setting the OFF threshold to the
3182 * full RX fifo size effectively disables PAUSE generation
3183 */
3184 if (cp->rx_fifo_size <= (2 * 1024)) {
3185 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3186 } else {
3187 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3188 if (max_frame * 3 > cp->rx_fifo_size) {
3189 cp->rx_pause_off = 7104;
3190 cp->rx_pause_on = 960;
3191 } else {
3192 int off = (cp->rx_fifo_size - (max_frame * 2));
3193 int on = off - max_frame;
3194 cp->rx_pause_off = off;
3195 cp->rx_pause_on = on;
3196 }
3197 }
3198 }
3199
3200 static int cas_vpd_match(const void __iomem *p, const char *str)
3201 {
3202 int len = strlen(str) + 1;
3203 int i;
3204
3205 for (i = 0; i < len; i++) {
3206 if (readb(p + i) != str[i])
3207 return 0;
3208 }
3209 return 1;
3210 }
3211
3212
3213 /* get the mac address by reading the vpd information in the rom.
3214 * also get the phy type and determine if there's an entropy generator.
3215 * NOTE: this is a bit convoluted for the following reasons:
3216 * 1) vpd info has order-dependent mac addresses for multinic cards
3217 * 2) the only way to determine the nic order is to use the slot
3218 * number.
3219 * 3) fiber cards don't have bridges, so their slot numbers don't
3220 * mean anything.
3221 * 4) we don't actually know we have a fiber card until after
3222 * the mac addresses are parsed.
3223 */
3224 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3225 const int offset)
3226 {
3227 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3228 void __iomem *base, *kstart;
3229 int i, len;
3230 int found = 0;
3231 #define VPD_FOUND_MAC 0x01
3232 #define VPD_FOUND_PHY 0x02
3233
3234 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3235 int mac_off = 0;
3236
3237 /* give us access to the PROM */
3238 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3239 cp->regs + REG_BIM_LOCAL_DEV_EN);
3240
3241 /* check for an expansion rom */
3242 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3243 goto use_random_mac_addr;
3244
3245 /* search for beginning of vpd */
3246 base = NULL;
3247 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3248 /* check for PCIR */
3249 if ((readb(p + i + 0) == 0x50) &&
3250 (readb(p + i + 1) == 0x43) &&
3251 (readb(p + i + 2) == 0x49) &&
3252 (readb(p + i + 3) == 0x52)) {
3253 base = p + (readb(p + i + 8) |
3254 (readb(p + i + 9) << 8));
3255 break;
3256 }
3257 }
3258
3259 if (!base || (readb(base) != 0x82))
3260 goto use_random_mac_addr;
3261
3262 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3263 while (i < EXPANSION_ROM_SIZE) {
3264 if (readb(base + i) != 0x90) /* no vpd found */
3265 goto use_random_mac_addr;
3266
3267 /* found a vpd field */
3268 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3269
3270 /* extract keywords */
3271 kstart = base + i + 3;
3272 p = kstart;
3273 while ((p - kstart) < len) {
3274 int klen = readb(p + 2);
3275 int j;
3276 char type;
3277
3278 p += 3;
3279
3280 /* look for the following things:
3281 * -- correct length == 29
3282 * 3 (type) + 2 (size) +
3283 * 18 (strlen("local-mac-address") + 1) +
3284 * 6 (mac addr)
3285 * -- VPD Instance 'I'
3286 * -- VPD Type Bytes 'B'
3287 * -- VPD data length == 6
3288 * -- property string == local-mac-address
3289 *
3290 * -- correct length == 24
3291 * 3 (type) + 2 (size) +
3292 * 12 (strlen("entropy-dev") + 1) +
3293 * 7 (strlen("vms110") + 1)
3294 * -- VPD Instance 'I'
3295 * -- VPD Type String 'B'
3296 * -- VPD data length == 7
3297 * -- property string == entropy-dev
3298 *
3299 * -- correct length == 18
3300 * 3 (type) + 2 (size) +
3301 * 9 (strlen("phy-type") + 1) +
3302 * 4 (strlen("pcs") + 1)
3303 * -- VPD Instance 'I'
3304 * -- VPD Type String 'S'
3305 * -- VPD data length == 4
3306 * -- property string == phy-type
3307 *
3308 * -- correct length == 23
3309 * 3 (type) + 2 (size) +
3310 * 14 (strlen("phy-interface") + 1) +
3311 * 4 (strlen("pcs") + 1)
3312 * -- VPD Instance 'I'
3313 * -- VPD Type String 'S'
3314 * -- VPD data length == 4
3315 * -- property string == phy-interface
3316 */
3317 if (readb(p) != 'I')
3318 goto next;
3319
3320 /* finally, check string and length */
3321 type = readb(p + 3);
3322 if (type == 'B') {
3323 if ((klen == 29) && readb(p + 4) == 6 &&
3324 cas_vpd_match(p + 5,
3325 "local-mac-address")) {
3326 if (mac_off++ > offset)
3327 goto next;
3328
3329 /* set mac address */
3330 for (j = 0; j < 6; j++)
3331 dev_addr[j] =
3332 readb(p + 23 + j);
3333 goto found_mac;
3334 }
3335 }
3336
3337 if (type != 'S')
3338 goto next;
3339
3340 #ifdef USE_ENTROPY_DEV
3341 if ((klen == 24) &&
3342 cas_vpd_match(p + 5, "entropy-dev") &&
3343 cas_vpd_match(p + 17, "vms110")) {
3344 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3345 goto next;
3346 }
3347 #endif
3348
3349 if (found & VPD_FOUND_PHY)
3350 goto next;
3351
3352 if ((klen == 18) && readb(p + 4) == 4 &&
3353 cas_vpd_match(p + 5, "phy-type")) {
3354 if (cas_vpd_match(p + 14, "pcs")) {
3355 phy_type = CAS_PHY_SERDES;
3356 goto found_phy;
3357 }
3358 }
3359
3360 if ((klen == 23) && readb(p + 4) == 4 &&
3361 cas_vpd_match(p + 5, "phy-interface")) {
3362 if (cas_vpd_match(p + 19, "pcs")) {
3363 phy_type = CAS_PHY_SERDES;
3364 goto found_phy;
3365 }
3366 }
3367 found_mac:
3368 found |= VPD_FOUND_MAC;
3369 goto next;
3370
3371 found_phy:
3372 found |= VPD_FOUND_PHY;
3373
3374 next:
3375 p += klen;
3376 }
3377 i += len + 3;
3378 }
3379
3380 use_random_mac_addr:
3381 if (found & VPD_FOUND_MAC)
3382 goto done;
3383
3384 /* Sun MAC prefix then 3 random bytes. */
3385 printk(PFX "MAC address not found in ROM VPD\n");
3386 dev_addr[0] = 0x08;
3387 dev_addr[1] = 0x00;
3388 dev_addr[2] = 0x20;
3389 get_random_bytes(dev_addr + 3, 3);
3390
3391 done:
3392 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3393 return phy_type;
3394 }
3395
3396 /* check pci invariants */
3397 static void cas_check_pci_invariants(struct cas *cp)
3398 {
3399 struct pci_dev *pdev = cp->pdev;
3400 u8 rev;
3401
3402 cp->cas_flags = 0;
3403 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
3404 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3405 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3406 if (rev >= CAS_ID_REVPLUS)
3407 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3408 if (rev < CAS_ID_REVPLUS02u)
3409 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3410
3411 /* Original Cassini supports HW CSUM, but it's not
3412 * enabled by default as it can trigger TX hangs.
3413 */
3414 if (rev < CAS_ID_REV2)
3415 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3416 } else {
3417 /* Only sun has original cassini chips. */
3418 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3419
3420 /* We use a flag because the same phy might be externally
3421 * connected.
3422 */
3423 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3424 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3425 cp->cas_flags |= CAS_FLAG_SATURN;
3426 }
3427 }
3428
3429
3430 static int cas_check_invariants(struct cas *cp)
3431 {
3432 struct pci_dev *pdev = cp->pdev;
3433 u32 cfg;
3434 int i;
3435
3436 /* get page size for rx buffers. */
3437 cp->page_order = 0;
3438 #ifdef USE_PAGE_ORDER
3439 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3440 /* see if we can allocate larger pages */
3441 struct page *page = alloc_pages(GFP_ATOMIC,
3442 CAS_JUMBO_PAGE_SHIFT -
3443 PAGE_SHIFT);
3444 if (page) {
3445 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3446 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3447 } else {
3448 printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3449 }
3450 }
3451 #endif
3452 cp->page_size = (PAGE_SIZE << cp->page_order);
3453
3454 /* Fetch the FIFO configurations. */
3455 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3456 cp->rx_fifo_size = RX_FIFO_SIZE;
3457
3458 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3459 * they're both connected.
3460 */
3461 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3462 PCI_SLOT(pdev->devfn));
3463 if (cp->phy_type & CAS_PHY_SERDES) {
3464 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3465 return 0; /* no more checking needed */
3466 }
3467
3468 /* MII */
3469 cfg = readl(cp->regs + REG_MIF_CFG);
3470 if (cfg & MIF_CFG_MDIO_1) {
3471 cp->phy_type = CAS_PHY_MII_MDIO1;
3472 } else if (cfg & MIF_CFG_MDIO_0) {
3473 cp->phy_type = CAS_PHY_MII_MDIO0;
3474 }
3475
3476 cas_mif_poll(cp, 0);
3477 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3478
3479 for (i = 0; i < 32; i++) {
3480 u32 phy_id;
3481 int j;
3482
3483 for (j = 0; j < 3; j++) {
3484 cp->phy_addr = i;
3485 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3486 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3487 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3488 cp->phy_id = phy_id;
3489 goto done;
3490 }
3491 }
3492 }
3493 printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3494 readl(cp->regs + REG_MIF_STATE_MACHINE));
3495 return -1;
3496
3497 done:
3498 /* see if we can do gigabit */
3499 cfg = cas_phy_read(cp, MII_BMSR);
3500 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3501 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3502 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3503 return 0;
3504 }
3505
3506 /* Must be invoked under cp->lock. */
3507 static inline void cas_start_dma(struct cas *cp)
3508 {
3509 int i;
3510 u32 val;
3511 int txfailed = 0;
3512
3513 /* enable dma */
3514 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3515 writel(val, cp->regs + REG_TX_CFG);
3516 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3517 writel(val, cp->regs + REG_RX_CFG);
3518
3519 /* enable the mac */
3520 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3521 writel(val, cp->regs + REG_MAC_TX_CFG);
3522 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3523 writel(val, cp->regs + REG_MAC_RX_CFG);
3524
3525 i = STOP_TRIES;
3526 while (i-- > 0) {
3527 val = readl(cp->regs + REG_MAC_TX_CFG);
3528 if ((val & MAC_TX_CFG_EN))
3529 break;
3530 udelay(10);
3531 }
3532 if (i < 0) txfailed = 1;
3533 i = STOP_TRIES;
3534 while (i-- > 0) {
3535 val = readl(cp->regs + REG_MAC_RX_CFG);
3536 if ((val & MAC_RX_CFG_EN)) {
3537 if (txfailed) {
3538 printk(KERN_ERR
3539 "%s: enabling mac failed [tx:%08x:%08x].\n",
3540 cp->dev->name,
3541 readl(cp->regs + REG_MIF_STATE_MACHINE),
3542 readl(cp->regs + REG_MAC_STATE_MACHINE));
3543 }
3544 goto enable_rx_done;
3545 }
3546 udelay(10);
3547 }
3548 printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
3549 cp->dev->name,
3550 (txfailed? "tx,rx":"rx"),
3551 readl(cp->regs + REG_MIF_STATE_MACHINE),
3552 readl(cp->regs + REG_MAC_STATE_MACHINE));
3553
3554 enable_rx_done:
3555 cas_unmask_intr(cp); /* enable interrupts */
3556 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3557 writel(0, cp->regs + REG_RX_COMP_TAIL);
3558
3559 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3560 if (N_RX_DESC_RINGS > 1)
3561 writel(RX_DESC_RINGN_SIZE(1) - 4,
3562 cp->regs + REG_PLUS_RX_KICK1);
3563
3564 for (i = 1; i < N_RX_COMP_RINGS; i++)
3565 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3566 }
3567 }
3568
3569 /* Must be invoked under cp->lock. */
3570 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3571 int *pause)
3572 {
3573 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3574 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3575 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3576 if (val & PCS_MII_LPA_ASYM_PAUSE)
3577 *pause |= 0x10;
3578 *spd = 1000;
3579 }
3580
3581 /* Must be invoked under cp->lock. */
3582 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3583 int *pause)
3584 {
3585 u32 val;
3586
3587 *fd = 0;
3588 *spd = 10;
3589 *pause = 0;
3590
3591 /* use GMII registers */
3592 val = cas_phy_read(cp, MII_LPA);
3593 if (val & CAS_LPA_PAUSE)
3594 *pause = 0x01;
3595
3596 if (val & CAS_LPA_ASYM_PAUSE)
3597 *pause |= 0x10;
3598
3599 if (val & LPA_DUPLEX)
3600 *fd = 1;
3601 if (val & LPA_100)
3602 *spd = 100;
3603
3604 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3605 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3606 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3607 *spd = 1000;
3608 if (val & CAS_LPA_1000FULL)
3609 *fd = 1;
3610 }
3611 }
3612
3613 /* A link-up condition has occurred, initialize and enable the
3614 * rest of the chip.
3615 *
3616 * Must be invoked under cp->lock.
3617 */
3618 static void cas_set_link_modes(struct cas *cp)
3619 {
3620 u32 val;
3621 int full_duplex, speed, pause;
3622
3623 full_duplex = 0;
3624 speed = 10;
3625 pause = 0;
3626
3627 if (CAS_PHY_MII(cp->phy_type)) {
3628 cas_mif_poll(cp, 0);
3629 val = cas_phy_read(cp, MII_BMCR);
3630 if (val & BMCR_ANENABLE) {
3631 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3632 &pause);
3633 } else {
3634 if (val & BMCR_FULLDPLX)
3635 full_duplex = 1;
3636
3637 if (val & BMCR_SPEED100)
3638 speed = 100;
3639 else if (val & CAS_BMCR_SPEED1000)
3640 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3641 1000 : 100;
3642 }
3643 cas_mif_poll(cp, 1);
3644
3645 } else {
3646 val = readl(cp->regs + REG_PCS_MII_CTRL);
3647 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3648 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3649 if (val & PCS_MII_CTRL_DUPLEX)
3650 full_duplex = 1;
3651 }
3652 }
3653
3654 if (netif_msg_link(cp))
3655 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3656 cp->dev->name, speed, (full_duplex ? "full" : "half"));
3657
3658 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3659 if (CAS_PHY_MII(cp->phy_type)) {
3660 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3661 if (!full_duplex)
3662 val |= MAC_XIF_DISABLE_ECHO;
3663 }
3664 if (full_duplex)
3665 val |= MAC_XIF_FDPLX_LED;
3666 if (speed == 1000)
3667 val |= MAC_XIF_GMII_MODE;
3668 writel(val, cp->regs + REG_MAC_XIF_CFG);
3669
3670 /* deal with carrier and collision detect. */
3671 val = MAC_TX_CFG_IPG_EN;
3672 if (full_duplex) {
3673 val |= MAC_TX_CFG_IGNORE_CARRIER;
3674 val |= MAC_TX_CFG_IGNORE_COLL;
3675 } else {
3676 #ifndef USE_CSMA_CD_PROTO
3677 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3678 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3679 #endif
3680 }
3681 /* val now set up for REG_MAC_TX_CFG */
3682
3683 /* If gigabit and half-duplex, enable carrier extension
3684 * mode. increase slot time to 512 bytes as well.
3685 * else, disable it and make sure slot time is 64 bytes.
3686 * also activate checksum bug workaround
3687 */
3688 if ((speed == 1000) && !full_duplex) {
3689 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3690 cp->regs + REG_MAC_TX_CFG);
3691
3692 val = readl(cp->regs + REG_MAC_RX_CFG);
3693 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3694 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3695 cp->regs + REG_MAC_RX_CFG);
3696
3697 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3698
3699 cp->crc_size = 4;
3700 /* minimum size gigabit frame at half duplex */
3701 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3702
3703 } else {
3704 writel(val, cp->regs + REG_MAC_TX_CFG);
3705
3706 /* checksum bug workaround. don't strip FCS when in
3707 * half-duplex mode
3708 */
3709 val = readl(cp->regs + REG_MAC_RX_CFG);
3710 if (full_duplex) {
3711 val |= MAC_RX_CFG_STRIP_FCS;
3712 cp->crc_size = 0;
3713 cp->min_frame_size = CAS_MIN_MTU;
3714 } else {
3715 val &= ~MAC_RX_CFG_STRIP_FCS;
3716 cp->crc_size = 4;
3717 cp->min_frame_size = CAS_MIN_FRAME;
3718 }
3719 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3720 cp->regs + REG_MAC_RX_CFG);
3721 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3722 }
3723
3724 if (netif_msg_link(cp)) {
3725 if (pause & 0x01) {
3726 printk(KERN_INFO "%s: Pause is enabled "
3727 "(rxfifo: %d off: %d on: %d)\n",
3728 cp->dev->name,
3729 cp->rx_fifo_size,
3730 cp->rx_pause_off,
3731 cp->rx_pause_on);
3732 } else if (pause & 0x10) {
3733 printk(KERN_INFO "%s: TX pause enabled\n",
3734 cp->dev->name);
3735 } else {
3736 printk(KERN_INFO "%s: Pause is disabled\n",
3737 cp->dev->name);
3738 }
3739 }
3740
3741 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3742 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3743 if (pause) { /* symmetric or asymmetric pause */
3744 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3745 if (pause & 0x01) { /* symmetric pause */
3746 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3747 }
3748 }
3749 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3750 cas_start_dma(cp);
3751 }
3752
3753 /* Must be invoked under cp->lock. */
3754 static void cas_init_hw(struct cas *cp, int restart_link)
3755 {
3756 if (restart_link)
3757 cas_phy_init(cp);
3758
3759 cas_init_pause_thresholds(cp);
3760 cas_init_mac(cp);
3761 cas_init_dma(cp);
3762
3763 if (restart_link) {
3764 /* Default aneg parameters */
3765 cp->timer_ticks = 0;
3766 cas_begin_auto_negotiation(cp, NULL);
3767 } else if (cp->lstate == link_up) {
3768 cas_set_link_modes(cp);
3769 netif_carrier_on(cp->dev);
3770 }
3771 }
3772
3773 /* Must be invoked under cp->lock. on earlier cassini boards,
3774 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3775 * let it settle out, and then restore pci state.
3776 */
3777 static void cas_hard_reset(struct cas *cp)
3778 {
3779 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3780 udelay(20);
3781 pci_restore_state(cp->pdev);
3782 }
3783
3784
3785 static void cas_global_reset(struct cas *cp, int blkflag)
3786 {
3787 int limit;
3788
3789 /* issue a global reset. don't use RSTOUT. */
3790 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3791 /* For PCS, when the blkflag is set, we should set the
3792 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3793 * the last autonegotiation from being cleared. We'll
3794 * need some special handling if the chip is set into a
3795 * loopback mode.
3796 */
3797 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3798 cp->regs + REG_SW_RESET);
3799 } else {
3800 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3801 }
3802
3803 /* need to wait at least 3ms before polling register */
3804 mdelay(3);
3805
3806 limit = STOP_TRIES;
3807 while (limit-- > 0) {
3808 u32 val = readl(cp->regs + REG_SW_RESET);
3809 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3810 goto done;
3811 udelay(10);
3812 }
3813 printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3814
3815 done:
3816 /* enable various BIM interrupts */
3817 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3818 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3819
3820 /* clear out pci error status mask for handled errors.
3821 * we don't deal with DMA counter overflows as they happen
3822 * all the time.
3823 */
3824 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3825 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3826 PCI_ERR_BIM_DMA_READ), cp->regs +
3827 REG_PCI_ERR_STATUS_MASK);
3828
3829 /* set up for MII by default to address mac rx reset timeout
3830 * issue
3831 */
3832 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3833 }
3834
3835 static void cas_reset(struct cas *cp, int blkflag)
3836 {
3837 u32 val;
3838
3839 cas_mask_intr(cp);
3840 cas_global_reset(cp, blkflag);
3841 cas_mac_reset(cp);
3842 cas_entropy_reset(cp);
3843
3844 /* disable dma engines. */
3845 val = readl(cp->regs + REG_TX_CFG);
3846 val &= ~TX_CFG_DMA_EN;
3847 writel(val, cp->regs + REG_TX_CFG);
3848
3849 val = readl(cp->regs + REG_RX_CFG);
3850 val &= ~RX_CFG_DMA_EN;
3851 writel(val, cp->regs + REG_RX_CFG);
3852
3853 /* program header parser */
3854 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3855 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3856 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3857 } else {
3858 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3859 }
3860
3861 /* clear out error registers */
3862 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3863 cas_clear_mac_err(cp);
3864 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3865 }
3866
3867 /* Shut down the chip, must be called with pm_sem held. */
3868 static void cas_shutdown(struct cas *cp)
3869 {
3870 unsigned long flags;
3871
3872 /* Make us not-running to avoid timers respawning */
3873 cp->hw_running = 0;
3874
3875 del_timer_sync(&cp->link_timer);
3876
3877 /* Stop the reset task */
3878 #if 0
3879 while (atomic_read(&cp->reset_task_pending_mtu) ||
3880 atomic_read(&cp->reset_task_pending_spare) ||
3881 atomic_read(&cp->reset_task_pending_all))
3882 schedule();
3883
3884 #else
3885 while (atomic_read(&cp->reset_task_pending))
3886 schedule();
3887 #endif
3888 /* Actually stop the chip */
3889 cas_lock_all_save(cp, flags);
3890 cas_reset(cp, 0);
3891 if (cp->cas_flags & CAS_FLAG_SATURN)
3892 cas_phy_powerdown(cp);
3893 cas_unlock_all_restore(cp, flags);
3894 }
3895
3896 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3897 {
3898 struct cas *cp = netdev_priv(dev);
3899
3900 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3901 return -EINVAL;
3902
3903 dev->mtu = new_mtu;
3904 if (!netif_running(dev) || !netif_device_present(dev))
3905 return 0;
3906
3907 /* let the reset task handle it */
3908 #if 1
3909 atomic_inc(&cp->reset_task_pending);
3910 if ((cp->phy_type & CAS_PHY_SERDES)) {
3911 atomic_inc(&cp->reset_task_pending_all);
3912 } else {
3913 atomic_inc(&cp->reset_task_pending_mtu);
3914 }
3915 schedule_work(&cp->reset_task);
3916 #else
3917 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3918 CAS_RESET_ALL : CAS_RESET_MTU);
3919 printk(KERN_ERR "reset called in cas_change_mtu\n");
3920 schedule_work(&cp->reset_task);
3921 #endif
3922
3923 flush_scheduled_work();
3924 return 0;
3925 }
3926
3927 static void cas_clean_txd(struct cas *cp, int ring)
3928 {
3929 struct cas_tx_desc *txd = cp->init_txds[ring];
3930 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3931 u64 daddr, dlen;
3932 int i, size;
3933
3934 size = TX_DESC_RINGN_SIZE(ring);
3935 for (i = 0; i < size; i++) {
3936 int frag;
3937
3938 if (skbs[i] == NULL)
3939 continue;
3940
3941 skb = skbs[i];
3942 skbs[i] = NULL;
3943
3944 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3945 int ent = i & (size - 1);
3946
3947 /* first buffer is never a tiny buffer and so
3948 * needs to be unmapped.
3949 */
3950 daddr = le64_to_cpu(txd[ent].buffer);
3951 dlen = CAS_VAL(TX_DESC_BUFLEN,
3952 le64_to_cpu(txd[ent].control));
3953 pci_unmap_page(cp->pdev, daddr, dlen,
3954 PCI_DMA_TODEVICE);
3955
3956 if (frag != skb_shinfo(skb)->nr_frags) {
3957 i++;
3958
3959 /* next buffer might by a tiny buffer.
3960 * skip past it.
3961 */
3962 ent = i & (size - 1);
3963 if (cp->tx_tiny_use[ring][ent].used)
3964 i++;
3965 }
3966 }
3967 dev_kfree_skb_any(skb);
3968 }
3969
3970 /* zero out tiny buf usage */
3971 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3972 }
3973
3974 /* freed on close */
3975 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3976 {
3977 cas_page_t **page = cp->rx_pages[ring];
3978 int i, size;
3979
3980 size = RX_DESC_RINGN_SIZE(ring);
3981 for (i = 0; i < size; i++) {
3982 if (page[i]) {
3983 cas_page_free(cp, page[i]);
3984 page[i] = NULL;
3985 }
3986 }
3987 }
3988
3989 static void cas_free_rxds(struct cas *cp)
3990 {
3991 int i;
3992
3993 for (i = 0; i < N_RX_DESC_RINGS; i++)
3994 cas_free_rx_desc(cp, i);
3995 }
3996
3997 /* Must be invoked under cp->lock. */
3998 static void cas_clean_rings(struct cas *cp)
3999 {
4000 int i;
4001
4002 /* need to clean all tx rings */
4003 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
4004 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
4005 for (i = 0; i < N_TX_RINGS; i++)
4006 cas_clean_txd(cp, i);
4007
4008 /* zero out init block */
4009 memset(cp->init_block, 0, sizeof(struct cas_init_block));
4010 cas_clean_rxds(cp);
4011 cas_clean_rxcs(cp);
4012 }
4013
4014 /* allocated on open */
4015 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4016 {
4017 cas_page_t **page = cp->rx_pages[ring];
4018 int size, i = 0;
4019
4020 size = RX_DESC_RINGN_SIZE(ring);
4021 for (i = 0; i < size; i++) {
4022 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4023 return -1;
4024 }
4025 return 0;
4026 }
4027
4028 static int cas_alloc_rxds(struct cas *cp)
4029 {
4030 int i;
4031
4032 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4033 if (cas_alloc_rx_desc(cp, i) < 0) {
4034 cas_free_rxds(cp);
4035 return -1;
4036 }
4037 }
4038 return 0;
4039 }
4040
4041 static void cas_reset_task(void *data)
4042 {
4043 struct cas *cp = (struct cas *) data;
4044 #if 0
4045 int pending = atomic_read(&cp->reset_task_pending);
4046 #else
4047 int pending_all = atomic_read(&cp->reset_task_pending_all);
4048 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4049 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4050
4051 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4052 /* We can have more tasks scheduled than actually
4053 * needed.
4054 */
4055 atomic_dec(&cp->reset_task_pending);
4056 return;
4057 }
4058 #endif
4059 /* The link went down, we reset the ring, but keep
4060 * DMA stopped. Use this function for reset
4061 * on error as well.
4062 */
4063 if (cp->hw_running) {
4064 unsigned long flags;
4065
4066 /* Make sure we don't get interrupts or tx packets */
4067 netif_device_detach(cp->dev);
4068 cas_lock_all_save(cp, flags);
4069
4070 if (cp->opened) {
4071 /* We call cas_spare_recover when we call cas_open.
4072 * but we do not initialize the lists cas_spare_recover
4073 * uses until cas_open is called.
4074 */
4075 cas_spare_recover(cp, GFP_ATOMIC);
4076 }
4077 #if 1
4078 /* test => only pending_spare set */
4079 if (!pending_all && !pending_mtu)
4080 goto done;
4081 #else
4082 if (pending == CAS_RESET_SPARE)
4083 goto done;
4084 #endif
4085 /* when pending == CAS_RESET_ALL, the following
4086 * call to cas_init_hw will restart auto negotiation.
4087 * Setting the second argument of cas_reset to
4088 * !(pending == CAS_RESET_ALL) will set this argument
4089 * to 1 (avoiding reinitializing the PHY for the normal
4090 * PCS case) when auto negotiation is not restarted.
4091 */
4092 #if 1
4093 cas_reset(cp, !(pending_all > 0));
4094 if (cp->opened)
4095 cas_clean_rings(cp);
4096 cas_init_hw(cp, (pending_all > 0));
4097 #else
4098 cas_reset(cp, !(pending == CAS_RESET_ALL));
4099 if (cp->opened)
4100 cas_clean_rings(cp);
4101 cas_init_hw(cp, pending == CAS_RESET_ALL);
4102 #endif
4103
4104 done:
4105 cas_unlock_all_restore(cp, flags);
4106 netif_device_attach(cp->dev);
4107 }
4108 #if 1
4109 atomic_sub(pending_all, &cp->reset_task_pending_all);
4110 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4111 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4112 atomic_dec(&cp->reset_task_pending);
4113 #else
4114 atomic_set(&cp->reset_task_pending, 0);
4115 #endif
4116 }
4117
4118 static void cas_link_timer(unsigned long data)
4119 {
4120 struct cas *cp = (struct cas *) data;
4121 int mask, pending = 0, reset = 0;
4122 unsigned long flags;
4123
4124 if (link_transition_timeout != 0 &&
4125 cp->link_transition_jiffies_valid &&
4126 ((jiffies - cp->link_transition_jiffies) >
4127 (link_transition_timeout))) {
4128 /* One-second counter so link-down workaround doesn't
4129 * cause resets to occur so fast as to fool the switch
4130 * into thinking the link is down.
4131 */
4132 cp->link_transition_jiffies_valid = 0;
4133 }
4134
4135 if (!cp->hw_running)
4136 return;
4137
4138 spin_lock_irqsave(&cp->lock, flags);
4139 cas_lock_tx(cp);
4140 cas_entropy_gather(cp);
4141
4142 /* If the link task is still pending, we just
4143 * reschedule the link timer
4144 */
4145 #if 1
4146 if (atomic_read(&cp->reset_task_pending_all) ||
4147 atomic_read(&cp->reset_task_pending_spare) ||
4148 atomic_read(&cp->reset_task_pending_mtu))
4149 goto done;
4150 #else
4151 if (atomic_read(&cp->reset_task_pending))
4152 goto done;
4153 #endif
4154
4155 /* check for rx cleaning */
4156 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4157 int i, rmask;
4158
4159 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4160 rmask = CAS_FLAG_RXD_POST(i);
4161 if ((mask & rmask) == 0)
4162 continue;
4163
4164 /* post_rxds will do a mod_timer */
4165 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4166 pending = 1;
4167 continue;
4168 }
4169 cp->cas_flags &= ~rmask;
4170 }
4171 }
4172
4173 if (CAS_PHY_MII(cp->phy_type)) {
4174 u16 bmsr;
4175 cas_mif_poll(cp, 0);
4176 bmsr = cas_phy_read(cp, MII_BMSR);
4177 /* WTZ: Solaris driver reads this twice, but that
4178 * may be due to the PCS case and the use of a
4179 * common implementation. Read it twice here to be
4180 * safe.
4181 */
4182 bmsr = cas_phy_read(cp, MII_BMSR);
4183 cas_mif_poll(cp, 1);
4184 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4185 reset = cas_mii_link_check(cp, bmsr);
4186 } else {
4187 reset = cas_pcs_link_check(cp);
4188 }
4189
4190 if (reset)
4191 goto done;
4192
4193 /* check for tx state machine confusion */
4194 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4195 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4196 u32 wptr, rptr;
4197 int tlm = CAS_VAL(MAC_SM_TLM, val);
4198
4199 if (((tlm == 0x5) || (tlm == 0x3)) &&
4200 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4201 if (netif_msg_tx_err(cp))
4202 printk(KERN_DEBUG "%s: tx err: "
4203 "MAC_STATE[%08x]\n",
4204 cp->dev->name, val);
4205 reset = 1;
4206 goto done;
4207 }
4208
4209 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4210 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4211 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4212 if ((val == 0) && (wptr != rptr)) {
4213 if (netif_msg_tx_err(cp))
4214 printk(KERN_DEBUG "%s: tx err: "
4215 "TX_FIFO[%08x:%08x:%08x]\n",
4216 cp->dev->name, val, wptr, rptr);
4217 reset = 1;
4218 }
4219
4220 if (reset)
4221 cas_hard_reset(cp);
4222 }
4223
4224 done:
4225 if (reset) {
4226 #if 1
4227 atomic_inc(&cp->reset_task_pending);
4228 atomic_inc(&cp->reset_task_pending_all);
4229 schedule_work(&cp->reset_task);
4230 #else
4231 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4232 printk(KERN_ERR "reset called in cas_link_timer\n");
4233 schedule_work(&cp->reset_task);
4234 #endif
4235 }
4236
4237 if (!pending)
4238 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4239 cas_unlock_tx(cp);
4240 spin_unlock_irqrestore(&cp->lock, flags);
4241 }
4242
4243 /* tiny buffers are used to avoid target abort issues with
4244 * older cassini's
4245 */
4246 static void cas_tx_tiny_free(struct cas *cp)
4247 {
4248 struct pci_dev *pdev = cp->pdev;
4249 int i;
4250
4251 for (i = 0; i < N_TX_RINGS; i++) {
4252 if (!cp->tx_tiny_bufs[i])
4253 continue;
4254
4255 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4256 cp->tx_tiny_bufs[i],
4257 cp->tx_tiny_dvma[i]);
4258 cp->tx_tiny_bufs[i] = NULL;
4259 }
4260 }
4261
4262 static int cas_tx_tiny_alloc(struct cas *cp)
4263 {
4264 struct pci_dev *pdev = cp->pdev;
4265 int i;
4266
4267 for (i = 0; i < N_TX_RINGS; i++) {
4268 cp->tx_tiny_bufs[i] =
4269 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4270 &cp->tx_tiny_dvma[i]);
4271 if (!cp->tx_tiny_bufs[i]) {
4272 cas_tx_tiny_free(cp);
4273 return -1;
4274 }
4275 }
4276 return 0;
4277 }
4278
4279
4280 static int cas_open(struct net_device *dev)
4281 {
4282 struct cas *cp = netdev_priv(dev);
4283 int hw_was_up, err;
4284 unsigned long flags;
4285
4286 down(&cp->pm_sem);
4287
4288 hw_was_up = cp->hw_running;
4289
4290 /* The power-management semaphore protects the hw_running
4291 * etc. state so it is safe to do this bit without cp->lock
4292 */
4293 if (!cp->hw_running) {
4294 /* Reset the chip */
4295 cas_lock_all_save(cp, flags);
4296 /* We set the second arg to cas_reset to zero
4297 * because cas_init_hw below will have its second
4298 * argument set to non-zero, which will force
4299 * autonegotiation to start.
4300 */
4301 cas_reset(cp, 0);
4302 cp->hw_running = 1;
4303 cas_unlock_all_restore(cp, flags);
4304 }
4305
4306 if (cas_tx_tiny_alloc(cp) < 0)
4307 return -ENOMEM;
4308
4309 /* alloc rx descriptors */
4310 err = -ENOMEM;
4311 if (cas_alloc_rxds(cp) < 0)
4312 goto err_tx_tiny;
4313
4314 /* allocate spares */
4315 cas_spare_init(cp);
4316 cas_spare_recover(cp, GFP_KERNEL);
4317
4318 /* We can now request the interrupt as we know it's masked
4319 * on the controller. cassini+ has up to 4 interrupts
4320 * that can be used, but you need to do explicit pci interrupt
4321 * mapping to expose them
4322 */
4323 if (request_irq(cp->pdev->irq, cas_interrupt,
4324 SA_SHIRQ, dev->name, (void *) dev)) {
4325 printk(KERN_ERR "%s: failed to request irq !\n",
4326 cp->dev->name);
4327 err = -EAGAIN;
4328 goto err_spare;
4329 }
4330
4331 /* init hw */
4332 cas_lock_all_save(cp, flags);
4333 cas_clean_rings(cp);
4334 cas_init_hw(cp, !hw_was_up);
4335 cp->opened = 1;
4336 cas_unlock_all_restore(cp, flags);
4337
4338 netif_start_queue(dev);
4339 up(&cp->pm_sem);
4340 return 0;
4341
4342 err_spare:
4343 cas_spare_free(cp);
4344 cas_free_rxds(cp);
4345 err_tx_tiny:
4346 cas_tx_tiny_free(cp);
4347 up(&cp->pm_sem);
4348 return err;
4349 }
4350
4351 static int cas_close(struct net_device *dev)
4352 {
4353 unsigned long flags;
4354 struct cas *cp = netdev_priv(dev);
4355
4356 /* Make sure we don't get distracted by suspend/resume */
4357 down(&cp->pm_sem);
4358
4359 netif_stop_queue(dev);
4360
4361 /* Stop traffic, mark us closed */
4362 cas_lock_all_save(cp, flags);
4363 cp->opened = 0;
4364 cas_reset(cp, 0);
4365 cas_phy_init(cp);
4366 cas_begin_auto_negotiation(cp, NULL);
4367 cas_clean_rings(cp);
4368 cas_unlock_all_restore(cp, flags);
4369
4370 free_irq(cp->pdev->irq, (void *) dev);
4371 cas_spare_free(cp);
4372 cas_free_rxds(cp);
4373 cas_tx_tiny_free(cp);
4374 up(&cp->pm_sem);
4375 return 0;
4376 }
4377
4378 static struct {
4379 const char name[ETH_GSTRING_LEN];
4380 } ethtool_cassini_statnames[] = {
4381 {"collisions"},
4382 {"rx_bytes"},
4383 {"rx_crc_errors"},
4384 {"rx_dropped"},
4385 {"rx_errors"},
4386 {"rx_fifo_errors"},
4387 {"rx_frame_errors"},
4388 {"rx_length_errors"},
4389 {"rx_over_errors"},
4390 {"rx_packets"},
4391 {"tx_aborted_errors"},
4392 {"tx_bytes"},
4393 {"tx_dropped"},
4394 {"tx_errors"},
4395 {"tx_fifo_errors"},
4396 {"tx_packets"}
4397 };
4398 #define CAS_NUM_STAT_KEYS (sizeof(ethtool_cassini_statnames)/ETH_GSTRING_LEN)
4399
4400 static struct {
4401 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4402 } ethtool_register_table[] = {
4403 {-MII_BMSR},
4404 {-MII_BMCR},
4405 {REG_CAWR},
4406 {REG_INF_BURST},
4407 {REG_BIM_CFG},
4408 {REG_RX_CFG},
4409 {REG_HP_CFG},
4410 {REG_MAC_TX_CFG},
4411 {REG_MAC_RX_CFG},
4412 {REG_MAC_CTRL_CFG},
4413 {REG_MAC_XIF_CFG},
4414 {REG_MIF_CFG},
4415 {REG_PCS_CFG},
4416 {REG_SATURN_PCFG},
4417 {REG_PCS_MII_STATUS},
4418 {REG_PCS_STATE_MACHINE},
4419 {REG_MAC_COLL_EXCESS},
4420 {REG_MAC_COLL_LATE}
4421 };
4422 #define CAS_REG_LEN (sizeof(ethtool_register_table)/sizeof(int))
4423 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4424
4425 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4426 {
4427 u8 *p;
4428 int i;
4429 unsigned long flags;
4430
4431 spin_lock_irqsave(&cp->lock, flags);
4432 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4433 u16 hval;
4434 u32 val;
4435 if (ethtool_register_table[i].offsets < 0) {
4436 hval = cas_phy_read(cp,
4437 -ethtool_register_table[i].offsets);
4438 val = hval;
4439 } else {
4440 val= readl(cp->regs+ethtool_register_table[i].offsets);
4441 }
4442 memcpy(p, (u8 *)&val, sizeof(u32));
4443 }
4444 spin_unlock_irqrestore(&cp->lock, flags);
4445 }
4446
4447 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4448 {
4449 struct cas *cp = netdev_priv(dev);
4450 struct net_device_stats *stats = cp->net_stats;
4451 unsigned long flags;
4452 int i;
4453 unsigned long tmp;
4454
4455 /* we collate all of the stats into net_stats[N_TX_RING] */
4456 if (!cp->hw_running)
4457 return stats + N_TX_RINGS;
4458
4459 /* collect outstanding stats */
4460 /* WTZ: the Cassini spec gives these as 16 bit counters but
4461 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4462 * in case the chip somehow puts any garbage in the other bits.
4463 * Also, counter usage didn't seem to mach what Adrian did
4464 * in the parts of the code that set these quantities. Made
4465 * that consistent.
4466 */
4467 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4468 stats[N_TX_RINGS].rx_crc_errors +=
4469 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4470 stats[N_TX_RINGS].rx_frame_errors +=
4471 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4472 stats[N_TX_RINGS].rx_length_errors +=
4473 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4474 #if 1
4475 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4476 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4477 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4478 stats[N_TX_RINGS].collisions +=
4479 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4480 #else
4481 stats[N_TX_RINGS].tx_aborted_errors +=
4482 readl(cp->regs + REG_MAC_COLL_EXCESS);
4483 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4484 readl(cp->regs + REG_MAC_COLL_LATE);
4485 #endif
4486 cas_clear_mac_err(cp);
4487
4488 /* saved bits that are unique to ring 0 */
4489 spin_lock(&cp->stat_lock[0]);
4490 stats[N_TX_RINGS].collisions += stats[0].collisions;
4491 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4492 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4493 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4494 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4495 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4496 spin_unlock(&cp->stat_lock[0]);
4497
4498 for (i = 0; i < N_TX_RINGS; i++) {
4499 spin_lock(&cp->stat_lock[i]);
4500 stats[N_TX_RINGS].rx_length_errors +=
4501 stats[i].rx_length_errors;
4502 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4503 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4504 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4505 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4506 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4507 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4508 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4509 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4510 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4511 memset(stats + i, 0, sizeof(struct net_device_stats));
4512 spin_unlock(&cp->stat_lock[i]);
4513 }
4514 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4515 return stats + N_TX_RINGS;
4516 }
4517
4518
4519 static void cas_set_multicast(struct net_device *dev)
4520 {
4521 struct cas *cp = netdev_priv(dev);
4522 u32 rxcfg, rxcfg_new;
4523 unsigned long flags;
4524 int limit = STOP_TRIES;
4525
4526 if (!cp->hw_running)
4527 return;
4528
4529 spin_lock_irqsave(&cp->lock, flags);
4530 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4531
4532 /* disable RX MAC and wait for completion */
4533 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4534 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4535 if (!limit--)
4536 break;
4537 udelay(10);
4538 }
4539
4540 /* disable hash filter and wait for completion */
4541 limit = STOP_TRIES;
4542 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4543 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4544 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4545 if (!limit--)
4546 break;
4547 udelay(10);
4548 }
4549
4550 /* program hash filters */
4551 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4552 rxcfg |= rxcfg_new;
4553 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4554 spin_unlock_irqrestore(&cp->lock, flags);
4555 }
4556
4557 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4558 {
4559 struct cas *cp = netdev_priv(dev);
4560 strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4561 strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4562 info->fw_version[0] = '\0';
4563 strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4564 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4565 cp->casreg_len : CAS_MAX_REGS;
4566 info->n_stats = CAS_NUM_STAT_KEYS;
4567 }
4568
4569 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4570 {
4571 struct cas *cp = netdev_priv(dev);
4572 u16 bmcr;
4573 int full_duplex, speed, pause;
4574 unsigned long flags;
4575 enum link_state linkstate = link_up;
4576
4577 cmd->advertising = 0;
4578 cmd->supported = SUPPORTED_Autoneg;
4579 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4580 cmd->supported |= SUPPORTED_1000baseT_Full;
4581 cmd->advertising |= ADVERTISED_1000baseT_Full;
4582 }
4583
4584 /* Record PHY settings if HW is on. */
4585 spin_lock_irqsave(&cp->lock, flags);
4586 bmcr = 0;
4587 linkstate = cp->lstate;
4588 if (CAS_PHY_MII(cp->phy_type)) {
4589 cmd->port = PORT_MII;
4590 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4591 XCVR_INTERNAL : XCVR_EXTERNAL;
4592 cmd->phy_address = cp->phy_addr;
4593 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4594 ADVERTISED_10baseT_Half |
4595 ADVERTISED_10baseT_Full |
4596 ADVERTISED_100baseT_Half |
4597 ADVERTISED_100baseT_Full;
4598
4599 cmd->supported |=
4600 (SUPPORTED_10baseT_Half |
4601 SUPPORTED_10baseT_Full |
4602 SUPPORTED_100baseT_Half |
4603 SUPPORTED_100baseT_Full |
4604 SUPPORTED_TP | SUPPORTED_MII);
4605
4606 if (cp->hw_running) {
4607 cas_mif_poll(cp, 0);
4608 bmcr = cas_phy_read(cp, MII_BMCR);
4609 cas_read_mii_link_mode(cp, &full_duplex,
4610 &speed, &pause);
4611 cas_mif_poll(cp, 1);
4612 }
4613
4614 } else {
4615 cmd->port = PORT_FIBRE;
4616 cmd->transceiver = XCVR_INTERNAL;
4617 cmd->phy_address = 0;
4618 cmd->supported |= SUPPORTED_FIBRE;
4619 cmd->advertising |= ADVERTISED_FIBRE;
4620
4621 if (cp->hw_running) {
4622 /* pcs uses the same bits as mii */
4623 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4624 cas_read_pcs_link_mode(cp, &full_duplex,
4625 &speed, &pause);
4626 }
4627 }
4628 spin_unlock_irqrestore(&cp->lock, flags);
4629
4630 if (bmcr & BMCR_ANENABLE) {
4631 cmd->advertising |= ADVERTISED_Autoneg;
4632 cmd->autoneg = AUTONEG_ENABLE;
4633 cmd->speed = ((speed == 10) ?
4634 SPEED_10 :
4635 ((speed == 1000) ?
4636 SPEED_1000 : SPEED_100));
4637 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4638 } else {
4639 cmd->autoneg = AUTONEG_DISABLE;
4640 cmd->speed =
4641 (bmcr & CAS_BMCR_SPEED1000) ?
4642 SPEED_1000 :
4643 ((bmcr & BMCR_SPEED100) ? SPEED_100:
4644 SPEED_10);
4645 cmd->duplex =
4646 (bmcr & BMCR_FULLDPLX) ?
4647 DUPLEX_FULL : DUPLEX_HALF;
4648 }
4649 if (linkstate != link_up) {
4650 /* Force these to "unknown" if the link is not up and
4651 * autonogotiation in enabled. We can set the link
4652 * speed to 0, but not cmd->duplex,
4653 * because its legal values are 0 and 1. Ethtool will
4654 * print the value reported in parentheses after the
4655 * word "Unknown" for unrecognized values.
4656 *
4657 * If in forced mode, we report the speed and duplex
4658 * settings that we configured.
4659 */
4660 if (cp->link_cntl & BMCR_ANENABLE) {
4661 cmd->speed = 0;
4662 cmd->duplex = 0xff;
4663 } else {
4664 cmd->speed = SPEED_10;
4665 if (cp->link_cntl & BMCR_SPEED100) {
4666 cmd->speed = SPEED_100;
4667 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4668 cmd->speed = SPEED_1000;
4669 }
4670 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4671 DUPLEX_FULL : DUPLEX_HALF;
4672 }
4673 }
4674 return 0;
4675 }
4676
4677 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4678 {
4679 struct cas *cp = netdev_priv(dev);
4680 unsigned long flags;
4681
4682 /* Verify the settings we care about. */
4683 if (cmd->autoneg != AUTONEG_ENABLE &&
4684 cmd->autoneg != AUTONEG_DISABLE)
4685 return -EINVAL;
4686
4687 if (cmd->autoneg == AUTONEG_DISABLE &&
4688 ((cmd->speed != SPEED_1000 &&
4689 cmd->speed != SPEED_100 &&
4690 cmd->speed != SPEED_10) ||
4691 (cmd->duplex != DUPLEX_HALF &&
4692 cmd->duplex != DUPLEX_FULL)))
4693 return -EINVAL;
4694
4695 /* Apply settings and restart link process. */
4696 spin_lock_irqsave(&cp->lock, flags);
4697 cas_begin_auto_negotiation(cp, cmd);
4698 spin_unlock_irqrestore(&cp->lock, flags);
4699 return 0;
4700 }
4701
4702 static int cas_nway_reset(struct net_device *dev)
4703 {
4704 struct cas *cp = netdev_priv(dev);
4705 unsigned long flags;
4706
4707 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4708 return -EINVAL;
4709
4710 /* Restart link process. */
4711 spin_lock_irqsave(&cp->lock, flags);
4712 cas_begin_auto_negotiation(cp, NULL);
4713 spin_unlock_irqrestore(&cp->lock, flags);
4714
4715 return 0;
4716 }
4717
4718 static u32 cas_get_link(struct net_device *dev)
4719 {
4720 struct cas *cp = netdev_priv(dev);
4721 return cp->lstate == link_up;
4722 }
4723
4724 static u32 cas_get_msglevel(struct net_device *dev)
4725 {
4726 struct cas *cp = netdev_priv(dev);
4727 return cp->msg_enable;
4728 }
4729
4730 static void cas_set_msglevel(struct net_device *dev, u32 value)
4731 {
4732 struct cas *cp = netdev_priv(dev);
4733 cp->msg_enable = value;
4734 }
4735
4736 static int cas_get_regs_len(struct net_device *dev)
4737 {
4738 struct cas *cp = netdev_priv(dev);
4739 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4740 }
4741
4742 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4743 void *p)
4744 {
4745 struct cas *cp = netdev_priv(dev);
4746 regs->version = 0;
4747 /* cas_read_regs handles locks (cp->lock). */
4748 cas_read_regs(cp, p, regs->len / sizeof(u32));
4749 }
4750
4751 static int cas_get_stats_count(struct net_device *dev)
4752 {
4753 return CAS_NUM_STAT_KEYS;
4754 }
4755
4756 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4757 {
4758 memcpy(data, &ethtool_cassini_statnames,
4759 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4760 }
4761
4762 static void cas_get_ethtool_stats(struct net_device *dev,
4763 struct ethtool_stats *estats, u64 *data)
4764 {
4765 struct cas *cp = netdev_priv(dev);
4766 struct net_device_stats *stats = cas_get_stats(cp->dev);
4767 int i = 0;
4768 data[i++] = stats->collisions;
4769 data[i++] = stats->rx_bytes;
4770 data[i++] = stats->rx_crc_errors;
4771 data[i++] = stats->rx_dropped;
4772 data[i++] = stats->rx_errors;
4773 data[i++] = stats->rx_fifo_errors;
4774 data[i++] = stats->rx_frame_errors;
4775 data[i++] = stats->rx_length_errors;
4776 data[i++] = stats->rx_over_errors;
4777 data[i++] = stats->rx_packets;
4778 data[i++] = stats->tx_aborted_errors;
4779 data[i++] = stats->tx_bytes;
4780 data[i++] = stats->tx_dropped;
4781 data[i++] = stats->tx_errors;
4782 data[i++] = stats->tx_fifo_errors;
4783 data[i++] = stats->tx_packets;
4784 BUG_ON(i != CAS_NUM_STAT_KEYS);
4785 }
4786
4787 static struct ethtool_ops cas_ethtool_ops = {
4788 .get_drvinfo = cas_get_drvinfo,
4789 .get_settings = cas_get_settings,
4790 .set_settings = cas_set_settings,
4791 .nway_reset = cas_nway_reset,
4792 .get_link = cas_get_link,
4793 .get_msglevel = cas_get_msglevel,
4794 .set_msglevel = cas_set_msglevel,
4795 .get_regs_len = cas_get_regs_len,
4796 .get_regs = cas_get_regs,
4797 .get_stats_count = cas_get_stats_count,
4798 .get_strings = cas_get_strings,
4799 .get_ethtool_stats = cas_get_ethtool_stats,
4800 };
4801
4802 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4803 {
4804 struct cas *cp = netdev_priv(dev);
4805 struct mii_ioctl_data *data = if_mii(ifr);
4806 unsigned long flags;
4807 int rc = -EOPNOTSUPP;
4808
4809 /* Hold the PM semaphore while doing ioctl's or we may collide
4810 * with open/close and power management and oops.
4811 */
4812 down(&cp->pm_sem);
4813 switch (cmd) {
4814 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4815 data->phy_id = cp->phy_addr;
4816 /* Fallthrough... */
4817
4818 case SIOCGMIIREG: /* Read MII PHY register. */
4819 spin_lock_irqsave(&cp->lock, flags);
4820 cas_mif_poll(cp, 0);
4821 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4822 cas_mif_poll(cp, 1);
4823 spin_unlock_irqrestore(&cp->lock, flags);
4824 rc = 0;
4825 break;
4826
4827 case SIOCSMIIREG: /* Write MII PHY register. */
4828 if (!capable(CAP_NET_ADMIN)) {
4829 rc = -EPERM;
4830 break;
4831 }
4832 spin_lock_irqsave(&cp->lock, flags);
4833 cas_mif_poll(cp, 0);
4834 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4835 cas_mif_poll(cp, 1);
4836 spin_unlock_irqrestore(&cp->lock, flags);
4837 break;
4838 default:
4839 break;
4840 };
4841
4842 up(&cp->pm_sem);
4843 return rc;
4844 }
4845
4846 static int __devinit cas_init_one(struct pci_dev *pdev,
4847 const struct pci_device_id *ent)
4848 {
4849 static int cas_version_printed = 0;
4850 unsigned long casreg_base, casreg_len;
4851 struct net_device *dev;
4852 struct cas *cp;
4853 int i, err, pci_using_dac;
4854 u16 pci_cmd;
4855 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4856
4857 if (cas_version_printed++ == 0)
4858 printk(KERN_INFO "%s", version);
4859
4860 err = pci_enable_device(pdev);
4861 if (err) {
4862 printk(KERN_ERR PFX "Cannot enable PCI device, "
4863 "aborting.\n");
4864 return err;
4865 }
4866
4867 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4868 printk(KERN_ERR PFX "Cannot find proper PCI device "
4869 "base address, aborting.\n");
4870 err = -ENODEV;
4871 goto err_out_disable_pdev;
4872 }
4873
4874 dev = alloc_etherdev(sizeof(*cp));
4875 if (!dev) {
4876 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
4877 err = -ENOMEM;
4878 goto err_out_disable_pdev;
4879 }
4880 SET_MODULE_OWNER(dev);
4881 SET_NETDEV_DEV(dev, &pdev->dev);
4882
4883 err = pci_request_regions(pdev, dev->name);
4884 if (err) {
4885 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
4886 "aborting.\n");
4887 goto err_out_free_netdev;
4888 }
4889 pci_set_master(pdev);
4890
4891 /* we must always turn on parity response or else parity
4892 * doesn't get generated properly. disable SERR/PERR as well.
4893 * in addition, we want to turn MWI on.
4894 */
4895 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4896 pci_cmd &= ~PCI_COMMAND_SERR;
4897 pci_cmd |= PCI_COMMAND_PARITY;
4898 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4899 pci_set_mwi(pdev);
4900 /*
4901 * On some architectures, the default cache line size set
4902 * by pci_set_mwi reduces perforamnce. We have to increase
4903 * it for this case. To start, we'll print some configuration
4904 * data.
4905 */
4906 #if 1
4907 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4908 &orig_cacheline_size);
4909 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4910 cas_cacheline_size =
4911 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4912 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4913 if (pci_write_config_byte(pdev,
4914 PCI_CACHE_LINE_SIZE,
4915 cas_cacheline_size)) {
4916 printk(KERN_ERR PFX "Could not set PCI cache "
4917 "line size\n");
4918 goto err_write_cacheline;
4919 }
4920 }
4921 #endif
4922
4923
4924 /* Configure DMA attributes. */
4925 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
4926 pci_using_dac = 1;
4927 err = pci_set_consistent_dma_mask(pdev,
4928 DMA_64BIT_MASK);
4929 if (err < 0) {
4930 printk(KERN_ERR PFX "Unable to obtain 64-bit DMA "
4931 "for consistent allocations\n");
4932 goto err_out_free_res;
4933 }
4934
4935 } else {
4936 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4937 if (err) {
4938 printk(KERN_ERR PFX "No usable DMA configuration, "
4939 "aborting.\n");
4940 goto err_out_free_res;
4941 }
4942 pci_using_dac = 0;
4943 }
4944
4945 casreg_base = pci_resource_start(pdev, 0);
4946 casreg_len = pci_resource_len(pdev, 0);
4947
4948 cp = netdev_priv(dev);
4949 cp->pdev = pdev;
4950 #if 1
4951 /* A value of 0 indicates we never explicitly set it */
4952 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
4953 #endif
4954 cp->dev = dev;
4955 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
4956 cassini_debug;
4957
4958 cp->link_transition = LINK_TRANSITION_UNKNOWN;
4959 cp->link_transition_jiffies_valid = 0;
4960
4961 spin_lock_init(&cp->lock);
4962 spin_lock_init(&cp->rx_inuse_lock);
4963 spin_lock_init(&cp->rx_spare_lock);
4964 for (i = 0; i < N_TX_RINGS; i++) {
4965 spin_lock_init(&cp->stat_lock[i]);
4966 spin_lock_init(&cp->tx_lock[i]);
4967 }
4968 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
4969 init_MUTEX(&cp->pm_sem);
4970
4971 init_timer(&cp->link_timer);
4972 cp->link_timer.function = cas_link_timer;
4973 cp->link_timer.data = (unsigned long) cp;
4974
4975 #if 1
4976 /* Just in case the implementation of atomic operations
4977 * change so that an explicit initialization is necessary.
4978 */
4979 atomic_set(&cp->reset_task_pending, 0);
4980 atomic_set(&cp->reset_task_pending_all, 0);
4981 atomic_set(&cp->reset_task_pending_spare, 0);
4982 atomic_set(&cp->reset_task_pending_mtu, 0);
4983 #endif
4984 INIT_WORK(&cp->reset_task, cas_reset_task, cp);
4985
4986 /* Default link parameters */
4987 if (link_mode >= 0 && link_mode <= 6)
4988 cp->link_cntl = link_modes[link_mode];
4989 else
4990 cp->link_cntl = BMCR_ANENABLE;
4991 cp->lstate = link_down;
4992 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
4993 netif_carrier_off(cp->dev);
4994 cp->timer_ticks = 0;
4995
4996 /* give us access to cassini registers */
4997 cp->regs = ioremap(casreg_base, casreg_len);
4998 if (cp->regs == 0UL) {
4999 printk(KERN_ERR PFX "Cannot map device registers, "
5000 "aborting.\n");
5001 goto err_out_free_res;
5002 }
5003 cp->casreg_len = casreg_len;
5004
5005 pci_save_state(pdev);
5006 cas_check_pci_invariants(cp);
5007 cas_hard_reset(cp);
5008 cas_reset(cp, 0);
5009 if (cas_check_invariants(cp))
5010 goto err_out_iounmap;
5011
5012 cp->init_block = (struct cas_init_block *)
5013 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5014 &cp->block_dvma);
5015 if (!cp->init_block) {
5016 printk(KERN_ERR PFX "Cannot allocate init block, "
5017 "aborting.\n");
5018 goto err_out_iounmap;
5019 }
5020
5021 for (i = 0; i < N_TX_RINGS; i++)
5022 cp->init_txds[i] = cp->init_block->txds[i];
5023
5024 for (i = 0; i < N_RX_DESC_RINGS; i++)
5025 cp->init_rxds[i] = cp->init_block->rxds[i];
5026
5027 for (i = 0; i < N_RX_COMP_RINGS; i++)
5028 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5029
5030 for (i = 0; i < N_RX_FLOWS; i++)
5031 skb_queue_head_init(&cp->rx_flows[i]);
5032
5033 dev->open = cas_open;
5034 dev->stop = cas_close;
5035 dev->hard_start_xmit = cas_start_xmit;
5036 dev->get_stats = cas_get_stats;
5037 dev->set_multicast_list = cas_set_multicast;
5038 dev->do_ioctl = cas_ioctl;
5039 dev->ethtool_ops = &cas_ethtool_ops;
5040 dev->tx_timeout = cas_tx_timeout;
5041 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5042 dev->change_mtu = cas_change_mtu;
5043 #ifdef USE_NAPI
5044 dev->poll = cas_poll;
5045 dev->weight = 64;
5046 #endif
5047 #ifdef CONFIG_NET_POLL_CONTROLLER
5048 dev->poll_controller = cas_netpoll;
5049 #endif
5050 dev->irq = pdev->irq;
5051 dev->dma = 0;
5052
5053 /* Cassini features. */
5054 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5055 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5056
5057 if (pci_using_dac)
5058 dev->features |= NETIF_F_HIGHDMA;
5059
5060 if (register_netdev(dev)) {
5061 printk(KERN_ERR PFX "Cannot register net device, "
5062 "aborting.\n");
5063 goto err_out_free_consistent;
5064 }
5065
5066 i = readl(cp->regs + REG_BIM_CFG);
5067 printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5068 "Ethernet[%d] ", dev->name,
5069 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5070 (i & BIM_CFG_32BIT) ? "32" : "64",
5071 (i & BIM_CFG_66MHZ) ? "66" : "33",
5072 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq);
5073
5074 for (i = 0; i < 6; i++)
5075 printk("%2.2x%c", dev->dev_addr[i],
5076 i == 5 ? ' ' : ':');
5077 printk("\n");
5078
5079 pci_set_drvdata(pdev, dev);
5080 cp->hw_running = 1;
5081 cas_entropy_reset(cp);
5082 cas_phy_init(cp);
5083 cas_begin_auto_negotiation(cp, NULL);
5084 return 0;
5085
5086 err_out_free_consistent:
5087 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5088 cp->init_block, cp->block_dvma);
5089
5090 err_out_iounmap:
5091 down(&cp->pm_sem);
5092 if (cp->hw_running)
5093 cas_shutdown(cp);
5094 up(&cp->pm_sem);
5095
5096 iounmap(cp->regs);
5097
5098
5099 err_out_free_res:
5100 pci_release_regions(pdev);
5101
5102 err_write_cacheline:
5103 /* Try to restore it in case the error occured after we
5104 * set it.
5105 */
5106 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5107
5108 err_out_free_netdev:
5109 free_netdev(dev);
5110
5111 err_out_disable_pdev:
5112 pci_disable_device(pdev);
5113 pci_set_drvdata(pdev, NULL);
5114 return -ENODEV;
5115 }
5116
5117 static void __devexit cas_remove_one(struct pci_dev *pdev)
5118 {
5119 struct net_device *dev = pci_get_drvdata(pdev);
5120 struct cas *cp;
5121 if (!dev)
5122 return;
5123
5124 cp = netdev_priv(dev);
5125 unregister_netdev(dev);
5126
5127 down(&cp->pm_sem);
5128 flush_scheduled_work();
5129 if (cp->hw_running)
5130 cas_shutdown(cp);
5131 up(&cp->pm_sem);
5132
5133 #if 1
5134 if (cp->orig_cacheline_size) {
5135 /* Restore the cache line size if we had modified
5136 * it.
5137 */
5138 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5139 cp->orig_cacheline_size);
5140 }
5141 #endif
5142 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5143 cp->init_block, cp->block_dvma);
5144 iounmap(cp->regs);
5145 free_netdev(dev);
5146 pci_release_regions(pdev);
5147 pci_disable_device(pdev);
5148 pci_set_drvdata(pdev, NULL);
5149 }
5150
5151 #ifdef CONFIG_PM
5152 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5153 {
5154 struct net_device *dev = pci_get_drvdata(pdev);
5155 struct cas *cp = netdev_priv(dev);
5156 unsigned long flags;
5157
5158 /* We hold the PM semaphore during entire driver
5159 * sleep time
5160 */
5161 down(&cp->pm_sem);
5162
5163 /* If the driver is opened, we stop the DMA */
5164 if (cp->opened) {
5165 netif_device_detach(dev);
5166
5167 cas_lock_all_save(cp, flags);
5168
5169 /* We can set the second arg of cas_reset to 0
5170 * because on resume, we'll call cas_init_hw with
5171 * its second arg set so that autonegotiation is
5172 * restarted.
5173 */
5174 cas_reset(cp, 0);
5175 cas_clean_rings(cp);
5176 cas_unlock_all_restore(cp, flags);
5177 }
5178
5179 if (cp->hw_running)
5180 cas_shutdown(cp);
5181
5182 return 0;
5183 }
5184
5185 static int cas_resume(struct pci_dev *pdev)
5186 {
5187 struct net_device *dev = pci_get_drvdata(pdev);
5188 struct cas *cp = netdev_priv(dev);
5189
5190 printk(KERN_INFO "%s: resuming\n", dev->name);
5191
5192 cas_hard_reset(cp);
5193 if (cp->opened) {
5194 unsigned long flags;
5195 cas_lock_all_save(cp, flags);
5196 cas_reset(cp, 0);
5197 cp->hw_running = 1;
5198 cas_clean_rings(cp);
5199 cas_init_hw(cp, 1);
5200 cas_unlock_all_restore(cp, flags);
5201
5202 netif_device_attach(dev);
5203 }
5204 up(&cp->pm_sem);
5205 return 0;
5206 }
5207 #endif /* CONFIG_PM */
5208
5209 static struct pci_driver cas_driver = {
5210 .name = DRV_MODULE_NAME,
5211 .id_table = cas_pci_tbl,
5212 .probe = cas_init_one,
5213 .remove = __devexit_p(cas_remove_one),
5214 #ifdef CONFIG_PM
5215 .suspend = cas_suspend,
5216 .resume = cas_resume
5217 #endif
5218 };
5219
5220 static int __init cas_init(void)
5221 {
5222 if (linkdown_timeout > 0)
5223 link_transition_timeout = linkdown_timeout * HZ;
5224 else
5225 link_transition_timeout = 0;
5226
5227 return pci_module_init(&cas_driver);
5228 }
5229
5230 static void __exit cas_cleanup(void)
5231 {
5232 pci_unregister_driver(&cas_driver);
5233 }
5234
5235 module_init(cas_init);
5236 module_exit(cas_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree