drivers/staging/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2008, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/version.h>
  24 #include <linux/kref.h>
  25
  26 #include <drm/drmP.h>
  27 #include "drm_global.h"
  28 #include "psb_drm.h"
  29 #include "psb_reg.h"
  30 #include "psb_intel_drv.h"
  31 #include "psb_gtt.h"
  32 #include "psb_powermgmt.h"
  33 #include "mrst.h"
  34
  35 /*Append new drm mode definition here, align with libdrm definition*/
  36 #define DRM_MODE_SCALE_NO_SCALE   2
  37
  38 extern struct ttm_bo_driver psb_ttm_bo_driver;
  39
  40 enum {
  41         CHIP_PSB_8108 = 0,
  42         CHIP_PSB_8109 = 1,
  43         CHIP_MRST_4100 = 2,
  44 };
  45
  46 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  47
  48 /*
  49  *Hardware bugfixes
  50  */
  51
  52 #define DRIVER_NAME "pvrsrvkm"
  53 #define DRIVER_DESC "drm driver for the Intel GMA500"
  54 #define DRIVER_AUTHOR "Intel Corporation"
  55
  56 #define PSB_DRM_DRIVER_DATE "2009-03-10"
  57 #define PSB_DRM_DRIVER_MAJOR 8
  58 #define PSB_DRM_DRIVER_MINOR 1
  59 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  60
  61 /*
  62  *TTM driver private offsets.
  63  */
  64
  65 #define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  66
  67 #define PSB_OBJECT_HASH_ORDER 13
  68 #define PSB_FILE_OBJECT_HASH_ORDER 12
  69 #define PSB_BO_HASH_ORDER 12
  70
  71 #define PSB_VDC_OFFSET           0x00000000
  72 #define PSB_VDC_SIZE             0x000080000
  73 #define MRST_MMIO_SIZE           0x0000C0000
  74 #define MDFLD_MMIO_SIZE          0x000100000
  75 #define PSB_SGX_SIZE             0x8000
  76 #define PSB_SGX_OFFSET           0x00040000
  77 #define MRST_SGX_OFFSET          0x00080000
  78 #define PSB_MMIO_RESOURCE        0
  79 #define PSB_GATT_RESOURCE        2
  80 #define PSB_GTT_RESOURCE         3
  81 #define PSB_GMCH_CTRL            0x52
  82 #define PSB_BSM                  0x5C
  83 #define _PSB_GMCH_ENABLED        0x4
  84 #define PSB_PGETBL_CTL           0x2020
  85 #define _PSB_PGETBL_ENABLED      0x00000001
  86 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  87 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  88 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  89 #define PSB_NUM_VALIDATE_BUFFERS 2048
  90
  91 /*
  92  *Flags for external memory type field.
  93  */
  94
  95 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
  96 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
  97 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
  98
  99 /*
 100  *PTE's and PDE's
 101  */
 102
 103 #define PSB_PDE_MASK              0x003FFFFF
 104 #define PSB_PDE_SHIFT             22
 105 #define PSB_PTE_SHIFT             12
 106
 107 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 108 #define PSB_PTE_WO                0x0002        /* Write only */
 109 #define PSB_PTE_RO                0x0004        /* Read only */
 110 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 111
 112 /*
 113  *VDC registers and bits
 114  */
 115 #define PSB_MSVDX_CLOCKGATING     0x2064
 116 #define PSB_TOPAZ_CLOCKGATING     0x2068
 117 #define PSB_HWSTAM                0x2098
 118 #define PSB_INSTPM                0x20C0
 119 #define PSB_INT_IDENTITY_R        0x20A4
 120 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 121 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 122 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 123 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 124 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 125 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 126 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 127 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 128 #define _MDFLD_MIPIA_FLAG         (1<<16)
 129 #define _MDFLD_MIPIC_FLAG         (1<<17)
 130 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 131 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 132 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 133
 134 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 135 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \
 136         _PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG)
 137 #define PSB_INT_IDENTITY_R        0x20A4
 138 #define PSB_INT_MASK_R            0x20A8
 139 #define PSB_INT_ENABLE_R          0x20A0
 140
 141 #define _PSB_MMU_ER_MASK      0x0001FF00
 142 #define _PSB_MMU_ER_HOST      (1 << 16)
 143 #define GPIOA                   0x5010
 144 #define GPIOB                   0x5014
 145 #define GPIOC                   0x5018
 146 #define GPIOD                   0x501c
 147 #define GPIOE                   0x5020
 148 #define GPIOF                   0x5024
 149 #define GPIOG                   0x5028
 150 #define GPIOH                   0x502c
 151 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 152 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 153 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 154 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 155 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 156 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 157 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 158 #define GPIO_DATA_DIR_MASK              (1 << 8)
 159 #define GPIO_DATA_DIR_IN                (0 << 9)
 160 #define GPIO_DATA_DIR_OUT               (1 << 9)
 161 #define GPIO_DATA_VAL_MASK              (1 << 10)
 162 #define GPIO_DATA_VAL_OUT               (1 << 11)
 163 #define GPIO_DATA_VAL_IN                (1 << 12)
 164 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 165
 166 #define VCLK_DIVISOR_VGA0   0x6000
 167 #define VCLK_DIVISOR_VGA1   0x6004
 168 #define VCLK_POST_DIV       0x6010
 169
 170 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 171 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 172 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 173 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 174 #define PSB_COMM_USER_IRQ (1024 >> 2)
 175 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 176 #define PSB_COMM_FW (2048 >> 2)
 177
 178 #define PSB_UIRQ_VISTEST               1
 179 #define PSB_UIRQ_OOM_REPLY             2
 180 #define PSB_UIRQ_FIRE_TA_REPLY         3
 181 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 182
 183 #define PSB_2D_SIZE (256*1024*1024)
 184 #define PSB_MAX_RELOC_PAGES 1024
 185
 186 #define PSB_LOW_REG_OFFS 0x0204
 187 #define PSB_HIGH_REG_OFFS 0x0600
 188
 189 #define PSB_NUM_VBLANKS 2
 190
 191
 192 #define PSB_2D_SIZE (256*1024*1024)
 193 #define PSB_MAX_RELOC_PAGES 1024
 194
 195 #define PSB_LOW_REG_OFFS 0x0204
 196 #define PSB_HIGH_REG_OFFS 0x0600
 197
 198 #define PSB_NUM_VBLANKS 2
 199 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 200 #define PSB_LID_DELAY (DRM_HZ / 10)
 201
 202 #define MDFLD_PNW_A0 0x00
 203 #define MDFLD_PNW_B0 0x04
 204 #define MDFLD_PNW_C0 0x08
 205
 206 #define PSB_PWR_STATE_ON                1
 207 #define PSB_PWR_STATE_OFF               2
 208
 209 #define PSB_PMPOLICY_NOPM               0
 210 #define PSB_PMPOLICY_CLOCKGATING        1
 211 #define PSB_PMPOLICY_POWERDOWN          2
 212
 213 #define PSB_PMSTATE_POWERUP             0
 214 #define PSB_PMSTATE_CLOCKGATED          1
 215 #define PSB_PMSTATE_POWERDOWN           2
 216 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 217 #define PSB_PCIx_MSI_DATA_LOC           0x98
 218
 219 struct opregion_header;
 220 struct opregion_acpi;
 221 struct opregion_swsci;
 222 struct opregion_asle;
 223
 224 struct psb_intel_opregion {
 225         struct opregion_header *header;
 226         struct opregion_acpi *acpi;
 227         struct opregion_swsci *swsci;
 228         struct opregion_asle *asle;
 229         int enabled;
 230 };
 231
 232
 233 struct drm_psb_private {
 234         struct drm_device *dev;
 235
 236         unsigned long chipset;
 237
 238         struct psb_gtt *pg;
 239
 240         /* GTT Memory manager */
 241         struct psb_gtt_mm *gtt_mm;
 242         struct page *scratch_page;
 243
 244         struct mutex gtt_mutex;
 245         struct resource *gtt_mem;       /* Our PCI resource */
 246         struct gtt_range *gtt_handles[GTT_MAX];
 247
 248         struct gtt_range *fb;           /* System frame buffer */
 249
 250         struct psb_mmu_driver *mmu;
 251         struct psb_mmu_pd *pf_pd;
 252
 253         /*
 254          * Register base
 255          */
 256
 257         uint8_t *sgx_reg;
 258         uint8_t *vdc_reg;
 259         uint32_t gatt_free_offset;
 260
 261         /*
 262          * Fencing / irq.
 263          */
 264
 265         uint32_t vdc_irq_mask;
 266         uint32_t pipestat[PSB_NUM_PIPE];
 267
 268         spinlock_t irqmask_lock;
 269
 270         /*
 271          * Power
 272          */
 273
 274         bool suspended;
 275         bool display_power;
 276         int display_count;
 277
 278         /*
 279          *Modesetting
 280          */
 281         struct psb_intel_mode_device mode_dev;
 282
 283         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 284         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 285         uint32_t num_pipe;
 286
 287         /*
 288          *Memory managers
 289          */
 290
 291         /*
 292         *OSPM info
 293         */
 294         uint32_t ospm_base;
 295
 296         /*
 297          * Sizes info
 298          */
 299
 300         struct drm_psb_sizes_arg sizes;
 301
 302         u32 fuse_reg_value;
 303         u32 video_device_fuse;
 304
 305         /* pci revision id for B0:D2:F0 */
 306         uint8_t platform_rev_id;
 307
 308         /*
 309          *LVDS info
 310          */
 311         int backlight_duty_cycle;       /* restore backlight to this value */
 312         bool panel_wants_dither;
 313         struct drm_display_mode *panel_fixed_mode;
 314         struct drm_display_mode *lfp_lvds_vbt_mode;
 315         struct drm_display_mode *sdvo_lvds_vbt_mode;
 316
 317         struct bdb_lvds_backlight *lvds_bl; /*LVDS backlight info from VBT*/
 318         struct psb_intel_i2c_chan *lvds_i2c_bus;
 319
 320         /* Feature bits from the VBIOS*/
 321         unsigned int int_tv_support:1;
 322         unsigned int lvds_dither:1;
 323         unsigned int lvds_vbt:1;
 324         unsigned int int_crt_support:1;
 325         unsigned int lvds_use_ssc:1;
 326         int lvds_ssc_freq;
 327         bool is_lvds_on;
 328         bool is_mipi_on;
 329
 330         unsigned int core_freq;
 331         uint32_t iLVDS_enable;
 332
 333         /*runtime PM state*/
 334         int rpm_enabled;
 335
 336         /* Moorestown specific */
 337         struct mrst_vbt vbt_data;
 338         struct mrst_gct_data gct_data;
 339
 340         /* Moorestown pipe config register value cache */
 341         uint32_t pipeconf;
 342         uint32_t pipeconf1;
 343         uint32_t pipeconf2;
 344
 345         /* Moorestown plane control register value cache */
 346         uint32_t dspcntr;
 347         uint32_t dspcntr1;
 348         uint32_t dspcntr2;
 349
 350         /*
 351          *Register state
 352          */
 353         uint32_t saveDSPACNTR;
 354         uint32_t saveDSPBCNTR;
 355         uint32_t savePIPEACONF;
 356         uint32_t savePIPEBCONF;
 357         uint32_t savePIPEASRC;
 358         uint32_t savePIPEBSRC;
 359         uint32_t saveFPA0;
 360         uint32_t saveFPA1;
 361         uint32_t saveDPLL_A;
 362         uint32_t saveDPLL_A_MD;
 363         uint32_t saveHTOTAL_A;
 364         uint32_t saveHBLANK_A;
 365         uint32_t saveHSYNC_A;
 366         uint32_t saveVTOTAL_A;
 367         uint32_t saveVBLANK_A;
 368         uint32_t saveVSYNC_A;
 369         uint32_t saveDSPASTRIDE;
 370         uint32_t saveDSPASIZE;
 371         uint32_t saveDSPAPOS;
 372         uint32_t saveDSPABASE;
 373         uint32_t saveDSPASURF;
 374         uint32_t saveFPB0;
 375         uint32_t saveFPB1;
 376         uint32_t saveDPLL_B;
 377         uint32_t saveDPLL_B_MD;
 378         uint32_t saveHTOTAL_B;
 379         uint32_t saveHBLANK_B;
 380         uint32_t saveHSYNC_B;
 381         uint32_t saveVTOTAL_B;
 382         uint32_t saveVBLANK_B;
 383         uint32_t saveVSYNC_B;
 384         uint32_t saveDSPBSTRIDE;
 385         uint32_t saveDSPBSIZE;
 386         uint32_t saveDSPBPOS;
 387         uint32_t saveDSPBBASE;
 388         uint32_t saveDSPBSURF;
 389         uint32_t saveVCLK_DIVISOR_VGA0;
 390         uint32_t saveVCLK_DIVISOR_VGA1;
 391         uint32_t saveVCLK_POST_DIV;
 392         uint32_t saveVGACNTRL;
 393         uint32_t saveADPA;
 394         uint32_t saveLVDS;
 395         uint32_t saveDVOA;
 396         uint32_t saveDVOB;
 397         uint32_t saveDVOC;
 398         uint32_t savePP_ON;
 399         uint32_t savePP_OFF;
 400         uint32_t savePP_CONTROL;
 401         uint32_t savePP_CYCLE;
 402         uint32_t savePFIT_CONTROL;
 403         uint32_t savePaletteA[256];
 404         uint32_t savePaletteB[256];
 405         uint32_t saveBLC_PWM_CTL2;
 406         uint32_t saveBLC_PWM_CTL;
 407         uint32_t saveCLOCKGATING;
 408         uint32_t saveDSPARB;
 409         uint32_t saveDSPATILEOFF;
 410         uint32_t saveDSPBTILEOFF;
 411         uint32_t saveDSPAADDR;
 412         uint32_t saveDSPBADDR;
 413         uint32_t savePFIT_AUTO_RATIOS;
 414         uint32_t savePFIT_PGM_RATIOS;
 415         uint32_t savePP_ON_DELAYS;
 416         uint32_t savePP_OFF_DELAYS;
 417         uint32_t savePP_DIVISOR;
 418         uint32_t saveBSM;
 419         uint32_t saveVBT;
 420         uint32_t saveBCLRPAT_A;
 421         uint32_t saveBCLRPAT_B;
 422         uint32_t saveDSPALINOFF;
 423         uint32_t saveDSPBLINOFF;
 424         uint32_t savePERF_MODE;
 425         uint32_t saveDSPFW1;
 426         uint32_t saveDSPFW2;
 427         uint32_t saveDSPFW3;
 428         uint32_t saveDSPFW4;
 429         uint32_t saveDSPFW5;
 430         uint32_t saveDSPFW6;
 431         uint32_t saveCHICKENBIT;
 432         uint32_t saveDSPACURSOR_CTRL;
 433         uint32_t saveDSPBCURSOR_CTRL;
 434         uint32_t saveDSPACURSOR_BASE;
 435         uint32_t saveDSPBCURSOR_BASE;
 436         uint32_t saveDSPACURSOR_POS;
 437         uint32_t saveDSPBCURSOR_POS;
 438         uint32_t save_palette_a[256];
 439         uint32_t save_palette_b[256];
 440         uint32_t saveOV_OVADD;
 441         uint32_t saveOV_OGAMC0;
 442         uint32_t saveOV_OGAMC1;
 443         uint32_t saveOV_OGAMC2;
 444         uint32_t saveOV_OGAMC3;
 445         uint32_t saveOV_OGAMC4;
 446         uint32_t saveOV_OGAMC5;
 447         uint32_t saveOVC_OVADD;
 448         uint32_t saveOVC_OGAMC0;
 449         uint32_t saveOVC_OGAMC1;
 450         uint32_t saveOVC_OGAMC2;
 451         uint32_t saveOVC_OGAMC3;
 452         uint32_t saveOVC_OGAMC4;
 453         uint32_t saveOVC_OGAMC5;
 454
 455         /* MSI reg save */
 456         uint32_t msi_addr;
 457         uint32_t msi_data;
 458
 459         /*
 460          * LID-Switch
 461          */
 462         spinlock_t lid_lock;
 463         struct timer_list lid_timer;
 464         struct psb_intel_opregion opregion;
 465         u32 *lid_state;
 466         u32 lid_last_state;
 467
 468         /*
 469          *Watchdog
 470          */
 471
 472         uint32_t apm_reg;
 473         uint16_t apm_base;
 474
 475         /*
 476          * Used for modifying backlight from
 477          * xrandr -- consider removing and using HAL instead
 478          */
 479         struct drm_property *backlight_property;
 480         uint32_t blc_adj1;
 481         uint32_t blc_adj2;
 482
 483         void * fbdev;
 484 };
 485
 486
 487 struct psb_mmu_driver;
 488
 489 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 490 extern int drm_pick_crtcs(struct drm_device *dev);
 491
 492 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 493 {
 494         return (struct drm_psb_private *) dev->dev_private;
 495 }
 496
 497 /*
 498  *MMU stuff.
 499  */
 500
 501 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 502                                         int trap_pagefaults,
 503                                         int invalid_type,
 504                                         struct drm_psb_private *dev_priv);
 505 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 506 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 507                                                  *driver);
 508 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 509                                uint32_t gtt_start, uint32_t gtt_pages);
 510 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 511                                            int trap_pagefaults,
 512                                            int invalid_type);
 513 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 514 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 515 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 516                                         unsigned long address,
 517                                         uint32_t num_pages);
 518 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 519                                        uint32_t start_pfn,
 520                                        unsigned long address,
 521                                        uint32_t num_pages, int type);
 522 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 523                                   unsigned long *pfn);
 524
 525 /*
 526  *Enable / disable MMU for different requestors.
 527  */
 528
 529
 530 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 531 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 532                                 unsigned long address, uint32_t num_pages,
 533                                 uint32_t desired_tile_stride,
 534                                 uint32_t hw_tile_stride, int type);
 535 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 536                                  unsigned long address, uint32_t num_pages,
 537                                  uint32_t desired_tile_stride,
 538                                  uint32_t hw_tile_stride);
 539 /*
 540  *psb_irq.c
 541  */
 542
 543 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 544 extern int psb_irq_enable_dpst(struct drm_device *dev);
 545 extern int psb_irq_disable_dpst(struct drm_device *dev);
 546 extern void psb_irq_preinstall(struct drm_device *dev);
 547 extern int psb_irq_postinstall(struct drm_device *dev);
 548 extern void psb_irq_uninstall(struct drm_device *dev);
 549 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 550 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 551
 552 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 553 extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence);
 554 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 555 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 556 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 557 void
 558 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 559
 560 void
 561 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 562
 563 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 564
 565 /*
 566  * psb_opregion.c
 567  */
 568 extern int psb_intel_opregion_init(struct drm_device *dev);
 569
 570 /*
 571  *psb_fb.c
 572  */
 573 extern int psbfb_probed(struct drm_device *dev);
 574 extern int psbfb_remove(struct drm_device *dev,
 575                         struct drm_framebuffer *fb);
 576 extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
 577                                struct drm_file *file_priv);
 578 extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
 579                               struct drm_file *file_priv);
 580 extern void *psbfb_vdc_reg(struct drm_device* dev);
 581
 582 /*
 583  * psb_2d.c
 584  */
 585 extern void psbfb_fillrect(struct fb_info *info,
 586                                         const struct fb_fillrect *rect);
 587 extern void psbfb_copyarea(struct fb_info *info,
 588                                         const struct fb_copyarea *region);
 589 extern void psbfb_imageblit(struct fb_info *info,
 590                                         const struct fb_image *image);
 591 extern int psbfb_sync(struct fb_info *info);
 592
 593 extern void psb_spank(struct drm_psb_private *dev_priv);
 594
 595 extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
 596                            unsigned size);
 597
 598 /*
 599  *psb_reset.c
 600  */
 601
 602 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 603 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 604 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 605
 606 /* modesetting */
 607 extern void psb_modeset_init(struct drm_device *dev);
 608 extern void psb_modeset_cleanup(struct drm_device *dev);
 609 extern int psb_fbdev_init(struct drm_device * dev);
 610
 611 /* psb_bl.c */
 612 int psb_backlight_init(struct drm_device *dev);
 613 void psb_backlight_exit(void);
 614 int psb_set_brightness(struct backlight_device *bd);
 615 int psb_get_brightness(struct backlight_device *bd);
 616 struct backlight_device * psb_get_backlight_device(void);
 617
 618 /* mrst_crtc.c */
 619 extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
 620
 621 /* mrst_lvds.c */
 622 extern void mrst_lvds_init(struct drm_device *dev,
 623                     struct psb_intel_mode_device *mode_dev);
 624
 625 /* psb_intel_lvds.c */
 626 extern void psb_intel_lvds_prepare(struct drm_encoder *encoder);
 627 extern void psb_intel_lvds_commit(struct drm_encoder *encoder);
 628 extern const struct drm_connector_helper_funcs
 629                                         psb_intel_lvds_connector_helper_funcs;
 630 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 631
 632
 633 /*
 634  *Debug print bits setting
 635  */
 636 #define PSB_D_GENERAL (1 << 0)
 637 #define PSB_D_INIT    (1 << 1)
 638 #define PSB_D_IRQ     (1 << 2)
 639 #define PSB_D_ENTRY   (1 << 3)
 640 /* debug the get H/V BP/FP count */
 641 #define PSB_D_HV      (1 << 4)
 642 #define PSB_D_DBI_BF  (1 << 5)
 643 #define PSB_D_PM      (1 << 6)
 644 #define PSB_D_RENDER  (1 << 7)
 645 #define PSB_D_REG     (1 << 8)
 646 #define PSB_D_MSVDX   (1 << 9)
 647 #define PSB_D_TOPAZ   (1 << 10)
 648
 649 #ifndef DRM_DEBUG_CODE
 650 /* To enable debug printout, set drm_psb_debug in psb_drv.c
 651  * to any combination of above print flags.
 652  */
 653 /* #define DRM_DEBUG_CODE 2 */
 654 #endif
 655
 656 extern int drm_psb_debug;
 657 extern int drm_psb_no_fb;
 658 extern int drm_idle_check_interval;
 659
 660 #define PSB_DEBUG_GENERAL(_fmt, _arg...) \
 661         PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
 662 #define PSB_DEBUG_INIT(_fmt, _arg...) \
 663         PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
 664 #define PSB_DEBUG_IRQ(_fmt, _arg...) \
 665         PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
 666 #define PSB_DEBUG_ENTRY(_fmt, _arg...) \
 667         PSB_DEBUG(PSB_D_ENTRY, _fmt, ##_arg)
 668 #define PSB_DEBUG_HV(_fmt, _arg...) \
 669         PSB_DEBUG(PSB_D_HV, _fmt, ##_arg)
 670 #define PSB_DEBUG_DBI_BF(_fmt, _arg...) \
 671         PSB_DEBUG(PSB_D_DBI_BF, _fmt, ##_arg)
 672 #define PSB_DEBUG_PM(_fmt, _arg...) \
 673         PSB_DEBUG(PSB_D_PM, _fmt, ##_arg)
 674 #define PSB_DEBUG_RENDER(_fmt, _arg...) \
 675         PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
 676 #define PSB_DEBUG_REG(_fmt, _arg...) \
 677         PSB_DEBUG(PSB_D_REG, _fmt, ##_arg)
 678 #define PSB_DEBUG_MSVDX(_fmt, _arg...) \
 679         PSB_DEBUG(PSB_D_MSVDX, _fmt, ##_arg)
 680 #define PSB_DEBUG_TOPAZ(_fmt, _arg...) \
 681         PSB_DEBUG(PSB_D_TOPAZ, _fmt, ##_arg)
 682
 683 #if DRM_DEBUG_CODE
 684 #define PSB_DEBUG(_flag, _fmt, _arg...)                                 \
 685         do {                                                            \
 686                 if (unlikely((_flag) & drm_psb_debug))                  \
 687                         printk(KERN_DEBUG                               \
 688                                "[psb:0x%02x:%s] " _fmt , _flag,         \
 689                                __func__ , ##_arg);                      \
 690         } while (0)
 691 #else
 692 #define PSB_DEBUG(_fmt, _arg...)     do { } while (0)
 693 #endif
 694
 695 /*
 696  *Utilities
 697  */
 698 #define DRM_DRIVER_PRIVATE_T struct drm_psb_private
 699
 700 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 701 {
 702         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 703         uint32_t ret_val = 0;
 704         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 705         pci_write_config_dword (pci_root, 0xD0, mcr);
 706         pci_read_config_dword (pci_root, 0xD4, &ret_val);
 707         pci_dev_put(pci_root);
 708         return ret_val;
 709 }
 710 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 711 {
 712         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 713         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 714         pci_write_config_dword (pci_root, 0xD4, value);
 715         pci_write_config_dword (pci_root, 0xD0, mcr);
 716         pci_dev_put(pci_root);
 717 }
 718 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 719 {
 720         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 721         uint32_t ret_val = 0;
 722         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 723         pci_write_config_dword (pci_root, 0xD0, mcr);
 724         pci_read_config_dword (pci_root, 0xD4, &ret_val);
 725         pci_dev_put(pci_root);
 726         return ret_val;
 727 }
 728 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 729 {
 730         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 731         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 732         pci_write_config_dword (pci_root, 0xD4, value);
 733         pci_write_config_dword (pci_root, 0xD0, mcr);
 734         pci_dev_put(pci_root);
 735 }
 736
 737 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 738 {
 739         struct drm_psb_private *dev_priv = dev->dev_private;
 740         int reg_val = ioread32(dev_priv->vdc_reg + (reg));
 741         PSB_DEBUG_REG("reg = 0x%x. reg_val = 0x%x. \n", reg, reg_val);
 742         return reg_val;
 743 }
 744
 745 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 746 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 747                                       uint32_t val)
 748 {
 749         struct drm_psb_private *dev_priv = dev->dev_private;
 750         if ((reg < 0x70084 || reg >0x70088) && (reg < 0xa000 || reg >0xa3ff))
 751                 PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
 752
 753         iowrite32((val), dev_priv->vdc_reg + (reg));
 754 }
 755
 756 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 757
 758 static inline void REGISTER_WRITE16(struct drm_device *dev,
 759                                         uint32_t reg, uint32_t val)
 760 {
 761         struct drm_psb_private *dev_priv = dev->dev_private;
 762
 763         PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
 764
 765         iowrite16((val), dev_priv->vdc_reg + (reg));
 766 }
 767
 768 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 769
 770 static inline void REGISTER_WRITE8(struct drm_device *dev,
 771                                        uint32_t reg, uint32_t val)
 772 {
 773         struct drm_psb_private *dev_priv = dev->dev_private;
 774
 775         PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
 776
 777         iowrite8((val), dev_priv->vdc_reg + (reg));
 778 }
 779
 780 #define REG_WRITE8(reg, val)     REGISTER_WRITE8(dev, (reg), (val))
 781
 782 #define PSB_ALIGN_TO(_val, _align) \
 783   (((_val) + ((_align) - 1)) & ~((_align) - 1))
 784 #define PSB_WVDC32(_val, _offs) \
 785   iowrite32(_val, dev_priv->vdc_reg + (_offs))
 786 #define PSB_RVDC32(_offs) \
 787   ioread32(dev_priv->vdc_reg + (_offs))
 788
 789 /* #define TRAP_SGX_PM_FAULT 1 */
 790 #ifdef TRAP_SGX_PM_FAULT
 791 #define PSB_RSGX32(_offs)                                       \
 792 ({                                                              \
 793     if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {          \
 794         printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \
 795                __FILE__, __LINE__);                             \
 796         mdelay(1000);                                           \
 797     }                                                           \
 798     ioread32(dev_priv->sgx_reg + (_offs));                      \
 799 })
 800 #else
 801 #define PSB_RSGX32(_offs)                                       \
 802   ioread32(dev_priv->sgx_reg + (_offs))
 803 #endif
 804 #define PSB_WSGX32(_val, _offs) \
 805   iowrite32(_val, dev_priv->sgx_reg + (_offs))
 806
 807 #define MSVDX_REG_DUMP 0
 808 #if MSVDX_REG_DUMP
 809
 810 #define PSB_WMSVDX32(_val, _offs) \
 811   printk("MSVDX: write %08x to reg 0x%08x\n", (unsigned int)(_val), (unsigned int)(_offs));\
 812   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 813 #define PSB_RMSVDX32(_offs) \
 814   ioread32(dev_priv->msvdx_reg + (_offs))
 815
 816 #else
 817
 818 #define PSB_WMSVDX32(_val, _offs) \
 819   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 820 #define PSB_RMSVDX32(_offs) \
 821   ioread32(dev_priv->msvdx_reg + (_offs))
 822
 823 #endif
 824
 825 #define PSB_ALPL(_val, _base)                   \
 826   (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
 827 #define PSB_ALPLM(_val, _base)                  \
 828   ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
 829
 830 #endif