arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/random.h>
  12 #include <linux/user-return-notifier.h>
  13 #include <linux/dmi.h>
  14 #include <linux/utsname.h>
  15 #include <trace/events/power.h>
  16 #include <linux/hw_breakpoint.h>
  17 #include <asm/system.h>
  18 #include <asm/apic.h>
  19 #include <asm/syscalls.h>
  20 #include <asm/idle.h>
  21 #include <asm/uaccess.h>
  22 #include <asm/i387.h>
  23 #include <asm/debugreg.h>
  24
  25 unsigned long idle_halt;
  26 EXPORT_SYMBOL(idle_halt);
  27 unsigned long idle_nomwait;
  28 EXPORT_SYMBOL(idle_nomwait);
  29
  30 struct kmem_cache *task_xstate_cachep;
  31 EXPORT_SYMBOL_GPL(task_xstate_cachep);
  32
  33 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  34 {
  35         int ret;
  36
  37         *dst = *src;
  38         if (fpu_allocated(&src->thread.fpu)) {
  39                 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
  40                 ret = fpu_alloc(&dst->thread.fpu);
  41                 if (ret)
  42                         return ret;
  43                 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
  44         }
  45         return 0;
  46 }
  47
  48 void free_thread_xstate(struct task_struct *tsk)
  49 {
  50         fpu_free(&tsk->thread.fpu);
  51 }
  52
  53 void free_thread_info(struct thread_info *ti)
  54 {
  55         free_thread_xstate(ti->task);
  56         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  57 }
  58
  59 void arch_task_cache_init(void)
  60 {
  61         task_xstate_cachep =
  62                 kmem_cache_create("task_xstate", xstate_size,
  63                                   __alignof__(union thread_xstate),
  64                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  65 }
  66
  67 /*
  68  * Free current thread data structures etc..
  69  */
  70 void exit_thread(void)
  71 {
  72         struct task_struct *me = current;
  73         struct thread_struct *t = &me->thread;
  74         unsigned long *bp = t->io_bitmap_ptr;
  75
  76         if (bp) {
  77                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  78
  79                 t->io_bitmap_ptr = NULL;
  80                 clear_thread_flag(TIF_IO_BITMAP);
  81                 /*
  82                  * Careful, clear this in the TSS too:
  83                  */
  84                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  85                 t->io_bitmap_max = 0;
  86                 put_cpu();
  87                 kfree(bp);
  88         }
  89 }
  90
  91 void show_regs(struct pt_regs *regs)
  92 {
  93         show_registers(regs);
  94         show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs),
  95                    regs->bp);
  96 }
  97
  98 void show_regs_common(void)
  99 {
 100         const char *board, *product;
 101
 102         board = dmi_get_system_info(DMI_BOARD_NAME);
 103         if (!board)
 104                 board = "";
 105         product = dmi_get_system_info(DMI_PRODUCT_NAME);
 106         if (!product)
 107                 product = "";
 108
 109         printk(KERN_CONT "\n");
 110         printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
 111                 current->pid, current->comm, print_tainted(),
 112                 init_utsname()->release,
 113                 (int)strcspn(init_utsname()->version, " "),
 114                 init_utsname()->version, board, product);
 115 }
 116
 117 void flush_thread(void)
 118 {
 119         struct task_struct *tsk = current;
 120
 121         flush_ptrace_hw_breakpoint(tsk);
 122         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 123         /*
 124          * Forget coprocessor state..
 125          */
 126         tsk->fpu_counter = 0;
 127         clear_fpu(tsk);
 128         clear_used_math();
 129 }
 130
 131 static void hard_disable_TSC(void)
 132 {
 133         write_cr4(read_cr4() | X86_CR4_TSD);
 134 }
 135
 136 void disable_TSC(void)
 137 {
 138         preempt_disable();
 139         if (!test_and_set_thread_flag(TIF_NOTSC))
 140                 /*
 141                  * Must flip the CPU state synchronously with
 142                  * TIF_NOTSC in the current running context.
 143                  */
 144                 hard_disable_TSC();
 145         preempt_enable();
 146 }
 147
 148 static void hard_enable_TSC(void)
 149 {
 150         write_cr4(read_cr4() & ~X86_CR4_TSD);
 151 }
 152
 153 static void enable_TSC(void)
 154 {
 155         preempt_disable();
 156         if (test_and_clear_thread_flag(TIF_NOTSC))
 157                 /*
 158                  * Must flip the CPU state synchronously with
 159                  * TIF_NOTSC in the current running context.
 160                  */
 161                 hard_enable_TSC();
 162         preempt_enable();
 163 }
 164
 165 int get_tsc_mode(unsigned long adr)
 166 {
 167         unsigned int val;
 168
 169         if (test_thread_flag(TIF_NOTSC))
 170                 val = PR_TSC_SIGSEGV;
 171         else
 172                 val = PR_TSC_ENABLE;
 173
 174         return put_user(val, (unsigned int __user *)adr);
 175 }
 176
 177 int set_tsc_mode(unsigned int val)
 178 {
 179         if (val == PR_TSC_SIGSEGV)
 180                 disable_TSC();
 181         else if (val == PR_TSC_ENABLE)
 182                 enable_TSC();
 183         else
 184                 return -EINVAL;
 185
 186         return 0;
 187 }
 188
 189 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 190                       struct tss_struct *tss)
 191 {
 192         struct thread_struct *prev, *next;
 193
 194         prev = &prev_p->thread;
 195         next = &next_p->thread;
 196
 197         if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
 198             test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
 199                 unsigned long debugctl = get_debugctlmsr();
 200
 201                 debugctl &= ~DEBUGCTLMSR_BTF;
 202                 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
 203                         debugctl |= DEBUGCTLMSR_BTF;
 204
 205                 update_debugctlmsr(debugctl);
 206         }
 207
 208         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 209             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 210                 /* prev and next are different */
 211                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 212                         hard_disable_TSC();
 213                 else
 214                         hard_enable_TSC();
 215         }
 216
 217         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 218                 /*
 219                  * Copy the relevant range of the IO bitmap.
 220                  * Normally this is 128 bytes or less:
 221                  */
 222                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 223                        max(prev->io_bitmap_max, next->io_bitmap_max));
 224         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 225                 /*
 226                  * Clear any possible leftover bits:
 227                  */
 228                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 229         }
 230         propagate_user_return_notify(prev_p, next_p);
 231 }
 232
 233 int sys_fork(struct pt_regs *regs)
 234 {
 235         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 236 }
 237
 238 /*
 239  * This is trivial, and on the face of it looks like it
 240  * could equally well be done in user mode.
 241  *
 242  * Not so, for quite unobvious reasons - register pressure.
 243  * In user mode vfork() cannot have a stack frame, and if
 244  * done by calling the "clone()" system call directly, you
 245  * do not have enough call-clobbered registers to hold all
 246  * the information you need.
 247  */
 248 int sys_vfork(struct pt_regs *regs)
 249 {
 250         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 251                        NULL, NULL);
 252 }
 253
 254 long
 255 sys_clone(unsigned long clone_flags, unsigned long newsp,
 256           void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
 257 {
 258         if (!newsp)
 259                 newsp = regs->sp;
 260         return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
 261 }
 262
 263 /*
 264  * This gets run with %si containing the
 265  * function to call, and %di containing
 266  * the "args".
 267  */
 268 extern void kernel_thread_helper(void);
 269
 270 /*
 271  * Create a kernel thread
 272  */
 273 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 274 {
 275         struct pt_regs regs;
 276
 277         memset(&regs, 0, sizeof(regs));
 278
 279         regs.si = (unsigned long) fn;
 280         regs.di = (unsigned long) arg;
 281
 282 #ifdef CONFIG_X86_32
 283         regs.ds = __USER_DS;
 284         regs.es = __USER_DS;
 285         regs.fs = __KERNEL_PERCPU;
 286         regs.gs = __KERNEL_STACK_CANARY;
 287 #else
 288         regs.ss = __KERNEL_DS;
 289 #endif
 290
 291         regs.orig_ax = -1;
 292         regs.ip = (unsigned long) kernel_thread_helper;
 293         regs.cs = __KERNEL_CS | get_kernel_rpl();
 294         regs.flags = X86_EFLAGS_IF | 0x2;
 295
 296         /* Ok, create the new process.. */
 297         return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 298 }
 299 EXPORT_SYMBOL(kernel_thread);
 300
 301 /*
 302  * sys_execve() executes a new program.
 303  */
 304 long sys_execve(char __user *name, char __user * __user *argv,
 305                 char __user * __user *envp, struct pt_regs *regs)
 306 {
 307         long error;
 308         char *filename;
 309
 310         filename = getname(name);
 311         error = PTR_ERR(filename);
 312         if (IS_ERR(filename))
 313                 return error;
 314         error = do_execve(filename, argv, envp, regs);
 315
 316 #ifdef CONFIG_X86_32
 317         if (error == 0) {
 318                 /* Make sure we don't return using sysenter.. */
 319                 set_thread_flag(TIF_IRET);
 320         }
 321 #endif
 322
 323         putname(filename);
 324         return error;
 325 }
 326
 327 /*
 328  * Idle related variables and functions
 329  */
 330 unsigned long boot_option_idle_override = 0;
 331 EXPORT_SYMBOL(boot_option_idle_override);
 332
 333 /*
 334  * Powermanagement idle function, if any..
 335  */
 336 void (*pm_idle)(void);
 337 EXPORT_SYMBOL(pm_idle);
 338
 339 #ifdef CONFIG_X86_32
 340 /*
 341  * This halt magic was a workaround for ancient floppy DMA
 342  * wreckage. It should be safe to remove.
 343  */
 344 static int hlt_counter;
 345 void disable_hlt(void)
 346 {
 347         hlt_counter++;
 348 }
 349 EXPORT_SYMBOL(disable_hlt);
 350
 351 void enable_hlt(void)
 352 {
 353         hlt_counter--;
 354 }
 355 EXPORT_SYMBOL(enable_hlt);
 356
 357 static inline int hlt_use_halt(void)
 358 {
 359         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 360 }
 361 #else
 362 static inline int hlt_use_halt(void)
 363 {
 364         return 1;
 365 }
 366 #endif
 367
 368 /*
 369  * We use this if we don't have any better
 370  * idle routine..
 371  */
 372 void default_idle(void)
 373 {
 374         if (hlt_use_halt()) {
 375                 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 376                 current_thread_info()->status &= ~TS_POLLING;
 377                 /*
 378                  * TS_POLLING-cleared state must be visible before we
 379                  * test NEED_RESCHED:
 380                  */
 381                 smp_mb();
 382
 383                 if (!need_resched())
 384                         safe_halt();    /* enables interrupts racelessly */
 385                 else
 386                         local_irq_enable();
 387                 current_thread_info()->status |= TS_POLLING;
 388         } else {
 389                 local_irq_enable();
 390                 /* loop is done by the caller */
 391                 cpu_relax();
 392         }
 393 }
 394 #ifdef CONFIG_APM_MODULE
 395 EXPORT_SYMBOL(default_idle);
 396 #endif
 397
 398 void stop_this_cpu(void *dummy)
 399 {
 400         local_irq_disable();
 401         /*
 402          * Remove this CPU:
 403          */
 404         set_cpu_online(smp_processor_id(), false);
 405         disable_local_APIC();
 406
 407         for (;;) {
 408                 if (hlt_works(smp_processor_id()))
 409                         halt();
 410         }
 411 }
 412
 413 static void do_nothing(void *unused)
 414 {
 415 }
 416
 417 /*
 418  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 419  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 420  * handler on SMP systems.
 421  *
 422  * Caller must have changed pm_idle to the new value before the call. Old
 423  * pm_idle value will not be used by any CPU after the return of this function.
 424  */
 425 void cpu_idle_wait(void)
 426 {
 427         smp_mb();
 428         /* kick all the CPUs so that they exit out of pm_idle */
 429         smp_call_function(do_nothing, NULL, 1);
 430 }
 431 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 432
 433 /*
 434  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 435  * which can obviate IPI to trigger checking of need_resched.
 436  * We execute MONITOR against need_resched and enter optimized wait state
 437  * through MWAIT. Whenever someone changes need_resched, we would be woken
 438  * up from MWAIT (without an IPI).
 439  *
 440  * New with Core Duo processors, MWAIT can take some hints based on CPU
 441  * capability.
 442  */
 443 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 444 {
 445         trace_power_start(POWER_CSTATE, (ax>>4)+1, smp_processor_id());
 446         if (!need_resched()) {
 447                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 448                         clflush((void *)&current_thread_info()->flags);
 449
 450                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 451                 smp_mb();
 452                 if (!need_resched())
 453                         __mwait(ax, cx);
 454         }
 455 }
 456
 457 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 458 static void mwait_idle(void)
 459 {
 460         if (!need_resched()) {
 461                 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 462                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 463                         clflush((void *)&current_thread_info()->flags);
 464
 465                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 466                 smp_mb();
 467                 if (!need_resched())
 468                         __sti_mwait(0, 0);
 469                 else
 470                         local_irq_enable();
 471         } else
 472                 local_irq_enable();
 473 }
 474
 475 /*
 476  * On SMP it's slightly faster (but much more power-consuming!)
 477  * to poll the ->work.need_resched flag instead of waiting for the
 478  * cross-CPU IPI to arrive. Use this option with caution.
 479  */
 480 static void poll_idle(void)
 481 {
 482         trace_power_start(POWER_CSTATE, 0, smp_processor_id());
 483         local_irq_enable();
 484         while (!need_resched())
 485                 cpu_relax();
 486         trace_power_end(0);
 487 }
 488
 489 /*
 490  * mwait selection logic:
 491  *
 492  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 493  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 494  * then depend on a clock divisor and current Pstate of the core. If
 495  * all cores of a processor are in halt state (C1) the processor can
 496  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 497  * happen.
 498  *
 499  * idle=mwait overrides this decision and forces the usage of mwait.
 500  */
 501 static int __cpuinitdata force_mwait;
 502
 503 #define MWAIT_INFO                      0x05
 504 #define MWAIT_ECX_EXTENDED_INFO         0x01
 505 #define MWAIT_EDX_C1                    0xf0
 506
 507 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 508 {
 509         u32 eax, ebx, ecx, edx;
 510
 511         if (force_mwait)
 512                 return 1;
 513
 514         if (c->cpuid_level < MWAIT_INFO)
 515                 return 0;
 516
 517         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 518         /* Check, whether EDX has extended info about MWAIT */
 519         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 520                 return 1;
 521
 522         /*
 523          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 524          * C1  supports MWAIT
 525          */
 526         return (edx & MWAIT_EDX_C1);
 527 }
 528
 529 /*
 530  * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e.
 531  * For more information see
 532  * - Erratum #400 for NPT family 0xf and family 0x10 CPUs
 533  * - Erratum #365 for family 0x11 (not affected because C1e not in use)
 534  */
 535 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 536 {
 537         u64 val;
 538         if (c->x86_vendor != X86_VENDOR_AMD)
 539                 goto no_c1e_idle;
 540
 541         /* Family 0x0f models < rev F do not have C1E */
 542         if (c->x86 == 0x0F && c->x86_model >= 0x40)
 543                 return 1;
 544
 545         if (c->x86 == 0x10) {
 546                 /*
 547                  * check OSVW bit for CPUs that are not affected
 548                  * by erratum #400
 549                  */
 550                 if (cpu_has(c, X86_FEATURE_OSVW)) {
 551                         rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
 552                         if (val >= 2) {
 553                                 rdmsrl(MSR_AMD64_OSVW_STATUS, val);
 554                                 if (!(val & BIT(1)))
 555                                         goto no_c1e_idle;
 556                         }
 557                 }
 558                 return 1;
 559         }
 560
 561 no_c1e_idle:
 562         return 0;
 563 }
 564
 565 static cpumask_var_t c1e_mask;
 566 static int c1e_detected;
 567
 568 void c1e_remove_cpu(int cpu)
 569 {
 570         if (c1e_mask != NULL)
 571                 cpumask_clear_cpu(cpu, c1e_mask);
 572 }
 573
 574 /*
 575  * C1E aware idle routine. We check for C1E active in the interrupt
 576  * pending message MSR. If we detect C1E, then we handle it the same
 577  * way as C3 power states (local apic timer and TSC stop)
 578  */
 579 static void c1e_idle(void)
 580 {
 581         if (need_resched())
 582                 return;
 583
 584         if (!c1e_detected) {
 585                 u32 lo, hi;
 586
 587                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 588                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 589                         c1e_detected = 1;
 590                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 591                                 mark_tsc_unstable("TSC halt in AMD C1E");
 592                         printk(KERN_INFO "System has AMD C1E enabled\n");
 593                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 594                 }
 595         }
 596
 597         if (c1e_detected) {
 598                 int cpu = smp_processor_id();
 599
 600                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 601                         cpumask_set_cpu(cpu, c1e_mask);
 602                         /*
 603                          * Force broadcast so ACPI can not interfere.
 604                          */
 605                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 606                                            &cpu);
 607                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 608                                cpu);
 609                 }
 610                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 611
 612                 default_idle();
 613
 614                 /*
 615                  * The switch back from broadcast mode needs to be
 616                  * called with interrupts disabled.
 617                  */
 618                  local_irq_disable();
 619                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 620                  local_irq_enable();
 621         } else
 622                 default_idle();
 623 }
 624
 625 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 626 {
 627 #ifdef CONFIG_SMP
 628         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 629                 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
 630                         " performance may degrade.\n");
 631         }
 632 #endif
 633         if (pm_idle)
 634                 return;
 635
 636         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 637                 /*
 638                  * One CPU supports mwait => All CPUs supports mwait
 639                  */
 640                 printk(KERN_INFO "using mwait in idle threads.\n");
 641                 pm_idle = mwait_idle;
 642         } else if (check_c1e_idle(c)) {
 643                 printk(KERN_INFO "using C1E aware idle routine\n");
 644                 pm_idle = c1e_idle;
 645         } else
 646                 pm_idle = default_idle;
 647 }
 648
 649 void __init init_c1e_mask(void)
 650 {
 651         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 652         if (pm_idle == c1e_idle)
 653                 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 654 }
 655
 656 static int __init idle_setup(char *str)
 657 {
 658         if (!str)
 659                 return -EINVAL;
 660
 661         if (!strcmp(str, "poll")) {
 662                 printk("using polling idle threads.\n");
 663                 pm_idle = poll_idle;
 664         } else if (!strcmp(str, "mwait"))
 665                 force_mwait = 1;
 666         else if (!strcmp(str, "halt")) {
 667                 /*
 668                  * When the boot option of idle=halt is added, halt is
 669                  * forced to be used for CPU idle. In such case CPU C2/C3
 670                  * won't be used again.
 671                  * To continue to load the CPU idle driver, don't touch
 672                  * the boot_option_idle_override.
 673                  */
 674                 pm_idle = default_idle;
 675                 idle_halt = 1;
 676                 return 0;
 677         } else if (!strcmp(str, "nomwait")) {
 678                 /*
 679                  * If the boot option of "idle=nomwait" is added,
 680                  * it means that mwait will be disabled for CPU C2/C3
 681                  * states. In such case it won't touch the variable
 682                  * of boot_option_idle_override.
 683                  */
 684                 idle_nomwait = 1;
 685                 return 0;
 686         } else
 687                 return -1;
 688
 689         boot_option_idle_override = 1;
 690         return 0;
 691 }
 692 early_param("idle", idle_setup);
 693
 694 unsigned long arch_align_stack(unsigned long sp)
 695 {
 696         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 697                 sp -= get_random_int() % 8192;
 698         return sp & ~0xf;
 699 }
 700
 701 unsigned long arch_randomize_brk(struct mm_struct *mm)
 702 {
 703         unsigned long range_end = mm->brk + 0x02000000;
 704         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 705 }
 706