drivers/net/bna/bfa_ioc_ct.c

   1 /*
   2  * Linux network driver for Brocade Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15  * All rights reserved
  16  * www.brocade.com
  17  */
  18
  19 #include "bfa_ioc.h"
  20 #include "cna.h"
  21 #include "bfi.h"
  22 #include "bfi_ctreg.h"
  23 #include "bfa_defs.h"
  24
  25 #define bfa_ioc_ct_sync_pos(__ioc)      \
  26                 ((u32) (1 << bfa_ioc_pcifn(__ioc)))
  27 #define BFA_IOC_SYNC_REQD_SH            16
  28 #define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
  29 #define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
  30 #define bfa_ioc_ct_get_sync_reqd(__val) (__val >> BFA_IOC_SYNC_REQD_SH)
  31 #define bfa_ioc_ct_sync_reqd_pos(__ioc) \
  32                 (bfa_ioc_ct_sync_pos(__ioc) << BFA_IOC_SYNC_REQD_SH)
  33
  34 /*
  35  * forward declarations
  36  */
  37 static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);
  38 static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
  39 static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
  40 static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
  41 static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
  42 static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);
  43 static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
  44 static bool bfa_ioc_ct_sync_start(struct bfa_ioc *ioc);
  45 static void bfa_ioc_ct_sync_join(struct bfa_ioc *ioc);
  46 static void bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc);
  47 static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc);
  48 static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);
  49 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode);
  50
  51 static struct bfa_ioc_hwif nw_hwif_ct;
  52
  53 /**
  54  * Called from bfa_ioc_attach() to map asic specific calls.
  55  */
  56 void
  57 bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc)
  58 {
  59         nw_hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
  60         nw_hwif_ct.ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
  61         nw_hwif_ct.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
  62         nw_hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
  63         nw_hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
  64         nw_hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
  65         nw_hwif_ct.ioc_notify_fail = bfa_ioc_ct_notify_fail;
  66         nw_hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
  67         nw_hwif_ct.ioc_sync_start = bfa_ioc_ct_sync_start;
  68         nw_hwif_ct.ioc_sync_join = bfa_ioc_ct_sync_join;
  69         nw_hwif_ct.ioc_sync_leave = bfa_ioc_ct_sync_leave;
  70         nw_hwif_ct.ioc_sync_ack = bfa_ioc_ct_sync_ack;
  71         nw_hwif_ct.ioc_sync_complete = bfa_ioc_ct_sync_complete;
  72
  73         ioc->ioc_hwif = &nw_hwif_ct;
  74 }
  75
  76 /**
  77  * Return true if firmware of current driver matches the running firmware.
  78  */
  79 static bool
  80 bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
  81 {
  82         enum bfi_ioc_state ioc_fwstate;
  83         u32 usecnt;
  84         struct bfi_ioc_image_hdr fwhdr;
  85
  86         /**
  87          * If bios boot (flash based) -- do not increment usage count
  88          */
  89         if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
  90                                                 BFA_IOC_FWIMG_MINSZ)
  91                 return true;
  92
  93         bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
  94         usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
  95
  96         /**
  97          * If usage count is 0, always return TRUE.
  98          */
  99         if (usecnt == 0) {
 100                 writel(1, ioc->ioc_regs.ioc_usage_reg);
 101                 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 102                 writel(0, ioc->ioc_regs.ioc_fail_sync);
 103                 return true;
 104         }
 105
 106         ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
 107
 108         /**
 109          * Use count cannot be non-zero and chip in uninitialized state.
 110          */
 111         BUG_ON(!(ioc_fwstate != BFI_IOC_UNINIT));
 112
 113         /**
 114          * Check if another driver with a different firmware is active
 115          */
 116         bfa_nw_ioc_fwver_get(ioc, &fwhdr);
 117         if (!bfa_nw_ioc_fwver_cmp(ioc, &fwhdr)) {
 118                 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 119                 return false;
 120         }
 121
 122         /**
 123          * Same firmware version. Increment the reference count.
 124          */
 125         usecnt++;
 126         writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
 127         bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 128         return true;
 129 }
 130
 131 static void
 132 bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
 133 {
 134         u32 usecnt;
 135
 136         /**
 137          * If bios boot (flash based) -- do not decrement usage count
 138          */
 139         if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
 140                                                 BFA_IOC_FWIMG_MINSZ)
 141                 return;
 142
 143         /**
 144          * decrement usage count
 145          */
 146         bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
 147         usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
 148         BUG_ON(!(usecnt > 0));
 149
 150         usecnt--;
 151         writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
 152
 153         bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 154 }
 155
 156 /**
 157  * Notify other functions on HB failure.
 158  */
 159 static void
 160 bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc)
 161 {
 162         if (ioc->cna) {
 163                 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
 164                 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
 165                 /* Wait for halt to take effect */
 166                 readl(ioc->ioc_regs.ll_halt);
 167                 readl(ioc->ioc_regs.alt_ll_halt);
 168         } else {
 169                 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
 170                 readl(ioc->ioc_regs.err_set);
 171         }
 172 }
 173
 174 /**
 175  * Host to LPU mailbox message addresses
 176  */
 177 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
 178         { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
 179         { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
 180         { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
 181         { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
 182 };
 183
 184 /**
 185  * Host <-> LPU mailbox command/status registers - port 0
 186  */
 187 static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
 188         { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT },
 189         { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT },
 190         { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT },
 191         { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT }
 192 };
 193
 194 /**
 195  * Host <-> LPU mailbox command/status registers - port 1
 196  */
 197 static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
 198         { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT },
 199         { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT },
 200         { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT },
 201         { HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT }
 202 };
 203
 204 static void
 205 bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
 206 {
 207         void __iomem *rb;
 208         int             pcifn = bfa_ioc_pcifn(ioc);
 209
 210         rb = bfa_ioc_bar0(ioc);
 211
 212         ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
 213         ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
 214         ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
 215
 216         if (ioc->port_id == 0) {
 217                 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
 218                 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
 219                 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
 220                 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
 221                 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
 222                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
 223                 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
 224         } else {
 225                 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
 226                 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
 227                 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
 228                 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
 229                 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
 230                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
 231                 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
 232         }
 233
 234         /*
 235          * PSS control registers
 236          */
 237         ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
 238         ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
 239         ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG);
 240         ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG);
 241
 242         /*
 243          * IOC semaphore registers and serialization
 244          */
 245         ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
 246         ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
 247         ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
 248         ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
 249         ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
 250
 251         /**
 252          * sram memory access
 253          */
 254         ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
 255         ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
 256
 257         /*
 258          * err set reg : for notification of hb failure in fcmode
 259          */
 260         ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
 261 }
 262
 263 /**
 264  * Initialize IOC to port mapping.
 265  */
 266
 267 #define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
 268 static void
 269 bfa_ioc_ct_map_port(struct bfa_ioc *ioc)
 270 {
 271         void __iomem *rb = ioc->pcidev.pci_bar_kva;
 272         u32     r32;
 273
 274         /**
 275          * For catapult, base port id on personality register and IOC type
 276          */
 277         r32 = readl(rb + FNC_PERS_REG);
 278         r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
 279         ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
 280
 281 }
 282
 283 /**
 284  * Set interrupt mode for a function: INTX or MSIX
 285  */
 286 static void
 287 bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix)
 288 {
 289         void __iomem *rb = ioc->pcidev.pci_bar_kva;
 290         u32     r32, mode;
 291
 292         r32 = readl(rb + FNC_PERS_REG);
 293
 294         mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
 295                 __F0_INTX_STATUS;
 296
 297         /**
 298          * If already in desired mode, do not change anything
 299          */
 300         if (!msix && mode)
 301                 return;
 302
 303         if (msix)
 304                 mode = __F0_INTX_STATUS_MSIX;
 305         else
 306                 mode = __F0_INTX_STATUS_INTA;
 307
 308         r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
 309         r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
 310
 311         writel(r32, rb + FNC_PERS_REG);
 312 }
 313
 314 /**
 315  * Cleanup hw semaphore and usecnt registers
 316  */
 317 static void
 318 bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
 319 {
 320         if (ioc->cna) {
 321                 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
 322                 writel(0, ioc->ioc_regs.ioc_usage_reg);
 323                 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 324         }
 325
 326         /*
 327          * Read the hw sem reg to make sure that it is locked
 328          * before we clear it. If it is not locked, writing 1
 329          * will lock it instead of clearing it.
 330          */
 331         readl(ioc->ioc_regs.ioc_sem_reg);
 332         bfa_nw_ioc_hw_sem_release(ioc);
 333 }
 334
 335 /**
 336  * Synchronized IOC failure processing routines
 337  */
 338 static bool
 339 bfa_ioc_ct_sync_start(struct bfa_ioc *ioc)
 340 {
 341         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 342         u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
 343
 344         /*
 345          * Driver load time.  If the sync required bit for this PCI fn
 346          * is set, it is due to an unclean exit by the driver for this
 347          * PCI fn in the previous incarnation. Whoever comes here first
 348          * should clean it up, no matter which PCI fn.
 349          */
 350
 351         if (sync_reqd & bfa_ioc_ct_sync_pos(ioc)) {
 352                 writel(0, ioc->ioc_regs.ioc_fail_sync);
 353                 writel(1, ioc->ioc_regs.ioc_usage_reg);
 354                 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
 355                 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
 356                 return true;
 357         }
 358
 359         return bfa_ioc_ct_sync_complete(ioc);
 360 }
 361 /**
 362  * Synchronized IOC failure processing routines
 363  */
 364 static void
 365 bfa_ioc_ct_sync_join(struct bfa_ioc *ioc)
 366 {
 367         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 368         u32 sync_pos = bfa_ioc_ct_sync_reqd_pos(ioc);
 369
 370         writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
 371 }
 372
 373 static void
 374 bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc)
 375 {
 376         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 377         u32 sync_msk = bfa_ioc_ct_sync_reqd_pos(ioc) |
 378                                         bfa_ioc_ct_sync_pos(ioc);
 379
 380         writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
 381 }
 382
 383 static void
 384 bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc)
 385 {
 386         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 387
 388         writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);
 389 }
 390
 391 static bool
 392 bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc)
 393 {
 394         u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
 395         u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
 396         u32 sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
 397         u32 tmp_ackd;
 398
 399         if (sync_ackd == 0)
 400                 return true;
 401
 402         /**
 403          * The check below is to see whether any other PCI fn
 404          * has reinitialized the ASIC (reset sync_ackd bits)
 405          * and failed again while this IOC was waiting for hw
 406          * semaphore (in bfa_iocpf_sm_semwait()).
 407          */
 408         tmp_ackd = sync_ackd;
 409         if ((sync_reqd &  bfa_ioc_ct_sync_pos(ioc)) &&
 410                         !(sync_ackd & bfa_ioc_ct_sync_pos(ioc)))
 411                 sync_ackd |= bfa_ioc_ct_sync_pos(ioc);
 412
 413         if (sync_reqd == sync_ackd) {
 414                 writel(bfa_ioc_ct_clear_sync_ackd(r32),
 415                                 ioc->ioc_regs.ioc_fail_sync);
 416                 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
 417                 writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
 418                 return true;
 419         }
 420
 421         /**
 422          * If another PCI fn reinitialized and failed again while
 423          * this IOC was waiting for hw sem, the sync_ackd bit for
 424          * this IOC need to be set again to allow reinitialization.
 425          */
 426         if (tmp_ackd != sync_ackd)
 427                 writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
 428
 429         return false;
 430 }
 431
 432 static enum bfa_status
 433 bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode)
 434 {
 435         u32     pll_sclk, pll_fclk, r32;
 436
 437         pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
 438                 __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
 439                 __APP_PLL_312_JITLMT0_1(3U) |
 440                 __APP_PLL_312_CNTLMT0_1(1U);
 441         pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
 442                 __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
 443                 __APP_PLL_425_JITLMT0_1(3U) |
 444                 __APP_PLL_425_CNTLMT0_1(1U);
 445         if (fcmode) {
 446                 writel(0, (rb + OP_MODE));
 447                 writel(__APP_EMS_CMLCKSEL |
 448                                 __APP_EMS_REFCKBUFEN2 |
 449                                 __APP_EMS_CHANNEL_SEL,
 450                                 (rb + ETH_MAC_SER_REG));
 451         } else {
 452                 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
 453                 writel(__APP_EMS_REFCKBUFEN1,
 454                                 (rb + ETH_MAC_SER_REG));
 455         }
 456         writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
 457         writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
 458         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
 459         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
 460         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
 461         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
 462         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
 463         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
 464         writel(pll_sclk |
 465                 __APP_PLL_312_LOGIC_SOFT_RESET,
 466                 rb + APP_PLL_312_CTL_REG);
 467         writel(pll_fclk |
 468                 __APP_PLL_425_LOGIC_SOFT_RESET,
 469                 rb + APP_PLL_425_CTL_REG);
 470         writel(pll_sclk |
 471                 __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE,
 472                 rb + APP_PLL_312_CTL_REG);
 473         writel(pll_fclk |
 474                 __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE,
 475                 rb + APP_PLL_425_CTL_REG);
 476         readl(rb + HOSTFN0_INT_MSK);
 477         udelay(2000);
 478         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
 479         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
 480         writel(pll_sclk |
 481                 __APP_PLL_312_ENABLE,
 482                 rb + APP_PLL_312_CTL_REG);
 483         writel(pll_fclk |
 484                 __APP_PLL_425_ENABLE,
 485                 rb + APP_PLL_425_CTL_REG);
 486         if (!fcmode) {
 487                 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
 488                 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
 489         }
 490         r32 = readl((rb + PSS_CTL_REG));
 491         r32 &= ~__PSS_LMEM_RESET;
 492         writel(r32, (rb + PSS_CTL_REG));
 493         udelay(1000);
 494         if (!fcmode) {
 495                 writel(0, (rb + PMM_1T_RESET_REG_P0));
 496                 writel(0, (rb + PMM_1T_RESET_REG_P1));
 497         }
 498
 499         writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
 500         udelay(1000);
 501         r32 = readl((rb + MBIST_STAT_REG));
 502         writel(0, (rb + MBIST_CTL_REG));
 503         return BFA_STATUS_OK;
 504 }