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[JFFS2] Prevent return of initialised variable in jffs2_init_acl_post()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / smc91x.h
blob729fd28c08b56f071050f30723bc2256730d7f36
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_BFIN)
59
60 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
61 #define RPC_LSA_DEFAULT RPC_LED_100_10
62 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
63
64 # if defined (CONFIG_BFIN561_EZKIT)
65 #define SMC_CAN_USE_8BIT 0
66 #define SMC_CAN_USE_16BIT 1
67 #define SMC_CAN_USE_32BIT 1
68 #define SMC_IO_SHIFT 0
69 #define SMC_NOWAIT 1
70 #define SMC_USE_BFIN_DMA 0
71
72
73 #define SMC_inw(a, r) readw((a) + (r))
74 #define SMC_outw(v, a, r) writew(v, (a) + (r))
75 #define SMC_inl(a, r) readl((a) + (r))
76 #define SMC_outl(v, a, r) writel(v, (a) + (r))
77 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
78 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
79 # else
80 #define SMC_CAN_USE_8BIT 0
81 #define SMC_CAN_USE_16BIT 1
82 #define SMC_CAN_USE_32BIT 0
83 #define SMC_IO_SHIFT 0
84 #define SMC_NOWAIT 1
85 #define SMC_USE_BFIN_DMA 0
86
87
88 #define SMC_inw(a, r) readw((a) + (r))
89 #define SMC_outw(v, a, r) writew(v, (a) + (r))
90 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
91 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
92 # endif
93 /* check if the mac in reg is valid */
94 #define SMC_GET_MAC_ADDR(addr) \
95 do { \
96 unsigned int __v; \
97 __v = SMC_inw(ioaddr, ADDR0_REG); \
98 addr[0] = __v; addr[1] = __v >> 8; \
99 __v = SMC_inw(ioaddr, ADDR1_REG); \
100 addr[2] = __v; addr[3] = __v >> 8; \
101 __v = SMC_inw(ioaddr, ADDR2_REG); \
102 addr[4] = __v; addr[5] = __v >> 8; \
103 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
104 random_ether_addr(addr); \
105 } \
106 } while (0)
107 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
108
109 /* We can only do 16-bit reads and writes in the static memory space. */
110 #define SMC_CAN_USE_8BIT 0
111 #define SMC_CAN_USE_16BIT 1
112 #define SMC_CAN_USE_32BIT 0
113 #define SMC_NOWAIT 1
114
115 #define SMC_IO_SHIFT 0
116
117 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
118 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
119 #define SMC_insw(a, r, p, l) \
120 do { \
121 unsigned long __port = (a) + (r); \
122 u16 *__p = (u16 *)(p); \
123 int __l = (l); \
124 insw(__port, __p, __l); \
125 while (__l > 0) { \
126 *__p = swab16(*__p); \
127 __p++; \
128 __l--; \
129 } \
130 } while (0)
131 #define SMC_outsw(a, r, p, l) \
132 do { \
133 unsigned long __port = (a) + (r); \
134 u16 *__p = (u16 *)(p); \
135 int __l = (l); \
136 while (__l > 0) { \
137 /* Believe it or not, the swab isn't needed. */ \
138 outw( /* swab16 */ (*__p++), __port); \
139 __l--; \
140 } \
141 } while (0)
142 #define SMC_IRQ_FLAGS (0)
143
144 #elif defined(CONFIG_SA1100_PLEB)
145 /* We can only do 16-bit reads and writes in the static memory space. */
146 #define SMC_CAN_USE_8BIT 1
147 #define SMC_CAN_USE_16BIT 1
148 #define SMC_CAN_USE_32BIT 0
149 #define SMC_IO_SHIFT 0
150 #define SMC_NOWAIT 1
151
152 #define SMC_inb(a, r) readb((a) + (r))
153 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
154 #define SMC_inw(a, r) readw((a) + (r))
155 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
156 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
157 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
158 #define SMC_outw(v, a, r) writew(v, (a) + (r))
159 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
160
161 #define SMC_IRQ_FLAGS (0)
162
163 #elif defined(CONFIG_SA1100_ASSABET)
164
165 #include <asm/arch/neponset.h>
166
167 /* We can only do 8-bit reads and writes in the static memory space. */
168 #define SMC_CAN_USE_8BIT 1
169 #define SMC_CAN_USE_16BIT 0
170 #define SMC_CAN_USE_32BIT 0
171 #define SMC_NOWAIT 1
172
173 /* The first two address lines aren't connected... */
174 #define SMC_IO_SHIFT 2
175
176 #define SMC_inb(a, r) readb((a) + (r))
177 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
178 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
179 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
180
181 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
182
183 #define SMC_CAN_USE_8BIT 0
184 #define SMC_CAN_USE_16BIT 1
185 #define SMC_CAN_USE_32BIT 0
186 #define SMC_IO_SHIFT 0
187 #define SMC_NOWAIT 1
188
189 #define SMC_inw(a, r) readw((a) + (r))
190 #define SMC_outw(v, a, r) writew(v, (a) + (r))
191 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
192 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
193
194 #elif defined(CONFIG_ARCH_INNOKOM) || \
195 defined(CONFIG_MACH_MAINSTONE) || \
196 defined(CONFIG_ARCH_PXA_IDP) || \
197 defined(CONFIG_ARCH_RAMSES)
198
199 #define SMC_CAN_USE_8BIT 1
200 #define SMC_CAN_USE_16BIT 1
201 #define SMC_CAN_USE_32BIT 1
202 #define SMC_IO_SHIFT 0
203 #define SMC_NOWAIT 1
204 #define SMC_USE_PXA_DMA 1
205
206 #define SMC_inb(a, r) readb((a) + (r))
207 #define SMC_inw(a, r) readw((a) + (r))
208 #define SMC_inl(a, r) readl((a) + (r))
209 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
210 #define SMC_outl(v, a, r) writel(v, (a) + (r))
211 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
212 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
213
214 /* We actually can't write halfwords properly if not word aligned */
215 static inline void
216 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
217 {
218 if (reg & 2) {
219 unsigned int v = val << 16;
220 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
221 writel(v, ioaddr + (reg & ~2));
222 } else {
223 writew(val, ioaddr + reg);
224 }
225 }
226
227 #elif defined(CONFIG_ARCH_OMAP)
228
229 /* We can only do 16-bit reads and writes in the static memory space. */
230 #define SMC_CAN_USE_8BIT 0
231 #define SMC_CAN_USE_16BIT 1
232 #define SMC_CAN_USE_32BIT 0
233 #define SMC_IO_SHIFT 0
234 #define SMC_NOWAIT 1
235
236 #define SMC_inw(a, r) readw((a) + (r))
237 #define SMC_outw(v, a, r) writew(v, (a) + (r))
238 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
239 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
240
241 #include <asm/mach-types.h>
242 #include <asm/arch/cpu.h>
243
244 #define SMC_IRQ_FLAGS (( \
245 machine_is_omap_h2() \
246 || machine_is_omap_h3() \
247 || machine_is_omap_h4() \
248 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
249 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
250
251
252 #elif defined(CONFIG_SH_SH4202_MICRODEV)
253
254 #define SMC_CAN_USE_8BIT 0
255 #define SMC_CAN_USE_16BIT 1
256 #define SMC_CAN_USE_32BIT 0
257
258 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
259 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
260 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
261 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
262 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
263 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
264 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
265 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
266 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
267 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
268
269 #define SMC_IRQ_FLAGS (0)
270
271 #elif defined(CONFIG_ISA)
272
273 #define SMC_CAN_USE_8BIT 1
274 #define SMC_CAN_USE_16BIT 1
275 #define SMC_CAN_USE_32BIT 0
276
277 #define SMC_inb(a, r) inb((a) + (r))
278 #define SMC_inw(a, r) inw((a) + (r))
279 #define SMC_outb(v, a, r) outb(v, (a) + (r))
280 #define SMC_outw(v, a, r) outw(v, (a) + (r))
281 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
282 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
283
284 #elif defined(CONFIG_SUPERH)
285
286 #ifdef CONFIG_SOLUTION_ENGINE
287 #define SMC_IRQ_FLAGS (0)
288 #define SMC_CAN_USE_8BIT 0
289 #define SMC_CAN_USE_16BIT 1
290 #define SMC_CAN_USE_32BIT 0
291 #define SMC_IO_SHIFT 0
292 #define SMC_NOWAIT 1
293
294 #define SMC_inw(a, r) inw((a) + (r))
295 #define SMC_outw(v, a, r) outw(v, (a) + (r))
296 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
297 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
298
299 #else /* BOARDS */
300
301 #define SMC_CAN_USE_8BIT 1
302 #define SMC_CAN_USE_16BIT 1
303 #define SMC_CAN_USE_32BIT 0
304
305 #define SMC_inb(a, r) inb((a) + (r))
306 #define SMC_inw(a, r) inw((a) + (r))
307 #define SMC_outb(v, a, r) outb(v, (a) + (r))
308 #define SMC_outw(v, a, r) outw(v, (a) + (r))
309 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
310 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
311
312 #endif /* BOARDS */
313
314 #elif defined(CONFIG_M32R)
315
316 #define SMC_CAN_USE_8BIT 0
317 #define SMC_CAN_USE_16BIT 1
318 #define SMC_CAN_USE_32BIT 0
319
320 #define SMC_inb(a, r) inb(((u32)a) + (r))
321 #define SMC_inw(a, r) inw(((u32)a) + (r))
322 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
323 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
324 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
325 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
326
327 #define SMC_IRQ_FLAGS (0)
328
329 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
330 #define RPC_LSB_DEFAULT RPC_LED_100_10
331
332 #elif defined(CONFIG_MACH_LPD79520) \
333 || defined(CONFIG_MACH_LPD7A400) \
334 || defined(CONFIG_MACH_LPD7A404)
335
336 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
337 * way that the CPU handles chip selects and the way that the SMC chip
338 * expects the chip select to operate. Refer to
339 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
340 * IOBARRIER is a byte, in order that we read the least-common
341 * denominator. It would be wasteful to read 32 bits from an 8-bit
342 * accessible region.
343 *
344 * There is no explicit protection against interrupts intervening
345 * between the writew and the IOBARRIER. In SMC ISR there is a
346 * preamble that performs an IOBARRIER in the extremely unlikely event
347 * that the driver interrupts itself between a writew to the chip an
348 * the IOBARRIER that follows *and* the cache is large enough that the
349 * first off-chip access while handing the interrupt is to the SMC
350 * chip. Other devices in the same address space as the SMC chip must
351 * be aware of the potential for trouble and perform a similar
352 * IOBARRIER on entry to their ISR.
353 */
354
355 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
356
357 #define SMC_CAN_USE_8BIT 0
358 #define SMC_CAN_USE_16BIT 1
359 #define SMC_CAN_USE_32BIT 0
360 #define SMC_NOWAIT 0
361 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
362
363 #define SMC_inw(a,r)\
364 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
365 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
366
367 #define SMC_insw LPD7_SMC_insw
368 static inline void LPD7_SMC_insw (unsigned char* a, int r,
369 unsigned char* p, int l)
370 {
371 unsigned short* ps = (unsigned short*) p;
372 while (l-- > 0) {
373 *ps++ = readw (a + r);
374 LPD7X_IOBARRIER;
375 }
376 }
377
378 #define SMC_outsw LPD7_SMC_outsw
379 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
380 unsigned char* p, int l)
381 {
382 unsigned short* ps = (unsigned short*) p;
383 while (l-- > 0) {
384 writew (*ps++, a + r);
385 LPD7X_IOBARRIER;
386 }
387 }
388
389 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
390
391 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
392 #define RPC_LSB_DEFAULT RPC_LED_100_10
393
394 #elif defined(CONFIG_SOC_AU1X00)
395
396 #include <au1xxx.h>
397
398 /* We can only do 16-bit reads and writes in the static memory space. */
399 #define SMC_CAN_USE_8BIT 0
400 #define SMC_CAN_USE_16BIT 1
401 #define SMC_CAN_USE_32BIT 0
402 #define SMC_IO_SHIFT 0
403 #define SMC_NOWAIT 1
404
405 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
406 #define SMC_insw(a, r, p, l) \
407 do { \
408 unsigned long _a = (unsigned long)((a) + (r)); \
409 int _l = (l); \
410 u16 *_p = (u16 *)(p); \
411 while (_l-- > 0) \
412 *_p++ = au_readw(_a); \
413 } while(0)
414 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
415 #define SMC_outsw(a, r, p, l) \
416 do { \
417 unsigned long _a = (unsigned long)((a) + (r)); \
418 int _l = (l); \
419 const u16 *_p = (const u16 *)(p); \
420 while (_l-- > 0) \
421 au_writew(*_p++ , _a); \
422 } while(0)
423
424 #define SMC_IRQ_FLAGS (0)
425
426 #elif defined(CONFIG_ARCH_VERSATILE)
427
428 #define SMC_CAN_USE_8BIT 1
429 #define SMC_CAN_USE_16BIT 1
430 #define SMC_CAN_USE_32BIT 1
431 #define SMC_NOWAIT 1
432
433 #define SMC_inb(a, r) readb((a) + (r))
434 #define SMC_inw(a, r) readw((a) + (r))
435 #define SMC_inl(a, r) readl((a) + (r))
436 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
437 #define SMC_outw(v, a, r) writew(v, (a) + (r))
438 #define SMC_outl(v, a, r) writel(v, (a) + (r))
439 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
440 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
441
442 #define SMC_IRQ_FLAGS (0)
443
444 #else
445
446 #define SMC_CAN_USE_8BIT 1
447 #define SMC_CAN_USE_16BIT 1
448 #define SMC_CAN_USE_32BIT 1
449 #define SMC_NOWAIT 1
450
451 #define SMC_inb(a, r) readb((a) + (r))
452 #define SMC_inw(a, r) readw((a) + (r))
453 #define SMC_inl(a, r) readl((a) + (r))
454 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
455 #define SMC_outw(v, a, r) writew(v, (a) + (r))
456 #define SMC_outl(v, a, r) writel(v, (a) + (r))
457 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
458 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
459
460 #define RPC_LSA_DEFAULT RPC_LED_100_10
461 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
462
463 #endif
464
465
466 /* store this information for the driver.. */
467 struct smc_local {
468 /*
469 * If I have to wait until memory is available to send a
470 * packet, I will store the skbuff here, until I get the
471 * desired memory. Then, I'll send it out and free it.
472 */
473 struct sk_buff *pending_tx_skb;
474 struct tasklet_struct tx_task;
475
476 /* version/revision of the SMC91x chip */
477 int version;
478
479 /* Contains the current active transmission mode */
480 int tcr_cur_mode;
481
482 /* Contains the current active receive mode */
483 int rcr_cur_mode;
484
485 /* Contains the current active receive/phy mode */
486 int rpc_cur_mode;
487 int ctl_rfduplx;
488 int ctl_rspeed;
489
490 u32 msg_enable;
491 u32 phy_type;
492 struct mii_if_info mii;
493
494 /* work queue */
495 struct work_struct phy_configure;
496 struct net_device *dev;
497 int work_pending;
498
499 spinlock_t lock;
500
501 #ifdef SMC_USE_PXA_DMA
502 /* DMA needs the physical address of the chip */
503 u_long physaddr;
504 struct device *device;
505 #endif
506 void __iomem *base;
507 void __iomem *datacs;
508 };
509
510
511 #ifdef SMC_USE_PXA_DMA
512 /*
513 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
514 * always happening in irq context so no need to worry about races. TX is
515 * different and probably not worth it for that reason, and not as critical
516 * as RX which can overrun memory and lose packets.
517 */
518 #include <linux/dma-mapping.h>
519 #include <asm/dma.h>
520 #include <asm/arch/pxa-regs.h>
521
522 #ifdef SMC_insl
523 #undef SMC_insl
524 #define SMC_insl(a, r, p, l) \
525 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
526 static inline void
527 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
528 u_char *buf, int len)
529 {
530 u_long physaddr = lp->physaddr;
531 dma_addr_t dmabuf;
532
533 /* fallback if no DMA available */
534 if (dma == (unsigned char)-1) {
535 readsl(ioaddr + reg, buf, len);
536 return;
537 }
538
539 /* 64 bit alignment is required for memory to memory DMA */
540 if ((long)buf & 4) {
541 *((u32 *)buf) = SMC_inl(ioaddr, reg);
542 buf += 4;
543 len--;
544 }
545
546 len *= 4;
547 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
548 DCSR(dma) = DCSR_NODESC;
549 DTADR(dma) = dmabuf;
550 DSADR(dma) = physaddr + reg;
551 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
552 DCMD_WIDTH4 | (DCMD_LENGTH & len));
553 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
554 while (!(DCSR(dma) & DCSR_STOPSTATE))
555 cpu_relax();
556 DCSR(dma) = 0;
557 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
558 }
559 #endif
560
561 #ifdef SMC_insw
562 #undef SMC_insw
563 #define SMC_insw(a, r, p, l) \
564 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
565 static inline void
566 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
567 u_char *buf, int len)
568 {
569 u_long physaddr = lp->physaddr;
570 dma_addr_t dmabuf;
571
572 /* fallback if no DMA available */
573 if (dma == (unsigned char)-1) {
574 readsw(ioaddr + reg, buf, len);
575 return;
576 }
577
578 /* 64 bit alignment is required for memory to memory DMA */
579 while ((long)buf & 6) {
580 *((u16 *)buf) = SMC_inw(ioaddr, reg);
581 buf += 2;
582 len--;
583 }
584
585 len *= 2;
586 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
587 DCSR(dma) = DCSR_NODESC;
588 DTADR(dma) = dmabuf;
589 DSADR(dma) = physaddr + reg;
590 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
591 DCMD_WIDTH2 | (DCMD_LENGTH & len));
592 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
593 while (!(DCSR(dma) & DCSR_STOPSTATE))
594 cpu_relax();
595 DCSR(dma) = 0;
596 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
597 }
598 #endif
599
600 static void
601 smc_pxa_dma_irq(int dma, void *dummy)
602 {
603 DCSR(dma) = 0;
604 }
605 #endif /* SMC_USE_PXA_DMA */
606
607
608 /*
609 * Everything a particular hardware setup needs should have been defined
610 * at this point. Add stubs for the undefined cases, mainly to avoid
611 * compilation warnings since they'll be optimized away, or to prevent buggy
612 * use of them.
613 */
614
615 #if ! SMC_CAN_USE_32BIT
616 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
617 #define SMC_outl(x, ioaddr, reg) BUG()
618 #define SMC_insl(a, r, p, l) BUG()
619 #define SMC_outsl(a, r, p, l) BUG()
620 #endif
621
622 #if !defined(SMC_insl) || !defined(SMC_outsl)
623 #define SMC_insl(a, r, p, l) BUG()
624 #define SMC_outsl(a, r, p, l) BUG()
625 #endif
626
627 #if ! SMC_CAN_USE_16BIT
628
629 /*
630 * Any 16-bit access is performed with two 8-bit accesses if the hardware
631 * can't do it directly. Most registers are 16-bit so those are mandatory.
632 */
633 #define SMC_outw(x, ioaddr, reg) \
634 do { \
635 unsigned int __val16 = (x); \
636 SMC_outb( __val16, ioaddr, reg ); \
637 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
638 } while (0)
639 #define SMC_inw(ioaddr, reg) \
640 ({ \
641 unsigned int __val16; \
642 __val16 = SMC_inb( ioaddr, reg ); \
643 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
644 __val16; \
645 })
646
647 #define SMC_insw(a, r, p, l) BUG()
648 #define SMC_outsw(a, r, p, l) BUG()
649
650 #endif
651
652 #if !defined(SMC_insw) || !defined(SMC_outsw)
653 #define SMC_insw(a, r, p, l) BUG()
654 #define SMC_outsw(a, r, p, l) BUG()
655 #endif
656
657 #if ! SMC_CAN_USE_8BIT
658 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
659 #define SMC_outb(x, ioaddr, reg) BUG()
660 #define SMC_insb(a, r, p, l) BUG()
661 #define SMC_outsb(a, r, p, l) BUG()
662 #endif
663
664 #if !defined(SMC_insb) || !defined(SMC_outsb)
665 #define SMC_insb(a, r, p, l) BUG()
666 #define SMC_outsb(a, r, p, l) BUG()
667 #endif
668
669 #ifndef SMC_CAN_USE_DATACS
670 #define SMC_CAN_USE_DATACS 0
671 #endif
672
673 #ifndef SMC_IO_SHIFT
674 #define SMC_IO_SHIFT 0
675 #endif
676
677 #ifndef SMC_IRQ_FLAGS
678 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
679 #endif
680
681 #ifndef SMC_INTERRUPT_PREAMBLE
682 #define SMC_INTERRUPT_PREAMBLE
683 #endif
684
685
686 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
687 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
688 #define SMC_DATA_EXTENT (4)
689
690 /*
691 . Bank Select Register:
692 .
693 . yyyy yyyy 0000 00xx
694 . xx = bank number
695 . yyyy yyyy = 0x33, for identification purposes.
696 */
697 #define BANK_SELECT (14 << SMC_IO_SHIFT)
698
699
700 // Transmit Control Register
701 /* BANK 0 */
702 #define TCR_REG SMC_REG(0x0000, 0)
703 #define TCR_ENABLE 0x0001 // When 1 we can transmit
704 #define TCR_LOOP 0x0002 // Controls output pin LBK
705 #define TCR_FORCOL 0x0004 // When 1 will force a collision
706 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
707 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
708 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
709 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
710 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
711 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
712 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
713
714 #define TCR_CLEAR 0 /* do NOTHING */
715 /* the default settings for the TCR register : */
716 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
717
718
719 // EPH Status Register
720 /* BANK 0 */
721 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
722 #define ES_TX_SUC 0x0001 // Last TX was successful
723 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
724 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
725 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
726 #define ES_16COL 0x0010 // 16 Collisions Reached
727 #define ES_SQET 0x0020 // Signal Quality Error Test
728 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
729 #define ES_TXDEFR 0x0080 // Transmit Deferred
730 #define ES_LATCOL 0x0200 // Late collision detected on last tx
731 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
732 #define ES_EXC_DEF 0x0800 // Excessive Deferral
733 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
734 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
735 #define ES_TXUNRN 0x8000 // Tx Underrun
736
737
738 // Receive Control Register
739 /* BANK 0 */
740 #define RCR_REG SMC_REG(0x0004, 0)
741 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
742 #define RCR_PRMS 0x0002 // Enable promiscuous mode
743 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
744 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
745 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
746 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
747 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
748 #define RCR_SOFTRST 0x8000 // resets the chip
749
750 /* the normal settings for the RCR register : */
751 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
752 #define RCR_CLEAR 0x0 // set it to a base state
753
754
755 // Counter Register
756 /* BANK 0 */
757 #define COUNTER_REG SMC_REG(0x0006, 0)
758
759
760 // Memory Information Register
761 /* BANK 0 */
762 #define MIR_REG SMC_REG(0x0008, 0)
763
764
765 // Receive/Phy Control Register
766 /* BANK 0 */
767 #define RPC_REG SMC_REG(0x000A, 0)
768 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
769 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
770 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
771 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
772 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
773 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
774 #define RPC_LED_RES (0x01) // LED = Reserved
775 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
776 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
777 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
778 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
779 #define RPC_LED_TX (0x06) // LED = TX packet occurred
780 #define RPC_LED_RX (0x07) // LED = RX packet occurred
781
782 #ifndef RPC_LSA_DEFAULT
783 #define RPC_LSA_DEFAULT RPC_LED_100
784 #endif
785 #ifndef RPC_LSB_DEFAULT
786 #define RPC_LSB_DEFAULT RPC_LED_FD
787 #endif
788
789 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
790
791
792 /* Bank 0 0x0C is reserved */
793
794 // Bank Select Register
795 /* All Banks */
796 #define BSR_REG 0x000E
797
798
799 // Configuration Reg
800 /* BANK 1 */
801 #define CONFIG_REG SMC_REG(0x0000, 1)
802 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
803 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
804 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
805 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
806
807 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
808 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
809
810
811 // Base Address Register
812 /* BANK 1 */
813 #define BASE_REG SMC_REG(0x0002, 1)
814
815
816 // Individual Address Registers
817 /* BANK 1 */
818 #define ADDR0_REG SMC_REG(0x0004, 1)
819 #define ADDR1_REG SMC_REG(0x0006, 1)
820 #define ADDR2_REG SMC_REG(0x0008, 1)
821
822
823 // General Purpose Register
824 /* BANK 1 */
825 #define GP_REG SMC_REG(0x000A, 1)
826
827
828 // Control Register
829 /* BANK 1 */
830 #define CTL_REG SMC_REG(0x000C, 1)
831 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
832 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
833 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
834 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
835 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
836 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
837 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
838 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
839
840
841 // MMU Command Register
842 /* BANK 2 */
843 #define MMU_CMD_REG SMC_REG(0x0000, 2)
844 #define MC_BUSY 1 // When 1 the last release has not completed
845 #define MC_NOP (0<<5) // No Op
846 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
847 #define MC_RESET (2<<5) // Reset MMU to initial state
848 #define MC_REMOVE (3<<5) // Remove the current rx packet
849 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
850 #define MC_FREEPKT (5<<5) // Release packet in PNR register
851 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
852 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
853
854
855 // Packet Number Register
856 /* BANK 2 */
857 #define PN_REG SMC_REG(0x0002, 2)
858
859
860 // Allocation Result Register
861 /* BANK 2 */
862 #define AR_REG SMC_REG(0x0003, 2)
863 #define AR_FAILED 0x80 // Alocation Failed
864
865
866 // TX FIFO Ports Register
867 /* BANK 2 */
868 #define TXFIFO_REG SMC_REG(0x0004, 2)
869 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
870
871 // RX FIFO Ports Register
872 /* BANK 2 */
873 #define RXFIFO_REG SMC_REG(0x0005, 2)
874 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
875
876 #define FIFO_REG SMC_REG(0x0004, 2)
877
878 // Pointer Register
879 /* BANK 2 */
880 #define PTR_REG SMC_REG(0x0006, 2)
881 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
882 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
883 #define PTR_READ 0x2000 // When 1 the operation is a read
884
885
886 // Data Register
887 /* BANK 2 */
888 #define DATA_REG SMC_REG(0x0008, 2)
889
890
891 // Interrupt Status/Acknowledge Register
892 /* BANK 2 */
893 #define INT_REG SMC_REG(0x000C, 2)
894
895
896 // Interrupt Mask Register
897 /* BANK 2 */
898 #define IM_REG SMC_REG(0x000D, 2)
899 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
900 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
901 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
902 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
903 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
904 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
905 #define IM_TX_INT 0x02 // Transmit Interrupt
906 #define IM_RCV_INT 0x01 // Receive Interrupt
907
908
909 // Multicast Table Registers
910 /* BANK 3 */
911 #define MCAST_REG1 SMC_REG(0x0000, 3)
912 #define MCAST_REG2 SMC_REG(0x0002, 3)
913 #define MCAST_REG3 SMC_REG(0x0004, 3)
914 #define MCAST_REG4 SMC_REG(0x0006, 3)
915
916
917 // Management Interface Register (MII)
918 /* BANK 3 */
919 #define MII_REG SMC_REG(0x0008, 3)
920 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
921 #define MII_MDOE 0x0008 // MII Output Enable
922 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
923 #define MII_MDI 0x0002 // MII Input, pin MDI
924 #define MII_MDO 0x0001 // MII Output, pin MDO
925
926
927 // Revision Register
928 /* BANK 3 */
929 /* ( hi: chip id low: rev # ) */
930 #define REV_REG SMC_REG(0x000A, 3)
931
932
933 // Early RCV Register
934 /* BANK 3 */
935 /* this is NOT on SMC9192 */
936 #define ERCV_REG SMC_REG(0x000C, 3)
937 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
938 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
939
940
941 // External Register
942 /* BANK 7 */
943 #define EXT_REG SMC_REG(0x0000, 7)
944
945
946 #define CHIP_9192 3
947 #define CHIP_9194 4
948 #define CHIP_9195 5
949 #define CHIP_9196 6
950 #define CHIP_91100 7
951 #define CHIP_91100FD 8
952 #define CHIP_91111FD 9
953
954 static const char * chip_ids[ 16 ] = {
955 NULL, NULL, NULL,
956 /* 3 */ "SMC91C90/91C92",
957 /* 4 */ "SMC91C94",
958 /* 5 */ "SMC91C95",
959 /* 6 */ "SMC91C96",
960 /* 7 */ "SMC91C100",
961 /* 8 */ "SMC91C100FD",
962 /* 9 */ "SMC91C11xFD",
963 NULL, NULL, NULL,
964 NULL, NULL, NULL};
965
966
967 /*
968 . Receive status bits
969 */
970 #define RS_ALGNERR 0x8000
971 #define RS_BRODCAST 0x4000
972 #define RS_BADCRC 0x2000
973 #define RS_ODDFRAME 0x1000
974 #define RS_TOOLONG 0x0800
975 #define RS_TOOSHORT 0x0400
976 #define RS_MULTICAST 0x0001
977 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
978
979
980 /*
981 * PHY IDs
982 * LAN83C183 == LAN91C111 Internal PHY
983 */
984 #define PHY_LAN83C183 0x0016f840
985 #define PHY_LAN83C180 0x02821c50
986
987 /*
988 * PHY Register Addresses (LAN91C111 Internal PHY)
989 *
990 * Generic PHY registers can be found in <linux/mii.h>
991 *
992 * These phy registers are specific to our on-board phy.
993 */
994
995 // PHY Configuration Register 1
996 #define PHY_CFG1_REG 0x10
997 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
998 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
999 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1000 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1001 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1002 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1003 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1004 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1005 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1006 #define PHY_CFG1_TLVL_MASK 0x003C
1007 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1008
1009
1010 // PHY Configuration Register 2
1011 #define PHY_CFG2_REG 0x11
1012 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1013 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1014 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1015 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1016
1017 // PHY Status Output (and Interrupt status) Register
1018 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1019 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1020 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1021 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1022 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1023 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1024 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1025 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1026 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1027 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1028 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1029
1030 // PHY Interrupt/Status Mask Register
1031 #define PHY_MASK_REG 0x13 // Interrupt Mask
1032 // Uses the same bit definitions as PHY_INT_REG
1033
1034
1035 /*
1036 * SMC91C96 ethernet config and status registers.
1037 * These are in the "attribute" space.
1038 */
1039 #define ECOR 0x8000
1040 #define ECOR_RESET 0x80
1041 #define ECOR_LEVEL_IRQ 0x40
1042 #define ECOR_WR_ATTRIB 0x04
1043 #define ECOR_ENABLE 0x01
1044
1045 #define ECSR 0x8002
1046 #define ECSR_IOIS8 0x20
1047 #define ECSR_PWRDWN 0x04
1048 #define ECSR_INT 0x02
1049
1050 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1051
1052
1053 /*
1054 * Macros to abstract register access according to the data bus
1055 * capabilities. Please use those and not the in/out primitives.
1056 * Note: the following macros do *not* select the bank -- this must
1057 * be done separately as needed in the main code. The SMC_REG() macro
1058 * only uses the bank argument for debugging purposes (when enabled).
1059 *
1060 * Note: despite inline functions being safer, everything leading to this
1061 * should preferably be macros to let BUG() display the line number in
1062 * the core source code since we're interested in the top call site
1063 * not in any inline function location.
1064 */
1065
1066 #if SMC_DEBUG > 0
1067 #define SMC_REG(reg, bank) \
1068 ({ \
1069 int __b = SMC_CURRENT_BANK(); \
1070 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1071 printk( "%s: bank reg screwed (0x%04x)\n", \
1072 CARDNAME, __b ); \
1073 BUG(); \
1074 } \
1075 reg<<SMC_IO_SHIFT; \
1076 })
1077 #else
1078 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1079 #endif
1080
1081 /*
1082 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1083 * aligned to a 32 bit boundary. I tell you that does exist!
1084 * Fortunately the affected register accesses can be easily worked around
1085 * since we can write zeroes to the preceeding 16 bits without adverse
1086 * effects and use a 32-bit access.
1087 *
1088 * Enforce it on any 32-bit capable setup for now.
1089 */
1090 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1091
1092 #define SMC_GET_PN() \
1093 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1094 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1095
1096 #define SMC_SET_PN(x) \
1097 do { \
1098 if (SMC_MUST_ALIGN_WRITE) \
1099 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1100 else if (SMC_CAN_USE_8BIT) \
1101 SMC_outb(x, ioaddr, PN_REG); \
1102 else \
1103 SMC_outw(x, ioaddr, PN_REG); \
1104 } while (0)
1105
1106 #define SMC_GET_AR() \
1107 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1108 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1109
1110 #define SMC_GET_TXFIFO() \
1111 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1112 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1113
1114 #define SMC_GET_RXFIFO() \
1115 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1116 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1117
1118 #define SMC_GET_INT() \
1119 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1120 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1121
1122 #define SMC_ACK_INT(x) \
1123 do { \
1124 if (SMC_CAN_USE_8BIT) \
1125 SMC_outb(x, ioaddr, INT_REG); \
1126 else { \
1127 unsigned long __flags; \
1128 int __mask; \
1129 local_irq_save(__flags); \
1130 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1131 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1132 local_irq_restore(__flags); \
1133 } \
1134 } while (0)
1135
1136 #define SMC_GET_INT_MASK() \
1137 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1138 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1139
1140 #define SMC_SET_INT_MASK(x) \
1141 do { \
1142 if (SMC_CAN_USE_8BIT) \
1143 SMC_outb(x, ioaddr, IM_REG); \
1144 else \
1145 SMC_outw((x) << 8, ioaddr, INT_REG); \
1146 } while (0)
1147
1148 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1149
1150 #define SMC_SELECT_BANK(x) \
1151 do { \
1152 if (SMC_MUST_ALIGN_WRITE) \
1153 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1154 else \
1155 SMC_outw(x, ioaddr, BANK_SELECT); \
1156 } while (0)
1157
1158 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1159
1160 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1161
1162 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1163
1164 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1165
1166 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1167
1168 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1169
1170 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1171
1172 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1173
1174 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1175
1176 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1177
1178 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1179
1180 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1181
1182 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1183
1184 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1185
1186 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1187
1188 #define SMC_SET_PTR(x) \
1189 do { \
1190 if (SMC_MUST_ALIGN_WRITE) \
1191 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1192 else \
1193 SMC_outw(x, ioaddr, PTR_REG); \
1194 } while (0)
1195
1196 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1197
1198 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1199
1200 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1201
1202 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1203
1204 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1205
1206 #define SMC_SET_RPC(x) \
1207 do { \
1208 if (SMC_MUST_ALIGN_WRITE) \
1209 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1210 else \
1211 SMC_outw(x, ioaddr, RPC_REG); \
1212 } while (0)
1213
1214 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1215
1216 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1217
1218 #ifndef SMC_GET_MAC_ADDR
1219 #define SMC_GET_MAC_ADDR(addr) \
1220 do { \
1221 unsigned int __v; \
1222 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1223 addr[0] = __v; addr[1] = __v >> 8; \
1224 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1225 addr[2] = __v; addr[3] = __v >> 8; \
1226 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1227 addr[4] = __v; addr[5] = __v >> 8; \
1228 } while (0)
1229 #endif
1230
1231 #define SMC_SET_MAC_ADDR(addr) \
1232 do { \
1233 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1234 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1235 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1236 } while (0)
1237
1238 #define SMC_SET_MCAST(x) \
1239 do { \
1240 const unsigned char *mt = (x); \
1241 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1242 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1243 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1244 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1245 } while (0)
1246
1247 #define SMC_PUT_PKT_HDR(status, length) \
1248 do { \
1249 if (SMC_CAN_USE_32BIT) \
1250 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1251 else { \
1252 SMC_outw(status, ioaddr, DATA_REG); \
1253 SMC_outw(length, ioaddr, DATA_REG); \
1254 } \
1255 } while (0)
1256
1257 #define SMC_GET_PKT_HDR(status, length) \
1258 do { \
1259 if (SMC_CAN_USE_32BIT) { \
1260 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1261 (status) = __val & 0xffff; \
1262 (length) = __val >> 16; \
1263 } else { \
1264 (status) = SMC_inw(ioaddr, DATA_REG); \
1265 (length) = SMC_inw(ioaddr, DATA_REG); \
1266 } \
1267 } while (0)
1268
1269 #define SMC_PUSH_DATA(p, l) \
1270 do { \
1271 if (SMC_CAN_USE_32BIT) { \
1272 void *__ptr = (p); \
1273 int __len = (l); \
1274 void __iomem *__ioaddr = ioaddr; \
1275 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1276 __len -= 2; \
1277 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1278 __ptr += 2; \
1279 } \
1280 if (SMC_CAN_USE_DATACS && lp->datacs) \
1281 __ioaddr = lp->datacs; \
1282 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1283 if (__len & 2) { \
1284 __ptr += (__len & ~3); \
1285 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1286 } \
1287 } else if (SMC_CAN_USE_16BIT) \
1288 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1289 else if (SMC_CAN_USE_8BIT) \
1290 SMC_outsb(ioaddr, DATA_REG, p, l); \
1291 } while (0)
1292
1293 #define SMC_PULL_DATA(p, l) \
1294 do { \
1295 if (SMC_CAN_USE_32BIT) { \
1296 void *__ptr = (p); \
1297 int __len = (l); \
1298 void __iomem *__ioaddr = ioaddr; \
1299 if ((unsigned long)__ptr & 2) { \
1300 /* \
1301 * We want 32bit alignment here. \
1302 * Since some buses perform a full \
1303 * 32bit fetch even for 16bit data \
1304 * we can't use SMC_inw() here. \
1305 * Back both source (on-chip) and \
1306 * destination pointers of 2 bytes. \
1307 * This is possible since the call to \
1308 * SMC_GET_PKT_HDR() already advanced \
1309 * the source pointer of 4 bytes, and \
1310 * the skb_reserve(skb, 2) advanced \
1311 * the destination pointer of 2 bytes. \
1312 */ \
1313 __ptr -= 2; \
1314 __len += 2; \
1315 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1316 } \
1317 if (SMC_CAN_USE_DATACS && lp->datacs) \
1318 __ioaddr = lp->datacs; \
1319 __len += 2; \
1320 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1321 } else if (SMC_CAN_USE_16BIT) \
1322 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1323 else if (SMC_CAN_USE_8BIT) \
1324 SMC_insb(ioaddr, DATA_REG, p, l); \
1325 } while (0)
1326
1327 #endif /* _SMC91X_H_ */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree