drivers/net/wireless/ath/ath5k/qcu.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  */
  18
  19 /********************************************\
  20 Queue Control Unit, DFS Control Unit Functions
  21 \********************************************/
  22
  23 #include "ath5k.h"
  24 #include "reg.h"
  25 #include "debug.h"
  26 #include "base.h"
  27
  28
  29 /******************\
  30 * Helper functions *
  31 \******************/
  32
  33 /*
  34  * Get number of pending frames
  35  * for a specific queue [5211+]
  36  */
  37 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
  38 {
  39         u32 pending;
  40         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
  41
  42         /* Return if queue is declared inactive */
  43         if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
  44                 return false;
  45
  46         /* XXX: How about AR5K_CFG_TXCNT ? */
  47         if (ah->ah_version == AR5K_AR5210)
  48                 return false;
  49
  50         pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
  51         pending &= AR5K_QCU_STS_FRMPENDCNT;
  52
  53         /* It's possible to have no frames pending even if TXE
  54          * is set. To indicate that q has not stopped return
  55          * true */
  56         if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
  57                 return true;
  58
  59         return pending;
  60 }
  61
  62 /*
  63  * Set a transmit queue inactive
  64  */
  65 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
  66 {
  67         if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
  68                 return;
  69
  70         /* This queue will be skipped in further operations */
  71         ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
  72         /*For SIMR setup*/
  73         AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
  74 }
  75
  76 /*
  77  * Make sure cw is a power of 2 minus 1 and smaller than 1024
  78  */
  79 static u16 ath5k_cw_validate(u16 cw_req)
  80 {
  81         u32 cw = 1;
  82         cw_req = min(cw_req, (u16)1023);
  83
  84         while (cw < cw_req)
  85                 cw = (cw << 1) | 1;
  86
  87         return cw;
  88 }
  89
  90 /*
  91  * Get properties for a transmit queue
  92  */
  93 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
  94                 struct ath5k_txq_info *queue_info)
  95 {
  96         memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
  97         return 0;
  98 }
  99
 100 /*
 101  * Set properties for a transmit queue
 102  */
 103 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
 104                                 const struct ath5k_txq_info *qinfo)
 105 {
 106         struct ath5k_txq_info *qi;
 107
 108         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 109
 110         qi = &ah->ah_txq[queue];
 111
 112         if (qi->tqi_type == AR5K_TX_QUEUE_INACTIVE)
 113                 return -EIO;
 114
 115         /* copy and validate values */
 116         qi->tqi_type = qinfo->tqi_type;
 117         qi->tqi_subtype = qinfo->tqi_subtype;
 118         qi->tqi_flags = qinfo->tqi_flags;
 119         /*
 120          * According to the docs: Although the AIFS field is 8 bit wide,
 121          * the maximum supported value is 0xFC. Setting it higher than that
 122          * will cause the DCU to hang.
 123          */
 124         qi->tqi_aifs = min(qinfo->tqi_aifs, (u8)0xFC);
 125         qi->tqi_cw_min = ath5k_cw_validate(qinfo->tqi_cw_min);
 126         qi->tqi_cw_max = ath5k_cw_validate(qinfo->tqi_cw_max);
 127         qi->tqi_cbr_period = qinfo->tqi_cbr_period;
 128         qi->tqi_cbr_overflow_limit = qinfo->tqi_cbr_overflow_limit;
 129         qi->tqi_burst_time = qinfo->tqi_burst_time;
 130         qi->tqi_ready_time = qinfo->tqi_ready_time;
 131
 132         /*XXX: Is this supported on 5210 ?*/
 133         /*XXX: Is this correct for AR5K_WME_AC_VI,VO ???*/
 134         if ((qinfo->tqi_type == AR5K_TX_QUEUE_DATA &&
 135                 ((qinfo->tqi_subtype == AR5K_WME_AC_VI) ||
 136                  (qinfo->tqi_subtype == AR5K_WME_AC_VO))) ||
 137              qinfo->tqi_type == AR5K_TX_QUEUE_UAPSD)
 138                 qi->tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
 139
 140         return 0;
 141 }
 142
 143 /*
 144  * Initialize a transmit queue
 145  */
 146 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
 147                 struct ath5k_txq_info *queue_info)
 148 {
 149         unsigned int queue;
 150         int ret;
 151
 152         /*
 153          * Get queue by type
 154          */
 155         /* 5210 only has 2 queues */
 156         if (ah->ah_capabilities.cap_queues.q_tx_num == 2) {
 157                 switch (queue_type) {
 158                 case AR5K_TX_QUEUE_DATA:
 159                         queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
 160                         break;
 161                 case AR5K_TX_QUEUE_BEACON:
 162                 case AR5K_TX_QUEUE_CAB:
 163                         queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
 164                         break;
 165                 default:
 166                         return -EINVAL;
 167                 }
 168         } else {
 169                 switch (queue_type) {
 170                 case AR5K_TX_QUEUE_DATA:
 171                         for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
 172                                 ah->ah_txq[queue].tqi_type !=
 173                                 AR5K_TX_QUEUE_INACTIVE; queue++) {
 174
 175                                 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
 176                                         return -EINVAL;
 177                         }
 178                         break;
 179                 case AR5K_TX_QUEUE_UAPSD:
 180                         queue = AR5K_TX_QUEUE_ID_UAPSD;
 181                         break;
 182                 case AR5K_TX_QUEUE_BEACON:
 183                         queue = AR5K_TX_QUEUE_ID_BEACON;
 184                         break;
 185                 case AR5K_TX_QUEUE_CAB:
 186                         queue = AR5K_TX_QUEUE_ID_CAB;
 187                         break;
 188                 default:
 189                         return -EINVAL;
 190                 }
 191         }
 192
 193         /*
 194          * Setup internal queue structure
 195          */
 196         memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
 197         ah->ah_txq[queue].tqi_type = queue_type;
 198
 199         if (queue_info != NULL) {
 200                 queue_info->tqi_type = queue_type;
 201                 ret = ath5k_hw_set_tx_queueprops(ah, queue, queue_info);
 202                 if (ret)
 203                         return ret;
 204         }
 205
 206         /*
 207          * We use ah_txq_status to hold a temp value for
 208          * the Secondary interrupt mask registers on 5211+
 209          * check out ath5k_hw_reset_tx_queue
 210          */
 211         AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
 212
 213         return queue;
 214 }
 215
 216
 217 /*******************************\
 218 * Single QCU/DCU initialization *
 219 \*******************************/
 220
 221 /*
 222  * Set tx retry limits on DCU
 223  */
 224 void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
 225                                   unsigned int queue)
 226 {
 227         /* Single data queue on AR5210 */
 228         if (ah->ah_version == AR5K_AR5210) {
 229                 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
 230
 231                 if (queue > 0)
 232                         return;
 233
 234                 ath5k_hw_reg_write(ah,
 235                         (tq->tqi_cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
 236                         | AR5K_REG_SM(ah->ah_retry_long,
 237                                       AR5K_NODCU_RETRY_LMT_SLG_RETRY)
 238                         | AR5K_REG_SM(ah->ah_retry_short,
 239                                       AR5K_NODCU_RETRY_LMT_SSH_RETRY)
 240                         | AR5K_REG_SM(ah->ah_retry_long,
 241                                       AR5K_NODCU_RETRY_LMT_LG_RETRY)
 242                         | AR5K_REG_SM(ah->ah_retry_short,
 243                                       AR5K_NODCU_RETRY_LMT_SH_RETRY),
 244                         AR5K_NODCU_RETRY_LMT);
 245         /* DCU on AR5211+ */
 246         } else {
 247                 ath5k_hw_reg_write(ah,
 248                         AR5K_REG_SM(ah->ah_retry_long,
 249                                     AR5K_DCU_RETRY_LMT_RTS)
 250                         | AR5K_REG_SM(ah->ah_retry_long,
 251                                       AR5K_DCU_RETRY_LMT_STA_RTS)
 252                         | AR5K_REG_SM(max(ah->ah_retry_long, ah->ah_retry_short),
 253                                       AR5K_DCU_RETRY_LMT_STA_DATA),
 254                         AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
 255         }
 256 }
 257
 258 /**
 259  * ath5k_hw_reset_tx_queue - Initialize a single hw queue
 260  *
 261  * @ah The &struct ath5k_hw
 262  * @queue The hw queue number
 263  *
 264  * Set DFS properties for the given transmit queue on DCU
 265  * and configures all queue-specific parameters.
 266  */
 267 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
 268 {
 269         struct ath5k_txq_info *tq = &ah->ah_txq[queue];
 270
 271         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 272
 273         tq = &ah->ah_txq[queue];
 274
 275         /* Skip if queue inactive or if we are on AR5210
 276          * that doesn't have QCU/DCU */
 277         if ((ah->ah_version == AR5K_AR5210) ||
 278         (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE))
 279                 return 0;
 280
 281         /*
 282          * Set contention window (cw_min/cw_max)
 283          * and arbitrated interframe space (aifs)...
 284          */
 285         ath5k_hw_reg_write(ah,
 286                 AR5K_REG_SM(tq->tqi_cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
 287                 AR5K_REG_SM(tq->tqi_cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
 288                 AR5K_REG_SM(tq->tqi_aifs, AR5K_DCU_LCL_IFS_AIFS),
 289                 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
 290
 291         /*
 292          * Set tx retry limits for this queue
 293          */
 294         ath5k_hw_set_tx_retry_limits(ah, queue);
 295
 296
 297         /*
 298          * Set misc registers
 299          */
 300
 301         /* Enable DCU to wait for next fragment from QCU */
 302         AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
 303                                 AR5K_DCU_MISC_FRAG_WAIT);
 304
 305         /* On Maui and Spirit use the global seqnum on DCU */
 306         if (ah->ah_mac_version < AR5K_SREV_AR5211)
 307                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
 308                                         AR5K_DCU_MISC_SEQNUM_CTL);
 309
 310         /* Constant bit rate period */
 311         if (tq->tqi_cbr_period) {
 312                 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
 313                                         AR5K_QCU_CBRCFG_INTVAL) |
 314                                         AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
 315                                         AR5K_QCU_CBRCFG_ORN_THRES),
 316                                         AR5K_QUEUE_CBRCFG(queue));
 317
 318                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
 319                                         AR5K_QCU_MISC_FRSHED_CBR);
 320
 321                 if (tq->tqi_cbr_overflow_limit)
 322                         AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
 323                                         AR5K_QCU_MISC_CBR_THRES_ENABLE);
 324         }
 325
 326         /* Ready time interval */
 327         if (tq->tqi_ready_time && (tq->tqi_type != AR5K_TX_QUEUE_CAB))
 328                 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
 329                                         AR5K_QCU_RDYTIMECFG_INTVAL) |
 330                                         AR5K_QCU_RDYTIMECFG_ENABLE,
 331                                         AR5K_QUEUE_RDYTIMECFG(queue));
 332
 333         if (tq->tqi_burst_time) {
 334                 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
 335                                         AR5K_DCU_CHAN_TIME_DUR) |
 336                                         AR5K_DCU_CHAN_TIME_ENABLE,
 337                                         AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
 338
 339                 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
 340                         AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
 341                                         AR5K_QCU_MISC_RDY_VEOL_POLICY);
 342         }
 343
 344         /* Enable/disable Post frame backoff */
 345         if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
 346                 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
 347                                         AR5K_QUEUE_DFS_MISC(queue));
 348
 349         /* Enable/disable fragmentation burst backoff */
 350         if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
 351                 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
 352                                         AR5K_QUEUE_DFS_MISC(queue));
 353
 354         /*
 355          * Set registers by queue type
 356          */
 357         switch (tq->tqi_type) {
 358         case AR5K_TX_QUEUE_BEACON:
 359                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
 360                                 AR5K_QCU_MISC_FRSHED_DBA_GT |
 361                                 AR5K_QCU_MISC_CBREXP_BCN_DIS |
 362                                 AR5K_QCU_MISC_BCN_ENABLE);
 363
 364                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
 365                                 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
 366                                 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
 367                                 AR5K_DCU_MISC_ARBLOCK_IGNORE |
 368                                 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
 369                                 AR5K_DCU_MISC_BCN_ENABLE);
 370                 break;
 371
 372         case AR5K_TX_QUEUE_CAB:
 373                 /* XXX: use BCN_SENT_GT, if we can figure out how */
 374                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
 375                                         AR5K_QCU_MISC_FRSHED_DBA_GT |
 376                                         AR5K_QCU_MISC_CBREXP_DIS |
 377                                         AR5K_QCU_MISC_CBREXP_BCN_DIS);
 378
 379                 ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -
 380                                         (AR5K_TUNE_SW_BEACON_RESP -
 381                                         AR5K_TUNE_DMA_BEACON_RESP) -
 382                                 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
 383                                         AR5K_QCU_RDYTIMECFG_ENABLE,
 384                                         AR5K_QUEUE_RDYTIMECFG(queue));
 385
 386                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
 387                                         (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
 388                                         AR5K_DCU_MISC_ARBLOCK_CTL_S));
 389                 break;
 390
 391         case AR5K_TX_QUEUE_UAPSD:
 392                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
 393                                         AR5K_QCU_MISC_CBREXP_DIS);
 394                 break;
 395
 396         case AR5K_TX_QUEUE_DATA:
 397         default:
 398                         break;
 399         }
 400
 401         /* TODO: Handle frame compression */
 402
 403         /*
 404          * Enable interrupts for this tx queue
 405          * in the secondary interrupt mask registers
 406          */
 407         if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
 408                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
 409
 410         if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
 411                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
 412
 413         if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
 414                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
 415
 416         if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
 417                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
 418
 419         if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
 420                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
 421
 422         if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
 423                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
 424
 425         if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
 426                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
 427
 428         if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
 429                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
 430
 431         if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
 432                 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
 433
 434         /* Update secondary interrupt mask registers */
 435
 436         /* Filter out inactive queues */
 437         ah->ah_txq_imr_txok &= ah->ah_txq_status;
 438         ah->ah_txq_imr_txerr &= ah->ah_txq_status;
 439         ah->ah_txq_imr_txurn &= ah->ah_txq_status;
 440         ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
 441         ah->ah_txq_imr_txeol &= ah->ah_txq_status;
 442         ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
 443         ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
 444         ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
 445         ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
 446
 447         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
 448                                         AR5K_SIMR0_QCU_TXOK) |
 449                                         AR5K_REG_SM(ah->ah_txq_imr_txdesc,
 450                                         AR5K_SIMR0_QCU_TXDESC),
 451                                         AR5K_SIMR0);
 452
 453         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
 454                                         AR5K_SIMR1_QCU_TXERR) |
 455                                         AR5K_REG_SM(ah->ah_txq_imr_txeol,
 456                                         AR5K_SIMR1_QCU_TXEOL),
 457                                         AR5K_SIMR1);
 458
 459         /* Update SIMR2 but don't overwrite rest simr2 settings */
 460         AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
 461         AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
 462                                 AR5K_REG_SM(ah->ah_txq_imr_txurn,
 463                                 AR5K_SIMR2_QCU_TXURN));
 464
 465         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
 466                                 AR5K_SIMR3_QCBRORN) |
 467                                 AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
 468                                 AR5K_SIMR3_QCBRURN),
 469                                 AR5K_SIMR3);
 470
 471         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
 472                                 AR5K_SIMR4_QTRIG), AR5K_SIMR4);
 473
 474         /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
 475         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
 476                                 AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
 477
 478         /* No queue has TXNOFRM enabled, disable the interrupt
 479          * by setting AR5K_TXNOFRM to zero */
 480         if (ah->ah_txq_imr_nofrm == 0)
 481                 ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);
 482
 483         /* Set QCU mask for this DCU to save power */
 484         AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
 485
 486         return 0;
 487 }
 488
 489
 490 /**************************\
 491 * Global QCU/DCU functions *
 492 \**************************/
 493
 494 /**
 495  * ath5k_hw_set_ifs_intervals  - Set global inter-frame spaces on DCU
 496  *
 497  * @ah The &struct ath5k_hw
 498  * @slot_time Slot time in us
 499  *
 500  * Sets the global IFS intervals on DCU (also works on AR5210) for
 501  * the given slot time and the current bwmode.
 502  */
 503 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)
 504 {
 505         struct ieee80211_channel *channel = ah->ah_current_channel;
 506         struct ieee80211_rate *rate;
 507         u32 ack_tx_time, eifs, eifs_clock, sifs, sifs_clock;
 508         u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time);
 509
 510         if (slot_time < 6 || slot_time_clock > AR5K_SLOT_TIME_MAX)
 511                 return -EINVAL;
 512
 513         sifs = ath5k_hw_get_default_sifs(ah);
 514         sifs_clock = ath5k_hw_htoclock(ah, sifs - 2);
 515
 516         /* EIFS
 517          * Txtime of ack at lowest rate + SIFS + DIFS
 518          * (DIFS = SIFS + 2 * Slot time)
 519          *
 520          * Note: HAL has some predefined values for EIFS
 521          * Turbo:   (37 + 2 * 6)
 522          * Default: (74 + 2 * 9)
 523          * Half:    (149 + 2 * 13)
 524          * Quarter: (298 + 2 * 21)
 525          *
 526          * (74 + 2 * 6) for AR5210 default and turbo !
 527          *
 528          * According to the formula we have
 529          * ack_tx_time = 25 for turbo and
 530          * ack_tx_time = 42.5 * clock multiplier
 531          * for default/half/quarter.
 532          *
 533          * This can't be right, 42 is what we would get
 534          * from ath5k_hw_get_frame_dur_for_bwmode or
 535          * ieee80211_generic_frame_duration for zero frame
 536          * length and without SIFS !
 537          *
 538          * Also we have different lowest rate for 802.11a
 539          */
 540         if (channel->hw_value & CHANNEL_5GHZ)
 541                 rate = &ah->sbands[IEEE80211_BAND_5GHZ].bitrates[0];
 542         else
 543                 rate = &ah->sbands[IEEE80211_BAND_2GHZ].bitrates[0];
 544
 545         ack_tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false);
 546
 547         /* ack_tx_time includes an SIFS already */
 548         eifs = ack_tx_time + sifs + 2 * slot_time;
 549         eifs_clock = ath5k_hw_htoclock(ah, eifs);
 550
 551         /* Set IFS settings on AR5210 */
 552         if (ah->ah_version == AR5K_AR5210) {
 553                 u32 pifs, pifs_clock, difs, difs_clock;
 554
 555                 /* Set slot time */
 556                 ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);
 557
 558                 /* Set EIFS */
 559                 eifs_clock = AR5K_REG_SM(eifs_clock, AR5K_IFS1_EIFS);
 560
 561                 /* PIFS = Slot time + SIFS */
 562                 pifs = slot_time + sifs;
 563                 pifs_clock = ath5k_hw_htoclock(ah, pifs);
 564                 pifs_clock = AR5K_REG_SM(pifs_clock, AR5K_IFS1_PIFS);
 565
 566                 /* DIFS = SIFS + 2 * Slot time */
 567                 difs = sifs + 2 * slot_time;
 568                 difs_clock = ath5k_hw_htoclock(ah, difs);
 569
 570                 /* Set SIFS/DIFS */
 571                 ath5k_hw_reg_write(ah, (difs_clock <<
 572                                 AR5K_IFS0_DIFS_S) | sifs_clock,
 573                                 AR5K_IFS0);
 574
 575                 /* Set PIFS/EIFS and preserve AR5K_INIT_CARR_SENSE_EN */
 576                 ath5k_hw_reg_write(ah, pifs_clock | eifs_clock |
 577                                 (AR5K_INIT_CARR_SENSE_EN << AR5K_IFS1_CS_EN_S),
 578                                 AR5K_IFS1);
 579
 580                 return 0;
 581         }
 582
 583         /* Set IFS slot time */
 584         ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);
 585
 586         /* Set EIFS interval */
 587         ath5k_hw_reg_write(ah, eifs_clock, AR5K_DCU_GBL_IFS_EIFS);
 588
 589         /* Set SIFS interval in usecs */
 590         AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
 591                                 AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC,
 592                                 sifs);
 593
 594         /* Set SIFS interval in clock cycles */
 595         ath5k_hw_reg_write(ah, sifs_clock, AR5K_DCU_GBL_IFS_SIFS);
 596
 597         return 0;
 598 }
 599
 600
 601 int ath5k_hw_init_queues(struct ath5k_hw *ah)
 602 {
 603         int i, ret;
 604
 605         /* TODO: HW Compression support for data queues */
 606         /* TODO: Burst prefetch for data queues */
 607
 608         /*
 609          * Reset queues and start beacon timers at the end of the reset routine
 610          * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
 611          * Note: If we want we can assign multiple qcus on one dcu.
 612          */
 613         if (ah->ah_version != AR5K_AR5210)
 614                 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
 615                         ret = ath5k_hw_reset_tx_queue(ah, i);
 616                         if (ret) {
 617                                 ATH5K_ERR(ah,
 618                                         "failed to reset TX queue #%d\n", i);
 619                                 return ret;
 620                         }
 621                 }
 622         else
 623                 /* No QCU/DCU on AR5210, just set tx
 624                  * retry limits. We set IFS parameters
 625                  * on ath5k_hw_set_ifs_intervals */
 626                 ath5k_hw_set_tx_retry_limits(ah, 0);
 627
 628         /* Set the turbo flag when operating on 40MHz */
 629         if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
 630                 AR5K_REG_ENABLE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
 631                                 AR5K_DCU_GBL_IFS_MISC_TURBO_MODE);
 632
 633         /* If we didn't set IFS timings through
 634          * ath5k_hw_set_coverage_class make sure
 635          * we set them here */
 636         if (!ah->ah_coverage_class) {
 637                 unsigned int slot_time = ath5k_hw_get_default_slottime(ah);
 638                 ath5k_hw_set_ifs_intervals(ah, slot_time);
 639         }
 640
 641         return 0;
 642 }