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[SPARC64]: Kill pci_controller->base_address_update().
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / sparc64 / kernel / pci_schizo.c
blob99912db4e7e891b8367bdb0506bd5ed23aabb61d
1 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
2 *
3 * Copyright (C) 2001, 2002, 2003, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12
13 #include <asm/pbm.h>
14 #include <asm/iommu.h>
15 #include <asm/irq.h>
16 #include <asm/upa.h>
17 #include <asm/pstate.h>
18 #include <asm/prom.h>
19
20 #include "pci_impl.h"
21 #include "iommu_common.h"
22
23 /* All SCHIZO registers are 64-bits. The following accessor
24 * routines are how they are accessed. The REG parameter
25 * is a physical address.
26 */
27 #define schizo_read(__reg) \
28 ({ u64 __ret; \
29 __asm__ __volatile__("ldxa [%1] %2, %0" \
30 : "=r" (__ret) \
31 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
32 : "memory"); \
33 __ret; \
34 })
35 #define schizo_write(__reg, __val) \
36 __asm__ __volatile__("stxa %0, [%1] %2" \
37 : /* no outputs */ \
38 : "r" (__val), "r" (__reg), \
39 "i" (ASI_PHYS_BYPASS_EC_E) \
40 : "memory")
41
42 /* This is a convention that at least Excalibur and Merlin
43 * follow. I suppose the SCHIZO used in Starcat and friends
44 * will do similar.
45 *
46 * The only way I could see this changing is if the newlink
47 * block requires more space in Schizo's address space than
48 * they predicted, thus requiring an address space reorg when
49 * the newer Schizo is taped out.
50 */
51
52 /* Streaming buffer control register. */
53 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
54 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
55 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
56 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
57 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
58
59 /* IOMMU control register. */
60 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
61 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
62 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
63 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
64 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
65 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
66 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
67 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
68 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
69 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
70 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
71 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
72 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
73 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
74 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
75 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
76 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
77 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
78
79 /* Schizo config space address format is nearly identical to
80 * that of PSYCHO:
81 *
82 * 32 24 23 16 15 11 10 8 7 2 1 0
83 * ---------------------------------------------------------
84 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
85 * ---------------------------------------------------------
86 */
87 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
88 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
89 (((unsigned long)(BUS) << 16) | \
90 ((unsigned long)(DEVFN) << 8) | \
91 ((unsigned long)(REG)))
92
93 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
94 unsigned char bus,
95 unsigned int devfn,
96 int where)
97 {
98 if (!pbm)
99 return NULL;
100 bus -= pbm->pci_first_busno;
101 return (void *)
102 (SCHIZO_CONFIG_BASE(pbm) |
103 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
104 }
105
106 /* Just make sure the bus number is in range. */
107 static int schizo_out_of_range(struct pci_pbm_info *pbm,
108 unsigned char bus,
109 unsigned char devfn)
110 {
111 if (bus < pbm->pci_first_busno ||
112 bus > pbm->pci_last_busno)
113 return 1;
114 return 0;
115 }
116
117 /* SCHIZO PCI configuration space accessors. */
118
119 static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
120 int where, int size, u32 *value)
121 {
122 struct pci_pbm_info *pbm = bus_dev->sysdata;
123 unsigned char bus = bus_dev->number;
124 u32 *addr;
125 u16 tmp16;
126 u8 tmp8;
127
128 switch (size) {
129 case 1:
130 *value = 0xff;
131 break;
132 case 2:
133 *value = 0xffff;
134 break;
135 case 4:
136 *value = 0xffffffff;
137 break;
138 }
139
140 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
141 if (!addr)
142 return PCIBIOS_SUCCESSFUL;
143
144 if (schizo_out_of_range(pbm, bus, devfn))
145 return PCIBIOS_SUCCESSFUL;
146 switch (size) {
147 case 1:
148 pci_config_read8((u8 *)addr, &tmp8);
149 *value = tmp8;
150 break;
151
152 case 2:
153 if (where & 0x01) {
154 printk("pci_read_config_word: misaligned reg [%x]\n",
155 where);
156 return PCIBIOS_SUCCESSFUL;
157 }
158 pci_config_read16((u16 *)addr, &tmp16);
159 *value = tmp16;
160 break;
161
162 case 4:
163 if (where & 0x03) {
164 printk("pci_read_config_dword: misaligned reg [%x]\n",
165 where);
166 return PCIBIOS_SUCCESSFUL;
167 }
168 pci_config_read32(addr, value);
169 break;
170 }
171 return PCIBIOS_SUCCESSFUL;
172 }
173
174 static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
175 int where, int size, u32 value)
176 {
177 struct pci_pbm_info *pbm = bus_dev->sysdata;
178 unsigned char bus = bus_dev->number;
179 u32 *addr;
180
181 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
182 if (!addr)
183 return PCIBIOS_SUCCESSFUL;
184
185 if (schizo_out_of_range(pbm, bus, devfn))
186 return PCIBIOS_SUCCESSFUL;
187
188 switch (size) {
189 case 1:
190 pci_config_write8((u8 *)addr, value);
191 break;
192
193 case 2:
194 if (where & 0x01) {
195 printk("pci_write_config_word: misaligned reg [%x]\n",
196 where);
197 return PCIBIOS_SUCCESSFUL;
198 }
199 pci_config_write16((u16 *)addr, value);
200 break;
201
202 case 4:
203 if (where & 0x03) {
204 printk("pci_write_config_dword: misaligned reg [%x]\n",
205 where);
206 return PCIBIOS_SUCCESSFUL;
207 }
208
209 pci_config_write32(addr, value);
210 }
211 return PCIBIOS_SUCCESSFUL;
212 }
213
214 static struct pci_ops schizo_ops = {
215 .read = schizo_read_pci_cfg,
216 .write = schizo_write_pci_cfg,
217 };
218
219 /* SCHIZO error handling support. */
220 enum schizo_error_type {
221 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
222 };
223
224 static DEFINE_SPINLOCK(stc_buf_lock);
225 static unsigned long stc_error_buf[128];
226 static unsigned long stc_tag_buf[16];
227 static unsigned long stc_line_buf[16];
228
229 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
230 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
231 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
232 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
233 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
234
235 struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
236 {
237 ino &= IMAP_INO;
238 if (p->pbm_A.ino_bitmap & (1UL << ino))
239 return &p->pbm_A;
240 if (p->pbm_B.ino_bitmap & (1UL << ino))
241 return &p->pbm_B;
242
243 printk("PCI%d: No ino_bitmap entry for ino[%x], bitmaps "
244 "PBM_A[%016lx] PBM_B[%016lx]",
245 p->index, ino,
246 p->pbm_A.ino_bitmap,
247 p->pbm_B.ino_bitmap);
248 printk("PCI%d: Using PBM_A, report this problem immediately.\n",
249 p->index);
250
251 return &p->pbm_A;
252 }
253
254 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
255 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
256 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
257
258 #define SCHIZO_STCERR_WRITE 0x2UL
259 #define SCHIZO_STCERR_READ 0x1UL
260
261 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
262 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
263 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
264 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
265
266 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
267 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
268 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
269 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
270 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
271 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
272
273 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
274 enum schizo_error_type type)
275 {
276 struct pci_strbuf *strbuf = &pbm->stc;
277 unsigned long regbase = pbm->pbm_regs;
278 unsigned long err_base, tag_base, line_base;
279 u64 control;
280 int i;
281
282 err_base = regbase + SCHIZO_STC_ERR;
283 tag_base = regbase + SCHIZO_STC_TAG;
284 line_base = regbase + SCHIZO_STC_LINE;
285
286 spin_lock(&stc_buf_lock);
287
288 /* This is __REALLY__ dangerous. When we put the
289 * streaming buffer into diagnostic mode to probe
290 * it's tags and error status, we _must_ clear all
291 * of the line tag valid bits before re-enabling
292 * the streaming buffer. If any dirty data lives
293 * in the STC when we do this, we will end up
294 * invalidating it before it has a chance to reach
295 * main memory.
296 */
297 control = schizo_read(strbuf->strbuf_control);
298 schizo_write(strbuf->strbuf_control,
299 (control | SCHIZO_STRBUF_CTRL_DENAB));
300 for (i = 0; i < 128; i++) {
301 unsigned long val;
302
303 val = schizo_read(err_base + (i * 8UL));
304 schizo_write(err_base + (i * 8UL), 0UL);
305 stc_error_buf[i] = val;
306 }
307 for (i = 0; i < 16; i++) {
308 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
309 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
310 schizo_write(tag_base + (i * 8UL), 0UL);
311 schizo_write(line_base + (i * 8UL), 0UL);
312 }
313
314 /* OK, state is logged, exit diagnostic mode. */
315 schizo_write(strbuf->strbuf_control, control);
316
317 for (i = 0; i < 16; i++) {
318 int j, saw_error, first, last;
319
320 saw_error = 0;
321 first = i * 8;
322 last = first + 8;
323 for (j = first; j < last; j++) {
324 unsigned long errval = stc_error_buf[j];
325 if (errval != 0) {
326 saw_error++;
327 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
328 pbm->name,
329 j,
330 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
331 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
332 }
333 }
334 if (saw_error != 0) {
335 unsigned long tagval = stc_tag_buf[i];
336 unsigned long lineval = stc_line_buf[i];
337 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
338 pbm->name,
339 i,
340 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
341 (tagval & SCHIZO_STCTAG_VPN),
342 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
343 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
344
345 /* XXX Should spit out per-bank error information... -DaveM */
346 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
347 "V(%d)FOFN(%d)]\n",
348 pbm->name,
349 i,
350 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
351 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
352 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
353 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
354 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
355 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
356 }
357 }
358
359 spin_unlock(&stc_buf_lock);
360 }
361
362 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
363 * controller level errors.
364 */
365
366 #define SCHIZO_IOMMU_TAG 0xa580UL
367 #define SCHIZO_IOMMU_DATA 0xa600UL
368
369 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
370 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
371 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
372 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
373 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
374 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
375 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
376
377 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
378 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
379 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
380
381 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
382 enum schizo_error_type type)
383 {
384 struct pci_iommu *iommu = pbm->iommu;
385 unsigned long iommu_tag[16];
386 unsigned long iommu_data[16];
387 unsigned long flags;
388 u64 control;
389 int i;
390
391 spin_lock_irqsave(&iommu->lock, flags);
392 control = schizo_read(iommu->iommu_control);
393 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
394 unsigned long base;
395 char *type_string;
396
397 /* Clear the error encountered bit. */
398 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
399 schizo_write(iommu->iommu_control, control);
400
401 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
402 case 0:
403 type_string = "Protection Error";
404 break;
405 case 1:
406 type_string = "Invalid Error";
407 break;
408 case 2:
409 type_string = "TimeOut Error";
410 break;
411 case 3:
412 default:
413 type_string = "ECC Error";
414 break;
415 };
416 printk("%s: IOMMU Error, type[%s]\n",
417 pbm->name, type_string);
418
419 /* Put the IOMMU into diagnostic mode and probe
420 * it's TLB for entries with error status.
421 *
422 * It is very possible for another DVMA to occur
423 * while we do this probe, and corrupt the system
424 * further. But we are so screwed at this point
425 * that we are likely to crash hard anyways, so
426 * get as much diagnostic information to the
427 * console as we can.
428 */
429 schizo_write(iommu->iommu_control,
430 control | SCHIZO_IOMMU_CTRL_DENAB);
431
432 base = pbm->pbm_regs;
433
434 for (i = 0; i < 16; i++) {
435 iommu_tag[i] =
436 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
437 iommu_data[i] =
438 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
439
440 /* Now clear out the entry. */
441 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
442 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
443 }
444
445 /* Leave diagnostic mode. */
446 schizo_write(iommu->iommu_control, control);
447
448 for (i = 0; i < 16; i++) {
449 unsigned long tag, data;
450
451 tag = iommu_tag[i];
452 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
453 continue;
454
455 data = iommu_data[i];
456 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
457 case 0:
458 type_string = "Protection Error";
459 break;
460 case 1:
461 type_string = "Invalid Error";
462 break;
463 case 2:
464 type_string = "TimeOut Error";
465 break;
466 case 3:
467 default:
468 type_string = "ECC Error";
469 break;
470 };
471 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
472 "sz(%dK) vpg(%08lx)]\n",
473 pbm->name, i, type_string,
474 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
475 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
476 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
477 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
478 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
479 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
480 pbm->name, i,
481 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
482 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
483 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
484 }
485 }
486 if (pbm->stc.strbuf_enabled)
487 __schizo_check_stc_error_pbm(pbm, type);
488 spin_unlock_irqrestore(&iommu->lock, flags);
489 }
490
491 static void schizo_check_iommu_error(struct pci_controller_info *p,
492 enum schizo_error_type type)
493 {
494 schizo_check_iommu_error_pbm(&p->pbm_A, type);
495 schizo_check_iommu_error_pbm(&p->pbm_B, type);
496 }
497
498 /* Uncorrectable ECC error status gathering. */
499 #define SCHIZO_UE_AFSR 0x10030UL
500 #define SCHIZO_UE_AFAR 0x10038UL
501
502 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
503 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
504 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
505 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
506 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
507 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
508 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
509 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
510 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
511 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
512 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
513 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
514 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
515 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
516
517 static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
518 {
519 struct pci_controller_info *p = dev_id;
520 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR;
521 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR;
522 unsigned long afsr, afar, error_bits;
523 int reported, limit;
524
525 /* Latch uncorrectable error status. */
526 afar = schizo_read(afar_reg);
527
528 /* If either of the error pending bits are set in the
529 * AFSR, the error status is being actively updated by
530 * the hardware and we must re-read to get a clean value.
531 */
532 limit = 1000;
533 do {
534 afsr = schizo_read(afsr_reg);
535 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
536
537 /* Clear the primary/secondary error status bits. */
538 error_bits = afsr &
539 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
540 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
541 if (!error_bits)
542 return IRQ_NONE;
543 schizo_write(afsr_reg, error_bits);
544
545 /* Log the error. */
546 printk("PCI%d: Uncorrectable Error, primary error type[%s]\n",
547 p->index,
548 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
549 "PIO" :
550 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
551 "DMA Read" :
552 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
553 "DMA Write" : "???")))));
554 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
555 p->index,
556 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
557 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
558 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
559 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
560 p->index,
561 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
562 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
563 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
564 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
565 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
566 printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar);
567 printk("PCI%d: UE Secondary errors [", p->index);
568 reported = 0;
569 if (afsr & SCHIZO_UEAFSR_SPIO) {
570 reported++;
571 printk("(PIO)");
572 }
573 if (afsr & SCHIZO_UEAFSR_SDMA) {
574 reported++;
575 printk("(DMA)");
576 }
577 if (!reported)
578 printk("(none)");
579 printk("]\n");
580
581 /* Interrogate IOMMU for error status. */
582 schizo_check_iommu_error(p, UE_ERR);
583
584 return IRQ_HANDLED;
585 }
586
587 #define SCHIZO_CE_AFSR 0x10040UL
588 #define SCHIZO_CE_AFAR 0x10048UL
589
590 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
591 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
592 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
593 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
594 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
595 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
596 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
597 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
598 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
599 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
600 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
601 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
602 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
603 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
604
605 static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
606 {
607 struct pci_controller_info *p = dev_id;
608 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR;
609 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR;
610 unsigned long afsr, afar, error_bits;
611 int reported, limit;
612
613 /* Latch error status. */
614 afar = schizo_read(afar_reg);
615
616 /* If either of the error pending bits are set in the
617 * AFSR, the error status is being actively updated by
618 * the hardware and we must re-read to get a clean value.
619 */
620 limit = 1000;
621 do {
622 afsr = schizo_read(afsr_reg);
623 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
624
625 /* Clear primary/secondary error status bits. */
626 error_bits = afsr &
627 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
628 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
629 if (!error_bits)
630 return IRQ_NONE;
631 schizo_write(afsr_reg, error_bits);
632
633 /* Log the error. */
634 printk("PCI%d: Correctable Error, primary error type[%s]\n",
635 p->index,
636 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
637 "PIO" :
638 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
639 "DMA Read" :
640 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
641 "DMA Write" : "???")))));
642
643 /* XXX Use syndrome and afar to print out module string just like
644 * XXX UDB CE trap handler does... -DaveM
645 */
646 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
647 p->index,
648 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
649 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
650 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
651 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
652 p->index,
653 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
654 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
655 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
656 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
657 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
658 printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar);
659 printk("PCI%d: CE Secondary errors [", p->index);
660 reported = 0;
661 if (afsr & SCHIZO_CEAFSR_SPIO) {
662 reported++;
663 printk("(PIO)");
664 }
665 if (afsr & SCHIZO_CEAFSR_SDMA) {
666 reported++;
667 printk("(DMA)");
668 }
669 if (!reported)
670 printk("(none)");
671 printk("]\n");
672
673 return IRQ_HANDLED;
674 }
675
676 #define SCHIZO_PCI_AFSR 0x2010UL
677 #define SCHIZO_PCI_AFAR 0x2018UL
678
679 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
680 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
681 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
682 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
683 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
684 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
685 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
686 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
687 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
688 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
689 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
690 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
691 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
692 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
693 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
694 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
695 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
696
697 #define SCHIZO_PCI_CTRL (0x2000UL)
698 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
699 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
700 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
701 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
702 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
703 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
704 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
705 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
706 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
707 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
708 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
709 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
710 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
711 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
712 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
713 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
714 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
715 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
716 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
717 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
718 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
719 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
720 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
721 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
722 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
723 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
724 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
725
726 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
727 {
728 unsigned long csr_reg, csr, csr_error_bits;
729 irqreturn_t ret = IRQ_NONE;
730 u16 stat;
731
732 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
733 csr = schizo_read(csr_reg);
734 csr_error_bits =
735 csr & (SCHIZO_PCICTRL_BUS_UNUS |
736 SCHIZO_PCICTRL_TTO_ERR |
737 SCHIZO_PCICTRL_RTRY_ERR |
738 SCHIZO_PCICTRL_DTO_ERR |
739 SCHIZO_PCICTRL_SBH_ERR |
740 SCHIZO_PCICTRL_SERR);
741 if (csr_error_bits) {
742 /* Clear the errors. */
743 schizo_write(csr_reg, csr);
744
745 /* Log 'em. */
746 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
747 printk("%s: Bus unusable error asserted.\n",
748 pbm->name);
749 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
750 printk("%s: PCI TRDY# timeout error asserted.\n",
751 pbm->name);
752 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
753 printk("%s: PCI excessive retry error asserted.\n",
754 pbm->name);
755 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
756 printk("%s: PCI discard timeout error asserted.\n",
757 pbm->name);
758 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
759 printk("%s: PCI streaming byte hole error asserted.\n",
760 pbm->name);
761 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
762 printk("%s: PCI SERR signal asserted.\n",
763 pbm->name);
764 ret = IRQ_HANDLED;
765 }
766 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
767 if (stat & (PCI_STATUS_PARITY |
768 PCI_STATUS_SIG_TARGET_ABORT |
769 PCI_STATUS_REC_TARGET_ABORT |
770 PCI_STATUS_REC_MASTER_ABORT |
771 PCI_STATUS_SIG_SYSTEM_ERROR)) {
772 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
773 pbm->name, stat);
774 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
775 ret = IRQ_HANDLED;
776 }
777 return ret;
778 }
779
780 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
781 {
782 struct pci_pbm_info *pbm = dev_id;
783 struct pci_controller_info *p = pbm->parent;
784 unsigned long afsr_reg, afar_reg, base;
785 unsigned long afsr, afar, error_bits;
786 int reported;
787
788 base = pbm->pbm_regs;
789
790 afsr_reg = base + SCHIZO_PCI_AFSR;
791 afar_reg = base + SCHIZO_PCI_AFAR;
792
793 /* Latch error status. */
794 afar = schizo_read(afar_reg);
795 afsr = schizo_read(afsr_reg);
796
797 /* Clear primary/secondary error status bits. */
798 error_bits = afsr &
799 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
800 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
801 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
802 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
803 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
804 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
805 if (!error_bits)
806 return schizo_pcierr_intr_other(pbm);
807 schizo_write(afsr_reg, error_bits);
808
809 /* Log the error. */
810 printk("%s: PCI Error, primary error type[%s]\n",
811 pbm->name,
812 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
813 "Master Abort" :
814 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
815 "Target Abort" :
816 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
817 "Excessive Retries" :
818 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
819 "Parity Error" :
820 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
821 "Timeout" :
822 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
823 "Bus Unusable" : "???"))))))));
824 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
825 pbm->name,
826 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
827 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
828 ((afsr & SCHIZO_PCIAFSR_CFG) ?
829 "Config" :
830 ((afsr & SCHIZO_PCIAFSR_MEM) ?
831 "Memory" :
832 ((afsr & SCHIZO_PCIAFSR_IO) ?
833 "I/O" : "???"))));
834 printk("%s: PCI AFAR [%016lx]\n",
835 pbm->name, afar);
836 printk("%s: PCI Secondary errors [",
837 pbm->name);
838 reported = 0;
839 if (afsr & SCHIZO_PCIAFSR_SMA) {
840 reported++;
841 printk("(Master Abort)");
842 }
843 if (afsr & SCHIZO_PCIAFSR_STA) {
844 reported++;
845 printk("(Target Abort)");
846 }
847 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
848 reported++;
849 printk("(Excessive Retries)");
850 }
851 if (afsr & SCHIZO_PCIAFSR_SPERR) {
852 reported++;
853 printk("(Parity Error)");
854 }
855 if (afsr & SCHIZO_PCIAFSR_STTO) {
856 reported++;
857 printk("(Timeout)");
858 }
859 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
860 reported++;
861 printk("(Bus Unusable)");
862 }
863 if (!reported)
864 printk("(none)");
865 printk("]\n");
866
867 /* For the error types shown, scan PBM's PCI bus for devices
868 * which have logged that error type.
869 */
870
871 /* If we see a Target Abort, this could be the result of an
872 * IOMMU translation error of some sort. It is extremely
873 * useful to log this information as usually it indicates
874 * a bug in the IOMMU support code or a PCI device driver.
875 */
876 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
877 schizo_check_iommu_error(p, PCI_ERR);
878 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
879 }
880 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
881 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
882
883 /* For excessive retries, PSYCHO/PBM will abort the device
884 * and there is no way to specifically check for excessive
885 * retries in the config space status registers. So what
886 * we hope is that we'll catch it via the master/target
887 * abort events.
888 */
889
890 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
891 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
892
893 return IRQ_HANDLED;
894 }
895
896 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
897
898 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
899
900 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
901 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
902 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
903 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
904 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
905 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
906 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
907 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
908 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
909 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
910 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
911 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
912 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
913 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
914 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
915 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
916 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
917 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
918 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
919 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
920 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
921 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
922 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
923 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
924 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
925 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
926 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
927 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
928 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
929 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
930 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
931
932 /* We only expect UNMAP errors here. The rest of the Safari errors
933 * are marked fatal and thus cause a system reset.
934 */
935 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
936 {
937 struct pci_controller_info *p = dev_id;
938 u64 errlog;
939
940 errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG);
941 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG,
942 errlog & ~(SAFARI_ERRLOG_ERROUT));
943
944 if (!(errlog & BUS_ERROR_UNMAP)) {
945 printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
946 p->index, errlog);
947
948 return IRQ_HANDLED;
949 }
950
951 printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
952 p->index);
953 schizo_check_iommu_error(p, SAFARI_ERR);
954
955 return IRQ_HANDLED;
956 }
957
958 /* Nearly identical to PSYCHO equivalents... */
959 #define SCHIZO_ECC_CTRL 0x10020UL
960 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
961 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
962 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
963
964 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
965 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
966 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
967 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
968
969 /* How the Tomatillo IRQs are routed around is pure guesswork here.
970 *
971 * All the Tomatillo devices I see in prtconf dumps seem to have only
972 * a single PCI bus unit attached to it. It would seem they are seperate
973 * devices because their PortID (ie. JBUS ID) values are all different
974 * and thus the registers are mapped to totally different locations.
975 *
976 * However, two Tomatillo's look "similar" in that the only difference
977 * in their PortID is the lowest bit.
978 *
979 * So if we were to ignore this lower bit, it certainly looks like two
980 * PCI bus units of the same Tomatillo. I still have not really
981 * figured this out...
982 */
983 static void tomatillo_register_error_handlers(struct pci_controller_info *p)
984 {
985 struct pci_pbm_info *pbm;
986 struct of_device *op;
987 u64 tmp, err_mask, err_no_mask;
988
989 /* Tomatillo IRQ property layout is:
990 * 0: PCIERR
991 * 1: UE ERR
992 * 2: CE ERR
993 * 3: SERR
994 * 4: POWER FAIL?
995 */
996
997 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
998 op = of_find_device_by_node(pbm->prom_node);
999 if (op)
1000 request_irq(op->irqs[1], schizo_ue_intr, IRQF_SHARED,
1001 "TOMATILLO_UE", p);
1002
1003 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1004 op = of_find_device_by_node(pbm->prom_node);
1005 if (op)
1006 request_irq(op->irqs[2], schizo_ce_intr, IRQF_SHARED,
1007 "TOMATILLO CE", p);
1008
1009 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1010 op = of_find_device_by_node(pbm->prom_node);
1011 if (op)
1012 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED,
1013 "TOMATILLO PCIERR-A", pbm);
1014
1015
1016 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1017 op = of_find_device_by_node(pbm->prom_node);
1018 if (op)
1019 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED,
1020 "TOMATILLO PCIERR-B", pbm);
1021
1022 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1023 op = of_find_device_by_node(pbm->prom_node);
1024 if (op)
1025 request_irq(op->irqs[3], schizo_safarierr_intr, IRQF_SHARED,
1026 "TOMATILLO SERR", p);
1027
1028 /* Enable UE and CE interrupts for controller. */
1029 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1030 (SCHIZO_ECCCTRL_EE |
1031 SCHIZO_ECCCTRL_UE |
1032 SCHIZO_ECCCTRL_CE));
1033
1034 schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL,
1035 (SCHIZO_ECCCTRL_EE |
1036 SCHIZO_ECCCTRL_UE |
1037 SCHIZO_ECCCTRL_CE));
1038
1039 /* Enable PCI Error interrupts and clear error
1040 * bits.
1041 */
1042 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1043 SCHIZO_PCICTRL_TTO_ERR |
1044 SCHIZO_PCICTRL_RTRY_ERR |
1045 SCHIZO_PCICTRL_SERR |
1046 SCHIZO_PCICTRL_EEN);
1047
1048 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
1049
1050 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1051 tmp |= err_mask;
1052 tmp &= ~err_no_mask;
1053 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1054
1055 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1056 tmp |= err_mask;
1057 tmp &= ~err_no_mask;
1058 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1059
1060 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1061 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1062 SCHIZO_PCIAFSR_PTTO |
1063 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1064 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1065 SCHIZO_PCIAFSR_STTO);
1066
1067 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1068 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1069
1070 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
1071 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
1072 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
1073 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
1074 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
1075 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
1076 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
1077 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
1078 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
1079
1080 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1081 (SCHIZO_SAFERRCTRL_EN | err_mask));
1082 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1083 (SCHIZO_SAFERRCTRL_EN | err_mask));
1084
1085 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1086 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1087 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1088 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1089 }
1090
1091 static void schizo_register_error_handlers(struct pci_controller_info *p)
1092 {
1093 struct pci_pbm_info *pbm;
1094 struct of_device *op;
1095 u64 tmp, err_mask, err_no_mask;
1096
1097 /* Schizo IRQ property layout is:
1098 * 0: PCIERR
1099 * 1: UE ERR
1100 * 2: CE ERR
1101 * 3: SERR
1102 * 4: POWER FAIL?
1103 */
1104
1105 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1106 op = of_find_device_by_node(pbm->prom_node);
1107 if (op)
1108 request_irq(op->irqs[1], schizo_ue_intr, IRQF_SHARED,
1109 "SCHIZO_UE", p);
1110
1111 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1112 op = of_find_device_by_node(pbm->prom_node);
1113 if (op)
1114 request_irq(op->irqs[2], schizo_ce_intr, IRQF_SHARED,
1115 "SCHIZO CE", p);
1116
1117 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1118 op = of_find_device_by_node(pbm->prom_node);
1119 if (op)
1120 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED,
1121 "SCHIZO PCIERR-A", pbm);
1122
1123
1124 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1125 op = of_find_device_by_node(pbm->prom_node);
1126 if (op)
1127 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED,
1128 "SCHIZO PCIERR-B", pbm);
1129
1130 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1131 op = of_find_device_by_node(pbm->prom_node);
1132 if (op)
1133 request_irq(op->irqs[3], schizo_safarierr_intr, IRQF_SHARED,
1134 "SCHIZO SERR", p);
1135
1136 /* Enable UE and CE interrupts for controller. */
1137 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1138 (SCHIZO_ECCCTRL_EE |
1139 SCHIZO_ECCCTRL_UE |
1140 SCHIZO_ECCCTRL_CE));
1141
1142 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1143 SCHIZO_PCICTRL_ESLCK |
1144 SCHIZO_PCICTRL_TTO_ERR |
1145 SCHIZO_PCICTRL_RTRY_ERR |
1146 SCHIZO_PCICTRL_SBH_ERR |
1147 SCHIZO_PCICTRL_SERR |
1148 SCHIZO_PCICTRL_EEN);
1149
1150 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1151 SCHIZO_PCICTRL_SBH_INT);
1152
1153 /* Enable PCI Error interrupts and clear error
1154 * bits for each PBM.
1155 */
1156 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1157 tmp |= err_mask;
1158 tmp &= ~err_no_mask;
1159 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1160
1161 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR,
1162 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1163 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1164 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1165 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1166 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1167 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1168
1169 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1170 tmp |= err_mask;
1171 tmp &= ~err_no_mask;
1172 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1173
1174 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR,
1175 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1176 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1177 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1178 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1179 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1180 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1181
1182 /* Make all Safari error conditions fatal except unmapped
1183 * errors which we make generate interrupts.
1184 */
1185 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1186 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1187 BUS_ERROR_BADMC |
1188 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1189 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1190 BUS_ERROR_CIQTO |
1191 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1192 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1193 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1194 BUS_ERROR_ILL);
1195 #if 1
1196 /* XXX Something wrong with some Excalibur systems
1197 * XXX Sun is shipping. The behavior on a 2-cpu
1198 * XXX machine is that both CPU1 parity error bits
1199 * XXX are set and are immediately set again when
1200 * XXX their error status bits are cleared. Just
1201 * XXX ignore them for now. -DaveM
1202 */
1203 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1204 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1205 #endif
1206
1207 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1208 (SCHIZO_SAFERRCTRL_EN | err_mask));
1209
1210 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1211 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1212 }
1213
1214 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1215 {
1216 u8 *addr;
1217
1218 /* Set cache-line size to 64 bytes, this is actually
1219 * a nop but I do it for completeness.
1220 */
1221 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1222 0, PCI_CACHE_LINE_SIZE);
1223 pci_config_write8(addr, 64 / sizeof(u32));
1224
1225 /* Set PBM latency timer to 64 PCI clocks. */
1226 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1227 0, PCI_LATENCY_TIMER);
1228 pci_config_write8(addr, 64);
1229 }
1230
1231 static void schizo_scan_bus(struct pci_controller_info *p)
1232 {
1233 pbm_config_busmastering(&p->pbm_B);
1234 p->pbm_B.is_66mhz_capable =
1235 (of_find_property(p->pbm_B.prom_node, "66mhz-capable", NULL)
1236 != NULL);
1237 pbm_config_busmastering(&p->pbm_A);
1238 p->pbm_A.is_66mhz_capable =
1239 (of_find_property(p->pbm_A.prom_node, "66mhz-capable", NULL)
1240 != NULL);
1241
1242 p->pbm_B.pci_bus = pci_scan_one_pbm(&p->pbm_B);
1243 p->pbm_A.pci_bus = pci_scan_one_pbm(&p->pbm_A);
1244
1245 /* After the PCI bus scan is complete, we can register
1246 * the error interrupt handlers.
1247 */
1248 if (p->pbm_B.chip_type == PBM_CHIP_TYPE_TOMATILLO)
1249 tomatillo_register_error_handlers(p);
1250 else
1251 schizo_register_error_handlers(p);
1252 }
1253
1254 #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1255 #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1256 #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1257 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1258 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1259
1260 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1261 {
1262 unsigned long base = pbm->pbm_regs;
1263 u64 control;
1264
1265 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1266 /* TOMATILLO lacks streaming cache. */
1267 return;
1268 }
1269
1270 /* SCHIZO has context flushing. */
1271 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1272 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1273 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1274 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1275 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1276
1277 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1278 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1279 + 63UL)
1280 & ~63UL);
1281 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1282 __pa(pbm->stc.strbuf_flushflag);
1283
1284 /* Turn off LRU locking and diag mode, enable the
1285 * streaming buffer and leave the rerun-disable
1286 * setting however OBP set it.
1287 */
1288 control = schizo_read(pbm->stc.strbuf_control);
1289 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1290 SCHIZO_STRBUF_CTRL_LENAB |
1291 SCHIZO_STRBUF_CTRL_DENAB);
1292 control |= SCHIZO_STRBUF_CTRL_ENAB;
1293 schizo_write(pbm->stc.strbuf_control, control);
1294
1295 pbm->stc.strbuf_enabled = 1;
1296 }
1297
1298 #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1299 #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1300 #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1301 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1302
1303 static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1304 {
1305 struct pci_iommu *iommu = pbm->iommu;
1306 unsigned long i, tagbase, database;
1307 struct property *prop;
1308 u32 vdma[2], dma_mask;
1309 u64 control;
1310 int tsbsize;
1311
1312 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
1313 if (prop) {
1314 u32 *val = prop->value;
1315
1316 vdma[0] = val[0];
1317 vdma[1] = val[1];
1318 } else {
1319 /* No property, use default values. */
1320 vdma[0] = 0xc0000000;
1321 vdma[1] = 0x40000000;
1322 }
1323
1324 dma_mask = vdma[0];
1325 switch (vdma[1]) {
1326 case 0x20000000:
1327 dma_mask |= 0x1fffffff;
1328 tsbsize = 64;
1329 break;
1330
1331 case 0x40000000:
1332 dma_mask |= 0x3fffffff;
1333 tsbsize = 128;
1334 break;
1335
1336 case 0x80000000:
1337 dma_mask |= 0x7fffffff;
1338 tsbsize = 128;
1339 break;
1340
1341 default:
1342 prom_printf("SCHIZO: strange virtual-dma size.\n");
1343 prom_halt();
1344 };
1345
1346 /* Register addresses, SCHIZO has iommu ctx flushing. */
1347 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1348 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1349 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1350 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1351
1352 /* We use the main control/status register of SCHIZO as the write
1353 * completion register.
1354 */
1355 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1356
1357 /*
1358 * Invalidate TLB Entries.
1359 */
1360 control = schizo_read(iommu->iommu_control);
1361 control |= SCHIZO_IOMMU_CTRL_DENAB;
1362 schizo_write(iommu->iommu_control, control);
1363
1364 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1365
1366 for(i = 0; i < 16; i++) {
1367 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1368 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1369 }
1370
1371 /* Leave diag mode enabled for full-flushing done
1372 * in pci_iommu.c
1373 */
1374 pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
1375
1376 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1377
1378 control = schizo_read(iommu->iommu_control);
1379 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1380 switch (tsbsize) {
1381 case 64:
1382 control |= SCHIZO_IOMMU_TSBSZ_64K;
1383 break;
1384 case 128:
1385 control |= SCHIZO_IOMMU_TSBSZ_128K;
1386 break;
1387 };
1388
1389 control |= SCHIZO_IOMMU_CTRL_ENAB;
1390 schizo_write(iommu->iommu_control, control);
1391 }
1392
1393 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1394 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1395
1396 #define SCHIZO_PCI_DIAG (0x2020UL)
1397 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1398 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1399 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1400 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1401 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1402 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1403 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1404 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1405 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1406
1407 #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1408 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1409 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1410 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1411 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1412 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1413 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1414 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1415 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1416 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1417 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1418 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1419 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1420 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1421 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1422 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1423
1424 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1425 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1426
1427 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1428 {
1429 struct property *prop;
1430 u64 tmp;
1431
1432 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1433
1434 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1435
1436 /* Enable arbiter for all PCI slots. */
1437 tmp |= 0xff;
1438
1439 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1440 pbm->chip_version >= 0x2)
1441 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1442
1443 prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL);
1444 if (!prop)
1445 tmp |= SCHIZO_PCICTRL_PARK;
1446 else
1447 tmp &= ~SCHIZO_PCICTRL_PARK;
1448
1449 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1450 pbm->chip_version <= 0x1)
1451 tmp |= SCHIZO_PCICTRL_DTO_INT;
1452 else
1453 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1454
1455 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1456 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1457 SCHIZO_PCICTRL_RDO_PREF |
1458 SCHIZO_PCICTRL_RDL_PREF);
1459
1460 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1461
1462 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1463 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1464 SCHIZO_PCIDIAG_D_RETRY |
1465 SCHIZO_PCIDIAG_D_INTSYNC);
1466 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1467
1468 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1469 /* Clear prefetch lengths to workaround a bug in
1470 * Jalapeno...
1471 */
1472 tmp = (TOMATILLO_IOC_PART_WPENAB |
1473 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1474 TOMATILLO_IOC_RDMULT_CPENAB |
1475 TOMATILLO_IOC_RDONE_CPENAB |
1476 TOMATILLO_IOC_RDLINE_CPENAB);
1477
1478 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1479 tmp);
1480 }
1481 }
1482
1483 static void schizo_pbm_init(struct pci_controller_info *p,
1484 struct device_node *dp, u32 portid,
1485 int chip_type)
1486 {
1487 struct linux_prom64_registers *regs;
1488 unsigned int *busrange;
1489 struct pci_pbm_info *pbm;
1490 const char *chipset_name;
1491 u32 *ino_bitmap;
1492 int is_pbm_a;
1493
1494 switch (chip_type) {
1495 case PBM_CHIP_TYPE_TOMATILLO:
1496 chipset_name = "TOMATILLO";
1497 break;
1498
1499 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1500 chipset_name = "SCHIZO+";
1501 break;
1502
1503 case PBM_CHIP_TYPE_SCHIZO:
1504 default:
1505 chipset_name = "SCHIZO";
1506 break;
1507 };
1508
1509 /* For SCHIZO, three OBP regs:
1510 * 1) PBM controller regs
1511 * 2) Schizo front-end controller regs (same for both PBMs)
1512 * 3) PBM PCI config space
1513 *
1514 * For TOMATILLO, four OBP regs:
1515 * 1) PBM controller regs
1516 * 2) Tomatillo front-end controller regs
1517 * 3) PBM PCI config space
1518 * 4) Ichip regs
1519 */
1520 regs = of_get_property(dp, "reg", NULL);
1521
1522 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1523 if (is_pbm_a)
1524 pbm = &p->pbm_A;
1525 else
1526 pbm = &p->pbm_B;
1527
1528 pbm->portid = portid;
1529 pbm->parent = p;
1530 pbm->prom_node = dp;
1531 pbm->pci_first_slot = 1;
1532
1533 pbm->chip_type = chip_type;
1534 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1535 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
1536
1537 pbm->pbm_regs = regs[0].phys_addr;
1538 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1539
1540 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1541 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
1542
1543 pbm->name = dp->full_name;
1544
1545 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
1546 pbm->name, chipset_name,
1547 pbm->chip_version, pbm->chip_revision);
1548
1549 schizo_pbm_hw_init(pbm);
1550
1551 pci_determine_mem_io_space(pbm);
1552
1553 ino_bitmap = of_get_property(dp, "ino-bitmap", NULL);
1554 pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
1555 ((u64)ino_bitmap[0] << 0UL));
1556
1557 busrange = of_get_property(dp, "bus-range", NULL);
1558 pbm->pci_first_busno = busrange[0];
1559 pbm->pci_last_busno = busrange[1];
1560
1561 schizo_pbm_iommu_init(pbm);
1562 schizo_pbm_strbuf_init(pbm);
1563 }
1564
1565 static inline int portid_compare(u32 x, u32 y, int chip_type)
1566 {
1567 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1568 if (x == (y ^ 1))
1569 return 1;
1570 return 0;
1571 }
1572 return (x == y);
1573 }
1574
1575 static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
1576 {
1577 struct pci_controller_info *p;
1578 struct pci_iommu *iommu;
1579 u32 portid;
1580
1581 portid = of_getintprop_default(dp, "portid", 0xff);
1582
1583 for (p = pci_controller_root; p; p = p->next) {
1584 struct pci_pbm_info *pbm;
1585
1586 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
1587 continue;
1588
1589 pbm = (p->pbm_A.prom_node ?
1590 &p->pbm_A :
1591 &p->pbm_B);
1592
1593 if (portid_compare(pbm->portid, portid, chip_type)) {
1594 schizo_pbm_init(p, dp, portid, chip_type);
1595 return;
1596 }
1597 }
1598
1599 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1600 if (!p)
1601 goto memfail;
1602
1603 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1604 if (!iommu)
1605 goto memfail;
1606
1607 p->pbm_A.iommu = iommu;
1608
1609 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1610 if (!iommu)
1611 goto memfail;
1612
1613 p->pbm_B.iommu = iommu;
1614
1615 p->next = pci_controller_root;
1616 pci_controller_root = p;
1617
1618 p->index = pci_num_controllers++;
1619 p->scan_bus = schizo_scan_bus;
1620 p->pci_ops = &schizo_ops;
1621
1622 /* Like PSYCHO we have a 2GB aligned area for memory space. */
1623 pci_memspace_mask = 0x7fffffffUL;
1624
1625 schizo_pbm_init(p, dp, portid, chip_type);
1626 return;
1627
1628 memfail:
1629 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1630 prom_halt();
1631 }
1632
1633 void schizo_init(struct device_node *dp, char *model_name)
1634 {
1635 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO);
1636 }
1637
1638 void schizo_plus_init(struct device_node *dp, char *model_name)
1639 {
1640 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
1641 }
1642
1643 void tomatillo_init(struct device_node *dp, char *model_name)
1644 {
1645 __schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO);
1646 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree