2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 Abstract: rt2800 generic device routines.
36 #include <linux/kernel.h>
37 #include <linux/module.h>
40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
41 #include "rt2x00usb.h"
43 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
44 #include "rt2x00pci.h"
46 #include "rt2800lib.h"
48 #include "rt2800usb.h"
50 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
51 MODULE_DESCRIPTION("rt2800 library");
52 MODULE_LICENSE("GPL");
56 * All access to the CSR registers will go through the methods
57 * rt2800_register_read and rt2800_register_write.
58 * BBP and RF register require indirect register access,
59 * and use the CSR registers BBPCSR and RFCSR to achieve this.
60 * These indirect registers work with busy bits,
61 * and we will try maximal REGISTER_BUSY_COUNT times to access
62 * the register while taking a REGISTER_BUSY_DELAY us delay
63 * between each attampt. When the busy bit is still set at that time,
64 * the access attempt is considered to have failed,
65 * and we will print an error.
66 * The _lock versions must be used if you already hold the csr_mutex
68 #define WAIT_FOR_BBP(__dev, __reg) \
69 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
70 #define WAIT_FOR_RFCSR(__dev, __reg) \
71 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
72 #define WAIT_FOR_RF(__dev, __reg) \
73 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
74 #define WAIT_FOR_MCU(__dev, __reg) \
75 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
76 H2M_MAILBOX_CSR_OWNER, (__reg))
78 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
79 const unsigned int word
, const u8 value
)
83 mutex_lock(&rt2x00dev
->csr_mutex
);
86 * Wait until the BBP becomes available, afterwards we
87 * can safely write the new data into the register.
89 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
91 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
92 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
93 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
94 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
95 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
96 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
98 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
101 mutex_unlock(&rt2x00dev
->csr_mutex
);
104 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
105 const unsigned int word
, u8
*value
)
109 mutex_lock(&rt2x00dev
->csr_mutex
);
112 * Wait until the BBP becomes available, afterwards we
113 * can safely write the read request into the register.
114 * After the data has been written, we wait until hardware
115 * returns the correct value, if at any time the register
116 * doesn't become available in time, reg will be 0xffffffff
117 * which means we return 0xff to the caller.
119 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
121 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
122 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
123 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
124 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
125 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
127 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
129 WAIT_FOR_BBP(rt2x00dev
, ®
);
132 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
134 mutex_unlock(&rt2x00dev
->csr_mutex
);
137 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
138 const unsigned int word
, const u8 value
)
142 mutex_lock(&rt2x00dev
->csr_mutex
);
145 * Wait until the RFCSR becomes available, afterwards we
146 * can safely write the new data into the register.
148 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
150 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
151 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
152 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
153 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
155 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
158 mutex_unlock(&rt2x00dev
->csr_mutex
);
161 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
162 const unsigned int word
, u8
*value
)
166 mutex_lock(&rt2x00dev
->csr_mutex
);
169 * Wait until the RFCSR becomes available, afterwards we
170 * can safely write the read request into the register.
171 * After the data has been written, we wait until hardware
172 * returns the correct value, if at any time the register
173 * doesn't become available in time, reg will be 0xffffffff
174 * which means we return 0xff to the caller.
176 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
178 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
179 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
180 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
182 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
184 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
187 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
189 mutex_unlock(&rt2x00dev
->csr_mutex
);
192 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
193 const unsigned int word
, const u32 value
)
197 mutex_lock(&rt2x00dev
->csr_mutex
);
200 * Wait until the RF becomes available, afterwards we
201 * can safely write the new data into the register.
203 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
205 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
206 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
207 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
208 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
210 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
211 rt2x00_rf_write(rt2x00dev
, word
, value
);
214 mutex_unlock(&rt2x00dev
->csr_mutex
);
217 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
218 const u8 command
, const u8 token
,
219 const u8 arg0
, const u8 arg1
)
224 * SOC devices don't support MCU requests.
226 if (rt2x00_is_soc(rt2x00dev
))
229 mutex_lock(&rt2x00dev
->csr_mutex
);
232 * Wait until the MCU becomes available, afterwards we
233 * can safely write the new data into the register.
235 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
236 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
237 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
238 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
239 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
240 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
243 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
244 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
247 mutex_unlock(&rt2x00dev
->csr_mutex
);
249 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
251 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
256 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
257 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
258 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
259 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
265 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
268 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
271 const struct rt2x00debug rt2800_rt2x00debug
= {
272 .owner
= THIS_MODULE
,
274 .read
= rt2800_register_read
,
275 .write
= rt2800_register_write
,
276 .flags
= RT2X00DEBUGFS_OFFSET
,
277 .word_base
= CSR_REG_BASE
,
278 .word_size
= sizeof(u32
),
279 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
282 .read
= rt2x00_eeprom_read
,
283 .write
= rt2x00_eeprom_write
,
284 .word_base
= EEPROM_BASE
,
285 .word_size
= sizeof(u16
),
286 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
289 .read
= rt2800_bbp_read
,
290 .write
= rt2800_bbp_write
,
291 .word_base
= BBP_BASE
,
292 .word_size
= sizeof(u8
),
293 .word_count
= BBP_SIZE
/ sizeof(u8
),
296 .read
= rt2x00_rf_read
,
297 .write
= rt2800_rf_write
,
298 .word_base
= RF_BASE
,
299 .word_size
= sizeof(u32
),
300 .word_count
= RF_SIZE
/ sizeof(u32
),
303 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
304 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
306 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
310 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
311 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
313 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
315 #ifdef CONFIG_RT2X00_LIB_LEDS
316 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
317 enum led_brightness brightness
)
319 struct rt2x00_led
*led
=
320 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
321 unsigned int enabled
= brightness
!= LED_OFF
;
322 unsigned int bg_mode
=
323 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
324 unsigned int polarity
=
325 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
326 EEPROM_FREQ_LED_POLARITY
);
327 unsigned int ledmode
=
328 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
329 EEPROM_FREQ_LED_MODE
);
331 if (led
->type
== LED_TYPE_RADIO
) {
332 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
334 } else if (led
->type
== LED_TYPE_ASSOC
) {
335 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
336 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
337 } else if (led
->type
== LED_TYPE_QUALITY
) {
339 * The brightness is divided into 6 levels (0 - 5),
340 * The specs tell us the following levels:
342 * to determine the level in a simple way we can simply
343 * work with bitshifting:
346 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
347 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
352 static int rt2800_blink_set(struct led_classdev
*led_cdev
,
353 unsigned long *delay_on
, unsigned long *delay_off
)
355 struct rt2x00_led
*led
=
356 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
359 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
360 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, *delay_on
);
361 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, *delay_off
);
362 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
367 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
368 struct rt2x00_led
*led
, enum led_type type
)
370 led
->rt2x00dev
= rt2x00dev
;
372 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
373 led
->led_dev
.blink_set
= rt2800_blink_set
;
374 led
->flags
= LED_INITIALIZED
;
376 #endif /* CONFIG_RT2X00_LIB_LEDS */
379 * Configuration handlers.
381 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
382 struct rt2x00lib_crypto
*crypto
,
383 struct ieee80211_key_conf
*key
)
385 struct mac_wcid_entry wcid_entry
;
386 struct mac_iveiv_entry iveiv_entry
;
390 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
392 rt2800_register_read(rt2x00dev
, offset
, ®
);
393 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
394 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
395 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
396 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
397 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
398 (crypto
->cmd
== SET_KEY
) * crypto
->bssidx
);
399 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
400 rt2800_register_write(rt2x00dev
, offset
, reg
);
402 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
404 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
405 if ((crypto
->cipher
== CIPHER_TKIP
) ||
406 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
407 (crypto
->cipher
== CIPHER_AES
))
408 iveiv_entry
.iv
[3] |= 0x20;
409 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
410 rt2800_register_multiwrite(rt2x00dev
, offset
,
411 &iveiv_entry
, sizeof(iveiv_entry
));
413 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
415 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
416 if (crypto
->cmd
== SET_KEY
)
417 memcpy(&wcid_entry
, crypto
->address
, ETH_ALEN
);
418 rt2800_register_multiwrite(rt2x00dev
, offset
,
419 &wcid_entry
, sizeof(wcid_entry
));
422 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
423 struct rt2x00lib_crypto
*crypto
,
424 struct ieee80211_key_conf
*key
)
426 struct hw_key_entry key_entry
;
427 struct rt2x00_field32 field
;
431 if (crypto
->cmd
== SET_KEY
) {
432 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
434 memcpy(key_entry
.key
, crypto
->key
,
435 sizeof(key_entry
.key
));
436 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
437 sizeof(key_entry
.tx_mic
));
438 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
439 sizeof(key_entry
.rx_mic
));
441 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
442 rt2800_register_multiwrite(rt2x00dev
, offset
,
443 &key_entry
, sizeof(key_entry
));
447 * The cipher types are stored over multiple registers
448 * starting with SHARED_KEY_MODE_BASE each word will have
449 * 32 bits and contains the cipher types for 2 bssidx each.
450 * Using the correct defines correctly will cause overhead,
451 * so just calculate the correct offset.
453 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
454 field
.bit_mask
= 0x7 << field
.bit_offset
;
456 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
458 rt2800_register_read(rt2x00dev
, offset
, ®
);
459 rt2x00_set_field32(®
, field
,
460 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
461 rt2800_register_write(rt2x00dev
, offset
, reg
);
464 * Update WCID information
466 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
470 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
472 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
473 struct rt2x00lib_crypto
*crypto
,
474 struct ieee80211_key_conf
*key
)
476 struct hw_key_entry key_entry
;
479 if (crypto
->cmd
== SET_KEY
) {
481 * 1 pairwise key is possible per AID, this means that the AID
482 * equals our hw_key_idx. Make sure the WCID starts _after_ the
483 * last possible shared key entry.
485 if (crypto
->aid
> (256 - 32))
488 key
->hw_key_idx
= 32 + crypto
->aid
;
490 memcpy(key_entry
.key
, crypto
->key
,
491 sizeof(key_entry
.key
));
492 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
493 sizeof(key_entry
.tx_mic
));
494 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
495 sizeof(key_entry
.rx_mic
));
497 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
498 rt2800_register_multiwrite(rt2x00dev
, offset
,
499 &key_entry
, sizeof(key_entry
));
503 * Update WCID information
505 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
509 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
511 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
512 const unsigned int filter_flags
)
517 * Start configuration steps.
518 * Note that the version error will always be dropped
519 * and broadcast frames will always be accepted since
520 * there is no filter for it at this time.
522 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
523 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
524 !(filter_flags
& FIF_FCSFAIL
));
525 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
526 !(filter_flags
& FIF_PLCPFAIL
));
527 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
528 !(filter_flags
& FIF_PROMISC_IN_BSS
));
529 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
530 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
531 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
532 !(filter_flags
& FIF_ALLMULTI
));
533 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
534 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
535 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
536 !(filter_flags
& FIF_CONTROL
));
537 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
538 !(filter_flags
& FIF_CONTROL
));
539 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
540 !(filter_flags
& FIF_CONTROL
));
541 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
542 !(filter_flags
& FIF_CONTROL
));
543 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
544 !(filter_flags
& FIF_CONTROL
));
545 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
546 !(filter_flags
& FIF_PSPOLL
));
547 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
548 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
549 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
550 !(filter_flags
& FIF_CONTROL
));
551 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
553 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
555 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
556 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
558 unsigned int beacon_base
;
561 if (flags
& CONFIG_UPDATE_TYPE
) {
563 * Clear current synchronisation setup.
564 * For the Beacon base registers we only need to clear
565 * the first byte since that byte contains the VALID and OWNER
566 * bits which (when set to 0) will invalidate the entire beacon.
568 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
569 rt2800_register_write(rt2x00dev
, beacon_base
, 0);
572 * Enable synchronisation.
574 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
575 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
576 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
577 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
,
578 (conf
->sync
== TSF_SYNC_BEACON
));
579 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
582 if (flags
& CONFIG_UPDATE_MAC
) {
583 reg
= le32_to_cpu(conf
->mac
[1]);
584 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
585 conf
->mac
[1] = cpu_to_le32(reg
);
587 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
588 conf
->mac
, sizeof(conf
->mac
));
591 if (flags
& CONFIG_UPDATE_BSSID
) {
592 reg
= le32_to_cpu(conf
->bssid
[1]);
593 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 0);
594 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 0);
595 conf
->bssid
[1] = cpu_to_le32(reg
);
597 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
598 conf
->bssid
, sizeof(conf
->bssid
));
601 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
603 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
)
607 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
608 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
609 !!erp
->short_preamble
);
610 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
611 !!erp
->short_preamble
);
612 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
614 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
615 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
616 erp
->cts_protection
? 2 : 0);
617 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
619 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
621 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
623 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
624 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, erp
->slot_time
);
625 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
627 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
628 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, erp
->sifs
);
629 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, erp
->sifs
);
630 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
631 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
633 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
634 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
635 erp
->beacon_int
* 16);
636 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
638 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
640 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
645 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
646 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
649 * Configure the TX antenna.
651 switch ((int)ant
->tx
) {
653 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
654 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
655 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
658 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
666 * Configure the RX antenna.
668 switch ((int)ant
->rx
) {
670 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
673 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
676 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
680 rt2800_bbp_write(rt2x00dev
, 3, r3
);
681 rt2800_bbp_write(rt2x00dev
, 1, r1
);
683 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
685 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
686 struct rt2x00lib_conf
*libconf
)
691 if (libconf
->rf
.channel
<= 14) {
692 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
693 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
694 } else if (libconf
->rf
.channel
<= 64) {
695 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
696 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
697 } else if (libconf
->rf
.channel
<= 128) {
698 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
699 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
701 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
702 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
705 rt2x00dev
->lna_gain
= lna_gain
;
708 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
709 struct ieee80211_conf
*conf
,
710 struct rf_channel
*rf
,
711 struct channel_info
*info
)
713 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
715 if (rt2x00dev
->default_ant
.tx
== 1)
716 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
718 if (rt2x00dev
->default_ant
.rx
== 1) {
719 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
720 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
721 } else if (rt2x00dev
->default_ant
.rx
== 2)
722 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
724 if (rf
->channel
> 14) {
726 * When TX power is below 0, we should increase it by 7 to
727 * make it a positive value (Minumum value is -7).
728 * However this means that values between 0 and 7 have
729 * double meaning, and we should set a 7DBm boost flag.
731 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
732 (info
->tx_power1
>= 0));
734 if (info
->tx_power1
< 0)
735 info
->tx_power1
+= 7;
737 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
,
738 TXPOWER_A_TO_DEV(info
->tx_power1
));
740 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
741 (info
->tx_power2
>= 0));
743 if (info
->tx_power2
< 0)
744 info
->tx_power2
+= 7;
746 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
,
747 TXPOWER_A_TO_DEV(info
->tx_power2
));
749 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
,
750 TXPOWER_G_TO_DEV(info
->tx_power1
));
751 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
,
752 TXPOWER_G_TO_DEV(info
->tx_power2
));
755 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
757 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
758 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
759 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
760 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
764 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
765 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
766 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
767 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
771 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
772 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
773 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
774 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
777 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
778 struct ieee80211_conf
*conf
,
779 struct rf_channel
*rf
,
780 struct channel_info
*info
)
784 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
785 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
787 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
788 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
789 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
791 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
792 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
793 TXPOWER_G_TO_DEV(info
->tx_power1
));
794 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
796 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
797 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
798 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
800 rt2800_rfcsr_write(rt2x00dev
, 24,
801 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
803 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
804 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
805 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
808 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
809 struct ieee80211_conf
*conf
,
810 struct rf_channel
*rf
,
811 struct channel_info
*info
)
817 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
818 rt2x00_rf(rt2x00dev
, RF3020
) ||
819 rt2x00_rf(rt2x00dev
, RF3021
) ||
820 rt2x00_rf(rt2x00dev
, RF3022
))
821 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
823 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
826 * Change BBP settings
828 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
829 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
830 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
831 rt2800_bbp_write(rt2x00dev
, 86, 0);
833 if (rf
->channel
<= 14) {
834 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
835 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
836 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
838 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
839 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
842 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
844 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
845 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
847 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
850 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
851 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_PLUS
, conf_is_ht40_plus(conf
));
852 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
853 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
854 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
858 /* Turn on unused PA or LNA when not using 1T or 1R */
859 if (rt2x00dev
->default_ant
.tx
!= 1) {
860 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
861 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
864 /* Turn on unused PA or LNA when not using 1T or 1R */
865 if (rt2x00dev
->default_ant
.rx
!= 1) {
866 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
867 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
870 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
871 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
872 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
873 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
874 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, rf
->channel
<= 14);
875 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
877 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
879 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
880 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
881 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
883 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
884 rt2x00_set_field8(&bbp
, BBP3_HT40_PLUS
, conf_is_ht40_plus(conf
));
885 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
887 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
888 if (conf_is_ht40(conf
)) {
889 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
890 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
891 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
893 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
894 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
895 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
902 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
906 u32 value
= TXPOWER_G_TO_DEV(txpower
);
909 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
910 rt2x00_set_field8(®
, BBP1_TX_POWER
, 0);
911 rt2800_bbp_write(rt2x00dev
, 1, r1
);
913 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
914 rt2x00_set_field32(®
, TX_PWR_CFG_0_1MBS
, value
);
915 rt2x00_set_field32(®
, TX_PWR_CFG_0_2MBS
, value
);
916 rt2x00_set_field32(®
, TX_PWR_CFG_0_55MBS
, value
);
917 rt2x00_set_field32(®
, TX_PWR_CFG_0_11MBS
, value
);
918 rt2x00_set_field32(®
, TX_PWR_CFG_0_6MBS
, value
);
919 rt2x00_set_field32(®
, TX_PWR_CFG_0_9MBS
, value
);
920 rt2x00_set_field32(®
, TX_PWR_CFG_0_12MBS
, value
);
921 rt2x00_set_field32(®
, TX_PWR_CFG_0_18MBS
, value
);
922 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0
, reg
);
924 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_1
, ®
);
925 rt2x00_set_field32(®
, TX_PWR_CFG_1_24MBS
, value
);
926 rt2x00_set_field32(®
, TX_PWR_CFG_1_36MBS
, value
);
927 rt2x00_set_field32(®
, TX_PWR_CFG_1_48MBS
, value
);
928 rt2x00_set_field32(®
, TX_PWR_CFG_1_54MBS
, value
);
929 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS0
, value
);
930 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS1
, value
);
931 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS2
, value
);
932 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS3
, value
);
933 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1
, reg
);
935 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_2
, ®
);
936 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS4
, value
);
937 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS5
, value
);
938 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS6
, value
);
939 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS7
, value
);
940 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS8
, value
);
941 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS9
, value
);
942 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS10
, value
);
943 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS11
, value
);
944 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2
, reg
);
946 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_3
, ®
);
947 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS12
, value
);
948 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS13
, value
);
949 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS14
, value
);
950 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS15
, value
);
951 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN1
, value
);
952 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN2
, value
);
953 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN3
, value
);
954 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN4
, value
);
955 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3
, reg
);
957 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_4
, ®
);
958 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN5
, value
);
959 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN6
, value
);
960 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN7
, value
);
961 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN8
, value
);
962 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4
, reg
);
965 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
966 struct rt2x00lib_conf
*libconf
)
970 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
971 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
972 libconf
->conf
->short_frame_max_tx_count
);
973 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
974 libconf
->conf
->long_frame_max_tx_count
);
975 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
978 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
979 struct rt2x00lib_conf
*libconf
)
981 enum dev_state state
=
982 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
983 STATE_SLEEP
: STATE_AWAKE
;
986 if (state
== STATE_SLEEP
) {
987 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
989 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
990 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
991 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
992 libconf
->conf
->listen_interval
- 1);
993 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
994 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
996 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
998 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
999 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
1000 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
1001 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
1002 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1004 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1008 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
1009 struct rt2x00lib_conf
*libconf
,
1010 const unsigned int flags
)
1012 /* Always recalculate LNA gain before changing configuration */
1013 rt2800_config_lna_gain(rt2x00dev
, libconf
);
1015 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
1016 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
1017 &libconf
->rf
, &libconf
->channel
);
1018 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
1019 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1020 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1021 rt2800_config_retry_limit(rt2x00dev
, libconf
);
1022 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1023 rt2800_config_ps(rt2x00dev
, libconf
);
1025 EXPORT_SYMBOL_GPL(rt2800_config
);
1030 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1035 * Update FCS error count from register.
1037 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1038 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
1040 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
1042 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
1044 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
1045 if (rt2x00_rt(rt2x00dev
, RT3070
))
1046 return 0x1c + (2 * rt2x00dev
->lna_gain
);
1048 return 0x2e + rt2x00dev
->lna_gain
;
1051 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
1052 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
1054 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
1057 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1058 struct link_qual
*qual
, u8 vgc_level
)
1060 if (qual
->vgc_level
!= vgc_level
) {
1061 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
1062 qual
->vgc_level
= vgc_level
;
1063 qual
->vgc_level_reg
= vgc_level
;
1067 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1069 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
1071 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
1073 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
1076 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
1080 * When RSSI is better then -80 increase VGC level with 0x10
1082 rt2800_set_vgc(rt2x00dev
, qual
,
1083 rt2800_get_default_vgc(rt2x00dev
) +
1084 ((qual
->rssi
> -80) * 0x10));
1086 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
1089 * Initialization functions.
1091 int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
1096 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1097 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1098 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1099 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1100 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1101 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
1102 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1104 if (rt2x00_is_usb(rt2x00dev
)) {
1106 * Wait until BBP and RF are ready.
1108 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1109 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1110 if (reg
&& reg
!= ~0)
1115 if (i
== REGISTER_BUSY_COUNT
) {
1116 ERROR(rt2x00dev
, "Unstable hardware.\n");
1120 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
1121 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
,
1123 } else if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
)) {
1127 rt2800_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
1128 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
1129 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
1130 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
1131 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
1132 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
1133 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
1134 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
1135 rt2800_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
1137 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
1138 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
1140 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
1143 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
1144 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_CSR
, 1);
1145 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_BBP
, 1);
1146 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
1148 if (rt2x00_is_usb(rt2x00dev
)) {
1149 rt2800_register_write(rt2x00dev
, USB_DMA_CFG
, 0x00000000);
1150 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1151 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
, 0,
1152 USB_MODE_RESET
, REGISTER_TIMEOUT
);
1156 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1158 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
1159 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
1160 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
1161 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
1162 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
1163 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
1165 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
1166 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
1167 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
1168 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
1169 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
1170 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
1172 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
1173 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1175 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1177 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1178 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 0);
1179 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
1180 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
1181 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
1182 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1183 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
1184 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1186 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
1188 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1189 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
1190 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
1191 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1193 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1194 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1196 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1197 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1198 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
1200 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1201 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1204 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
1205 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1208 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
1209 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
1210 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
1211 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
1212 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
1213 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
1214 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
1215 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
1216 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
1217 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
1219 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
1220 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
1221 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
1222 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
1223 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
1225 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
1226 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
1227 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
1228 rt2x00_rt(rt2x00dev
, RT2883
) ||
1229 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
1230 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
1232 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
1233 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
1234 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
1235 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
1237 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1238 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
1239 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
1240 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
1241 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
1242 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
1243 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
1244 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
1245 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1247 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
1249 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1250 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
1251 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
1252 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
1253 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
1254 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
1255 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
1256 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1258 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1259 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
1260 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
1261 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
1262 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
1263 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
1264 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
1265 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
1266 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1268 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
1269 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
1270 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
1271 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV
, 1);
1272 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1273 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1274 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1275 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1276 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1277 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1278 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
1279 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
1281 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1282 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
1283 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
1284 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV
, 1);
1285 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1286 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1287 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1288 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1289 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1290 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1291 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
1292 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1294 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1295 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
1296 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
1297 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV
, 1);
1298 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1299 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1300 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1301 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1302 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1303 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1304 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
1305 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1307 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1308 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
1309 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
,
1310 !rt2x00_is_usb(rt2x00dev
));
1311 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV
, 1);
1312 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1313 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1314 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1315 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1316 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1317 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1318 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
1319 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1321 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1322 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
1323 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
1324 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV
, 1);
1325 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1326 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1327 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1328 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1329 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1330 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1331 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
1332 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1334 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1335 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
1336 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
1337 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV
, 1);
1338 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1339 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1340 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1341 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1342 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1343 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1344 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
1345 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1347 if (rt2x00_is_usb(rt2x00dev
)) {
1348 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
1350 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1351 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1352 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1353 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1354 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1355 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
1356 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
1357 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
1358 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
1359 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
1360 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1363 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, 0x0000583f);
1364 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
1366 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
1367 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
1368 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
1369 IEEE80211_MAX_RTS_THRESHOLD
);
1370 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
1371 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
1373 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
1375 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1376 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 32);
1377 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 32);
1378 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
1379 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
1380 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
1381 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1383 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
1386 * ASIC will keep garbage value after boot, clear encryption keys.
1388 for (i
= 0; i
< 4; i
++)
1389 rt2800_register_write(rt2x00dev
,
1390 SHARED_KEY_MODE_ENTRY(i
), 0);
1392 for (i
= 0; i
< 256; i
++) {
1393 u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
1394 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
1395 wcid
, sizeof(wcid
));
1397 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 1);
1398 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
1403 * For the Beacon base registers we only need to clear
1404 * the first byte since that byte contains the VALID and OWNER
1405 * bits which (when set to 0) will invalidate the entire beacon.
1407 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1408 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1409 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1410 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1411 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE4
, 0);
1412 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE5
, 0);
1413 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE6
, 0);
1414 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE7
, 0);
1416 if (rt2x00_is_usb(rt2x00dev
)) {
1417 rt2800_register_read(rt2x00dev
, USB_CYC_CFG
, ®
);
1418 rt2x00_set_field32(®
, USB_CYC_CFG_CLOCK_CYCLE
, 30);
1419 rt2800_register_write(rt2x00dev
, USB_CYC_CFG
, reg
);
1422 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
1423 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
1424 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
1425 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
1426 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
1427 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
1428 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
1429 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
1430 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
1431 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
1433 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
1434 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
1435 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
1436 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
1437 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
1438 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
1439 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
1440 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
1441 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
1442 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
1444 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
1445 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
1446 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
1447 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
1448 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
1449 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
1450 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
1451 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
1452 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
1453 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
1455 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
1456 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
1457 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
1458 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
1459 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
1460 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
1463 * We must clear the error counters.
1464 * These registers are cleared on read,
1465 * so we may pass a useless variable to store the value.
1467 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1468 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
1469 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
1470 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
1471 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
1472 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
1476 EXPORT_SYMBOL_GPL(rt2800_init_registers
);
1478 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
1483 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1484 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
1485 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
1488 udelay(REGISTER_BUSY_DELAY
);
1491 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
1495 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1501 * BBP was enabled after firmware was loaded,
1502 * but we need to reactivate it now.
1504 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
1505 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1508 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1509 rt2800_bbp_read(rt2x00dev
, 0, &value
);
1510 if ((value
!= 0xff) && (value
!= 0x00))
1512 udelay(REGISTER_BUSY_DELAY
);
1515 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1519 int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1526 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
1527 rt2800_wait_bbp_ready(rt2x00dev
)))
1530 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
1531 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
1533 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1534 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1535 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
1537 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
1538 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
1541 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1543 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1544 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
1545 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
1546 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
1548 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
1551 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1552 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
1554 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
) ||
1555 rt2x00_rt_rev(rt2x00dev
, RT2870
, REV_RT2870D
))
1556 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
1558 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
1560 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
1561 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
1562 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
1564 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
))
1565 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
1567 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
1569 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
1570 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
1572 if (rt2x00_rt(rt2x00dev
, RT2872
)) {
1573 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
1574 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
1575 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
1578 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1579 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1581 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1582 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1583 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1584 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
1590 EXPORT_SYMBOL_GPL(rt2800_init_bbp
);
1592 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
1593 bool bw40
, u8 rfcsr24
, u8 filter_target
)
1602 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1604 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1605 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
1606 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1608 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
1609 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
1610 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
1613 * Set power & frequency of passband test tone
1615 rt2800_bbp_write(rt2x00dev
, 24, 0);
1617 for (i
= 0; i
< 100; i
++) {
1618 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1621 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
1627 * Set power & frequency of stopband test tone
1629 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
1631 for (i
= 0; i
< 100; i
++) {
1632 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1635 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
1637 if ((passband
- stopband
) <= filter_target
) {
1639 overtuned
+= ((passband
- stopband
) == filter_target
);
1643 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1646 rfcsr24
-= !!overtuned
;
1648 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1652 int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
1659 if (!rt2x00_rt(rt2x00dev
, RT3070
))
1663 * Init RF calibration.
1665 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1666 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1667 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1669 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1670 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1672 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1673 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1674 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
1675 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
1676 rt2800_rfcsr_write(rt2x00dev
, 7, 0x70);
1677 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
1678 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
1679 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1680 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
1681 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1682 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
1683 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
1684 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
1685 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
1686 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
1687 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
1688 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
1689 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
1690 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1691 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
1694 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1695 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
1696 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
1697 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
1698 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
1702 * Set RX Filter calibration for 20MHz and 40MHz
1704 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1705 rt2x00dev
->calibration
[0] =
1706 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
1707 rt2x00dev
->calibration
[1] =
1708 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
1712 * Set back to initial state
1714 rt2800_bbp_write(rt2x00dev
, 24, 0);
1716 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
1717 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
1718 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
1721 * set BBP back to BW20
1723 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1724 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
1725 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1727 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
1728 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
1730 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
1731 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
1732 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
1734 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1735 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
1736 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
1737 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
1738 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
1739 rt2x00_get_field16(eeprom
,
1740 EEPROM_TXMIXER_GAIN_BG_VAL
));
1741 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1743 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1744 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
1745 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
1746 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
1748 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
1749 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
1750 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
1751 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
1752 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
1757 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr
);
1759 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
1763 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
1765 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
1767 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
1769 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
1773 mutex_lock(&rt2x00dev
->csr_mutex
);
1775 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
1776 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
1777 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
1778 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
1779 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
1781 /* Wait until the EEPROM has been loaded */
1782 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
1784 /* Apparently the data is read from end to start */
1785 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
1786 (u32
*)&rt2x00dev
->eeprom
[i
]);
1787 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
1788 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
1789 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
1790 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
1791 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
1792 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
1794 mutex_unlock(&rt2x00dev
->csr_mutex
);
1797 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
1801 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
1802 rt2800_efuse_read(rt2x00dev
, i
);
1804 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
1806 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1810 u8 default_lna_gain
;
1813 * Start validation of the data that has been read.
1815 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1816 if (!is_valid_ether_addr(mac
)) {
1817 random_ether_addr(mac
);
1818 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
1821 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1822 if (word
== 0xffff) {
1823 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
1824 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TXPATH
, 1);
1825 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2820
);
1826 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1827 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1828 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
1829 rt2x00_rt(rt2x00dev
, RT2870
) ||
1830 rt2x00_rt(rt2x00dev
, RT2872
) ||
1831 rt2x00_rt(rt2x00dev
, RT2872
)) {
1833 * There is a max of 2 RX streams for RT28x0 series
1835 if (rt2x00_get_field16(word
, EEPROM_ANTENNA_RXPATH
) > 2)
1836 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
1837 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1840 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1841 if (word
== 0xffff) {
1842 rt2x00_set_field16(&word
, EEPROM_NIC_HW_RADIO
, 0);
1843 rt2x00_set_field16(&word
, EEPROM_NIC_DYNAMIC_TX_AGC
, 0);
1844 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
1845 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
1846 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
1847 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_BG
, 0);
1848 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_A
, 0);
1849 rt2x00_set_field16(&word
, EEPROM_NIC_WPS_PBC
, 0);
1850 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_BG
, 0);
1851 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_A
, 0);
1852 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1853 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1856 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
1857 if ((word
& 0x00ff) == 0x00ff) {
1858 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
1859 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
1860 LED_MODE_TXRX_ACTIVITY
);
1861 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
1862 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
1863 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED1
, 0x5555);
1864 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED2
, 0x2221);
1865 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED3
, 0xa9f8);
1866 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
1870 * During the LNA validation we are going to use
1871 * lna0 as correct value. Note that EEPROM_LNA
1872 * is never validated.
1874 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
1875 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
1877 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
1878 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
1879 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
1880 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
1881 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
1882 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
1884 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
1885 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
1886 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
1887 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
1888 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
1889 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
1891 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
1893 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
1894 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
1895 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
1896 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
1897 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
1898 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
1900 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
1901 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
1902 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
1903 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
1904 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
1905 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
1907 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
1911 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
1913 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1920 * Read EEPROM word for configuration.
1922 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1925 * Identify RF chipset.
1927 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1928 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1930 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
1931 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
1933 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
1934 !rt2x00_rt(rt2x00dev
, RT2870
) &&
1935 !rt2x00_rt(rt2x00dev
, RT2872
) &&
1936 !rt2x00_rt(rt2x00dev
, RT2883
) &&
1937 !rt2x00_rt(rt2x00dev
, RT3070
) &&
1938 !rt2x00_rt(rt2x00dev
, RT3071
) &&
1939 !rt2x00_rt(rt2x00dev
, RT3090
) &&
1940 !rt2x00_rt(rt2x00dev
, RT3390
) &&
1941 !rt2x00_rt(rt2x00dev
, RT3572
)) {
1942 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
1946 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
1947 !rt2x00_rf(rt2x00dev
, RF2850
) &&
1948 !rt2x00_rf(rt2x00dev
, RF2720
) &&
1949 !rt2x00_rf(rt2x00dev
, RF2750
) &&
1950 !rt2x00_rf(rt2x00dev
, RF3020
) &&
1951 !rt2x00_rf(rt2x00dev
, RF2020
) &&
1952 !rt2x00_rf(rt2x00dev
, RF3021
) &&
1953 !rt2x00_rf(rt2x00dev
, RF3022
) &&
1954 !rt2x00_rf(rt2x00dev
, RF3052
)) {
1955 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1960 * Identify default antenna configuration.
1962 rt2x00dev
->default_ant
.tx
=
1963 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
);
1964 rt2x00dev
->default_ant
.rx
=
1965 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
);
1968 * Read frequency offset and RF programming sequence.
1970 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1971 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
1974 * Read external LNA informations.
1976 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1978 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
1979 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
1980 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
1981 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
1984 * Detect if this device has an hardware controlled radio.
1986 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_HW_RADIO
))
1987 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1990 * Store led settings, for correct led behaviour.
1992 #ifdef CONFIG_RT2X00_LIB_LEDS
1993 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
1994 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
1995 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
1997 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &rt2x00dev
->led_mcu_reg
);
1998 #endif /* CONFIG_RT2X00_LIB_LEDS */
2002 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
2005 * RF value list for rt28x0
2006 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2008 static const struct rf_channel rf_vals
[] = {
2009 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2010 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2011 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2012 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2013 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2014 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2015 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2016 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2017 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2018 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2019 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2020 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2021 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2022 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2024 /* 802.11 UNI / HyperLan 2 */
2025 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2026 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2027 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2028 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2029 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2030 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2031 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2032 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2033 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2034 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2035 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2036 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2038 /* 802.11 HyperLan 2 */
2039 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2040 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2041 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2042 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2043 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2044 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2045 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2046 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2047 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2048 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2049 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2050 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2051 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2052 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2053 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2054 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2057 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2058 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2059 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2060 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2061 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2062 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2063 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2064 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2065 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2066 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2067 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2070 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2071 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2072 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2073 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2074 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2075 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2076 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2080 * RF value list for rt3070
2083 static const struct rf_channel rf_vals_302x
[] = {
2100 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2102 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2103 struct channel_info
*info
;
2110 * Disable powersaving as default on PCI devices.
2112 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
2113 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2116 * Initialize all hw fields.
2118 rt2x00dev
->hw
->flags
=
2119 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2120 IEEE80211_HW_SIGNAL_DBM
|
2121 IEEE80211_HW_SUPPORTS_PS
|
2122 IEEE80211_HW_PS_NULLFUNC_STACK
;
2124 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2125 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2126 rt2x00_eeprom_addr(rt2x00dev
,
2127 EEPROM_MAC_ADDR_0
));
2129 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2132 * Initialize hw_mode information.
2134 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2135 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2137 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
2138 rt2x00_rf(rt2x00dev
, RF2720
) ||
2139 rt2x00_rf(rt2x00dev
, RF3052
)) {
2140 spec
->num_channels
= 14;
2141 spec
->channels
= rf_vals
;
2142 } else if (rt2x00_rf(rt2x00dev
, RF2850
) || rt2x00_rf(rt2x00dev
, RF2750
)) {
2143 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2144 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
2145 spec
->channels
= rf_vals
;
2146 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
2147 rt2x00_rf(rt2x00dev
, RF2020
) ||
2148 rt2x00_rf(rt2x00dev
, RF3021
) ||
2149 rt2x00_rf(rt2x00dev
, RF3022
)) {
2150 spec
->num_channels
= ARRAY_SIZE(rf_vals_302x
);
2151 spec
->channels
= rf_vals_302x
;
2155 * Initialize HT information.
2157 if (!rt2x00_rf(rt2x00dev
, RF2020
))
2158 spec
->ht
.ht_supported
= true;
2160 spec
->ht
.ht_supported
= false;
2163 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
2164 IEEE80211_HT_CAP_GRN_FLD
|
2165 IEEE80211_HT_CAP_SGI_20
|
2166 IEEE80211_HT_CAP_SGI_40
|
2167 IEEE80211_HT_CAP_TX_STBC
|
2168 IEEE80211_HT_CAP_RX_STBC
;
2169 spec
->ht
.ampdu_factor
= 3;
2170 spec
->ht
.ampdu_density
= 4;
2171 spec
->ht
.mcs
.tx_params
=
2172 IEEE80211_HT_MCS_TX_DEFINED
|
2173 IEEE80211_HT_MCS_TX_RX_DIFF
|
2174 ((rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) - 1) <<
2175 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
2177 switch (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
)) {
2179 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
2181 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
2183 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
2184 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
2189 * Create channel information array
2191 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2195 spec
->channels_info
= info
;
2197 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
2198 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
2200 for (i
= 0; i
< 14; i
++) {
2201 info
[i
].tx_power1
= TXPOWER_G_FROM_DEV(tx_power1
[i
]);
2202 info
[i
].tx_power2
= TXPOWER_G_FROM_DEV(tx_power2
[i
]);
2205 if (spec
->num_channels
> 14) {
2206 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
2207 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
2209 for (i
= 14; i
< spec
->num_channels
; i
++) {
2210 info
[i
].tx_power1
= TXPOWER_A_FROM_DEV(tx_power1
[i
]);
2211 info
[i
].tx_power2
= TXPOWER_A_FROM_DEV(tx_power2
[i
]);
2217 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
2220 * IEEE80211 stack callback functions.
2222 static void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
,
2223 u32
*iv32
, u16
*iv16
)
2225 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2226 struct mac_iveiv_entry iveiv_entry
;
2229 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
2230 rt2800_register_multiread(rt2x00dev
, offset
,
2231 &iveiv_entry
, sizeof(iveiv_entry
));
2233 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
2234 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
2237 static int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
2239 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2241 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
2243 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2244 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
2245 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2247 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2248 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
2249 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2251 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2252 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
2253 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2255 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2256 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
2257 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2259 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2260 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
2261 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2263 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2264 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
2265 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2267 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2268 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
2269 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2274 static int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2275 const struct ieee80211_tx_queue_params
*params
)
2277 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2278 struct data_queue
*queue
;
2279 struct rt2x00_field32 field
;
2285 * First pass the configuration through rt2x00lib, that will
2286 * update the queue settings and validate the input. After that
2287 * we are free to update the registers based on the value
2288 * in the queue parameter.
2290 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2295 * We only need to perform additional register initialization
2301 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2303 /* Update WMM TXOP register */
2304 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2305 field
.bit_offset
= (queue_idx
& 1) * 16;
2306 field
.bit_mask
= 0xffff << field
.bit_offset
;
2308 rt2800_register_read(rt2x00dev
, offset
, ®
);
2309 rt2x00_set_field32(®
, field
, queue
->txop
);
2310 rt2800_register_write(rt2x00dev
, offset
, reg
);
2312 /* Update WMM registers */
2313 field
.bit_offset
= queue_idx
* 4;
2314 field
.bit_mask
= 0xf << field
.bit_offset
;
2316 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
2317 rt2x00_set_field32(®
, field
, queue
->aifs
);
2318 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
2320 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
2321 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2322 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
2324 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
2325 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2326 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
2328 /* Update EDCA registers */
2329 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
2331 rt2800_register_read(rt2x00dev
, offset
, ®
);
2332 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
2333 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
2334 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
2335 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
2336 rt2800_register_write(rt2x00dev
, offset
, reg
);
2341 static u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
2343 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2347 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
2348 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
2349 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
2350 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
2355 const struct ieee80211_ops rt2800_mac80211_ops
= {
2357 .start
= rt2x00mac_start
,
2358 .stop
= rt2x00mac_stop
,
2359 .add_interface
= rt2x00mac_add_interface
,
2360 .remove_interface
= rt2x00mac_remove_interface
,
2361 .config
= rt2x00mac_config
,
2362 .configure_filter
= rt2x00mac_configure_filter
,
2363 .set_tim
= rt2x00mac_set_tim
,
2364 .set_key
= rt2x00mac_set_key
,
2365 .get_stats
= rt2x00mac_get_stats
,
2366 .get_tkip_seq
= rt2800_get_tkip_seq
,
2367 .set_rts_threshold
= rt2800_set_rts_threshold
,
2368 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2369 .conf_tx
= rt2800_conf_tx
,
2370 .get_tsf
= rt2800_get_tsf
,
2371 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2373 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops
);