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x86: hpet: provide separate functions to stop and start the counter
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / intel-agp.c
blob4373adb2119aeea256758abc7602504477d5c5ad
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
36 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
37 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38 #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
43 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
44 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
45
46 /* cover 915 and 945 variants */
47 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
49 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
50 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
51 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
52 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
53
54 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
57 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
58 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
59 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
60
61 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
63 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
64
65 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
67 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
68 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
69 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB)
70
71 extern int agp_memory_reserved;
72
73
74 /* Intel 815 register */
75 #define INTEL_815_APCONT 0x51
76 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
77
78 /* Intel i820 registers */
79 #define INTEL_I820_RDCR 0x51
80 #define INTEL_I820_ERRSTS 0xc8
81
82 /* Intel i840 registers */
83 #define INTEL_I840_MCHCFG 0x50
84 #define INTEL_I840_ERRSTS 0xc8
85
86 /* Intel i850 registers */
87 #define INTEL_I850_MCHCFG 0x50
88 #define INTEL_I850_ERRSTS 0xc8
89
90 /* intel 915G registers */
91 #define I915_GMADDR 0x18
92 #define I915_MMADDR 0x10
93 #define I915_PTEADDR 0x1C
94 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
95 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
96 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
97 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
98 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
99 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
100 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
101 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
102
103 #define I915_IFPADDR 0x60
104
105 /* Intel 965G registers */
106 #define I965_MSAC 0x62
107 #define I965_IFPADDR 0x70
108
109 /* Intel 7505 registers */
110 #define INTEL_I7505_APSIZE 0x74
111 #define INTEL_I7505_NCAPID 0x60
112 #define INTEL_I7505_NISTAT 0x6c
113 #define INTEL_I7505_ATTBASE 0x78
114 #define INTEL_I7505_ERRSTS 0x42
115 #define INTEL_I7505_AGPCTRL 0x70
116 #define INTEL_I7505_MCHCFG 0x50
117
118 static const struct aper_size_info_fixed intel_i810_sizes[] =
119 {
120 {64, 16384, 4},
121 /* The 32M mode still requires a 64k gatt */
122 {32, 8192, 4}
123 };
124
125 #define AGP_DCACHE_MEMORY 1
126 #define AGP_PHYS_MEMORY 2
127 #define INTEL_AGP_CACHED_MEMORY 3
128
129 static struct gatt_mask intel_i810_masks[] =
130 {
131 {.mask = I810_PTE_VALID, .type = 0},
132 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
133 {.mask = I810_PTE_VALID, .type = 0},
134 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
135 .type = INTEL_AGP_CACHED_MEMORY}
136 };
137
138 static struct _intel_private {
139 struct pci_dev *pcidev; /* device one */
140 u8 __iomem *registers;
141 u32 __iomem *gtt; /* I915G */
142 int num_dcache_entries;
143 /* gtt_entries is the number of gtt entries that are already mapped
144 * to stolen memory. Stolen memory is larger than the memory mapped
145 * through gtt_entries, as it includes some reserved space for the BIOS
146 * popup and for the GTT.
147 */
148 int gtt_entries; /* i830+ */
149 union {
150 void __iomem *i9xx_flush_page;
151 void *i8xx_flush_page;
152 };
153 struct page *i8xx_page;
154 struct resource ifp_resource;
155 int resource_valid;
156 } intel_private;
157
158 static int intel_i810_fetch_size(void)
159 {
160 u32 smram_miscc;
161 struct aper_size_info_fixed *values;
162
163 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
164 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
165
166 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
167 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
168 return 0;
169 }
170 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
171 agp_bridge->previous_size =
172 agp_bridge->current_size = (void *) (values + 1);
173 agp_bridge->aperture_size_idx = 1;
174 return values[1].size;
175 } else {
176 agp_bridge->previous_size =
177 agp_bridge->current_size = (void *) (values);
178 agp_bridge->aperture_size_idx = 0;
179 return values[0].size;
180 }
181
182 return 0;
183 }
184
185 static int intel_i810_configure(void)
186 {
187 struct aper_size_info_fixed *current_size;
188 u32 temp;
189 int i;
190
191 current_size = A_SIZE_FIX(agp_bridge->current_size);
192
193 if (!intel_private.registers) {
194 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
195 temp &= 0xfff80000;
196
197 intel_private.registers = ioremap(temp, 128 * 4096);
198 if (!intel_private.registers) {
199 dev_err(&intel_private.pcidev->dev,
200 "can't remap memory\n");
201 return -ENOMEM;
202 }
203 }
204
205 if ((readl(intel_private.registers+I810_DRAM_CTL)
206 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
207 /* This will need to be dynamically assigned */
208 dev_info(&intel_private.pcidev->dev,
209 "detected 4MB dedicated video ram\n");
210 intel_private.num_dcache_entries = 1024;
211 }
212 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
213 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
214 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
215 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
216
217 if (agp_bridge->driver->needs_scratch_page) {
218 for (i = 0; i < current_size->num_entries; i++) {
219 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
220 }
221 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
222 }
223 global_cache_flush();
224 return 0;
225 }
226
227 static void intel_i810_cleanup(void)
228 {
229 writel(0, intel_private.registers+I810_PGETBL_CTL);
230 readl(intel_private.registers); /* PCI Posting. */
231 iounmap(intel_private.registers);
232 }
233
234 static void intel_i810_tlbflush(struct agp_memory *mem)
235 {
236 return;
237 }
238
239 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
240 {
241 return;
242 }
243
244 /* Exists to support ARGB cursors */
245 static void *i8xx_alloc_pages(void)
246 {
247 struct page *page;
248
249 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
250 if (page == NULL)
251 return NULL;
252
253 if (set_pages_uc(page, 4) < 0) {
254 set_pages_wb(page, 4);
255 __free_pages(page, 2);
256 return NULL;
257 }
258 get_page(page);
259 atomic_inc(&agp_bridge->current_memory_agp);
260 return page_address(page);
261 }
262
263 static void i8xx_destroy_pages(void *addr)
264 {
265 struct page *page;
266
267 if (addr == NULL)
268 return;
269
270 page = virt_to_page(addr);
271 set_pages_wb(page, 4);
272 put_page(page);
273 __free_pages(page, 2);
274 atomic_dec(&agp_bridge->current_memory_agp);
275 }
276
277 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
278 int type)
279 {
280 if (type < AGP_USER_TYPES)
281 return type;
282 else if (type == AGP_USER_CACHED_MEMORY)
283 return INTEL_AGP_CACHED_MEMORY;
284 else
285 return 0;
286 }
287
288 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
289 int type)
290 {
291 int i, j, num_entries;
292 void *temp;
293 int ret = -EINVAL;
294 int mask_type;
295
296 if (mem->page_count == 0)
297 goto out;
298
299 temp = agp_bridge->current_size;
300 num_entries = A_SIZE_FIX(temp)->num_entries;
301
302 if ((pg_start + mem->page_count) > num_entries)
303 goto out_err;
304
305
306 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
307 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
308 ret = -EBUSY;
309 goto out_err;
310 }
311 }
312
313 if (type != mem->type)
314 goto out_err;
315
316 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
317
318 switch (mask_type) {
319 case AGP_DCACHE_MEMORY:
320 if (!mem->is_flushed)
321 global_cache_flush();
322 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
323 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
324 intel_private.registers+I810_PTE_BASE+(i*4));
325 }
326 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
327 break;
328 case AGP_PHYS_MEMORY:
329 case AGP_NORMAL_MEMORY:
330 if (!mem->is_flushed)
331 global_cache_flush();
332 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
333 writel(agp_bridge->driver->mask_memory(agp_bridge,
334 mem->memory[i],
335 mask_type),
336 intel_private.registers+I810_PTE_BASE+(j*4));
337 }
338 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
339 break;
340 default:
341 goto out_err;
342 }
343
344 agp_bridge->driver->tlb_flush(mem);
345 out:
346 ret = 0;
347 out_err:
348 mem->is_flushed = true;
349 return ret;
350 }
351
352 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
353 int type)
354 {
355 int i;
356
357 if (mem->page_count == 0)
358 return 0;
359
360 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
361 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
362 }
363 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
364
365 agp_bridge->driver->tlb_flush(mem);
366 return 0;
367 }
368
369 /*
370 * The i810/i830 requires a physical address to program its mouse
371 * pointer into hardware.
372 * However the Xserver still writes to it through the agp aperture.
373 */
374 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
375 {
376 struct agp_memory *new;
377 void *addr;
378
379 switch (pg_count) {
380 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
381 break;
382 case 4:
383 /* kludge to get 4 physical pages for ARGB cursor */
384 addr = i8xx_alloc_pages();
385 break;
386 default:
387 return NULL;
388 }
389
390 if (addr == NULL)
391 return NULL;
392
393 new = agp_create_memory(pg_count);
394 if (new == NULL)
395 return NULL;
396
397 new->memory[0] = virt_to_gart(addr);
398 if (pg_count == 4) {
399 /* kludge to get 4 physical pages for ARGB cursor */
400 new->memory[1] = new->memory[0] + PAGE_SIZE;
401 new->memory[2] = new->memory[1] + PAGE_SIZE;
402 new->memory[3] = new->memory[2] + PAGE_SIZE;
403 }
404 new->page_count = pg_count;
405 new->num_scratch_pages = pg_count;
406 new->type = AGP_PHYS_MEMORY;
407 new->physical = new->memory[0];
408 return new;
409 }
410
411 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
412 {
413 struct agp_memory *new;
414
415 if (type == AGP_DCACHE_MEMORY) {
416 if (pg_count != intel_private.num_dcache_entries)
417 return NULL;
418
419 new = agp_create_memory(1);
420 if (new == NULL)
421 return NULL;
422
423 new->type = AGP_DCACHE_MEMORY;
424 new->page_count = pg_count;
425 new->num_scratch_pages = 0;
426 agp_free_page_array(new);
427 return new;
428 }
429 if (type == AGP_PHYS_MEMORY)
430 return alloc_agpphysmem_i8xx(pg_count, type);
431 return NULL;
432 }
433
434 static void intel_i810_free_by_type(struct agp_memory *curr)
435 {
436 agp_free_key(curr->key);
437 if (curr->type == AGP_PHYS_MEMORY) {
438 if (curr->page_count == 4)
439 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
440 else {
441 void *va = gart_to_virt(curr->memory[0]);
442
443 agp_bridge->driver->agp_destroy_page(va,
444 AGP_PAGE_DESTROY_UNMAP);
445 agp_bridge->driver->agp_destroy_page(va,
446 AGP_PAGE_DESTROY_FREE);
447 }
448 agp_free_page_array(curr);
449 }
450 kfree(curr);
451 }
452
453 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
454 unsigned long addr, int type)
455 {
456 /* Type checking must be done elsewhere */
457 return addr | bridge->driver->masks[type].mask;
458 }
459
460 static struct aper_size_info_fixed intel_i830_sizes[] =
461 {
462 {128, 32768, 5},
463 /* The 64M mode still requires a 128k gatt */
464 {64, 16384, 5},
465 {256, 65536, 6},
466 {512, 131072, 7},
467 };
468
469 static void intel_i830_init_gtt_entries(void)
470 {
471 u16 gmch_ctrl;
472 int gtt_entries;
473 u8 rdct;
474 int local = 0;
475 static const int ddt[4] = { 0, 16, 32, 64 };
476 int size; /* reserved space (in kb) at the top of stolen memory */
477
478 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
479
480 if (IS_I965) {
481 u32 pgetbl_ctl;
482 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
483
484 /* The 965 has a field telling us the size of the GTT,
485 * which may be larger than what is necessary to map the
486 * aperture.
487 */
488 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
489 case I965_PGETBL_SIZE_128KB:
490 size = 128;
491 break;
492 case I965_PGETBL_SIZE_256KB:
493 size = 256;
494 break;
495 case I965_PGETBL_SIZE_512KB:
496 size = 512;
497 break;
498 case I965_PGETBL_SIZE_1MB:
499 size = 1024;
500 break;
501 case I965_PGETBL_SIZE_2MB:
502 size = 2048;
503 break;
504 case I965_PGETBL_SIZE_1_5MB:
505 size = 1024 + 512;
506 break;
507 default:
508 dev_info(&intel_private.pcidev->dev,
509 "unknown page table size, assuming 512KB\n");
510 size = 512;
511 }
512 size += 4; /* add in BIOS popup space */
513 } else if (IS_G33) {
514 /* G33's GTT size defined in gmch_ctrl */
515 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
516 case G33_PGETBL_SIZE_1M:
517 size = 1024;
518 break;
519 case G33_PGETBL_SIZE_2M:
520 size = 2048;
521 break;
522 default:
523 dev_info(&agp_bridge->dev->dev,
524 "unknown page table size 0x%x, assuming 512KB\n",
525 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
526 size = 512;
527 }
528 size += 4;
529 } else if (IS_G4X) {
530 /* On 4 series hardware, GTT stolen is separate from graphics
531 * stolen, ignore it in stolen gtt entries counting. However,
532 * 4KB of the stolen memory doesn't get mapped to the GTT.
533 */
534 size = 4;
535 } else {
536 /* On previous hardware, the GTT size was just what was
537 * required to map the aperture.
538 */
539 size = agp_bridge->driver->fetch_size() + 4;
540 }
541
542 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
543 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
544 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
545 case I830_GMCH_GMS_STOLEN_512:
546 gtt_entries = KB(512) - KB(size);
547 break;
548 case I830_GMCH_GMS_STOLEN_1024:
549 gtt_entries = MB(1) - KB(size);
550 break;
551 case I830_GMCH_GMS_STOLEN_8192:
552 gtt_entries = MB(8) - KB(size);
553 break;
554 case I830_GMCH_GMS_LOCAL:
555 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
556 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
557 MB(ddt[I830_RDRAM_DDT(rdct)]);
558 local = 1;
559 break;
560 default:
561 gtt_entries = 0;
562 break;
563 }
564 } else {
565 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
566 case I855_GMCH_GMS_STOLEN_1M:
567 gtt_entries = MB(1) - KB(size);
568 break;
569 case I855_GMCH_GMS_STOLEN_4M:
570 gtt_entries = MB(4) - KB(size);
571 break;
572 case I855_GMCH_GMS_STOLEN_8M:
573 gtt_entries = MB(8) - KB(size);
574 break;
575 case I855_GMCH_GMS_STOLEN_16M:
576 gtt_entries = MB(16) - KB(size);
577 break;
578 case I855_GMCH_GMS_STOLEN_32M:
579 gtt_entries = MB(32) - KB(size);
580 break;
581 case I915_GMCH_GMS_STOLEN_48M:
582 /* Check it's really I915G */
583 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
584 gtt_entries = MB(48) - KB(size);
585 else
586 gtt_entries = 0;
587 break;
588 case I915_GMCH_GMS_STOLEN_64M:
589 /* Check it's really I915G */
590 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
591 gtt_entries = MB(64) - KB(size);
592 else
593 gtt_entries = 0;
594 break;
595 case G33_GMCH_GMS_STOLEN_128M:
596 if (IS_G33 || IS_I965 || IS_G4X)
597 gtt_entries = MB(128) - KB(size);
598 else
599 gtt_entries = 0;
600 break;
601 case G33_GMCH_GMS_STOLEN_256M:
602 if (IS_G33 || IS_I965 || IS_G4X)
603 gtt_entries = MB(256) - KB(size);
604 else
605 gtt_entries = 0;
606 break;
607 case INTEL_GMCH_GMS_STOLEN_96M:
608 if (IS_I965 || IS_G4X)
609 gtt_entries = MB(96) - KB(size);
610 else
611 gtt_entries = 0;
612 break;
613 case INTEL_GMCH_GMS_STOLEN_160M:
614 if (IS_I965 || IS_G4X)
615 gtt_entries = MB(160) - KB(size);
616 else
617 gtt_entries = 0;
618 break;
619 case INTEL_GMCH_GMS_STOLEN_224M:
620 if (IS_I965 || IS_G4X)
621 gtt_entries = MB(224) - KB(size);
622 else
623 gtt_entries = 0;
624 break;
625 case INTEL_GMCH_GMS_STOLEN_352M:
626 if (IS_I965 || IS_G4X)
627 gtt_entries = MB(352) - KB(size);
628 else
629 gtt_entries = 0;
630 break;
631 default:
632 gtt_entries = 0;
633 break;
634 }
635 }
636 if (gtt_entries > 0) {
637 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
638 gtt_entries / KB(1), local ? "local" : "stolen");
639 gtt_entries /= KB(4);
640 } else {
641 dev_info(&agp_bridge->dev->dev,
642 "no pre-allocated video memory detected\n");
643 gtt_entries = 0;
644 }
645
646 intel_private.gtt_entries = gtt_entries;
647 }
648
649 static void intel_i830_fini_flush(void)
650 {
651 kunmap(intel_private.i8xx_page);
652 intel_private.i8xx_flush_page = NULL;
653 unmap_page_from_agp(intel_private.i8xx_page);
654
655 __free_page(intel_private.i8xx_page);
656 intel_private.i8xx_page = NULL;
657 }
658
659 static void intel_i830_setup_flush(void)
660 {
661 /* return if we've already set the flush mechanism up */
662 if (intel_private.i8xx_page)
663 return;
664
665 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
666 if (!intel_private.i8xx_page)
667 return;
668
669 /* make page uncached */
670 map_page_into_agp(intel_private.i8xx_page);
671
672 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
673 if (!intel_private.i8xx_flush_page)
674 intel_i830_fini_flush();
675 }
676
677 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
678 {
679 unsigned int *pg = intel_private.i8xx_flush_page;
680 int i;
681
682 for (i = 0; i < 256; i += 2)
683 *(pg + i) = i;
684
685 wmb();
686 }
687
688 /* The intel i830 automatically initializes the agp aperture during POST.
689 * Use the memory already set aside for in the GTT.
690 */
691 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
692 {
693 int page_order;
694 struct aper_size_info_fixed *size;
695 int num_entries;
696 u32 temp;
697
698 size = agp_bridge->current_size;
699 page_order = size->page_order;
700 num_entries = size->num_entries;
701 agp_bridge->gatt_table_real = NULL;
702
703 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
704 temp &= 0xfff80000;
705
706 intel_private.registers = ioremap(temp, 128 * 4096);
707 if (!intel_private.registers)
708 return -ENOMEM;
709
710 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
711 global_cache_flush(); /* FIXME: ?? */
712
713 /* we have to call this as early as possible after the MMIO base address is known */
714 intel_i830_init_gtt_entries();
715
716 agp_bridge->gatt_table = NULL;
717
718 agp_bridge->gatt_bus_addr = temp;
719
720 return 0;
721 }
722
723 /* Return the gatt table to a sane state. Use the top of stolen
724 * memory for the GTT.
725 */
726 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
727 {
728 return 0;
729 }
730
731 static int intel_i830_fetch_size(void)
732 {
733 u16 gmch_ctrl;
734 struct aper_size_info_fixed *values;
735
736 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
737
738 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
739 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
740 /* 855GM/852GM/865G has 128MB aperture size */
741 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
742 agp_bridge->aperture_size_idx = 0;
743 return values[0].size;
744 }
745
746 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
747
748 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
749 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
750 agp_bridge->aperture_size_idx = 0;
751 return values[0].size;
752 } else {
753 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
754 agp_bridge->aperture_size_idx = 1;
755 return values[1].size;
756 }
757
758 return 0;
759 }
760
761 static int intel_i830_configure(void)
762 {
763 struct aper_size_info_fixed *current_size;
764 u32 temp;
765 u16 gmch_ctrl;
766 int i;
767
768 current_size = A_SIZE_FIX(agp_bridge->current_size);
769
770 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
771 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
772
773 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
774 gmch_ctrl |= I830_GMCH_ENABLED;
775 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
776
777 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
778 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
779
780 if (agp_bridge->driver->needs_scratch_page) {
781 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
782 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
783 }
784 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
785 }
786
787 global_cache_flush();
788
789 intel_i830_setup_flush();
790 return 0;
791 }
792
793 static void intel_i830_cleanup(void)
794 {
795 iounmap(intel_private.registers);
796 }
797
798 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
799 int type)
800 {
801 int i, j, num_entries;
802 void *temp;
803 int ret = -EINVAL;
804 int mask_type;
805
806 if (mem->page_count == 0)
807 goto out;
808
809 temp = agp_bridge->current_size;
810 num_entries = A_SIZE_FIX(temp)->num_entries;
811
812 if (pg_start < intel_private.gtt_entries) {
813 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
814 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
815 pg_start, intel_private.gtt_entries);
816
817 dev_info(&intel_private.pcidev->dev,
818 "trying to insert into local/stolen memory\n");
819 goto out_err;
820 }
821
822 if ((pg_start + mem->page_count) > num_entries)
823 goto out_err;
824
825 /* The i830 can't check the GTT for entries since its read only,
826 * depend on the caller to make the correct offset decisions.
827 */
828
829 if (type != mem->type)
830 goto out_err;
831
832 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
833
834 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
835 mask_type != INTEL_AGP_CACHED_MEMORY)
836 goto out_err;
837
838 if (!mem->is_flushed)
839 global_cache_flush();
840
841 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
842 writel(agp_bridge->driver->mask_memory(agp_bridge,
843 mem->memory[i], mask_type),
844 intel_private.registers+I810_PTE_BASE+(j*4));
845 }
846 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
847 agp_bridge->driver->tlb_flush(mem);
848
849 out:
850 ret = 0;
851 out_err:
852 mem->is_flushed = true;
853 return ret;
854 }
855
856 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
857 int type)
858 {
859 int i;
860
861 if (mem->page_count == 0)
862 return 0;
863
864 if (pg_start < intel_private.gtt_entries) {
865 dev_info(&intel_private.pcidev->dev,
866 "trying to disable local/stolen memory\n");
867 return -EINVAL;
868 }
869
870 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
871 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
872 }
873 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
874
875 agp_bridge->driver->tlb_flush(mem);
876 return 0;
877 }
878
879 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
880 {
881 if (type == AGP_PHYS_MEMORY)
882 return alloc_agpphysmem_i8xx(pg_count, type);
883 /* always return NULL for other allocation types for now */
884 return NULL;
885 }
886
887 static int intel_alloc_chipset_flush_resource(void)
888 {
889 int ret;
890 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
891 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
892 pcibios_align_resource, agp_bridge->dev);
893
894 return ret;
895 }
896
897 static void intel_i915_setup_chipset_flush(void)
898 {
899 int ret;
900 u32 temp;
901
902 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
903 if (!(temp & 0x1)) {
904 intel_alloc_chipset_flush_resource();
905 intel_private.resource_valid = 1;
906 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
907 } else {
908 temp &= ~1;
909
910 intel_private.resource_valid = 1;
911 intel_private.ifp_resource.start = temp;
912 intel_private.ifp_resource.end = temp + PAGE_SIZE;
913 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
914 /* some BIOSes reserve this area in a pnp some don't */
915 if (ret)
916 intel_private.resource_valid = 0;
917 }
918 }
919
920 static void intel_i965_g33_setup_chipset_flush(void)
921 {
922 u32 temp_hi, temp_lo;
923 int ret;
924
925 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
926 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
927
928 if (!(temp_lo & 0x1)) {
929
930 intel_alloc_chipset_flush_resource();
931
932 intel_private.resource_valid = 1;
933 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
934 upper_32_bits(intel_private.ifp_resource.start));
935 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
936 } else {
937 u64 l64;
938
939 temp_lo &= ~0x1;
940 l64 = ((u64)temp_hi << 32) | temp_lo;
941
942 intel_private.resource_valid = 1;
943 intel_private.ifp_resource.start = l64;
944 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
945 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
946 /* some BIOSes reserve this area in a pnp some don't */
947 if (ret)
948 intel_private.resource_valid = 0;
949 }
950 }
951
952 static void intel_i9xx_setup_flush(void)
953 {
954 /* return if already configured */
955 if (intel_private.ifp_resource.start)
956 return;
957
958 /* setup a resource for this object */
959 intel_private.ifp_resource.name = "Intel Flush Page";
960 intel_private.ifp_resource.flags = IORESOURCE_MEM;
961
962 /* Setup chipset flush for 915 */
963 if (IS_I965 || IS_G33 || IS_G4X) {
964 intel_i965_g33_setup_chipset_flush();
965 } else {
966 intel_i915_setup_chipset_flush();
967 }
968
969 if (intel_private.ifp_resource.start) {
970 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
971 if (!intel_private.i9xx_flush_page)
972 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
973 }
974 }
975
976 static int intel_i915_configure(void)
977 {
978 struct aper_size_info_fixed *current_size;
979 u32 temp;
980 u16 gmch_ctrl;
981 int i;
982
983 current_size = A_SIZE_FIX(agp_bridge->current_size);
984
985 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
986
987 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
988
989 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
990 gmch_ctrl |= I830_GMCH_ENABLED;
991 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
992
993 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
994 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
995
996 if (agp_bridge->driver->needs_scratch_page) {
997 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
998 writel(agp_bridge->scratch_page, intel_private.gtt+i);
999 }
1000 readl(intel_private.gtt+i-1); /* PCI Posting. */
1001 }
1002
1003 global_cache_flush();
1004
1005 intel_i9xx_setup_flush();
1006
1007 return 0;
1008 }
1009
1010 static void intel_i915_cleanup(void)
1011 {
1012 if (intel_private.i9xx_flush_page)
1013 iounmap(intel_private.i9xx_flush_page);
1014 if (intel_private.resource_valid)
1015 release_resource(&intel_private.ifp_resource);
1016 intel_private.ifp_resource.start = 0;
1017 intel_private.resource_valid = 0;
1018 iounmap(intel_private.gtt);
1019 iounmap(intel_private.registers);
1020 }
1021
1022 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1023 {
1024 if (intel_private.i9xx_flush_page)
1025 writel(1, intel_private.i9xx_flush_page);
1026 }
1027
1028 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1029 int type)
1030 {
1031 int i, j, num_entries;
1032 void *temp;
1033 int ret = -EINVAL;
1034 int mask_type;
1035
1036 if (mem->page_count == 0)
1037 goto out;
1038
1039 temp = agp_bridge->current_size;
1040 num_entries = A_SIZE_FIX(temp)->num_entries;
1041
1042 if (pg_start < intel_private.gtt_entries) {
1043 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1044 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1045 pg_start, intel_private.gtt_entries);
1046
1047 dev_info(&intel_private.pcidev->dev,
1048 "trying to insert into local/stolen memory\n");
1049 goto out_err;
1050 }
1051
1052 if ((pg_start + mem->page_count) > num_entries)
1053 goto out_err;
1054
1055 /* The i915 can't check the GTT for entries since its read only,
1056 * depend on the caller to make the correct offset decisions.
1057 */
1058
1059 if (type != mem->type)
1060 goto out_err;
1061
1062 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1063
1064 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1065 mask_type != INTEL_AGP_CACHED_MEMORY)
1066 goto out_err;
1067
1068 if (!mem->is_flushed)
1069 global_cache_flush();
1070
1071 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1072 writel(agp_bridge->driver->mask_memory(agp_bridge,
1073 mem->memory[i], mask_type), intel_private.gtt+j);
1074 }
1075
1076 readl(intel_private.gtt+j-1);
1077 agp_bridge->driver->tlb_flush(mem);
1078
1079 out:
1080 ret = 0;
1081 out_err:
1082 mem->is_flushed = true;
1083 return ret;
1084 }
1085
1086 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1087 int type)
1088 {
1089 int i;
1090
1091 if (mem->page_count == 0)
1092 return 0;
1093
1094 if (pg_start < intel_private.gtt_entries) {
1095 dev_info(&intel_private.pcidev->dev,
1096 "trying to disable local/stolen memory\n");
1097 return -EINVAL;
1098 }
1099
1100 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1101 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1102
1103 readl(intel_private.gtt+i-1);
1104
1105 agp_bridge->driver->tlb_flush(mem);
1106 return 0;
1107 }
1108
1109 /* Return the aperture size by just checking the resource length. The effect
1110 * described in the spec of the MSAC registers is just changing of the
1111 * resource size.
1112 */
1113 static int intel_i9xx_fetch_size(void)
1114 {
1115 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1116 int aper_size; /* size in megabytes */
1117 int i;
1118
1119 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1120
1121 for (i = 0; i < num_sizes; i++) {
1122 if (aper_size == intel_i830_sizes[i].size) {
1123 agp_bridge->current_size = intel_i830_sizes + i;
1124 agp_bridge->previous_size = agp_bridge->current_size;
1125 return aper_size;
1126 }
1127 }
1128
1129 return 0;
1130 }
1131
1132 /* The intel i915 automatically initializes the agp aperture during POST.
1133 * Use the memory already set aside for in the GTT.
1134 */
1135 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1136 {
1137 int page_order;
1138 struct aper_size_info_fixed *size;
1139 int num_entries;
1140 u32 temp, temp2;
1141 int gtt_map_size = 256 * 1024;
1142
1143 size = agp_bridge->current_size;
1144 page_order = size->page_order;
1145 num_entries = size->num_entries;
1146 agp_bridge->gatt_table_real = NULL;
1147
1148 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1149 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1150
1151 if (IS_G33)
1152 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1153 intel_private.gtt = ioremap(temp2, gtt_map_size);
1154 if (!intel_private.gtt)
1155 return -ENOMEM;
1156
1157 temp &= 0xfff80000;
1158
1159 intel_private.registers = ioremap(temp, 128 * 4096);
1160 if (!intel_private.registers) {
1161 iounmap(intel_private.gtt);
1162 return -ENOMEM;
1163 }
1164
1165 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1166 global_cache_flush(); /* FIXME: ? */
1167
1168 /* we have to call this as early as possible after the MMIO base address is known */
1169 intel_i830_init_gtt_entries();
1170
1171 agp_bridge->gatt_table = NULL;
1172
1173 agp_bridge->gatt_bus_addr = temp;
1174
1175 return 0;
1176 }
1177
1178 /*
1179 * The i965 supports 36-bit physical addresses, but to keep
1180 * the format of the GTT the same, the bits that don't fit
1181 * in a 32-bit word are shifted down to bits 4..7.
1182 *
1183 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1184 * is always zero on 32-bit architectures, so no need to make
1185 * this conditional.
1186 */
1187 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1188 unsigned long addr, int type)
1189 {
1190 /* Shift high bits down */
1191 addr |= (addr >> 28) & 0xf0;
1192
1193 /* Type checking must be done elsewhere */
1194 return addr | bridge->driver->masks[type].mask;
1195 }
1196
1197 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1198 {
1199 switch (agp_bridge->dev->device) {
1200 case PCI_DEVICE_ID_INTEL_GM45_HB:
1201 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1202 case PCI_DEVICE_ID_INTEL_Q45_HB:
1203 case PCI_DEVICE_ID_INTEL_G45_HB:
1204 case PCI_DEVICE_ID_INTEL_G41_HB:
1205 *gtt_offset = *gtt_size = MB(2);
1206 break;
1207 default:
1208 *gtt_offset = *gtt_size = KB(512);
1209 }
1210 }
1211
1212 /* The intel i965 automatically initializes the agp aperture during POST.
1213 * Use the memory already set aside for in the GTT.
1214 */
1215 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1216 {
1217 int page_order;
1218 struct aper_size_info_fixed *size;
1219 int num_entries;
1220 u32 temp;
1221 int gtt_offset, gtt_size;
1222
1223 size = agp_bridge->current_size;
1224 page_order = size->page_order;
1225 num_entries = size->num_entries;
1226 agp_bridge->gatt_table_real = NULL;
1227
1228 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1229
1230 temp &= 0xfff00000;
1231
1232 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1233
1234 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1235
1236 if (!intel_private.gtt)
1237 return -ENOMEM;
1238
1239 intel_private.registers = ioremap(temp, 128 * 4096);
1240 if (!intel_private.registers) {
1241 iounmap(intel_private.gtt);
1242 return -ENOMEM;
1243 }
1244
1245 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1246 global_cache_flush(); /* FIXME: ? */
1247
1248 /* we have to call this as early as possible after the MMIO base address is known */
1249 intel_i830_init_gtt_entries();
1250
1251 agp_bridge->gatt_table = NULL;
1252
1253 agp_bridge->gatt_bus_addr = temp;
1254
1255 return 0;
1256 }
1257
1258
1259 static int intel_fetch_size(void)
1260 {
1261 int i;
1262 u16 temp;
1263 struct aper_size_info_16 *values;
1264
1265 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1266 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1267
1268 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1269 if (temp == values[i].size_value) {
1270 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1271 agp_bridge->aperture_size_idx = i;
1272 return values[i].size;
1273 }
1274 }
1275
1276 return 0;
1277 }
1278
1279 static int __intel_8xx_fetch_size(u8 temp)
1280 {
1281 int i;
1282 struct aper_size_info_8 *values;
1283
1284 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1285
1286 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1287 if (temp == values[i].size_value) {
1288 agp_bridge->previous_size =
1289 agp_bridge->current_size = (void *) (values + i);
1290 agp_bridge->aperture_size_idx = i;
1291 return values[i].size;
1292 }
1293 }
1294 return 0;
1295 }
1296
1297 static int intel_8xx_fetch_size(void)
1298 {
1299 u8 temp;
1300
1301 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1302 return __intel_8xx_fetch_size(temp);
1303 }
1304
1305 static int intel_815_fetch_size(void)
1306 {
1307 u8 temp;
1308
1309 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1310 * one non-reserved bit, so mask the others out ... */
1311 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1312 temp &= (1 << 3);
1313
1314 return __intel_8xx_fetch_size(temp);
1315 }
1316
1317 static void intel_tlbflush(struct agp_memory *mem)
1318 {
1319 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1320 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1321 }
1322
1323
1324 static void intel_8xx_tlbflush(struct agp_memory *mem)
1325 {
1326 u32 temp;
1327 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1328 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1329 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1330 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1331 }
1332
1333
1334 static void intel_cleanup(void)
1335 {
1336 u16 temp;
1337 struct aper_size_info_16 *previous_size;
1338
1339 previous_size = A_SIZE_16(agp_bridge->previous_size);
1340 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1341 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1342 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1343 }
1344
1345
1346 static void intel_8xx_cleanup(void)
1347 {
1348 u16 temp;
1349 struct aper_size_info_8 *previous_size;
1350
1351 previous_size = A_SIZE_8(agp_bridge->previous_size);
1352 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1353 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1354 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1355 }
1356
1357
1358 static int intel_configure(void)
1359 {
1360 u32 temp;
1361 u16 temp2;
1362 struct aper_size_info_16 *current_size;
1363
1364 current_size = A_SIZE_16(agp_bridge->current_size);
1365
1366 /* aperture size */
1367 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1368
1369 /* address to map to */
1370 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1371 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1372
1373 /* attbase - aperture base */
1374 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1375
1376 /* agpctrl */
1377 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1378
1379 /* paccfg/nbxcfg */
1380 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1381 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1382 (temp2 & ~(1 << 10)) | (1 << 9));
1383 /* clear any possible error conditions */
1384 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1385 return 0;
1386 }
1387
1388 static int intel_815_configure(void)
1389 {
1390 u32 temp, addr;
1391 u8 temp2;
1392 struct aper_size_info_8 *current_size;
1393
1394 /* attbase - aperture base */
1395 /* the Intel 815 chipset spec. says that bits 29-31 in the
1396 * ATTBASE register are reserved -> try not to write them */
1397 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1398 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1399 return -EINVAL;
1400 }
1401
1402 current_size = A_SIZE_8(agp_bridge->current_size);
1403
1404 /* aperture size */
1405 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1406 current_size->size_value);
1407
1408 /* address to map to */
1409 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1410 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1411
1412 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1413 addr &= INTEL_815_ATTBASE_MASK;
1414 addr |= agp_bridge->gatt_bus_addr;
1415 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1416
1417 /* agpctrl */
1418 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1419
1420 /* apcont */
1421 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1422 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1423
1424 /* clear any possible error conditions */
1425 /* Oddness : this chipset seems to have no ERRSTS register ! */
1426 return 0;
1427 }
1428
1429 static void intel_820_tlbflush(struct agp_memory *mem)
1430 {
1431 return;
1432 }
1433
1434 static void intel_820_cleanup(void)
1435 {
1436 u8 temp;
1437 struct aper_size_info_8 *previous_size;
1438
1439 previous_size = A_SIZE_8(agp_bridge->previous_size);
1440 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1441 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1442 temp & ~(1 << 1));
1443 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1444 previous_size->size_value);
1445 }
1446
1447
1448 static int intel_820_configure(void)
1449 {
1450 u32 temp;
1451 u8 temp2;
1452 struct aper_size_info_8 *current_size;
1453
1454 current_size = A_SIZE_8(agp_bridge->current_size);
1455
1456 /* aperture size */
1457 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1458
1459 /* address to map to */
1460 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1461 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1462
1463 /* attbase - aperture base */
1464 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1465
1466 /* agpctrl */
1467 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1468
1469 /* global enable aperture access */
1470 /* This flag is not accessed through MCHCFG register as in */
1471 /* i850 chipset. */
1472 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1473 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1474 /* clear any possible AGP-related error conditions */
1475 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1476 return 0;
1477 }
1478
1479 static int intel_840_configure(void)
1480 {
1481 u32 temp;
1482 u16 temp2;
1483 struct aper_size_info_8 *current_size;
1484
1485 current_size = A_SIZE_8(agp_bridge->current_size);
1486
1487 /* aperture size */
1488 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1489
1490 /* address to map to */
1491 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1492 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1493
1494 /* attbase - aperture base */
1495 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1496
1497 /* agpctrl */
1498 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1499
1500 /* mcgcfg */
1501 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1502 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1503 /* clear any possible error conditions */
1504 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1505 return 0;
1506 }
1507
1508 static int intel_845_configure(void)
1509 {
1510 u32 temp;
1511 u8 temp2;
1512 struct aper_size_info_8 *current_size;
1513
1514 current_size = A_SIZE_8(agp_bridge->current_size);
1515
1516 /* aperture size */
1517 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1518
1519 if (agp_bridge->apbase_config != 0) {
1520 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1521 agp_bridge->apbase_config);
1522 } else {
1523 /* address to map to */
1524 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1525 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1526 agp_bridge->apbase_config = temp;
1527 }
1528
1529 /* attbase - aperture base */
1530 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1531
1532 /* agpctrl */
1533 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1534
1535 /* agpm */
1536 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1537 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1538 /* clear any possible error conditions */
1539 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1540
1541 intel_i830_setup_flush();
1542 return 0;
1543 }
1544
1545 static int intel_850_configure(void)
1546 {
1547 u32 temp;
1548 u16 temp2;
1549 struct aper_size_info_8 *current_size;
1550
1551 current_size = A_SIZE_8(agp_bridge->current_size);
1552
1553 /* aperture size */
1554 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1555
1556 /* address to map to */
1557 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1558 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1559
1560 /* attbase - aperture base */
1561 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1562
1563 /* agpctrl */
1564 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1565
1566 /* mcgcfg */
1567 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1568 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1569 /* clear any possible AGP-related error conditions */
1570 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1571 return 0;
1572 }
1573
1574 static int intel_860_configure(void)
1575 {
1576 u32 temp;
1577 u16 temp2;
1578 struct aper_size_info_8 *current_size;
1579
1580 current_size = A_SIZE_8(agp_bridge->current_size);
1581
1582 /* aperture size */
1583 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1584
1585 /* address to map to */
1586 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1587 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1588
1589 /* attbase - aperture base */
1590 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1591
1592 /* agpctrl */
1593 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1594
1595 /* mcgcfg */
1596 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1597 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1598 /* clear any possible AGP-related error conditions */
1599 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1600 return 0;
1601 }
1602
1603 static int intel_830mp_configure(void)
1604 {
1605 u32 temp;
1606 u16 temp2;
1607 struct aper_size_info_8 *current_size;
1608
1609 current_size = A_SIZE_8(agp_bridge->current_size);
1610
1611 /* aperture size */
1612 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1613
1614 /* address to map to */
1615 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1616 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1617
1618 /* attbase - aperture base */
1619 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1620
1621 /* agpctrl */
1622 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1623
1624 /* gmch */
1625 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1626 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1627 /* clear any possible AGP-related error conditions */
1628 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1629 return 0;
1630 }
1631
1632 static int intel_7505_configure(void)
1633 {
1634 u32 temp;
1635 u16 temp2;
1636 struct aper_size_info_8 *current_size;
1637
1638 current_size = A_SIZE_8(agp_bridge->current_size);
1639
1640 /* aperture size */
1641 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1642
1643 /* address to map to */
1644 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1645 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1646
1647 /* attbase - aperture base */
1648 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1649
1650 /* agpctrl */
1651 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1652
1653 /* mchcfg */
1654 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1655 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1656
1657 return 0;
1658 }
1659
1660 /* Setup function */
1661 static const struct gatt_mask intel_generic_masks[] =
1662 {
1663 {.mask = 0x00000017, .type = 0}
1664 };
1665
1666 static const struct aper_size_info_8 intel_815_sizes[2] =
1667 {
1668 {64, 16384, 4, 0},
1669 {32, 8192, 3, 8},
1670 };
1671
1672 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1673 {
1674 {256, 65536, 6, 0},
1675 {128, 32768, 5, 32},
1676 {64, 16384, 4, 48},
1677 {32, 8192, 3, 56},
1678 {16, 4096, 2, 60},
1679 {8, 2048, 1, 62},
1680 {4, 1024, 0, 63}
1681 };
1682
1683 static const struct aper_size_info_16 intel_generic_sizes[7] =
1684 {
1685 {256, 65536, 6, 0},
1686 {128, 32768, 5, 32},
1687 {64, 16384, 4, 48},
1688 {32, 8192, 3, 56},
1689 {16, 4096, 2, 60},
1690 {8, 2048, 1, 62},
1691 {4, 1024, 0, 63}
1692 };
1693
1694 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1695 {
1696 {256, 65536, 6, 0},
1697 {128, 32768, 5, 32},
1698 {64, 16384, 4, 48},
1699 {32, 8192, 3, 56}
1700 };
1701
1702 static const struct agp_bridge_driver intel_generic_driver = {
1703 .owner = THIS_MODULE,
1704 .aperture_sizes = intel_generic_sizes,
1705 .size_type = U16_APER_SIZE,
1706 .num_aperture_sizes = 7,
1707 .configure = intel_configure,
1708 .fetch_size = intel_fetch_size,
1709 .cleanup = intel_cleanup,
1710 .tlb_flush = intel_tlbflush,
1711 .mask_memory = agp_generic_mask_memory,
1712 .masks = intel_generic_masks,
1713 .agp_enable = agp_generic_enable,
1714 .cache_flush = global_cache_flush,
1715 .create_gatt_table = agp_generic_create_gatt_table,
1716 .free_gatt_table = agp_generic_free_gatt_table,
1717 .insert_memory = agp_generic_insert_memory,
1718 .remove_memory = agp_generic_remove_memory,
1719 .alloc_by_type = agp_generic_alloc_by_type,
1720 .free_by_type = agp_generic_free_by_type,
1721 .agp_alloc_page = agp_generic_alloc_page,
1722 .agp_alloc_pages = agp_generic_alloc_pages,
1723 .agp_destroy_page = agp_generic_destroy_page,
1724 .agp_destroy_pages = agp_generic_destroy_pages,
1725 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1726 };
1727
1728 static const struct agp_bridge_driver intel_810_driver = {
1729 .owner = THIS_MODULE,
1730 .aperture_sizes = intel_i810_sizes,
1731 .size_type = FIXED_APER_SIZE,
1732 .num_aperture_sizes = 2,
1733 .needs_scratch_page = true,
1734 .configure = intel_i810_configure,
1735 .fetch_size = intel_i810_fetch_size,
1736 .cleanup = intel_i810_cleanup,
1737 .tlb_flush = intel_i810_tlbflush,
1738 .mask_memory = intel_i810_mask_memory,
1739 .masks = intel_i810_masks,
1740 .agp_enable = intel_i810_agp_enable,
1741 .cache_flush = global_cache_flush,
1742 .create_gatt_table = agp_generic_create_gatt_table,
1743 .free_gatt_table = agp_generic_free_gatt_table,
1744 .insert_memory = intel_i810_insert_entries,
1745 .remove_memory = intel_i810_remove_entries,
1746 .alloc_by_type = intel_i810_alloc_by_type,
1747 .free_by_type = intel_i810_free_by_type,
1748 .agp_alloc_page = agp_generic_alloc_page,
1749 .agp_alloc_pages = agp_generic_alloc_pages,
1750 .agp_destroy_page = agp_generic_destroy_page,
1751 .agp_destroy_pages = agp_generic_destroy_pages,
1752 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1753 };
1754
1755 static const struct agp_bridge_driver intel_815_driver = {
1756 .owner = THIS_MODULE,
1757 .aperture_sizes = intel_815_sizes,
1758 .size_type = U8_APER_SIZE,
1759 .num_aperture_sizes = 2,
1760 .configure = intel_815_configure,
1761 .fetch_size = intel_815_fetch_size,
1762 .cleanup = intel_8xx_cleanup,
1763 .tlb_flush = intel_8xx_tlbflush,
1764 .mask_memory = agp_generic_mask_memory,
1765 .masks = intel_generic_masks,
1766 .agp_enable = agp_generic_enable,
1767 .cache_flush = global_cache_flush,
1768 .create_gatt_table = agp_generic_create_gatt_table,
1769 .free_gatt_table = agp_generic_free_gatt_table,
1770 .insert_memory = agp_generic_insert_memory,
1771 .remove_memory = agp_generic_remove_memory,
1772 .alloc_by_type = agp_generic_alloc_by_type,
1773 .free_by_type = agp_generic_free_by_type,
1774 .agp_alloc_page = agp_generic_alloc_page,
1775 .agp_alloc_pages = agp_generic_alloc_pages,
1776 .agp_destroy_page = agp_generic_destroy_page,
1777 .agp_destroy_pages = agp_generic_destroy_pages,
1778 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1779 };
1780
1781 static const struct agp_bridge_driver intel_830_driver = {
1782 .owner = THIS_MODULE,
1783 .aperture_sizes = intel_i830_sizes,
1784 .size_type = FIXED_APER_SIZE,
1785 .num_aperture_sizes = 4,
1786 .needs_scratch_page = true,
1787 .configure = intel_i830_configure,
1788 .fetch_size = intel_i830_fetch_size,
1789 .cleanup = intel_i830_cleanup,
1790 .tlb_flush = intel_i810_tlbflush,
1791 .mask_memory = intel_i810_mask_memory,
1792 .masks = intel_i810_masks,
1793 .agp_enable = intel_i810_agp_enable,
1794 .cache_flush = global_cache_flush,
1795 .create_gatt_table = intel_i830_create_gatt_table,
1796 .free_gatt_table = intel_i830_free_gatt_table,
1797 .insert_memory = intel_i830_insert_entries,
1798 .remove_memory = intel_i830_remove_entries,
1799 .alloc_by_type = intel_i830_alloc_by_type,
1800 .free_by_type = intel_i810_free_by_type,
1801 .agp_alloc_page = agp_generic_alloc_page,
1802 .agp_alloc_pages = agp_generic_alloc_pages,
1803 .agp_destroy_page = agp_generic_destroy_page,
1804 .agp_destroy_pages = agp_generic_destroy_pages,
1805 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1806 .chipset_flush = intel_i830_chipset_flush,
1807 };
1808
1809 static const struct agp_bridge_driver intel_820_driver = {
1810 .owner = THIS_MODULE,
1811 .aperture_sizes = intel_8xx_sizes,
1812 .size_type = U8_APER_SIZE,
1813 .num_aperture_sizes = 7,
1814 .configure = intel_820_configure,
1815 .fetch_size = intel_8xx_fetch_size,
1816 .cleanup = intel_820_cleanup,
1817 .tlb_flush = intel_820_tlbflush,
1818 .mask_memory = agp_generic_mask_memory,
1819 .masks = intel_generic_masks,
1820 .agp_enable = agp_generic_enable,
1821 .cache_flush = global_cache_flush,
1822 .create_gatt_table = agp_generic_create_gatt_table,
1823 .free_gatt_table = agp_generic_free_gatt_table,
1824 .insert_memory = agp_generic_insert_memory,
1825 .remove_memory = agp_generic_remove_memory,
1826 .alloc_by_type = agp_generic_alloc_by_type,
1827 .free_by_type = agp_generic_free_by_type,
1828 .agp_alloc_page = agp_generic_alloc_page,
1829 .agp_alloc_pages = agp_generic_alloc_pages,
1830 .agp_destroy_page = agp_generic_destroy_page,
1831 .agp_destroy_pages = agp_generic_destroy_pages,
1832 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1833 };
1834
1835 static const struct agp_bridge_driver intel_830mp_driver = {
1836 .owner = THIS_MODULE,
1837 .aperture_sizes = intel_830mp_sizes,
1838 .size_type = U8_APER_SIZE,
1839 .num_aperture_sizes = 4,
1840 .configure = intel_830mp_configure,
1841 .fetch_size = intel_8xx_fetch_size,
1842 .cleanup = intel_8xx_cleanup,
1843 .tlb_flush = intel_8xx_tlbflush,
1844 .mask_memory = agp_generic_mask_memory,
1845 .masks = intel_generic_masks,
1846 .agp_enable = agp_generic_enable,
1847 .cache_flush = global_cache_flush,
1848 .create_gatt_table = agp_generic_create_gatt_table,
1849 .free_gatt_table = agp_generic_free_gatt_table,
1850 .insert_memory = agp_generic_insert_memory,
1851 .remove_memory = agp_generic_remove_memory,
1852 .alloc_by_type = agp_generic_alloc_by_type,
1853 .free_by_type = agp_generic_free_by_type,
1854 .agp_alloc_page = agp_generic_alloc_page,
1855 .agp_alloc_pages = agp_generic_alloc_pages,
1856 .agp_destroy_page = agp_generic_destroy_page,
1857 .agp_destroy_pages = agp_generic_destroy_pages,
1858 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1859 };
1860
1861 static const struct agp_bridge_driver intel_840_driver = {
1862 .owner = THIS_MODULE,
1863 .aperture_sizes = intel_8xx_sizes,
1864 .size_type = U8_APER_SIZE,
1865 .num_aperture_sizes = 7,
1866 .configure = intel_840_configure,
1867 .fetch_size = intel_8xx_fetch_size,
1868 .cleanup = intel_8xx_cleanup,
1869 .tlb_flush = intel_8xx_tlbflush,
1870 .mask_memory = agp_generic_mask_memory,
1871 .masks = intel_generic_masks,
1872 .agp_enable = agp_generic_enable,
1873 .cache_flush = global_cache_flush,
1874 .create_gatt_table = agp_generic_create_gatt_table,
1875 .free_gatt_table = agp_generic_free_gatt_table,
1876 .insert_memory = agp_generic_insert_memory,
1877 .remove_memory = agp_generic_remove_memory,
1878 .alloc_by_type = agp_generic_alloc_by_type,
1879 .free_by_type = agp_generic_free_by_type,
1880 .agp_alloc_page = agp_generic_alloc_page,
1881 .agp_alloc_pages = agp_generic_alloc_pages,
1882 .agp_destroy_page = agp_generic_destroy_page,
1883 .agp_destroy_pages = agp_generic_destroy_pages,
1884 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1885 };
1886
1887 static const struct agp_bridge_driver intel_845_driver = {
1888 .owner = THIS_MODULE,
1889 .aperture_sizes = intel_8xx_sizes,
1890 .size_type = U8_APER_SIZE,
1891 .num_aperture_sizes = 7,
1892 .configure = intel_845_configure,
1893 .fetch_size = intel_8xx_fetch_size,
1894 .cleanup = intel_8xx_cleanup,
1895 .tlb_flush = intel_8xx_tlbflush,
1896 .mask_memory = agp_generic_mask_memory,
1897 .masks = intel_generic_masks,
1898 .agp_enable = agp_generic_enable,
1899 .cache_flush = global_cache_flush,
1900 .create_gatt_table = agp_generic_create_gatt_table,
1901 .free_gatt_table = agp_generic_free_gatt_table,
1902 .insert_memory = agp_generic_insert_memory,
1903 .remove_memory = agp_generic_remove_memory,
1904 .alloc_by_type = agp_generic_alloc_by_type,
1905 .free_by_type = agp_generic_free_by_type,
1906 .agp_alloc_page = agp_generic_alloc_page,
1907 .agp_alloc_pages = agp_generic_alloc_pages,
1908 .agp_destroy_page = agp_generic_destroy_page,
1909 .agp_destroy_pages = agp_generic_destroy_pages,
1910 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1911 .chipset_flush = intel_i830_chipset_flush,
1912 };
1913
1914 static const struct agp_bridge_driver intel_850_driver = {
1915 .owner = THIS_MODULE,
1916 .aperture_sizes = intel_8xx_sizes,
1917 .size_type = U8_APER_SIZE,
1918 .num_aperture_sizes = 7,
1919 .configure = intel_850_configure,
1920 .fetch_size = intel_8xx_fetch_size,
1921 .cleanup = intel_8xx_cleanup,
1922 .tlb_flush = intel_8xx_tlbflush,
1923 .mask_memory = agp_generic_mask_memory,
1924 .masks = intel_generic_masks,
1925 .agp_enable = agp_generic_enable,
1926 .cache_flush = global_cache_flush,
1927 .create_gatt_table = agp_generic_create_gatt_table,
1928 .free_gatt_table = agp_generic_free_gatt_table,
1929 .insert_memory = agp_generic_insert_memory,
1930 .remove_memory = agp_generic_remove_memory,
1931 .alloc_by_type = agp_generic_alloc_by_type,
1932 .free_by_type = agp_generic_free_by_type,
1933 .agp_alloc_page = agp_generic_alloc_page,
1934 .agp_alloc_pages = agp_generic_alloc_pages,
1935 .agp_destroy_page = agp_generic_destroy_page,
1936 .agp_destroy_pages = agp_generic_destroy_pages,
1937 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1938 };
1939
1940 static const struct agp_bridge_driver intel_860_driver = {
1941 .owner = THIS_MODULE,
1942 .aperture_sizes = intel_8xx_sizes,
1943 .size_type = U8_APER_SIZE,
1944 .num_aperture_sizes = 7,
1945 .configure = intel_860_configure,
1946 .fetch_size = intel_8xx_fetch_size,
1947 .cleanup = intel_8xx_cleanup,
1948 .tlb_flush = intel_8xx_tlbflush,
1949 .mask_memory = agp_generic_mask_memory,
1950 .masks = intel_generic_masks,
1951 .agp_enable = agp_generic_enable,
1952 .cache_flush = global_cache_flush,
1953 .create_gatt_table = agp_generic_create_gatt_table,
1954 .free_gatt_table = agp_generic_free_gatt_table,
1955 .insert_memory = agp_generic_insert_memory,
1956 .remove_memory = agp_generic_remove_memory,
1957 .alloc_by_type = agp_generic_alloc_by_type,
1958 .free_by_type = agp_generic_free_by_type,
1959 .agp_alloc_page = agp_generic_alloc_page,
1960 .agp_alloc_pages = agp_generic_alloc_pages,
1961 .agp_destroy_page = agp_generic_destroy_page,
1962 .agp_destroy_pages = agp_generic_destroy_pages,
1963 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1964 };
1965
1966 static const struct agp_bridge_driver intel_915_driver = {
1967 .owner = THIS_MODULE,
1968 .aperture_sizes = intel_i830_sizes,
1969 .size_type = FIXED_APER_SIZE,
1970 .num_aperture_sizes = 4,
1971 .needs_scratch_page = true,
1972 .configure = intel_i915_configure,
1973 .fetch_size = intel_i9xx_fetch_size,
1974 .cleanup = intel_i915_cleanup,
1975 .tlb_flush = intel_i810_tlbflush,
1976 .mask_memory = intel_i810_mask_memory,
1977 .masks = intel_i810_masks,
1978 .agp_enable = intel_i810_agp_enable,
1979 .cache_flush = global_cache_flush,
1980 .create_gatt_table = intel_i915_create_gatt_table,
1981 .free_gatt_table = intel_i830_free_gatt_table,
1982 .insert_memory = intel_i915_insert_entries,
1983 .remove_memory = intel_i915_remove_entries,
1984 .alloc_by_type = intel_i830_alloc_by_type,
1985 .free_by_type = intel_i810_free_by_type,
1986 .agp_alloc_page = agp_generic_alloc_page,
1987 .agp_alloc_pages = agp_generic_alloc_pages,
1988 .agp_destroy_page = agp_generic_destroy_page,
1989 .agp_destroy_pages = agp_generic_destroy_pages,
1990 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1991 .chipset_flush = intel_i915_chipset_flush,
1992 };
1993
1994 static const struct agp_bridge_driver intel_i965_driver = {
1995 .owner = THIS_MODULE,
1996 .aperture_sizes = intel_i830_sizes,
1997 .size_type = FIXED_APER_SIZE,
1998 .num_aperture_sizes = 4,
1999 .needs_scratch_page = true,
2000 .configure = intel_i915_configure,
2001 .fetch_size = intel_i9xx_fetch_size,
2002 .cleanup = intel_i915_cleanup,
2003 .tlb_flush = intel_i810_tlbflush,
2004 .mask_memory = intel_i965_mask_memory,
2005 .masks = intel_i810_masks,
2006 .agp_enable = intel_i810_agp_enable,
2007 .cache_flush = global_cache_flush,
2008 .create_gatt_table = intel_i965_create_gatt_table,
2009 .free_gatt_table = intel_i830_free_gatt_table,
2010 .insert_memory = intel_i915_insert_entries,
2011 .remove_memory = intel_i915_remove_entries,
2012 .alloc_by_type = intel_i830_alloc_by_type,
2013 .free_by_type = intel_i810_free_by_type,
2014 .agp_alloc_page = agp_generic_alloc_page,
2015 .agp_alloc_pages = agp_generic_alloc_pages,
2016 .agp_destroy_page = agp_generic_destroy_page,
2017 .agp_destroy_pages = agp_generic_destroy_pages,
2018 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2019 .chipset_flush = intel_i915_chipset_flush,
2020 };
2021
2022 static const struct agp_bridge_driver intel_7505_driver = {
2023 .owner = THIS_MODULE,
2024 .aperture_sizes = intel_8xx_sizes,
2025 .size_type = U8_APER_SIZE,
2026 .num_aperture_sizes = 7,
2027 .configure = intel_7505_configure,
2028 .fetch_size = intel_8xx_fetch_size,
2029 .cleanup = intel_8xx_cleanup,
2030 .tlb_flush = intel_8xx_tlbflush,
2031 .mask_memory = agp_generic_mask_memory,
2032 .masks = intel_generic_masks,
2033 .agp_enable = agp_generic_enable,
2034 .cache_flush = global_cache_flush,
2035 .create_gatt_table = agp_generic_create_gatt_table,
2036 .free_gatt_table = agp_generic_free_gatt_table,
2037 .insert_memory = agp_generic_insert_memory,
2038 .remove_memory = agp_generic_remove_memory,
2039 .alloc_by_type = agp_generic_alloc_by_type,
2040 .free_by_type = agp_generic_free_by_type,
2041 .agp_alloc_page = agp_generic_alloc_page,
2042 .agp_alloc_pages = agp_generic_alloc_pages,
2043 .agp_destroy_page = agp_generic_destroy_page,
2044 .agp_destroy_pages = agp_generic_destroy_pages,
2045 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2046 };
2047
2048 static const struct agp_bridge_driver intel_g33_driver = {
2049 .owner = THIS_MODULE,
2050 .aperture_sizes = intel_i830_sizes,
2051 .size_type = FIXED_APER_SIZE,
2052 .num_aperture_sizes = 4,
2053 .needs_scratch_page = true,
2054 .configure = intel_i915_configure,
2055 .fetch_size = intel_i9xx_fetch_size,
2056 .cleanup = intel_i915_cleanup,
2057 .tlb_flush = intel_i810_tlbflush,
2058 .mask_memory = intel_i965_mask_memory,
2059 .masks = intel_i810_masks,
2060 .agp_enable = intel_i810_agp_enable,
2061 .cache_flush = global_cache_flush,
2062 .create_gatt_table = intel_i915_create_gatt_table,
2063 .free_gatt_table = intel_i830_free_gatt_table,
2064 .insert_memory = intel_i915_insert_entries,
2065 .remove_memory = intel_i915_remove_entries,
2066 .alloc_by_type = intel_i830_alloc_by_type,
2067 .free_by_type = intel_i810_free_by_type,
2068 .agp_alloc_page = agp_generic_alloc_page,
2069 .agp_alloc_pages = agp_generic_alloc_pages,
2070 .agp_destroy_page = agp_generic_destroy_page,
2071 .agp_destroy_pages = agp_generic_destroy_pages,
2072 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2073 .chipset_flush = intel_i915_chipset_flush,
2074 };
2075
2076 static int find_gmch(u16 device)
2077 {
2078 struct pci_dev *gmch_device;
2079
2080 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2081 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2082 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2083 device, gmch_device);
2084 }
2085
2086 if (!gmch_device)
2087 return 0;
2088
2089 intel_private.pcidev = gmch_device;
2090 return 1;
2091 }
2092
2093 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2094 * driver and gmch_driver must be non-null, and find_gmch will determine
2095 * which one should be used if a gmch_chip_id is present.
2096 */
2097 static const struct intel_driver_description {
2098 unsigned int chip_id;
2099 unsigned int gmch_chip_id;
2100 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2101 char *name;
2102 const struct agp_bridge_driver *driver;
2103 const struct agp_bridge_driver *gmch_driver;
2104 } intel_agp_chipsets[] = {
2105 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2106 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2107 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2108 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2109 NULL, &intel_810_driver },
2110 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2111 NULL, &intel_810_driver },
2112 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2113 NULL, &intel_810_driver },
2114 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2115 &intel_815_driver, &intel_810_driver },
2116 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2117 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2118 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2119 &intel_830mp_driver, &intel_830_driver },
2120 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2121 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2122 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2123 &intel_845_driver, &intel_830_driver },
2124 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2125 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2126 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2127 &intel_845_driver, &intel_830_driver },
2128 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2129 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2130 &intel_845_driver, &intel_830_driver },
2131 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2132 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2133 NULL, &intel_915_driver },
2134 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2135 NULL, &intel_915_driver },
2136 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2137 NULL, &intel_915_driver },
2138 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2139 NULL, &intel_915_driver },
2140 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2141 NULL, &intel_915_driver },
2142 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2143 NULL, &intel_915_driver },
2144 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2145 NULL, &intel_i965_driver },
2146 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2147 NULL, &intel_i965_driver },
2148 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2149 NULL, &intel_i965_driver },
2150 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2151 NULL, &intel_i965_driver },
2152 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2153 NULL, &intel_i965_driver },
2154 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2155 NULL, &intel_i965_driver },
2156 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2157 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2158 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2159 NULL, &intel_g33_driver },
2160 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2161 NULL, &intel_g33_driver },
2162 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2163 NULL, &intel_g33_driver },
2164 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2165 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2166 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2167 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2168 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2169 "Q45/Q43", NULL, &intel_i965_driver },
2170 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2171 "G45/G43", NULL, &intel_i965_driver },
2172 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2173 "G41", NULL, &intel_i965_driver },
2174 { 0, 0, 0, NULL, NULL, NULL }
2175 };
2176
2177 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2178 const struct pci_device_id *ent)
2179 {
2180 struct agp_bridge_data *bridge;
2181 u8 cap_ptr = 0;
2182 struct resource *r;
2183 int i;
2184
2185 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2186
2187 bridge = agp_alloc_bridge();
2188 if (!bridge)
2189 return -ENOMEM;
2190
2191 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2192 /* In case that multiple models of gfx chip may
2193 stand on same host bridge type, this can be
2194 sure we detect the right IGD. */
2195 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2196 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2197 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2198 bridge->driver =
2199 intel_agp_chipsets[i].gmch_driver;
2200 break;
2201 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2202 continue;
2203 } else {
2204 bridge->driver = intel_agp_chipsets[i].driver;
2205 break;
2206 }
2207 }
2208 }
2209
2210 if (intel_agp_chipsets[i].name == NULL) {
2211 if (cap_ptr)
2212 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2213 pdev->vendor, pdev->device);
2214 agp_put_bridge(bridge);
2215 return -ENODEV;
2216 }
2217
2218 if (bridge->driver == NULL) {
2219 /* bridge has no AGP and no IGD detected */
2220 if (cap_ptr)
2221 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2222 intel_agp_chipsets[i].gmch_chip_id);
2223 agp_put_bridge(bridge);
2224 return -ENODEV;
2225 }
2226
2227 bridge->dev = pdev;
2228 bridge->capndx = cap_ptr;
2229 bridge->dev_private_data = &intel_private;
2230
2231 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2232
2233 /*
2234 * The following fixes the case where the BIOS has "forgotten" to
2235 * provide an address range for the GART.
2236 * 20030610 - hamish@zot.org
2237 */
2238 r = &pdev->resource[0];
2239 if (!r->start && r->end) {
2240 if (pci_assign_resource(pdev, 0)) {
2241 dev_err(&pdev->dev, "can't assign resource 0\n");
2242 agp_put_bridge(bridge);
2243 return -ENODEV;
2244 }
2245 }
2246
2247 /*
2248 * If the device has not been properly setup, the following will catch
2249 * the problem and should stop the system from crashing.
2250 * 20030610 - hamish@zot.org
2251 */
2252 if (pci_enable_device(pdev)) {
2253 dev_err(&pdev->dev, "can't enable PCI device\n");
2254 agp_put_bridge(bridge);
2255 return -ENODEV;
2256 }
2257
2258 /* Fill in the mode register */
2259 if (cap_ptr) {
2260 pci_read_config_dword(pdev,
2261 bridge->capndx+PCI_AGP_STATUS,
2262 &bridge->mode);
2263 }
2264
2265 pci_set_drvdata(pdev, bridge);
2266 return agp_add_bridge(bridge);
2267 }
2268
2269 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2270 {
2271 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2272
2273 agp_remove_bridge(bridge);
2274
2275 if (intel_private.pcidev)
2276 pci_dev_put(intel_private.pcidev);
2277
2278 agp_put_bridge(bridge);
2279 }
2280
2281 #ifdef CONFIG_PM
2282 static int agp_intel_resume(struct pci_dev *pdev)
2283 {
2284 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2285 int ret_val;
2286
2287 pci_restore_state(pdev);
2288
2289 /* We should restore our graphics device's config space,
2290 * as host bridge (00:00) resumes before graphics device (02:00),
2291 * then our access to its pci space can work right.
2292 */
2293 if (intel_private.pcidev)
2294 pci_restore_state(intel_private.pcidev);
2295
2296 if (bridge->driver == &intel_generic_driver)
2297 intel_configure();
2298 else if (bridge->driver == &intel_850_driver)
2299 intel_850_configure();
2300 else if (bridge->driver == &intel_845_driver)
2301 intel_845_configure();
2302 else if (bridge->driver == &intel_830mp_driver)
2303 intel_830mp_configure();
2304 else if (bridge->driver == &intel_915_driver)
2305 intel_i915_configure();
2306 else if (bridge->driver == &intel_830_driver)
2307 intel_i830_configure();
2308 else if (bridge->driver == &intel_810_driver)
2309 intel_i810_configure();
2310 else if (bridge->driver == &intel_i965_driver)
2311 intel_i915_configure();
2312
2313 ret_val = agp_rebind_memory();
2314 if (ret_val != 0)
2315 return ret_val;
2316
2317 return 0;
2318 }
2319 #endif
2320
2321 static struct pci_device_id agp_intel_pci_table[] = {
2322 #define ID(x) \
2323 { \
2324 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2325 .class_mask = ~0, \
2326 .vendor = PCI_VENDOR_ID_INTEL, \
2327 .device = x, \
2328 .subvendor = PCI_ANY_ID, \
2329 .subdevice = PCI_ANY_ID, \
2330 }
2331 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2332 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2333 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2334 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2335 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2336 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2337 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2338 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2339 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2340 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2341 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2342 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2343 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2344 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2345 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2346 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2347 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2348 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2349 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2350 ID(PCI_DEVICE_ID_INTEL_7505_0),
2351 ID(PCI_DEVICE_ID_INTEL_7205_0),
2352 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2353 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2354 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2355 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2356 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2357 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2358 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2359 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2360 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2361 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2362 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2363 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2364 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2365 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2366 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2367 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2368 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2369 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2370 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2371 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2372 { }
2373 };
2374
2375 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2376
2377 static struct pci_driver agp_intel_pci_driver = {
2378 .name = "agpgart-intel",
2379 .id_table = agp_intel_pci_table,
2380 .probe = agp_intel_probe,
2381 .remove = __devexit_p(agp_intel_remove),
2382 #ifdef CONFIG_PM
2383 .resume = agp_intel_resume,
2384 #endif
2385 };
2386
2387 static int __init agp_intel_init(void)
2388 {
2389 if (agp_off)
2390 return -EINVAL;
2391 return pci_register_driver(&agp_intel_pci_driver);
2392 }
2393
2394 static void __exit agp_intel_cleanup(void)
2395 {
2396 pci_unregister_driver(&agp_intel_pci_driver);
2397 }
2398
2399 module_init(agp_intel_init);
2400 module_exit(agp_intel_cleanup);
2401
2402 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2403 MODULE_LICENSE("GPL and additional rights");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree