?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: Remove redundant K6 MSRs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / svm.c
blob24a2206962986dcb82326c4c810281a120831acd
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
30
31 #include <asm/tlbflush.h>
32 #include <asm/desc.h>
33
34 #include <asm/virtext.h>
35 #include "trace.h"
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 #define IOPM_ALLOC_ORDER 2
43 #define MSRPM_ALLOC_ORDER 1
44
45 #define SEG_TYPE_LDT 2
46 #define SEG_TYPE_BUSY_TSS16 3
47
48 #define SVM_FEATURE_NPT (1 << 0)
49 #define SVM_FEATURE_LBRV (1 << 1)
50 #define SVM_FEATURE_SVML (1 << 2)
51 #define SVM_FEATURE_NRIP (1 << 3)
52 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
53
54 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
55 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
56 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
57
58 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
59
60 static bool erratum_383_found __read_mostly;
61
62 static const u32 host_save_user_msrs[] = {
63 #ifdef CONFIG_X86_64
64 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
65 MSR_FS_BASE,
66 #endif
67 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
68 };
69
70 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
71
72 struct kvm_vcpu;
73
74 struct nested_state {
75 struct vmcb *hsave;
76 u64 hsave_msr;
77 u64 vm_cr_msr;
78 u64 vmcb;
79
80 /* These are the merged vectors */
81 u32 *msrpm;
82
83 /* gpa pointers to the real vectors */
84 u64 vmcb_msrpm;
85 u64 vmcb_iopm;
86
87 /* A VMEXIT is required but not yet emulated */
88 bool exit_required;
89
90 /* cache for intercepts of the guest */
91 u16 intercept_cr_read;
92 u16 intercept_cr_write;
93 u16 intercept_dr_read;
94 u16 intercept_dr_write;
95 u32 intercept_exceptions;
96 u64 intercept;
97
98 };
99
100 #define MSRPM_OFFSETS 16
101 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
102
103 struct vcpu_svm {
104 struct kvm_vcpu vcpu;
105 struct vmcb *vmcb;
106 unsigned long vmcb_pa;
107 struct svm_cpu_data *svm_data;
108 uint64_t asid_generation;
109 uint64_t sysenter_esp;
110 uint64_t sysenter_eip;
111
112 u64 next_rip;
113
114 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
115 u64 host_gs_base;
116
117 u32 *msrpm;
118
119 struct nested_state nested;
120
121 bool nmi_singlestep;
122
123 unsigned int3_injected;
124 unsigned long int3_rip;
125 };
126
127 #define MSR_INVALID 0xffffffffU
128
129 static struct svm_direct_access_msrs {
130 u32 index; /* Index of the MSR */
131 bool always; /* True if intercept is always on */
132 } direct_access_msrs[] = {
133 { .index = MSR_STAR, .always = true },
134 { .index = MSR_IA32_SYSENTER_CS, .always = true },
135 #ifdef CONFIG_X86_64
136 { .index = MSR_GS_BASE, .always = true },
137 { .index = MSR_FS_BASE, .always = true },
138 { .index = MSR_KERNEL_GS_BASE, .always = true },
139 { .index = MSR_LSTAR, .always = true },
140 { .index = MSR_CSTAR, .always = true },
141 { .index = MSR_SYSCALL_MASK, .always = true },
142 #endif
143 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
144 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
145 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
146 { .index = MSR_IA32_LASTINTTOIP, .always = false },
147 { .index = MSR_INVALID, .always = false },
148 };
149
150 /* enable NPT for AMD64 and X86 with PAE */
151 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
152 static bool npt_enabled = true;
153 #else
154 static bool npt_enabled;
155 #endif
156 static int npt = 1;
157
158 module_param(npt, int, S_IRUGO);
159
160 static int nested = 1;
161 module_param(nested, int, S_IRUGO);
162
163 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
164 static void svm_complete_interrupts(struct vcpu_svm *svm);
165
166 static int nested_svm_exit_handled(struct vcpu_svm *svm);
167 static int nested_svm_intercept(struct vcpu_svm *svm);
168 static int nested_svm_vmexit(struct vcpu_svm *svm);
169 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
170 bool has_error_code, u32 error_code);
171
172 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
173 {
174 return container_of(vcpu, struct vcpu_svm, vcpu);
175 }
176
177 static inline bool is_nested(struct vcpu_svm *svm)
178 {
179 return svm->nested.vmcb;
180 }
181
182 static inline void enable_gif(struct vcpu_svm *svm)
183 {
184 svm->vcpu.arch.hflags |= HF_GIF_MASK;
185 }
186
187 static inline void disable_gif(struct vcpu_svm *svm)
188 {
189 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
190 }
191
192 static inline bool gif_set(struct vcpu_svm *svm)
193 {
194 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
195 }
196
197 static unsigned long iopm_base;
198
199 struct kvm_ldttss_desc {
200 u16 limit0;
201 u16 base0;
202 unsigned base1:8, type:5, dpl:2, p:1;
203 unsigned limit1:4, zero0:3, g:1, base2:8;
204 u32 base3;
205 u32 zero1;
206 } __attribute__((packed));
207
208 struct svm_cpu_data {
209 int cpu;
210
211 u64 asid_generation;
212 u32 max_asid;
213 u32 next_asid;
214 struct kvm_ldttss_desc *tss_desc;
215
216 struct page *save_area;
217 };
218
219 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
220 static uint32_t svm_features;
221
222 struct svm_init_data {
223 int cpu;
224 int r;
225 };
226
227 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
228
229 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
230 #define MSRS_RANGE_SIZE 2048
231 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
232
233 static u32 svm_msrpm_offset(u32 msr)
234 {
235 u32 offset;
236 int i;
237
238 for (i = 0; i < NUM_MSR_MAPS; i++) {
239 if (msr < msrpm_ranges[i] ||
240 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
241 continue;
242
243 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
244 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
245
246 /* Now we have the u8 offset - but need the u32 offset */
247 return offset / 4;
248 }
249
250 /* MSR not in any range */
251 return MSR_INVALID;
252 }
253
254 #define MAX_INST_SIZE 15
255
256 static inline u32 svm_has(u32 feat)
257 {
258 return svm_features & feat;
259 }
260
261 static inline void clgi(void)
262 {
263 asm volatile (__ex(SVM_CLGI));
264 }
265
266 static inline void stgi(void)
267 {
268 asm volatile (__ex(SVM_STGI));
269 }
270
271 static inline void invlpga(unsigned long addr, u32 asid)
272 {
273 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
274 }
275
276 static inline void force_new_asid(struct kvm_vcpu *vcpu)
277 {
278 to_svm(vcpu)->asid_generation--;
279 }
280
281 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
282 {
283 force_new_asid(vcpu);
284 }
285
286 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
287 {
288 if (!npt_enabled && !(efer & EFER_LMA))
289 efer &= ~EFER_LME;
290
291 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
292 vcpu->arch.efer = efer;
293 }
294
295 static int is_external_interrupt(u32 info)
296 {
297 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
298 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
299 }
300
301 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
302 {
303 struct vcpu_svm *svm = to_svm(vcpu);
304 u32 ret = 0;
305
306 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
307 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
308 return ret & mask;
309 }
310
311 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
312 {
313 struct vcpu_svm *svm = to_svm(vcpu);
314
315 if (mask == 0)
316 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
317 else
318 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
319
320 }
321
322 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
323 {
324 struct vcpu_svm *svm = to_svm(vcpu);
325
326 if (svm->vmcb->control.next_rip != 0)
327 svm->next_rip = svm->vmcb->control.next_rip;
328
329 if (!svm->next_rip) {
330 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
331 EMULATE_DONE)
332 printk(KERN_DEBUG "%s: NOP\n", __func__);
333 return;
334 }
335 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
336 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
337 __func__, kvm_rip_read(vcpu), svm->next_rip);
338
339 kvm_rip_write(vcpu, svm->next_rip);
340 svm_set_interrupt_shadow(vcpu, 0);
341 }
342
343 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
344 bool has_error_code, u32 error_code,
345 bool reinject)
346 {
347 struct vcpu_svm *svm = to_svm(vcpu);
348
349 /*
350 * If we are within a nested VM we'd better #VMEXIT and let the guest
351 * handle the exception
352 */
353 if (!reinject &&
354 nested_svm_check_exception(svm, nr, has_error_code, error_code))
355 return;
356
357 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
358 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
359
360 /*
361 * For guest debugging where we have to reinject #BP if some
362 * INT3 is guest-owned:
363 * Emulate nRIP by moving RIP forward. Will fail if injection
364 * raises a fault that is not intercepted. Still better than
365 * failing in all cases.
366 */
367 skip_emulated_instruction(&svm->vcpu);
368 rip = kvm_rip_read(&svm->vcpu);
369 svm->int3_rip = rip + svm->vmcb->save.cs.base;
370 svm->int3_injected = rip - old_rip;
371 }
372
373 svm->vmcb->control.event_inj = nr
374 | SVM_EVTINJ_VALID
375 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
376 | SVM_EVTINJ_TYPE_EXEPT;
377 svm->vmcb->control.event_inj_err = error_code;
378 }
379
380 static void svm_init_erratum_383(void)
381 {
382 u32 low, high;
383 int err;
384 u64 val;
385
386 /* Only Fam10h is affected */
387 if (boot_cpu_data.x86 != 0x10)
388 return;
389
390 /* Use _safe variants to not break nested virtualization */
391 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
392 if (err)
393 return;
394
395 val |= (1ULL << 47);
396
397 low = lower_32_bits(val);
398 high = upper_32_bits(val);
399
400 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
401
402 erratum_383_found = true;
403 }
404
405 static int has_svm(void)
406 {
407 const char *msg;
408
409 if (!cpu_has_svm(&msg)) {
410 printk(KERN_INFO "has_svm: %s\n", msg);
411 return 0;
412 }
413
414 return 1;
415 }
416
417 static void svm_hardware_disable(void *garbage)
418 {
419 cpu_svm_disable();
420 }
421
422 static int svm_hardware_enable(void *garbage)
423 {
424
425 struct svm_cpu_data *sd;
426 uint64_t efer;
427 struct desc_ptr gdt_descr;
428 struct desc_struct *gdt;
429 int me = raw_smp_processor_id();
430
431 rdmsrl(MSR_EFER, efer);
432 if (efer & EFER_SVME)
433 return -EBUSY;
434
435 if (!has_svm()) {
436 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
437 me);
438 return -EINVAL;
439 }
440 sd = per_cpu(svm_data, me);
441
442 if (!sd) {
443 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
444 me);
445 return -EINVAL;
446 }
447
448 sd->asid_generation = 1;
449 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
450 sd->next_asid = sd->max_asid + 1;
451
452 native_store_gdt(&gdt_descr);
453 gdt = (struct desc_struct *)gdt_descr.address;
454 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
455
456 wrmsrl(MSR_EFER, efer | EFER_SVME);
457
458 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
459
460 svm_init_erratum_383();
461
462 return 0;
463 }
464
465 static void svm_cpu_uninit(int cpu)
466 {
467 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
468
469 if (!sd)
470 return;
471
472 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
473 __free_page(sd->save_area);
474 kfree(sd);
475 }
476
477 static int svm_cpu_init(int cpu)
478 {
479 struct svm_cpu_data *sd;
480 int r;
481
482 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
483 if (!sd)
484 return -ENOMEM;
485 sd->cpu = cpu;
486 sd->save_area = alloc_page(GFP_KERNEL);
487 r = -ENOMEM;
488 if (!sd->save_area)
489 goto err_1;
490
491 per_cpu(svm_data, cpu) = sd;
492
493 return 0;
494
495 err_1:
496 kfree(sd);
497 return r;
498
499 }
500
501 static bool valid_msr_intercept(u32 index)
502 {
503 int i;
504
505 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
506 if (direct_access_msrs[i].index == index)
507 return true;
508
509 return false;
510 }
511
512 static void set_msr_interception(u32 *msrpm, unsigned msr,
513 int read, int write)
514 {
515 u8 bit_read, bit_write;
516 unsigned long tmp;
517 u32 offset;
518
519 /*
520 * If this warning triggers extend the direct_access_msrs list at the
521 * beginning of the file
522 */
523 WARN_ON(!valid_msr_intercept(msr));
524
525 offset = svm_msrpm_offset(msr);
526 bit_read = 2 * (msr & 0x0f);
527 bit_write = 2 * (msr & 0x0f) + 1;
528 tmp = msrpm[offset];
529
530 BUG_ON(offset == MSR_INVALID);
531
532 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
533 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
534
535 msrpm[offset] = tmp;
536 }
537
538 static void svm_vcpu_init_msrpm(u32 *msrpm)
539 {
540 int i;
541
542 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
543
544 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
545 if (!direct_access_msrs[i].always)
546 continue;
547
548 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
549 }
550 }
551
552 static void add_msr_offset(u32 offset)
553 {
554 int i;
555
556 for (i = 0; i < MSRPM_OFFSETS; ++i) {
557
558 /* Offset already in list? */
559 if (msrpm_offsets[i] == offset)
560 return;
561
562 /* Slot used by another offset? */
563 if (msrpm_offsets[i] != MSR_INVALID)
564 continue;
565
566 /* Add offset to list */
567 msrpm_offsets[i] = offset;
568
569 return;
570 }
571
572 /*
573 * If this BUG triggers the msrpm_offsets table has an overflow. Just
574 * increase MSRPM_OFFSETS in this case.
575 */
576 BUG();
577 }
578
579 static void init_msrpm_offsets(void)
580 {
581 int i;
582
583 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
584
585 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
586 u32 offset;
587
588 offset = svm_msrpm_offset(direct_access_msrs[i].index);
589 BUG_ON(offset == MSR_INVALID);
590
591 add_msr_offset(offset);
592 }
593 }
594
595 static void svm_enable_lbrv(struct vcpu_svm *svm)
596 {
597 u32 *msrpm = svm->msrpm;
598
599 svm->vmcb->control.lbr_ctl = 1;
600 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
601 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
602 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
603 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
604 }
605
606 static void svm_disable_lbrv(struct vcpu_svm *svm)
607 {
608 u32 *msrpm = svm->msrpm;
609
610 svm->vmcb->control.lbr_ctl = 0;
611 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
612 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
613 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
614 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
615 }
616
617 static __init int svm_hardware_setup(void)
618 {
619 int cpu;
620 struct page *iopm_pages;
621 void *iopm_va;
622 int r;
623
624 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
625
626 if (!iopm_pages)
627 return -ENOMEM;
628
629 iopm_va = page_address(iopm_pages);
630 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
631 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
632
633 init_msrpm_offsets();
634
635 if (boot_cpu_has(X86_FEATURE_NX))
636 kvm_enable_efer_bits(EFER_NX);
637
638 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
639 kvm_enable_efer_bits(EFER_FFXSR);
640
641 if (nested) {
642 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
643 kvm_enable_efer_bits(EFER_SVME);
644 }
645
646 for_each_possible_cpu(cpu) {
647 r = svm_cpu_init(cpu);
648 if (r)
649 goto err;
650 }
651
652 svm_features = cpuid_edx(SVM_CPUID_FUNC);
653
654 if (!svm_has(SVM_FEATURE_NPT))
655 npt_enabled = false;
656
657 if (npt_enabled && !npt) {
658 printk(KERN_INFO "kvm: Nested Paging disabled\n");
659 npt_enabled = false;
660 }
661
662 if (npt_enabled) {
663 printk(KERN_INFO "kvm: Nested Paging enabled\n");
664 kvm_enable_tdp();
665 } else
666 kvm_disable_tdp();
667
668 return 0;
669
670 err:
671 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
672 iopm_base = 0;
673 return r;
674 }
675
676 static __exit void svm_hardware_unsetup(void)
677 {
678 int cpu;
679
680 for_each_possible_cpu(cpu)
681 svm_cpu_uninit(cpu);
682
683 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
684 iopm_base = 0;
685 }
686
687 static void init_seg(struct vmcb_seg *seg)
688 {
689 seg->selector = 0;
690 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
691 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
692 seg->limit = 0xffff;
693 seg->base = 0;
694 }
695
696 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
697 {
698 seg->selector = 0;
699 seg->attrib = SVM_SELECTOR_P_MASK | type;
700 seg->limit = 0xffff;
701 seg->base = 0;
702 }
703
704 static void init_vmcb(struct vcpu_svm *svm)
705 {
706 struct vmcb_control_area *control = &svm->vmcb->control;
707 struct vmcb_save_area *save = &svm->vmcb->save;
708
709 svm->vcpu.fpu_active = 1;
710
711 control->intercept_cr_read = INTERCEPT_CR0_MASK |
712 INTERCEPT_CR3_MASK |
713 INTERCEPT_CR4_MASK;
714
715 control->intercept_cr_write = INTERCEPT_CR0_MASK |
716 INTERCEPT_CR3_MASK |
717 INTERCEPT_CR4_MASK |
718 INTERCEPT_CR8_MASK;
719
720 control->intercept_dr_read = INTERCEPT_DR0_MASK |
721 INTERCEPT_DR1_MASK |
722 INTERCEPT_DR2_MASK |
723 INTERCEPT_DR3_MASK |
724 INTERCEPT_DR4_MASK |
725 INTERCEPT_DR5_MASK |
726 INTERCEPT_DR6_MASK |
727 INTERCEPT_DR7_MASK;
728
729 control->intercept_dr_write = INTERCEPT_DR0_MASK |
730 INTERCEPT_DR1_MASK |
731 INTERCEPT_DR2_MASK |
732 INTERCEPT_DR3_MASK |
733 INTERCEPT_DR4_MASK |
734 INTERCEPT_DR5_MASK |
735 INTERCEPT_DR6_MASK |
736 INTERCEPT_DR7_MASK;
737
738 control->intercept_exceptions = (1 << PF_VECTOR) |
739 (1 << UD_VECTOR) |
740 (1 << MC_VECTOR);
741
742
743 control->intercept = (1ULL << INTERCEPT_INTR) |
744 (1ULL << INTERCEPT_NMI) |
745 (1ULL << INTERCEPT_SMI) |
746 (1ULL << INTERCEPT_SELECTIVE_CR0) |
747 (1ULL << INTERCEPT_CPUID) |
748 (1ULL << INTERCEPT_INVD) |
749 (1ULL << INTERCEPT_HLT) |
750 (1ULL << INTERCEPT_INVLPG) |
751 (1ULL << INTERCEPT_INVLPGA) |
752 (1ULL << INTERCEPT_IOIO_PROT) |
753 (1ULL << INTERCEPT_MSR_PROT) |
754 (1ULL << INTERCEPT_TASK_SWITCH) |
755 (1ULL << INTERCEPT_SHUTDOWN) |
756 (1ULL << INTERCEPT_VMRUN) |
757 (1ULL << INTERCEPT_VMMCALL) |
758 (1ULL << INTERCEPT_VMLOAD) |
759 (1ULL << INTERCEPT_VMSAVE) |
760 (1ULL << INTERCEPT_STGI) |
761 (1ULL << INTERCEPT_CLGI) |
762 (1ULL << INTERCEPT_SKINIT) |
763 (1ULL << INTERCEPT_WBINVD) |
764 (1ULL << INTERCEPT_MONITOR) |
765 (1ULL << INTERCEPT_MWAIT);
766
767 control->iopm_base_pa = iopm_base;
768 control->msrpm_base_pa = __pa(svm->msrpm);
769 control->tsc_offset = 0;
770 control->int_ctl = V_INTR_MASKING_MASK;
771
772 init_seg(&save->es);
773 init_seg(&save->ss);
774 init_seg(&save->ds);
775 init_seg(&save->fs);
776 init_seg(&save->gs);
777
778 save->cs.selector = 0xf000;
779 /* Executable/Readable Code Segment */
780 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
781 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
782 save->cs.limit = 0xffff;
783 /*
784 * cs.base should really be 0xffff0000, but vmx can't handle that, so
785 * be consistent with it.
786 *
787 * Replace when we have real mode working for vmx.
788 */
789 save->cs.base = 0xf0000;
790
791 save->gdtr.limit = 0xffff;
792 save->idtr.limit = 0xffff;
793
794 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
795 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
796
797 save->efer = EFER_SVME;
798 save->dr6 = 0xffff0ff0;
799 save->dr7 = 0x400;
800 save->rflags = 2;
801 save->rip = 0x0000fff0;
802 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
803
804 /*
805 * This is the guest-visible cr0 value.
806 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
807 */
808 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
809 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
810
811 save->cr4 = X86_CR4_PAE;
812 /* rdx = ?? */
813
814 if (npt_enabled) {
815 /* Setup VMCB for Nested Paging */
816 control->nested_ctl = 1;
817 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
818 (1ULL << INTERCEPT_INVLPG));
819 control->intercept_exceptions &= ~(1 << PF_VECTOR);
820 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
821 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
822 save->g_pat = 0x0007040600070406ULL;
823 save->cr3 = 0;
824 save->cr4 = 0;
825 }
826 force_new_asid(&svm->vcpu);
827
828 svm->nested.vmcb = 0;
829 svm->vcpu.arch.hflags = 0;
830
831 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
832 control->pause_filter_count = 3000;
833 control->intercept |= (1ULL << INTERCEPT_PAUSE);
834 }
835
836 enable_gif(svm);
837 }
838
839 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
840 {
841 struct vcpu_svm *svm = to_svm(vcpu);
842
843 init_vmcb(svm);
844
845 if (!kvm_vcpu_is_bsp(vcpu)) {
846 kvm_rip_write(vcpu, 0);
847 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
848 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
849 }
850 vcpu->arch.regs_avail = ~0;
851 vcpu->arch.regs_dirty = ~0;
852
853 return 0;
854 }
855
856 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
857 {
858 struct vcpu_svm *svm;
859 struct page *page;
860 struct page *msrpm_pages;
861 struct page *hsave_page;
862 struct page *nested_msrpm_pages;
863 int err;
864
865 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
866 if (!svm) {
867 err = -ENOMEM;
868 goto out;
869 }
870
871 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
872 if (err)
873 goto free_svm;
874
875 err = -ENOMEM;
876 page = alloc_page(GFP_KERNEL);
877 if (!page)
878 goto uninit;
879
880 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
881 if (!msrpm_pages)
882 goto free_page1;
883
884 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
885 if (!nested_msrpm_pages)
886 goto free_page2;
887
888 hsave_page = alloc_page(GFP_KERNEL);
889 if (!hsave_page)
890 goto free_page3;
891
892 svm->nested.hsave = page_address(hsave_page);
893
894 svm->msrpm = page_address(msrpm_pages);
895 svm_vcpu_init_msrpm(svm->msrpm);
896
897 svm->nested.msrpm = page_address(nested_msrpm_pages);
898 svm_vcpu_init_msrpm(svm->nested.msrpm);
899
900 svm->vmcb = page_address(page);
901 clear_page(svm->vmcb);
902 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
903 svm->asid_generation = 0;
904 init_vmcb(svm);
905
906 fx_init(&svm->vcpu);
907 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
908 if (kvm_vcpu_is_bsp(&svm->vcpu))
909 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
910
911 return &svm->vcpu;
912
913 free_page3:
914 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
915 free_page2:
916 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
917 free_page1:
918 __free_page(page);
919 uninit:
920 kvm_vcpu_uninit(&svm->vcpu);
921 free_svm:
922 kmem_cache_free(kvm_vcpu_cache, svm);
923 out:
924 return ERR_PTR(err);
925 }
926
927 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
928 {
929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
932 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
933 __free_page(virt_to_page(svm->nested.hsave));
934 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
935 kvm_vcpu_uninit(vcpu);
936 kmem_cache_free(kvm_vcpu_cache, svm);
937 }
938
939 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
940 {
941 struct vcpu_svm *svm = to_svm(vcpu);
942 int i;
943
944 if (unlikely(cpu != vcpu->cpu)) {
945 u64 delta;
946
947 if (check_tsc_unstable()) {
948 /*
949 * Make sure that the guest sees a monotonically
950 * increasing TSC.
951 */
952 delta = vcpu->arch.host_tsc - native_read_tsc();
953 svm->vmcb->control.tsc_offset += delta;
954 if (is_nested(svm))
955 svm->nested.hsave->control.tsc_offset += delta;
956 }
957 vcpu->cpu = cpu;
958 kvm_migrate_timers(vcpu);
959 svm->asid_generation = 0;
960 }
961
962 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
963 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
964 }
965
966 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
967 {
968 struct vcpu_svm *svm = to_svm(vcpu);
969 int i;
970
971 ++vcpu->stat.host_state_reload;
972 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
973 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
974
975 vcpu->arch.host_tsc = native_read_tsc();
976 }
977
978 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
979 {
980 return to_svm(vcpu)->vmcb->save.rflags;
981 }
982
983 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
984 {
985 to_svm(vcpu)->vmcb->save.rflags = rflags;
986 }
987
988 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
989 {
990 switch (reg) {
991 case VCPU_EXREG_PDPTR:
992 BUG_ON(!npt_enabled);
993 load_pdptrs(vcpu, vcpu->arch.cr3);
994 break;
995 default:
996 BUG();
997 }
998 }
999
1000 static void svm_set_vintr(struct vcpu_svm *svm)
1001 {
1002 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1003 }
1004
1005 static void svm_clear_vintr(struct vcpu_svm *svm)
1006 {
1007 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1008 }
1009
1010 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1011 {
1012 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1013
1014 switch (seg) {
1015 case VCPU_SREG_CS: return &save->cs;
1016 case VCPU_SREG_DS: return &save->ds;
1017 case VCPU_SREG_ES: return &save->es;
1018 case VCPU_SREG_FS: return &save->fs;
1019 case VCPU_SREG_GS: return &save->gs;
1020 case VCPU_SREG_SS: return &save->ss;
1021 case VCPU_SREG_TR: return &save->tr;
1022 case VCPU_SREG_LDTR: return &save->ldtr;
1023 }
1024 BUG();
1025 return NULL;
1026 }
1027
1028 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1029 {
1030 struct vmcb_seg *s = svm_seg(vcpu, seg);
1031
1032 return s->base;
1033 }
1034
1035 static void svm_get_segment(struct kvm_vcpu *vcpu,
1036 struct kvm_segment *var, int seg)
1037 {
1038 struct vmcb_seg *s = svm_seg(vcpu, seg);
1039
1040 var->base = s->base;
1041 var->limit = s->limit;
1042 var->selector = s->selector;
1043 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1044 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1045 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1046 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1047 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1048 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1049 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1050 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1051
1052 /*
1053 * AMD's VMCB does not have an explicit unusable field, so emulate it
1054 * for cross vendor migration purposes by "not present"
1055 */
1056 var->unusable = !var->present || (var->type == 0);
1057
1058 switch (seg) {
1059 case VCPU_SREG_CS:
1060 /*
1061 * SVM always stores 0 for the 'G' bit in the CS selector in
1062 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1063 * Intel's VMENTRY has a check on the 'G' bit.
1064 */
1065 var->g = s->limit > 0xfffff;
1066 break;
1067 case VCPU_SREG_TR:
1068 /*
1069 * Work around a bug where the busy flag in the tr selector
1070 * isn't exposed
1071 */
1072 var->type |= 0x2;
1073 break;
1074 case VCPU_SREG_DS:
1075 case VCPU_SREG_ES:
1076 case VCPU_SREG_FS:
1077 case VCPU_SREG_GS:
1078 /*
1079 * The accessed bit must always be set in the segment
1080 * descriptor cache, although it can be cleared in the
1081 * descriptor, the cached bit always remains at 1. Since
1082 * Intel has a check on this, set it here to support
1083 * cross-vendor migration.
1084 */
1085 if (!var->unusable)
1086 var->type |= 0x1;
1087 break;
1088 case VCPU_SREG_SS:
1089 /*
1090 * On AMD CPUs sometimes the DB bit in the segment
1091 * descriptor is left as 1, although the whole segment has
1092 * been made unusable. Clear it here to pass an Intel VMX
1093 * entry check when cross vendor migrating.
1094 */
1095 if (var->unusable)
1096 var->db = 0;
1097 break;
1098 }
1099 }
1100
1101 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1102 {
1103 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1104
1105 return save->cpl;
1106 }
1107
1108 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1109 {
1110 struct vcpu_svm *svm = to_svm(vcpu);
1111
1112 dt->size = svm->vmcb->save.idtr.limit;
1113 dt->address = svm->vmcb->save.idtr.base;
1114 }
1115
1116 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1117 {
1118 struct vcpu_svm *svm = to_svm(vcpu);
1119
1120 svm->vmcb->save.idtr.limit = dt->size;
1121 svm->vmcb->save.idtr.base = dt->address ;
1122 }
1123
1124 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1125 {
1126 struct vcpu_svm *svm = to_svm(vcpu);
1127
1128 dt->size = svm->vmcb->save.gdtr.limit;
1129 dt->address = svm->vmcb->save.gdtr.base;
1130 }
1131
1132 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1133 {
1134 struct vcpu_svm *svm = to_svm(vcpu);
1135
1136 svm->vmcb->save.gdtr.limit = dt->size;
1137 svm->vmcb->save.gdtr.base = dt->address ;
1138 }
1139
1140 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1141 {
1142 }
1143
1144 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1145 {
1146 }
1147
1148 static void update_cr0_intercept(struct vcpu_svm *svm)
1149 {
1150 struct vmcb *vmcb = svm->vmcb;
1151 ulong gcr0 = svm->vcpu.arch.cr0;
1152 u64 *hcr0 = &svm->vmcb->save.cr0;
1153
1154 if (!svm->vcpu.fpu_active)
1155 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1156 else
1157 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1158 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1159
1160
1161 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1162 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1163 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1164 if (is_nested(svm)) {
1165 struct vmcb *hsave = svm->nested.hsave;
1166
1167 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1168 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1169 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1170 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1171 }
1172 } else {
1173 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1174 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1175 if (is_nested(svm)) {
1176 struct vmcb *hsave = svm->nested.hsave;
1177
1178 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1179 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1180 }
1181 }
1182 }
1183
1184 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1185 {
1186 struct vcpu_svm *svm = to_svm(vcpu);
1187
1188 if (is_nested(svm)) {
1189 /*
1190 * We are here because we run in nested mode, the host kvm
1191 * intercepts cr0 writes but the l1 hypervisor does not.
1192 * But the L1 hypervisor may intercept selective cr0 writes.
1193 * This needs to be checked here.
1194 */
1195 unsigned long old, new;
1196
1197 /* Remove bits that would trigger a real cr0 write intercept */
1198 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1199 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1200
1201 if (old == new) {
1202 /* cr0 write with ts and mp unchanged */
1203 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1204 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1205 return;
1206 }
1207 }
1208
1209 #ifdef CONFIG_X86_64
1210 if (vcpu->arch.efer & EFER_LME) {
1211 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1212 vcpu->arch.efer |= EFER_LMA;
1213 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1214 }
1215
1216 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1217 vcpu->arch.efer &= ~EFER_LMA;
1218 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1219 }
1220 }
1221 #endif
1222 vcpu->arch.cr0 = cr0;
1223
1224 if (!npt_enabled)
1225 cr0 |= X86_CR0_PG | X86_CR0_WP;
1226
1227 if (!vcpu->fpu_active)
1228 cr0 |= X86_CR0_TS;
1229 /*
1230 * re-enable caching here because the QEMU bios
1231 * does not do it - this results in some delay at
1232 * reboot
1233 */
1234 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1235 svm->vmcb->save.cr0 = cr0;
1236 update_cr0_intercept(svm);
1237 }
1238
1239 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1240 {
1241 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1242 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1243
1244 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1245 force_new_asid(vcpu);
1246
1247 vcpu->arch.cr4 = cr4;
1248 if (!npt_enabled)
1249 cr4 |= X86_CR4_PAE;
1250 cr4 |= host_cr4_mce;
1251 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1252 }
1253
1254 static void svm_set_segment(struct kvm_vcpu *vcpu,
1255 struct kvm_segment *var, int seg)
1256 {
1257 struct vcpu_svm *svm = to_svm(vcpu);
1258 struct vmcb_seg *s = svm_seg(vcpu, seg);
1259
1260 s->base = var->base;
1261 s->limit = var->limit;
1262 s->selector = var->selector;
1263 if (var->unusable)
1264 s->attrib = 0;
1265 else {
1266 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1267 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1268 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1269 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1270 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1271 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1272 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1273 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1274 }
1275 if (seg == VCPU_SREG_CS)
1276 svm->vmcb->save.cpl
1277 = (svm->vmcb->save.cs.attrib
1278 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1279
1280 }
1281
1282 static void update_db_intercept(struct kvm_vcpu *vcpu)
1283 {
1284 struct vcpu_svm *svm = to_svm(vcpu);
1285
1286 svm->vmcb->control.intercept_exceptions &=
1287 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1288
1289 if (svm->nmi_singlestep)
1290 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1291
1292 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1293 if (vcpu->guest_debug &
1294 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1295 svm->vmcb->control.intercept_exceptions |=
1296 1 << DB_VECTOR;
1297 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1298 svm->vmcb->control.intercept_exceptions |=
1299 1 << BP_VECTOR;
1300 } else
1301 vcpu->guest_debug = 0;
1302 }
1303
1304 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1305 {
1306 struct vcpu_svm *svm = to_svm(vcpu);
1307
1308 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1309 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1310 else
1311 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1312
1313 update_db_intercept(vcpu);
1314 }
1315
1316 static void load_host_msrs(struct kvm_vcpu *vcpu)
1317 {
1318 #ifdef CONFIG_X86_64
1319 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1320 #endif
1321 }
1322
1323 static void save_host_msrs(struct kvm_vcpu *vcpu)
1324 {
1325 #ifdef CONFIG_X86_64
1326 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1327 #endif
1328 }
1329
1330 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1331 {
1332 if (sd->next_asid > sd->max_asid) {
1333 ++sd->asid_generation;
1334 sd->next_asid = 1;
1335 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1336 }
1337
1338 svm->asid_generation = sd->asid_generation;
1339 svm->vmcb->control.asid = sd->next_asid++;
1340 }
1341
1342 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1343 {
1344 struct vcpu_svm *svm = to_svm(vcpu);
1345
1346 svm->vmcb->save.dr7 = value;
1347 }
1348
1349 static int pf_interception(struct vcpu_svm *svm)
1350 {
1351 u64 fault_address;
1352 u32 error_code;
1353
1354 fault_address = svm->vmcb->control.exit_info_2;
1355 error_code = svm->vmcb->control.exit_info_1;
1356
1357 trace_kvm_page_fault(fault_address, error_code);
1358 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1359 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1360 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1361 }
1362
1363 static int db_interception(struct vcpu_svm *svm)
1364 {
1365 struct kvm_run *kvm_run = svm->vcpu.run;
1366
1367 if (!(svm->vcpu.guest_debug &
1368 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1369 !svm->nmi_singlestep) {
1370 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1371 return 1;
1372 }
1373
1374 if (svm->nmi_singlestep) {
1375 svm->nmi_singlestep = false;
1376 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1377 svm->vmcb->save.rflags &=
1378 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1379 update_db_intercept(&svm->vcpu);
1380 }
1381
1382 if (svm->vcpu.guest_debug &
1383 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1384 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1385 kvm_run->debug.arch.pc =
1386 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1387 kvm_run->debug.arch.exception = DB_VECTOR;
1388 return 0;
1389 }
1390
1391 return 1;
1392 }
1393
1394 static int bp_interception(struct vcpu_svm *svm)
1395 {
1396 struct kvm_run *kvm_run = svm->vcpu.run;
1397
1398 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1399 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1400 kvm_run->debug.arch.exception = BP_VECTOR;
1401 return 0;
1402 }
1403
1404 static int ud_interception(struct vcpu_svm *svm)
1405 {
1406 int er;
1407
1408 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1409 if (er != EMULATE_DONE)
1410 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1411 return 1;
1412 }
1413
1414 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1415 {
1416 struct vcpu_svm *svm = to_svm(vcpu);
1417 u32 excp;
1418
1419 if (is_nested(svm)) {
1420 u32 h_excp, n_excp;
1421
1422 h_excp = svm->nested.hsave->control.intercept_exceptions;
1423 n_excp = svm->nested.intercept_exceptions;
1424 h_excp &= ~(1 << NM_VECTOR);
1425 excp = h_excp | n_excp;
1426 } else {
1427 excp = svm->vmcb->control.intercept_exceptions;
1428 excp &= ~(1 << NM_VECTOR);
1429 }
1430
1431 svm->vmcb->control.intercept_exceptions = excp;
1432
1433 svm->vcpu.fpu_active = 1;
1434 update_cr0_intercept(svm);
1435 }
1436
1437 static int nm_interception(struct vcpu_svm *svm)
1438 {
1439 svm_fpu_activate(&svm->vcpu);
1440 return 1;
1441 }
1442
1443 static bool is_erratum_383(void)
1444 {
1445 int err, i;
1446 u64 value;
1447
1448 if (!erratum_383_found)
1449 return false;
1450
1451 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1452 if (err)
1453 return false;
1454
1455 /* Bit 62 may or may not be set for this mce */
1456 value &= ~(1ULL << 62);
1457
1458 if (value != 0xb600000000010015ULL)
1459 return false;
1460
1461 /* Clear MCi_STATUS registers */
1462 for (i = 0; i < 6; ++i)
1463 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1464
1465 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1466 if (!err) {
1467 u32 low, high;
1468
1469 value &= ~(1ULL << 2);
1470 low = lower_32_bits(value);
1471 high = upper_32_bits(value);
1472
1473 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1474 }
1475
1476 /* Flush tlb to evict multi-match entries */
1477 __flush_tlb_all();
1478
1479 return true;
1480 }
1481
1482 static void svm_handle_mce(struct vcpu_svm *svm)
1483 {
1484 if (is_erratum_383()) {
1485 /*
1486 * Erratum 383 triggered. Guest state is corrupt so kill the
1487 * guest.
1488 */
1489 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1490
1491 set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
1492
1493 return;
1494 }
1495
1496 /*
1497 * On an #MC intercept the MCE handler is not called automatically in
1498 * the host. So do it by hand here.
1499 */
1500 asm volatile (
1501 "int $0x12\n");
1502 /* not sure if we ever come back to this point */
1503
1504 return;
1505 }
1506
1507 static int mc_interception(struct vcpu_svm *svm)
1508 {
1509 return 1;
1510 }
1511
1512 static int shutdown_interception(struct vcpu_svm *svm)
1513 {
1514 struct kvm_run *kvm_run = svm->vcpu.run;
1515
1516 /*
1517 * VMCB is undefined after a SHUTDOWN intercept
1518 * so reinitialize it.
1519 */
1520 clear_page(svm->vmcb);
1521 init_vmcb(svm);
1522
1523 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1524 return 0;
1525 }
1526
1527 static int io_interception(struct vcpu_svm *svm)
1528 {
1529 struct kvm_vcpu *vcpu = &svm->vcpu;
1530 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1531 int size, in, string;
1532 unsigned port;
1533
1534 ++svm->vcpu.stat.io_exits;
1535 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1536 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1537 if (string || in)
1538 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1539
1540 port = io_info >> 16;
1541 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1542 svm->next_rip = svm->vmcb->control.exit_info_2;
1543 skip_emulated_instruction(&svm->vcpu);
1544
1545 return kvm_fast_pio_out(vcpu, size, port);
1546 }
1547
1548 static int nmi_interception(struct vcpu_svm *svm)
1549 {
1550 return 1;
1551 }
1552
1553 static int intr_interception(struct vcpu_svm *svm)
1554 {
1555 ++svm->vcpu.stat.irq_exits;
1556 return 1;
1557 }
1558
1559 static int nop_on_interception(struct vcpu_svm *svm)
1560 {
1561 return 1;
1562 }
1563
1564 static int halt_interception(struct vcpu_svm *svm)
1565 {
1566 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1567 skip_emulated_instruction(&svm->vcpu);
1568 return kvm_emulate_halt(&svm->vcpu);
1569 }
1570
1571 static int vmmcall_interception(struct vcpu_svm *svm)
1572 {
1573 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1574 skip_emulated_instruction(&svm->vcpu);
1575 kvm_emulate_hypercall(&svm->vcpu);
1576 return 1;
1577 }
1578
1579 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1580 {
1581 if (!(svm->vcpu.arch.efer & EFER_SVME)
1582 || !is_paging(&svm->vcpu)) {
1583 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1584 return 1;
1585 }
1586
1587 if (svm->vmcb->save.cpl) {
1588 kvm_inject_gp(&svm->vcpu, 0);
1589 return 1;
1590 }
1591
1592 return 0;
1593 }
1594
1595 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1596 bool has_error_code, u32 error_code)
1597 {
1598 int vmexit;
1599
1600 if (!is_nested(svm))
1601 return 0;
1602
1603 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1604 svm->vmcb->control.exit_code_hi = 0;
1605 svm->vmcb->control.exit_info_1 = error_code;
1606 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1607
1608 vmexit = nested_svm_intercept(svm);
1609 if (vmexit == NESTED_EXIT_DONE)
1610 svm->nested.exit_required = true;
1611
1612 return vmexit;
1613 }
1614
1615 /* This function returns true if it is save to enable the irq window */
1616 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1617 {
1618 if (!is_nested(svm))
1619 return true;
1620
1621 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1622 return true;
1623
1624 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1625 return false;
1626
1627 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1628 svm->vmcb->control.exit_info_1 = 0;
1629 svm->vmcb->control.exit_info_2 = 0;
1630
1631 if (svm->nested.intercept & 1ULL) {
1632 /*
1633 * The #vmexit can't be emulated here directly because this
1634 * code path runs with irqs and preemtion disabled. A
1635 * #vmexit emulation might sleep. Only signal request for
1636 * the #vmexit here.
1637 */
1638 svm->nested.exit_required = true;
1639 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1640 return false;
1641 }
1642
1643 return true;
1644 }
1645
1646 /* This function returns true if it is save to enable the nmi window */
1647 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1648 {
1649 if (!is_nested(svm))
1650 return true;
1651
1652 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1653 return true;
1654
1655 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1656 svm->nested.exit_required = true;
1657
1658 return false;
1659 }
1660
1661 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1662 {
1663 struct page *page;
1664
1665 might_sleep();
1666
1667 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1668 if (is_error_page(page))
1669 goto error;
1670
1671 *_page = page;
1672
1673 return kmap(page);
1674
1675 error:
1676 kvm_release_page_clean(page);
1677 kvm_inject_gp(&svm->vcpu, 0);
1678
1679 return NULL;
1680 }
1681
1682 static void nested_svm_unmap(struct page *page)
1683 {
1684 kunmap(page);
1685 kvm_release_page_dirty(page);
1686 }
1687
1688 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1689 {
1690 unsigned port;
1691 u8 val, bit;
1692 u64 gpa;
1693
1694 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1695 return NESTED_EXIT_HOST;
1696
1697 port = svm->vmcb->control.exit_info_1 >> 16;
1698 gpa = svm->nested.vmcb_iopm + (port / 8);
1699 bit = port % 8;
1700 val = 0;
1701
1702 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1703 val &= (1 << bit);
1704
1705 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1706 }
1707
1708 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1709 {
1710 u32 offset, msr, value;
1711 int write, mask;
1712
1713 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1714 return NESTED_EXIT_HOST;
1715
1716 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1717 offset = svm_msrpm_offset(msr);
1718 write = svm->vmcb->control.exit_info_1 & 1;
1719 mask = 1 << ((2 * (msr & 0xf)) + write);
1720
1721 if (offset == MSR_INVALID)
1722 return NESTED_EXIT_DONE;
1723
1724 /* Offset is in 32 bit units but need in 8 bit units */
1725 offset *= 4;
1726
1727 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1728 return NESTED_EXIT_DONE;
1729
1730 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1731 }
1732
1733 static int nested_svm_exit_special(struct vcpu_svm *svm)
1734 {
1735 u32 exit_code = svm->vmcb->control.exit_code;
1736
1737 switch (exit_code) {
1738 case SVM_EXIT_INTR:
1739 case SVM_EXIT_NMI:
1740 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1741 return NESTED_EXIT_HOST;
1742 case SVM_EXIT_NPF:
1743 /* For now we are always handling NPFs when using them */
1744 if (npt_enabled)
1745 return NESTED_EXIT_HOST;
1746 break;
1747 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1748 /* When we're shadowing, trap PFs */
1749 if (!npt_enabled)
1750 return NESTED_EXIT_HOST;
1751 break;
1752 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1753 nm_interception(svm);
1754 break;
1755 default:
1756 break;
1757 }
1758
1759 return NESTED_EXIT_CONTINUE;
1760 }
1761
1762 /*
1763 * If this function returns true, this #vmexit was already handled
1764 */
1765 static int nested_svm_intercept(struct vcpu_svm *svm)
1766 {
1767 u32 exit_code = svm->vmcb->control.exit_code;
1768 int vmexit = NESTED_EXIT_HOST;
1769
1770 switch (exit_code) {
1771 case SVM_EXIT_MSR:
1772 vmexit = nested_svm_exit_handled_msr(svm);
1773 break;
1774 case SVM_EXIT_IOIO:
1775 vmexit = nested_svm_intercept_ioio(svm);
1776 break;
1777 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1778 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1779 if (svm->nested.intercept_cr_read & cr_bits)
1780 vmexit = NESTED_EXIT_DONE;
1781 break;
1782 }
1783 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1784 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1785 if (svm->nested.intercept_cr_write & cr_bits)
1786 vmexit = NESTED_EXIT_DONE;
1787 break;
1788 }
1789 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1790 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1791 if (svm->nested.intercept_dr_read & dr_bits)
1792 vmexit = NESTED_EXIT_DONE;
1793 break;
1794 }
1795 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1796 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1797 if (svm->nested.intercept_dr_write & dr_bits)
1798 vmexit = NESTED_EXIT_DONE;
1799 break;
1800 }
1801 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1802 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1803 if (svm->nested.intercept_exceptions & excp_bits)
1804 vmexit = NESTED_EXIT_DONE;
1805 break;
1806 }
1807 case SVM_EXIT_ERR: {
1808 vmexit = NESTED_EXIT_DONE;
1809 break;
1810 }
1811 default: {
1812 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1813 if (svm->nested.intercept & exit_bits)
1814 vmexit = NESTED_EXIT_DONE;
1815 }
1816 }
1817
1818 return vmexit;
1819 }
1820
1821 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1822 {
1823 int vmexit;
1824
1825 vmexit = nested_svm_intercept(svm);
1826
1827 if (vmexit == NESTED_EXIT_DONE)
1828 nested_svm_vmexit(svm);
1829
1830 return vmexit;
1831 }
1832
1833 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1834 {
1835 struct vmcb_control_area *dst = &dst_vmcb->control;
1836 struct vmcb_control_area *from = &from_vmcb->control;
1837
1838 dst->intercept_cr_read = from->intercept_cr_read;
1839 dst->intercept_cr_write = from->intercept_cr_write;
1840 dst->intercept_dr_read = from->intercept_dr_read;
1841 dst->intercept_dr_write = from->intercept_dr_write;
1842 dst->intercept_exceptions = from->intercept_exceptions;
1843 dst->intercept = from->intercept;
1844 dst->iopm_base_pa = from->iopm_base_pa;
1845 dst->msrpm_base_pa = from->msrpm_base_pa;
1846 dst->tsc_offset = from->tsc_offset;
1847 dst->asid = from->asid;
1848 dst->tlb_ctl = from->tlb_ctl;
1849 dst->int_ctl = from->int_ctl;
1850 dst->int_vector = from->int_vector;
1851 dst->int_state = from->int_state;
1852 dst->exit_code = from->exit_code;
1853 dst->exit_code_hi = from->exit_code_hi;
1854 dst->exit_info_1 = from->exit_info_1;
1855 dst->exit_info_2 = from->exit_info_2;
1856 dst->exit_int_info = from->exit_int_info;
1857 dst->exit_int_info_err = from->exit_int_info_err;
1858 dst->nested_ctl = from->nested_ctl;
1859 dst->event_inj = from->event_inj;
1860 dst->event_inj_err = from->event_inj_err;
1861 dst->nested_cr3 = from->nested_cr3;
1862 dst->lbr_ctl = from->lbr_ctl;
1863 }
1864
1865 static int nested_svm_vmexit(struct vcpu_svm *svm)
1866 {
1867 struct vmcb *nested_vmcb;
1868 struct vmcb *hsave = svm->nested.hsave;
1869 struct vmcb *vmcb = svm->vmcb;
1870 struct page *page;
1871
1872 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1873 vmcb->control.exit_info_1,
1874 vmcb->control.exit_info_2,
1875 vmcb->control.exit_int_info,
1876 vmcb->control.exit_int_info_err);
1877
1878 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1879 if (!nested_vmcb)
1880 return 1;
1881
1882 /* Exit nested SVM mode */
1883 svm->nested.vmcb = 0;
1884
1885 /* Give the current vmcb to the guest */
1886 disable_gif(svm);
1887
1888 nested_vmcb->save.es = vmcb->save.es;
1889 nested_vmcb->save.cs = vmcb->save.cs;
1890 nested_vmcb->save.ss = vmcb->save.ss;
1891 nested_vmcb->save.ds = vmcb->save.ds;
1892 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1893 nested_vmcb->save.idtr = vmcb->save.idtr;
1894 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
1895 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
1896 nested_vmcb->save.cr2 = vmcb->save.cr2;
1897 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
1898 nested_vmcb->save.rflags = vmcb->save.rflags;
1899 nested_vmcb->save.rip = vmcb->save.rip;
1900 nested_vmcb->save.rsp = vmcb->save.rsp;
1901 nested_vmcb->save.rax = vmcb->save.rax;
1902 nested_vmcb->save.dr7 = vmcb->save.dr7;
1903 nested_vmcb->save.dr6 = vmcb->save.dr6;
1904 nested_vmcb->save.cpl = vmcb->save.cpl;
1905
1906 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1907 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1908 nested_vmcb->control.int_state = vmcb->control.int_state;
1909 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1910 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1911 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1912 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1913 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1914 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1915
1916 /*
1917 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1918 * to make sure that we do not lose injected events. So check event_inj
1919 * here and copy it to exit_int_info if it is valid.
1920 * Exit_int_info and event_inj can't be both valid because the case
1921 * below only happens on a VMRUN instruction intercept which has
1922 * no valid exit_int_info set.
1923 */
1924 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1925 struct vmcb_control_area *nc = &nested_vmcb->control;
1926
1927 nc->exit_int_info = vmcb->control.event_inj;
1928 nc->exit_int_info_err = vmcb->control.event_inj_err;
1929 }
1930
1931 nested_vmcb->control.tlb_ctl = 0;
1932 nested_vmcb->control.event_inj = 0;
1933 nested_vmcb->control.event_inj_err = 0;
1934
1935 /* We always set V_INTR_MASKING and remember the old value in hflags */
1936 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1937 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1938
1939 /* Restore the original control entries */
1940 copy_vmcb_control_area(vmcb, hsave);
1941
1942 kvm_clear_exception_queue(&svm->vcpu);
1943 kvm_clear_interrupt_queue(&svm->vcpu);
1944
1945 /* Restore selected save entries */
1946 svm->vmcb->save.es = hsave->save.es;
1947 svm->vmcb->save.cs = hsave->save.cs;
1948 svm->vmcb->save.ss = hsave->save.ss;
1949 svm->vmcb->save.ds = hsave->save.ds;
1950 svm->vmcb->save.gdtr = hsave->save.gdtr;
1951 svm->vmcb->save.idtr = hsave->save.idtr;
1952 svm->vmcb->save.rflags = hsave->save.rflags;
1953 svm_set_efer(&svm->vcpu, hsave->save.efer);
1954 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1955 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1956 if (npt_enabled) {
1957 svm->vmcb->save.cr3 = hsave->save.cr3;
1958 svm->vcpu.arch.cr3 = hsave->save.cr3;
1959 } else {
1960 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1961 }
1962 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1963 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1964 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1965 svm->vmcb->save.dr7 = 0;
1966 svm->vmcb->save.cpl = 0;
1967 svm->vmcb->control.exit_int_info = 0;
1968
1969 nested_svm_unmap(page);
1970
1971 kvm_mmu_reset_context(&svm->vcpu);
1972 kvm_mmu_load(&svm->vcpu);
1973
1974 return 0;
1975 }
1976
1977 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1978 {
1979 /*
1980 * This function merges the msr permission bitmaps of kvm and the
1981 * nested vmcb. It is omptimized in that it only merges the parts where
1982 * the kvm msr permission bitmap may contain zero bits
1983 */
1984 int i;
1985
1986 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1987 return true;
1988
1989 for (i = 0; i < MSRPM_OFFSETS; i++) {
1990 u32 value, p;
1991 u64 offset;
1992
1993 if (msrpm_offsets[i] == 0xffffffff)
1994 break;
1995
1996 p = msrpm_offsets[i];
1997 offset = svm->nested.vmcb_msrpm + (p * 4);
1998
1999 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2000 return false;
2001
2002 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2003 }
2004
2005 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2006
2007 return true;
2008 }
2009
2010 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2011 {
2012 struct vmcb *nested_vmcb;
2013 struct vmcb *hsave = svm->nested.hsave;
2014 struct vmcb *vmcb = svm->vmcb;
2015 struct page *page;
2016 u64 vmcb_gpa;
2017
2018 vmcb_gpa = svm->vmcb->save.rax;
2019
2020 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2021 if (!nested_vmcb)
2022 return false;
2023
2024 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
2025 nested_vmcb->save.rip,
2026 nested_vmcb->control.int_ctl,
2027 nested_vmcb->control.event_inj,
2028 nested_vmcb->control.nested_ctl);
2029
2030 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2031 nested_vmcb->control.intercept_cr_write,
2032 nested_vmcb->control.intercept_exceptions,
2033 nested_vmcb->control.intercept);
2034
2035 /* Clear internal status */
2036 kvm_clear_exception_queue(&svm->vcpu);
2037 kvm_clear_interrupt_queue(&svm->vcpu);
2038
2039 /*
2040 * Save the old vmcb, so we don't need to pick what we save, but can
2041 * restore everything when a VMEXIT occurs
2042 */
2043 hsave->save.es = vmcb->save.es;
2044 hsave->save.cs = vmcb->save.cs;
2045 hsave->save.ss = vmcb->save.ss;
2046 hsave->save.ds = vmcb->save.ds;
2047 hsave->save.gdtr = vmcb->save.gdtr;
2048 hsave->save.idtr = vmcb->save.idtr;
2049 hsave->save.efer = svm->vcpu.arch.efer;
2050 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2051 hsave->save.cr4 = svm->vcpu.arch.cr4;
2052 hsave->save.rflags = vmcb->save.rflags;
2053 hsave->save.rip = svm->next_rip;
2054 hsave->save.rsp = vmcb->save.rsp;
2055 hsave->save.rax = vmcb->save.rax;
2056 if (npt_enabled)
2057 hsave->save.cr3 = vmcb->save.cr3;
2058 else
2059 hsave->save.cr3 = svm->vcpu.arch.cr3;
2060
2061 copy_vmcb_control_area(hsave, vmcb);
2062
2063 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2064 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2065 else
2066 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2067
2068 /* Load the nested guest state */
2069 svm->vmcb->save.es = nested_vmcb->save.es;
2070 svm->vmcb->save.cs = nested_vmcb->save.cs;
2071 svm->vmcb->save.ss = nested_vmcb->save.ss;
2072 svm->vmcb->save.ds = nested_vmcb->save.ds;
2073 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2074 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2075 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2076 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2077 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2078 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2079 if (npt_enabled) {
2080 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2081 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2082 } else
2083 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2084
2085 /* Guest paging mode is active - reset mmu */
2086 kvm_mmu_reset_context(&svm->vcpu);
2087
2088 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2089 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2090 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2091 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2092
2093 /* In case we don't even reach vcpu_run, the fields are not updated */
2094 svm->vmcb->save.rax = nested_vmcb->save.rax;
2095 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2096 svm->vmcb->save.rip = nested_vmcb->save.rip;
2097 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2098 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2099 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2100
2101 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2102 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2103
2104 /* cache intercepts */
2105 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2106 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2107 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2108 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2109 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2110 svm->nested.intercept = nested_vmcb->control.intercept;
2111
2112 force_new_asid(&svm->vcpu);
2113 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2114 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2115 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2116 else
2117 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2118
2119 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2120 /* We only want the cr8 intercept bits of the guest */
2121 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2122 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2123 }
2124
2125 /* We don't want to see VMMCALLs from a nested guest */
2126 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2127
2128 /*
2129 * We don't want a nested guest to be more powerful than the guest, so
2130 * all intercepts are ORed
2131 */
2132 svm->vmcb->control.intercept_cr_read |=
2133 nested_vmcb->control.intercept_cr_read;
2134 svm->vmcb->control.intercept_cr_write |=
2135 nested_vmcb->control.intercept_cr_write;
2136 svm->vmcb->control.intercept_dr_read |=
2137 nested_vmcb->control.intercept_dr_read;
2138 svm->vmcb->control.intercept_dr_write |=
2139 nested_vmcb->control.intercept_dr_write;
2140 svm->vmcb->control.intercept_exceptions |=
2141 nested_vmcb->control.intercept_exceptions;
2142
2143 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2144
2145 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2146 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2147 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2148 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2149 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2150 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2151
2152 nested_svm_unmap(page);
2153
2154 /* nested_vmcb is our indicator if nested SVM is activated */
2155 svm->nested.vmcb = vmcb_gpa;
2156
2157 enable_gif(svm);
2158
2159 return true;
2160 }
2161
2162 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2163 {
2164 to_vmcb->save.fs = from_vmcb->save.fs;
2165 to_vmcb->save.gs = from_vmcb->save.gs;
2166 to_vmcb->save.tr = from_vmcb->save.tr;
2167 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2168 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2169 to_vmcb->save.star = from_vmcb->save.star;
2170 to_vmcb->save.lstar = from_vmcb->save.lstar;
2171 to_vmcb->save.cstar = from_vmcb->save.cstar;
2172 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2173 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2174 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2175 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2176 }
2177
2178 static int vmload_interception(struct vcpu_svm *svm)
2179 {
2180 struct vmcb *nested_vmcb;
2181 struct page *page;
2182
2183 if (nested_svm_check_permissions(svm))
2184 return 1;
2185
2186 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2187 skip_emulated_instruction(&svm->vcpu);
2188
2189 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2190 if (!nested_vmcb)
2191 return 1;
2192
2193 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2194 nested_svm_unmap(page);
2195
2196 return 1;
2197 }
2198
2199 static int vmsave_interception(struct vcpu_svm *svm)
2200 {
2201 struct vmcb *nested_vmcb;
2202 struct page *page;
2203
2204 if (nested_svm_check_permissions(svm))
2205 return 1;
2206
2207 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2208 skip_emulated_instruction(&svm->vcpu);
2209
2210 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2211 if (!nested_vmcb)
2212 return 1;
2213
2214 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2215 nested_svm_unmap(page);
2216
2217 return 1;
2218 }
2219
2220 static int vmrun_interception(struct vcpu_svm *svm)
2221 {
2222 if (nested_svm_check_permissions(svm))
2223 return 1;
2224
2225 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2226 skip_emulated_instruction(&svm->vcpu);
2227
2228 if (!nested_svm_vmrun(svm))
2229 return 1;
2230
2231 if (!nested_svm_vmrun_msrpm(svm))
2232 goto failed;
2233
2234 return 1;
2235
2236 failed:
2237
2238 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2239 svm->vmcb->control.exit_code_hi = 0;
2240 svm->vmcb->control.exit_info_1 = 0;
2241 svm->vmcb->control.exit_info_2 = 0;
2242
2243 nested_svm_vmexit(svm);
2244
2245 return 1;
2246 }
2247
2248 static int stgi_interception(struct vcpu_svm *svm)
2249 {
2250 if (nested_svm_check_permissions(svm))
2251 return 1;
2252
2253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2254 skip_emulated_instruction(&svm->vcpu);
2255
2256 enable_gif(svm);
2257
2258 return 1;
2259 }
2260
2261 static int clgi_interception(struct vcpu_svm *svm)
2262 {
2263 if (nested_svm_check_permissions(svm))
2264 return 1;
2265
2266 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2267 skip_emulated_instruction(&svm->vcpu);
2268
2269 disable_gif(svm);
2270
2271 /* After a CLGI no interrupts should come */
2272 svm_clear_vintr(svm);
2273 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2274
2275 return 1;
2276 }
2277
2278 static int invlpga_interception(struct vcpu_svm *svm)
2279 {
2280 struct kvm_vcpu *vcpu = &svm->vcpu;
2281
2282 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2283 vcpu->arch.regs[VCPU_REGS_RAX]);
2284
2285 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2286 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2287
2288 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2289 skip_emulated_instruction(&svm->vcpu);
2290 return 1;
2291 }
2292
2293 static int skinit_interception(struct vcpu_svm *svm)
2294 {
2295 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2296
2297 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2298 return 1;
2299 }
2300
2301 static int invalid_op_interception(struct vcpu_svm *svm)
2302 {
2303 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2304 return 1;
2305 }
2306
2307 static int task_switch_interception(struct vcpu_svm *svm)
2308 {
2309 u16 tss_selector;
2310 int reason;
2311 int int_type = svm->vmcb->control.exit_int_info &
2312 SVM_EXITINTINFO_TYPE_MASK;
2313 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2314 uint32_t type =
2315 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2316 uint32_t idt_v =
2317 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2318 bool has_error_code = false;
2319 u32 error_code = 0;
2320
2321 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2322
2323 if (svm->vmcb->control.exit_info_2 &
2324 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2325 reason = TASK_SWITCH_IRET;
2326 else if (svm->vmcb->control.exit_info_2 &
2327 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2328 reason = TASK_SWITCH_JMP;
2329 else if (idt_v)
2330 reason = TASK_SWITCH_GATE;
2331 else
2332 reason = TASK_SWITCH_CALL;
2333
2334 if (reason == TASK_SWITCH_GATE) {
2335 switch (type) {
2336 case SVM_EXITINTINFO_TYPE_NMI:
2337 svm->vcpu.arch.nmi_injected = false;
2338 break;
2339 case SVM_EXITINTINFO_TYPE_EXEPT:
2340 if (svm->vmcb->control.exit_info_2 &
2341 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2342 has_error_code = true;
2343 error_code =
2344 (u32)svm->vmcb->control.exit_info_2;
2345 }
2346 kvm_clear_exception_queue(&svm->vcpu);
2347 break;
2348 case SVM_EXITINTINFO_TYPE_INTR:
2349 kvm_clear_interrupt_queue(&svm->vcpu);
2350 break;
2351 default:
2352 break;
2353 }
2354 }
2355
2356 if (reason != TASK_SWITCH_GATE ||
2357 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2358 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2359 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2360 skip_emulated_instruction(&svm->vcpu);
2361
2362 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2363 has_error_code, error_code) == EMULATE_FAIL) {
2364 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2365 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2366 svm->vcpu.run->internal.ndata = 0;
2367 return 0;
2368 }
2369 return 1;
2370 }
2371
2372 static int cpuid_interception(struct vcpu_svm *svm)
2373 {
2374 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2375 kvm_emulate_cpuid(&svm->vcpu);
2376 return 1;
2377 }
2378
2379 static int iret_interception(struct vcpu_svm *svm)
2380 {
2381 ++svm->vcpu.stat.nmi_window_exits;
2382 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2383 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2384 return 1;
2385 }
2386
2387 static int invlpg_interception(struct vcpu_svm *svm)
2388 {
2389 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2390 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2391 return 1;
2392 }
2393
2394 static int emulate_on_interception(struct vcpu_svm *svm)
2395 {
2396 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2397 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2398 return 1;
2399 }
2400
2401 static int cr8_write_interception(struct vcpu_svm *svm)
2402 {
2403 struct kvm_run *kvm_run = svm->vcpu.run;
2404
2405 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2406 /* instruction emulation calls kvm_set_cr8() */
2407 emulate_instruction(&svm->vcpu, 0, 0, 0);
2408 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2409 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2410 return 1;
2411 }
2412 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2413 return 1;
2414 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2415 return 0;
2416 }
2417
2418 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2419 {
2420 struct vcpu_svm *svm = to_svm(vcpu);
2421
2422 switch (ecx) {
2423 case MSR_IA32_TSC: {
2424 u64 tsc_offset;
2425
2426 if (is_nested(svm))
2427 tsc_offset = svm->nested.hsave->control.tsc_offset;
2428 else
2429 tsc_offset = svm->vmcb->control.tsc_offset;
2430
2431 *data = tsc_offset + native_read_tsc();
2432 break;
2433 }
2434 case MSR_STAR:
2435 *data = svm->vmcb->save.star;
2436 break;
2437 #ifdef CONFIG_X86_64
2438 case MSR_LSTAR:
2439 *data = svm->vmcb->save.lstar;
2440 break;
2441 case MSR_CSTAR:
2442 *data = svm->vmcb->save.cstar;
2443 break;
2444 case MSR_KERNEL_GS_BASE:
2445 *data = svm->vmcb->save.kernel_gs_base;
2446 break;
2447 case MSR_SYSCALL_MASK:
2448 *data = svm->vmcb->save.sfmask;
2449 break;
2450 #endif
2451 case MSR_IA32_SYSENTER_CS:
2452 *data = svm->vmcb->save.sysenter_cs;
2453 break;
2454 case MSR_IA32_SYSENTER_EIP:
2455 *data = svm->sysenter_eip;
2456 break;
2457 case MSR_IA32_SYSENTER_ESP:
2458 *data = svm->sysenter_esp;
2459 break;
2460 /*
2461 * Nobody will change the following 5 values in the VMCB so we can
2462 * safely return them on rdmsr. They will always be 0 until LBRV is
2463 * implemented.
2464 */
2465 case MSR_IA32_DEBUGCTLMSR:
2466 *data = svm->vmcb->save.dbgctl;
2467 break;
2468 case MSR_IA32_LASTBRANCHFROMIP:
2469 *data = svm->vmcb->save.br_from;
2470 break;
2471 case MSR_IA32_LASTBRANCHTOIP:
2472 *data = svm->vmcb->save.br_to;
2473 break;
2474 case MSR_IA32_LASTINTFROMIP:
2475 *data = svm->vmcb->save.last_excp_from;
2476 break;
2477 case MSR_IA32_LASTINTTOIP:
2478 *data = svm->vmcb->save.last_excp_to;
2479 break;
2480 case MSR_VM_HSAVE_PA:
2481 *data = svm->nested.hsave_msr;
2482 break;
2483 case MSR_VM_CR:
2484 *data = svm->nested.vm_cr_msr;
2485 break;
2486 case MSR_IA32_UCODE_REV:
2487 *data = 0x01000065;
2488 break;
2489 default:
2490 return kvm_get_msr_common(vcpu, ecx, data);
2491 }
2492 return 0;
2493 }
2494
2495 static int rdmsr_interception(struct vcpu_svm *svm)
2496 {
2497 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2498 u64 data;
2499
2500 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2501 trace_kvm_msr_read_ex(ecx);
2502 kvm_inject_gp(&svm->vcpu, 0);
2503 } else {
2504 trace_kvm_msr_read(ecx, data);
2505
2506 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2507 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2508 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2509 skip_emulated_instruction(&svm->vcpu);
2510 }
2511 return 1;
2512 }
2513
2514 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2515 {
2516 struct vcpu_svm *svm = to_svm(vcpu);
2517 int svm_dis, chg_mask;
2518
2519 if (data & ~SVM_VM_CR_VALID_MASK)
2520 return 1;
2521
2522 chg_mask = SVM_VM_CR_VALID_MASK;
2523
2524 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2525 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2526
2527 svm->nested.vm_cr_msr &= ~chg_mask;
2528 svm->nested.vm_cr_msr |= (data & chg_mask);
2529
2530 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2531
2532 /* check for svm_disable while efer.svme is set */
2533 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2534 return 1;
2535
2536 return 0;
2537 }
2538
2539 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2540 {
2541 struct vcpu_svm *svm = to_svm(vcpu);
2542
2543 switch (ecx) {
2544 case MSR_IA32_TSC: {
2545 u64 tsc_offset = data - native_read_tsc();
2546 u64 g_tsc_offset = 0;
2547
2548 if (is_nested(svm)) {
2549 g_tsc_offset = svm->vmcb->control.tsc_offset -
2550 svm->nested.hsave->control.tsc_offset;
2551 svm->nested.hsave->control.tsc_offset = tsc_offset;
2552 }
2553
2554 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2555
2556 break;
2557 }
2558 case MSR_STAR:
2559 svm->vmcb->save.star = data;
2560 break;
2561 #ifdef CONFIG_X86_64
2562 case MSR_LSTAR:
2563 svm->vmcb->save.lstar = data;
2564 break;
2565 case MSR_CSTAR:
2566 svm->vmcb->save.cstar = data;
2567 break;
2568 case MSR_KERNEL_GS_BASE:
2569 svm->vmcb->save.kernel_gs_base = data;
2570 break;
2571 case MSR_SYSCALL_MASK:
2572 svm->vmcb->save.sfmask = data;
2573 break;
2574 #endif
2575 case MSR_IA32_SYSENTER_CS:
2576 svm->vmcb->save.sysenter_cs = data;
2577 break;
2578 case MSR_IA32_SYSENTER_EIP:
2579 svm->sysenter_eip = data;
2580 svm->vmcb->save.sysenter_eip = data;
2581 break;
2582 case MSR_IA32_SYSENTER_ESP:
2583 svm->sysenter_esp = data;
2584 svm->vmcb->save.sysenter_esp = data;
2585 break;
2586 case MSR_IA32_DEBUGCTLMSR:
2587 if (!svm_has(SVM_FEATURE_LBRV)) {
2588 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2589 __func__, data);
2590 break;
2591 }
2592 if (data & DEBUGCTL_RESERVED_BITS)
2593 return 1;
2594
2595 svm->vmcb->save.dbgctl = data;
2596 if (data & (1ULL<<0))
2597 svm_enable_lbrv(svm);
2598 else
2599 svm_disable_lbrv(svm);
2600 break;
2601 case MSR_VM_HSAVE_PA:
2602 svm->nested.hsave_msr = data;
2603 break;
2604 case MSR_VM_CR:
2605 return svm_set_vm_cr(vcpu, data);
2606 case MSR_VM_IGNNE:
2607 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2608 break;
2609 default:
2610 return kvm_set_msr_common(vcpu, ecx, data);
2611 }
2612 return 0;
2613 }
2614
2615 static int wrmsr_interception(struct vcpu_svm *svm)
2616 {
2617 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2618 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2619 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2620
2621
2622 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2623 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2624 trace_kvm_msr_write_ex(ecx, data);
2625 kvm_inject_gp(&svm->vcpu, 0);
2626 } else {
2627 trace_kvm_msr_write(ecx, data);
2628 skip_emulated_instruction(&svm->vcpu);
2629 }
2630 return 1;
2631 }
2632
2633 static int msr_interception(struct vcpu_svm *svm)
2634 {
2635 if (svm->vmcb->control.exit_info_1)
2636 return wrmsr_interception(svm);
2637 else
2638 return rdmsr_interception(svm);
2639 }
2640
2641 static int interrupt_window_interception(struct vcpu_svm *svm)
2642 {
2643 struct kvm_run *kvm_run = svm->vcpu.run;
2644
2645 svm_clear_vintr(svm);
2646 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2647 /*
2648 * If the user space waits to inject interrupts, exit as soon as
2649 * possible
2650 */
2651 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2652 kvm_run->request_interrupt_window &&
2653 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2654 ++svm->vcpu.stat.irq_window_exits;
2655 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2656 return 0;
2657 }
2658
2659 return 1;
2660 }
2661
2662 static int pause_interception(struct vcpu_svm *svm)
2663 {
2664 kvm_vcpu_on_spin(&(svm->vcpu));
2665 return 1;
2666 }
2667
2668 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2669 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2670 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2671 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2672 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2673 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2674 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2675 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2676 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2677 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2678 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2679 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2680 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2681 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2682 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2683 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2684 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2685 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2686 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2687 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2688 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2689 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2690 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2691 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2692 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2693 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2694 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2695 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2696 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2697 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2698 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2699 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2700 [SVM_EXIT_INTR] = intr_interception,
2701 [SVM_EXIT_NMI] = nmi_interception,
2702 [SVM_EXIT_SMI] = nop_on_interception,
2703 [SVM_EXIT_INIT] = nop_on_interception,
2704 [SVM_EXIT_VINTR] = interrupt_window_interception,
2705 [SVM_EXIT_CPUID] = cpuid_interception,
2706 [SVM_EXIT_IRET] = iret_interception,
2707 [SVM_EXIT_INVD] = emulate_on_interception,
2708 [SVM_EXIT_PAUSE] = pause_interception,
2709 [SVM_EXIT_HLT] = halt_interception,
2710 [SVM_EXIT_INVLPG] = invlpg_interception,
2711 [SVM_EXIT_INVLPGA] = invlpga_interception,
2712 [SVM_EXIT_IOIO] = io_interception,
2713 [SVM_EXIT_MSR] = msr_interception,
2714 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2715 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2716 [SVM_EXIT_VMRUN] = vmrun_interception,
2717 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2718 [SVM_EXIT_VMLOAD] = vmload_interception,
2719 [SVM_EXIT_VMSAVE] = vmsave_interception,
2720 [SVM_EXIT_STGI] = stgi_interception,
2721 [SVM_EXIT_CLGI] = clgi_interception,
2722 [SVM_EXIT_SKINIT] = skinit_interception,
2723 [SVM_EXIT_WBINVD] = emulate_on_interception,
2724 [SVM_EXIT_MONITOR] = invalid_op_interception,
2725 [SVM_EXIT_MWAIT] = invalid_op_interception,
2726 [SVM_EXIT_NPF] = pf_interception,
2727 };
2728
2729 static int handle_exit(struct kvm_vcpu *vcpu)
2730 {
2731 struct vcpu_svm *svm = to_svm(vcpu);
2732 struct kvm_run *kvm_run = vcpu->run;
2733 u32 exit_code = svm->vmcb->control.exit_code;
2734
2735 trace_kvm_exit(exit_code, vcpu);
2736
2737 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2738 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2739 if (npt_enabled)
2740 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2741
2742 if (unlikely(svm->nested.exit_required)) {
2743 nested_svm_vmexit(svm);
2744 svm->nested.exit_required = false;
2745
2746 return 1;
2747 }
2748
2749 if (is_nested(svm)) {
2750 int vmexit;
2751
2752 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2753 svm->vmcb->control.exit_info_1,
2754 svm->vmcb->control.exit_info_2,
2755 svm->vmcb->control.exit_int_info,
2756 svm->vmcb->control.exit_int_info_err);
2757
2758 vmexit = nested_svm_exit_special(svm);
2759
2760 if (vmexit == NESTED_EXIT_CONTINUE)
2761 vmexit = nested_svm_exit_handled(svm);
2762
2763 if (vmexit == NESTED_EXIT_DONE)
2764 return 1;
2765 }
2766
2767 svm_complete_interrupts(svm);
2768
2769 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2770 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2771 kvm_run->fail_entry.hardware_entry_failure_reason
2772 = svm->vmcb->control.exit_code;
2773 return 0;
2774 }
2775
2776 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2777 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2778 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2779 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2780 "exit_code 0x%x\n",
2781 __func__, svm->vmcb->control.exit_int_info,
2782 exit_code);
2783
2784 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2785 || !svm_exit_handlers[exit_code]) {
2786 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2787 kvm_run->hw.hardware_exit_reason = exit_code;
2788 return 0;
2789 }
2790
2791 return svm_exit_handlers[exit_code](svm);
2792 }
2793
2794 static void reload_tss(struct kvm_vcpu *vcpu)
2795 {
2796 int cpu = raw_smp_processor_id();
2797
2798 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2799 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2800 load_TR_desc();
2801 }
2802
2803 static void pre_svm_run(struct vcpu_svm *svm)
2804 {
2805 int cpu = raw_smp_processor_id();
2806
2807 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2808
2809 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2810 /* FIXME: handle wraparound of asid_generation */
2811 if (svm->asid_generation != sd->asid_generation)
2812 new_asid(svm, sd);
2813 }
2814
2815 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2816 {
2817 struct vcpu_svm *svm = to_svm(vcpu);
2818
2819 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2820 vcpu->arch.hflags |= HF_NMI_MASK;
2821 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2822 ++vcpu->stat.nmi_injections;
2823 }
2824
2825 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2826 {
2827 struct vmcb_control_area *control;
2828
2829 trace_kvm_inj_virq(irq);
2830
2831 ++svm->vcpu.stat.irq_injections;
2832 control = &svm->vmcb->control;
2833 control->int_vector = irq;
2834 control->int_ctl &= ~V_INTR_PRIO_MASK;
2835 control->int_ctl |= V_IRQ_MASK |
2836 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2837 }
2838
2839 static void svm_set_irq(struct kvm_vcpu *vcpu)
2840 {
2841 struct vcpu_svm *svm = to_svm(vcpu);
2842
2843 BUG_ON(!(gif_set(svm)));
2844
2845 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2846 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2847 }
2848
2849 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2850 {
2851 struct vcpu_svm *svm = to_svm(vcpu);
2852
2853 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2854 return;
2855
2856 if (irr == -1)
2857 return;
2858
2859 if (tpr >= irr)
2860 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2861 }
2862
2863 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2864 {
2865 struct vcpu_svm *svm = to_svm(vcpu);
2866 struct vmcb *vmcb = svm->vmcb;
2867 int ret;
2868 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2869 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2870 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2871
2872 return ret;
2873 }
2874
2875 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2876 {
2877 struct vcpu_svm *svm = to_svm(vcpu);
2878
2879 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2880 }
2881
2882 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2883 {
2884 struct vcpu_svm *svm = to_svm(vcpu);
2885
2886 if (masked) {
2887 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2888 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2889 } else {
2890 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2891 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2892 }
2893 }
2894
2895 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2896 {
2897 struct vcpu_svm *svm = to_svm(vcpu);
2898 struct vmcb *vmcb = svm->vmcb;
2899 int ret;
2900
2901 if (!gif_set(svm) ||
2902 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2903 return 0;
2904
2905 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2906
2907 if (is_nested(svm))
2908 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2909
2910 return ret;
2911 }
2912
2913 static void enable_irq_window(struct kvm_vcpu *vcpu)
2914 {
2915 struct vcpu_svm *svm = to_svm(vcpu);
2916
2917 /*
2918 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2919 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2920 * get that intercept, this function will be called again though and
2921 * we'll get the vintr intercept.
2922 */
2923 if (gif_set(svm) && nested_svm_intr(svm)) {
2924 svm_set_vintr(svm);
2925 svm_inject_irq(svm, 0x0);
2926 }
2927 }
2928
2929 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2930 {
2931 struct vcpu_svm *svm = to_svm(vcpu);
2932
2933 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2934 == HF_NMI_MASK)
2935 return; /* IRET will cause a vm exit */
2936
2937 /*
2938 * Something prevents NMI from been injected. Single step over possible
2939 * problem (IRET or exception injection or interrupt shadow)
2940 */
2941 svm->nmi_singlestep = true;
2942 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2943 update_db_intercept(vcpu);
2944 }
2945
2946 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2947 {
2948 return 0;
2949 }
2950
2951 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2952 {
2953 force_new_asid(vcpu);
2954 }
2955
2956 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2957 {
2958 }
2959
2960 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2961 {
2962 struct vcpu_svm *svm = to_svm(vcpu);
2963
2964 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2965 return;
2966
2967 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2968 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2969 kvm_set_cr8(vcpu, cr8);
2970 }
2971 }
2972
2973 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2974 {
2975 struct vcpu_svm *svm = to_svm(vcpu);
2976 u64 cr8;
2977
2978 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2979 return;
2980
2981 cr8 = kvm_get_cr8(vcpu);
2982 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2983 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2984 }
2985
2986 static void svm_complete_interrupts(struct vcpu_svm *svm)
2987 {
2988 u8 vector;
2989 int type;
2990 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2991 unsigned int3_injected = svm->int3_injected;
2992
2993 svm->int3_injected = 0;
2994
2995 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2996 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2997
2998 svm->vcpu.arch.nmi_injected = false;
2999 kvm_clear_exception_queue(&svm->vcpu);
3000 kvm_clear_interrupt_queue(&svm->vcpu);
3001
3002 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3003 return;
3004
3005 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3006 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3007
3008 switch (type) {
3009 case SVM_EXITINTINFO_TYPE_NMI:
3010 svm->vcpu.arch.nmi_injected = true;
3011 break;
3012 case SVM_EXITINTINFO_TYPE_EXEPT:
3013 /*
3014 * In case of software exceptions, do not reinject the vector,
3015 * but re-execute the instruction instead. Rewind RIP first
3016 * if we emulated INT3 before.
3017 */
3018 if (kvm_exception_is_soft(vector)) {
3019 if (vector == BP_VECTOR && int3_injected &&
3020 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3021 kvm_rip_write(&svm->vcpu,
3022 kvm_rip_read(&svm->vcpu) -
3023 int3_injected);
3024 break;
3025 }
3026 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3027 u32 err = svm->vmcb->control.exit_int_info_err;
3028 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3029
3030 } else
3031 kvm_requeue_exception(&svm->vcpu, vector);
3032 break;
3033 case SVM_EXITINTINFO_TYPE_INTR:
3034 kvm_queue_interrupt(&svm->vcpu, vector, false);
3035 break;
3036 default:
3037 break;
3038 }
3039 }
3040
3041 #ifdef CONFIG_X86_64
3042 #define R "r"
3043 #else
3044 #define R "e"
3045 #endif
3046
3047 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3048 {
3049 struct vcpu_svm *svm = to_svm(vcpu);
3050 u16 fs_selector;
3051 u16 gs_selector;
3052 u16 ldt_selector;
3053
3054 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3055 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3056 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3057
3058 /*
3059 * A vmexit emulation is required before the vcpu can be executed
3060 * again.
3061 */
3062 if (unlikely(svm->nested.exit_required))
3063 return;
3064
3065 pre_svm_run(svm);
3066
3067 sync_lapic_to_cr8(vcpu);
3068
3069 save_host_msrs(vcpu);
3070 fs_selector = kvm_read_fs();
3071 gs_selector = kvm_read_gs();
3072 ldt_selector = kvm_read_ldt();
3073 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3074 /* required for live migration with NPT */
3075 if (npt_enabled)
3076 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3077
3078 clgi();
3079
3080 local_irq_enable();
3081
3082 asm volatile (
3083 "push %%"R"bp; \n\t"
3084 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3085 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3086 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3087 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3088 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3089 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3090 #ifdef CONFIG_X86_64
3091 "mov %c[r8](%[svm]), %%r8 \n\t"
3092 "mov %c[r9](%[svm]), %%r9 \n\t"
3093 "mov %c[r10](%[svm]), %%r10 \n\t"
3094 "mov %c[r11](%[svm]), %%r11 \n\t"
3095 "mov %c[r12](%[svm]), %%r12 \n\t"
3096 "mov %c[r13](%[svm]), %%r13 \n\t"
3097 "mov %c[r14](%[svm]), %%r14 \n\t"
3098 "mov %c[r15](%[svm]), %%r15 \n\t"
3099 #endif
3100
3101 /* Enter guest mode */
3102 "push %%"R"ax \n\t"
3103 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3104 __ex(SVM_VMLOAD) "\n\t"
3105 __ex(SVM_VMRUN) "\n\t"
3106 __ex(SVM_VMSAVE) "\n\t"
3107 "pop %%"R"ax \n\t"
3108
3109 /* Save guest registers, load host registers */
3110 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3111 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3112 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3113 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3114 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3115 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3116 #ifdef CONFIG_X86_64
3117 "mov %%r8, %c[r8](%[svm]) \n\t"
3118 "mov %%r9, %c[r9](%[svm]) \n\t"
3119 "mov %%r10, %c[r10](%[svm]) \n\t"
3120 "mov %%r11, %c[r11](%[svm]) \n\t"
3121 "mov %%r12, %c[r12](%[svm]) \n\t"
3122 "mov %%r13, %c[r13](%[svm]) \n\t"
3123 "mov %%r14, %c[r14](%[svm]) \n\t"
3124 "mov %%r15, %c[r15](%[svm]) \n\t"
3125 #endif
3126 "pop %%"R"bp"
3127 :
3128 : [svm]"a"(svm),
3129 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3130 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3131 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3132 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3133 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3134 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3135 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3136 #ifdef CONFIG_X86_64
3137 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3138 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3139 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3140 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3141 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3142 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3143 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3144 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3145 #endif
3146 : "cc", "memory"
3147 , R"bx", R"cx", R"dx", R"si", R"di"
3148 #ifdef CONFIG_X86_64
3149 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3150 #endif
3151 );
3152
3153 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3154 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3155 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3156 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3157
3158 kvm_load_fs(fs_selector);
3159 kvm_load_gs(gs_selector);
3160 kvm_load_ldt(ldt_selector);
3161 load_host_msrs(vcpu);
3162
3163 reload_tss(vcpu);
3164
3165 local_irq_disable();
3166
3167 stgi();
3168
3169 sync_cr8_to_lapic(vcpu);
3170
3171 svm->next_rip = 0;
3172
3173 if (npt_enabled) {
3174 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3175 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3176 }
3177
3178 /*
3179 * We need to handle MC intercepts here before the vcpu has a chance to
3180 * change the physical cpu
3181 */
3182 if (unlikely(svm->vmcb->control.exit_code ==
3183 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3184 svm_handle_mce(svm);
3185 }
3186
3187 #undef R
3188
3189 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3190 {
3191 struct vcpu_svm *svm = to_svm(vcpu);
3192
3193 if (npt_enabled) {
3194 svm->vmcb->control.nested_cr3 = root;
3195 force_new_asid(vcpu);
3196 return;
3197 }
3198
3199 svm->vmcb->save.cr3 = root;
3200 force_new_asid(vcpu);
3201 }
3202
3203 static int is_disabled(void)
3204 {
3205 u64 vm_cr;
3206
3207 rdmsrl(MSR_VM_CR, vm_cr);
3208 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3209 return 1;
3210
3211 return 0;
3212 }
3213
3214 static void
3215 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3216 {
3217 /*
3218 * Patch in the VMMCALL instruction:
3219 */
3220 hypercall[0] = 0x0f;
3221 hypercall[1] = 0x01;
3222 hypercall[2] = 0xd9;
3223 }
3224
3225 static void svm_check_processor_compat(void *rtn)
3226 {
3227 *(int *)rtn = 0;
3228 }
3229
3230 static bool svm_cpu_has_accelerated_tpr(void)
3231 {
3232 return false;
3233 }
3234
3235 static int get_npt_level(void)
3236 {
3237 #ifdef CONFIG_X86_64
3238 return PT64_ROOT_LEVEL;
3239 #else
3240 return PT32E_ROOT_LEVEL;
3241 #endif
3242 }
3243
3244 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3245 {
3246 return 0;
3247 }
3248
3249 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3250 {
3251 }
3252
3253 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3254 {
3255 switch (func) {
3256 case 0x8000000A:
3257 entry->eax = 1; /* SVM revision 1 */
3258 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3259 ASID emulation to nested SVM */
3260 entry->ecx = 0; /* Reserved */
3261 entry->edx = 0; /* Do not support any additional features */
3262
3263 break;
3264 }
3265 }
3266
3267 static const struct trace_print_flags svm_exit_reasons_str[] = {
3268 { SVM_EXIT_READ_CR0, "read_cr0" },
3269 { SVM_EXIT_READ_CR3, "read_cr3" },
3270 { SVM_EXIT_READ_CR4, "read_cr4" },
3271 { SVM_EXIT_READ_CR8, "read_cr8" },
3272 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3273 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3274 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3275 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3276 { SVM_EXIT_READ_DR0, "read_dr0" },
3277 { SVM_EXIT_READ_DR1, "read_dr1" },
3278 { SVM_EXIT_READ_DR2, "read_dr2" },
3279 { SVM_EXIT_READ_DR3, "read_dr3" },
3280 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3281 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3282 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3283 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3284 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3285 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3286 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3287 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3288 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3289 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3290 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3291 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3292 { SVM_EXIT_INTR, "interrupt" },
3293 { SVM_EXIT_NMI, "nmi" },
3294 { SVM_EXIT_SMI, "smi" },
3295 { SVM_EXIT_INIT, "init" },
3296 { SVM_EXIT_VINTR, "vintr" },
3297 { SVM_EXIT_CPUID, "cpuid" },
3298 { SVM_EXIT_INVD, "invd" },
3299 { SVM_EXIT_HLT, "hlt" },
3300 { SVM_EXIT_INVLPG, "invlpg" },
3301 { SVM_EXIT_INVLPGA, "invlpga" },
3302 { SVM_EXIT_IOIO, "io" },
3303 { SVM_EXIT_MSR, "msr" },
3304 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3305 { SVM_EXIT_SHUTDOWN, "shutdown" },
3306 { SVM_EXIT_VMRUN, "vmrun" },
3307 { SVM_EXIT_VMMCALL, "hypercall" },
3308 { SVM_EXIT_VMLOAD, "vmload" },
3309 { SVM_EXIT_VMSAVE, "vmsave" },
3310 { SVM_EXIT_STGI, "stgi" },
3311 { SVM_EXIT_CLGI, "clgi" },
3312 { SVM_EXIT_SKINIT, "skinit" },
3313 { SVM_EXIT_WBINVD, "wbinvd" },
3314 { SVM_EXIT_MONITOR, "monitor" },
3315 { SVM_EXIT_MWAIT, "mwait" },
3316 { SVM_EXIT_NPF, "npf" },
3317 { -1, NULL }
3318 };
3319
3320 static int svm_get_lpage_level(void)
3321 {
3322 return PT_PDPE_LEVEL;
3323 }
3324
3325 static bool svm_rdtscp_supported(void)
3326 {
3327 return false;
3328 }
3329
3330 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3331 {
3332 struct vcpu_svm *svm = to_svm(vcpu);
3333
3334 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3335 if (is_nested(svm))
3336 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3337 update_cr0_intercept(svm);
3338 }
3339
3340 static struct kvm_x86_ops svm_x86_ops = {
3341 .cpu_has_kvm_support = has_svm,
3342 .disabled_by_bios = is_disabled,
3343 .hardware_setup = svm_hardware_setup,
3344 .hardware_unsetup = svm_hardware_unsetup,
3345 .check_processor_compatibility = svm_check_processor_compat,
3346 .hardware_enable = svm_hardware_enable,
3347 .hardware_disable = svm_hardware_disable,
3348 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3349
3350 .vcpu_create = svm_create_vcpu,
3351 .vcpu_free = svm_free_vcpu,
3352 .vcpu_reset = svm_vcpu_reset,
3353
3354 .prepare_guest_switch = svm_prepare_guest_switch,
3355 .vcpu_load = svm_vcpu_load,
3356 .vcpu_put = svm_vcpu_put,
3357
3358 .set_guest_debug = svm_guest_debug,
3359 .get_msr = svm_get_msr,
3360 .set_msr = svm_set_msr,
3361 .get_segment_base = svm_get_segment_base,
3362 .get_segment = svm_get_segment,
3363 .set_segment = svm_set_segment,
3364 .get_cpl = svm_get_cpl,
3365 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3366 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3367 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3368 .set_cr0 = svm_set_cr0,
3369 .set_cr3 = svm_set_cr3,
3370 .set_cr4 = svm_set_cr4,
3371 .set_efer = svm_set_efer,
3372 .get_idt = svm_get_idt,
3373 .set_idt = svm_set_idt,
3374 .get_gdt = svm_get_gdt,
3375 .set_gdt = svm_set_gdt,
3376 .set_dr7 = svm_set_dr7,
3377 .cache_reg = svm_cache_reg,
3378 .get_rflags = svm_get_rflags,
3379 .set_rflags = svm_set_rflags,
3380 .fpu_activate = svm_fpu_activate,
3381 .fpu_deactivate = svm_fpu_deactivate,
3382
3383 .tlb_flush = svm_flush_tlb,
3384
3385 .run = svm_vcpu_run,
3386 .handle_exit = handle_exit,
3387 .skip_emulated_instruction = skip_emulated_instruction,
3388 .set_interrupt_shadow = svm_set_interrupt_shadow,
3389 .get_interrupt_shadow = svm_get_interrupt_shadow,
3390 .patch_hypercall = svm_patch_hypercall,
3391 .set_irq = svm_set_irq,
3392 .set_nmi = svm_inject_nmi,
3393 .queue_exception = svm_queue_exception,
3394 .interrupt_allowed = svm_interrupt_allowed,
3395 .nmi_allowed = svm_nmi_allowed,
3396 .get_nmi_mask = svm_get_nmi_mask,
3397 .set_nmi_mask = svm_set_nmi_mask,
3398 .enable_nmi_window = enable_nmi_window,
3399 .enable_irq_window = enable_irq_window,
3400 .update_cr8_intercept = update_cr8_intercept,
3401
3402 .set_tss_addr = svm_set_tss_addr,
3403 .get_tdp_level = get_npt_level,
3404 .get_mt_mask = svm_get_mt_mask,
3405
3406 .exit_reasons_str = svm_exit_reasons_str,
3407 .get_lpage_level = svm_get_lpage_level,
3408
3409 .cpuid_update = svm_cpuid_update,
3410
3411 .rdtscp_supported = svm_rdtscp_supported,
3412
3413 .set_supported_cpuid = svm_set_supported_cpuid,
3414 };
3415
3416 static int __init svm_init(void)
3417 {
3418 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3419 __alignof__(struct vcpu_svm), THIS_MODULE);
3420 }
3421
3422 static void __exit svm_exit(void)
3423 {
3424 kvm_exit();
3425 }
3426
3427 module_init(svm_init)
3428 module_exit(svm_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree