1 #ifndef __X86_64_MMU_CONTEXT_H
2 #define __X86_64_MMU_CONTEXT_H
4 #include <linux/config.h>
6 #include <asm/atomic.h>
7 #include <asm/pgalloc.h>
9 #include <asm/pgtable.h>
10 #include <asm/tlbflush.h>
13 * possibly do the LDT unload here?
15 int init_new_context(struct task_struct
*tsk
, struct mm_struct
*mm
);
16 void destroy_context(struct mm_struct
*mm
);
18 static inline void enter_lazy_tlb(struct mm_struct
*mm
, struct task_struct
*tsk
)
21 if (read_pda(mmu_state
) == TLBSTATE_OK
)
22 write_pda(mmu_state
, TLBSTATE_LAZY
);
26 static inline void load_cr3(pgd_t
*pgd
)
28 asm volatile("movq %0,%%cr3" :: "r" (__pa(pgd
)) : "memory");
31 static inline void switch_mm(struct mm_struct
*prev
, struct mm_struct
*next
,
32 struct task_struct
*tsk
)
34 unsigned cpu
= smp_processor_id();
35 if (likely(prev
!= next
)) {
36 /* stop flush ipis for the previous mm */
37 cpu_clear(cpu
, prev
->cpu_vm_mask
);
39 write_pda(mmu_state
, TLBSTATE_OK
);
40 write_pda(active_mm
, next
);
42 cpu_set(cpu
, next
->cpu_vm_mask
);
45 if (unlikely(next
->context
.ldt
!= prev
->context
.ldt
))
46 load_LDT_nolock(&next
->context
, cpu
);
50 write_pda(mmu_state
, TLBSTATE_OK
);
51 if (read_pda(active_mm
) != next
)
53 if (!cpu_test_and_set(cpu
, next
->cpu_vm_mask
)) {
54 /* We were in lazy tlb mode and leave_mm disabled
55 * tlb flush IPI delivery. We must reload CR3
56 * to make sure to use no freed page tables.
59 load_LDT_nolock(&next
->context
, cpu
);
65 #define deactivate_mm(tsk,mm) do { \
67 asm volatile("movl %0,%%fs"::"r"(0)); \
70 #define activate_mm(prev, next) \
71 switch_mm((prev),(next),NULL)