2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/debugfs.h>
44 #include <linux/mii.h>
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define SKY2_VLAN_TAG_USED 1
54 #define DRV_NAME "sky2"
55 #define DRV_VERSION "1.27"
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
68 /* This is the worst case number of transmit list elements for a single skb:
69 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
70 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
71 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
72 #define TX_MAX_PENDING 4096
73 #define TX_DEF_PENDING 127
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
81 #define SKY2_EEPROM_MAGIC 0x9955aabb
84 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
86 static const u32 default_msg
=
87 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
88 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
91 static int debug
= -1; /* defaults above */
92 module_param(debug
, int, 0);
93 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
95 static int copybreak __read_mostly
= 128;
96 module_param(copybreak
, int, 0);
97 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
99 static int disable_msi
= 0;
100 module_param(disable_msi
, int, 0);
101 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
103 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E01) }, /* SK-9E21M */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4381) }, /* 88E8059 */
148 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
150 /* Avoid conditionals by using array */
151 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
152 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
153 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
155 static void sky2_set_multicast(struct net_device
*dev
);
157 /* Access to PHY via serial interconnect */
158 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
162 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
163 gma_write16(hw
, port
, GM_SMI_CTRL
,
164 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
166 for (i
= 0; i
< PHY_RETRIES
; i
++) {
167 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
171 if (!(ctrl
& GM_SMI_CT_BUSY
))
177 dev_warn(&hw
->pdev
->dev
,"%s: phy write timeout\n", hw
->dev
[port
]->name
);
181 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
185 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
189 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
190 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
192 for (i
= 0; i
< PHY_RETRIES
; i
++) {
193 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
197 if (ctrl
& GM_SMI_CT_RD_VAL
) {
198 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
205 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
208 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
212 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
215 __gm_phy_read(hw
, port
, reg
, &v
);
220 static void sky2_power_on(struct sky2_hw
*hw
)
222 /* switch power to VCC (WA for VAUX problem) */
223 sky2_write8(hw
, B0_POWER_CTRL
,
224 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
226 /* disable Core Clock Division, */
227 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
229 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
230 /* enable bits are inverted */
231 sky2_write8(hw
, B2_Y2_CLK_GATE
,
232 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
233 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
234 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
236 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
238 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
241 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
243 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
244 /* set all bits to 0 except bits 15..12 and 8 */
245 reg
&= P_ASPM_CONTROL_MSK
;
246 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
248 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
249 /* set all bits to 0 except bits 28 & 27 */
250 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
251 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
253 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
255 sky2_write16(hw
, B0_CTST
, Y2_HW_WOL_ON
);
257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg
= sky2_read32(hw
, B2_GP_IO
);
259 reg
|= GLB_GPIO_STAT_RACE_DIS
;
260 sky2_write32(hw
, B2_GP_IO
, reg
);
262 sky2_read32(hw
, B2_GP_IO
);
265 /* Turn on "driver loaded" LED */
266 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_ON
);
269 static void sky2_power_aux(struct sky2_hw
*hw
)
271 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
272 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
274 /* enable bits are inverted */
275 sky2_write8(hw
, B2_Y2_CLK_GATE
,
276 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
277 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
278 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
280 /* switch power to VAUX if supported and PME from D3cold */
281 if ( (sky2_read32(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
282 pci_pme_capable(hw
->pdev
, PCI_D3cold
))
283 sky2_write8(hw
, B0_POWER_CTRL
,
284 (PC_VAUX_ENA
| PC_VCC_ENA
|
285 PC_VAUX_ON
| PC_VCC_OFF
));
287 /* turn off "driver loaded LED" */
288 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_OFF
);
291 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
298 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
299 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
300 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
301 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
303 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
304 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
305 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
308 /* flow control to advertise bits */
309 static const u16 copper_fc_adv
[] = {
311 [FC_TX
] = PHY_M_AN_ASP
,
312 [FC_RX
] = PHY_M_AN_PC
,
313 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
316 /* flow control to advertise bits when using 1000BaseX */
317 static const u16 fiber_fc_adv
[] = {
318 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
319 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
320 [FC_RX
] = PHY_M_P_SYM_MD_X
,
321 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
324 /* flow control to GMA disable bits */
325 static const u16 gm_fc_disable
[] = {
326 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
327 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
328 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
333 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
335 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
336 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
338 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
339 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
340 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
342 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
344 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
346 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
347 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
348 /* set downshift counter to 3x and enable downshift */
349 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
351 /* set master & slave downshift counter to 1x */
352 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
354 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
357 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
358 if (sky2_is_copper(hw
)) {
359 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
360 /* enable automatic crossover */
361 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
363 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
364 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
367 /* Enable Class A driver for FE+ A0 */
368 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
369 spec
|= PHY_M_FESC_SEL_CL_A
;
370 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
373 /* disable energy detect */
374 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
376 /* enable automatic crossover */
377 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
379 /* downshift on PHY 88E1112 and 88E1149 is changed */
380 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
381 (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
382 /* set downshift counter to 3x and enable downshift */
383 ctrl
&= ~PHY_M_PC_DSC_MSK
;
384 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
388 /* workaround for deviation #4.88 (CRC errors) */
389 /* disable Automatic Crossover */
391 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
394 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
396 /* special setup for PHY 88E1112 Fiber */
397 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
398 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
400 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
401 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
402 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
403 ctrl
&= ~PHY_M_MAC_MD_MSK
;
404 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
405 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
407 if (hw
->pmd_type
== 'P') {
408 /* select page 1 to access Fiber registers */
409 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
411 /* for SFP-module set SIGDET polarity to low */
412 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
413 ctrl
|= PHY_M_FIB_SIGD_POL
;
414 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
417 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
425 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) {
426 if (sky2_is_copper(hw
)) {
427 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
428 ct1000
|= PHY_M_1000C_AFD
;
429 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
430 ct1000
|= PHY_M_1000C_AHD
;
431 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
432 adv
|= PHY_M_AN_100_FD
;
433 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
434 adv
|= PHY_M_AN_100_HD
;
435 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
436 adv
|= PHY_M_AN_10_FD
;
437 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
438 adv
|= PHY_M_AN_10_HD
;
440 } else { /* special defines for FIBER (88E1040S only) */
441 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
442 adv
|= PHY_M_AN_1000X_AFD
;
443 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
444 adv
|= PHY_M_AN_1000X_AHD
;
447 /* Restart Auto-negotiation */
448 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
450 /* forced speed/duplex settings */
451 ct1000
= PHY_M_1000C_MSE
;
453 /* Disable auto update for duplex flow control and duplex */
454 reg
|= GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_SPD_DIS
;
456 switch (sky2
->speed
) {
458 ctrl
|= PHY_CT_SP1000
;
459 reg
|= GM_GPCR_SPEED_1000
;
462 ctrl
|= PHY_CT_SP100
;
463 reg
|= GM_GPCR_SPEED_100
;
467 if (sky2
->duplex
== DUPLEX_FULL
) {
468 reg
|= GM_GPCR_DUP_FULL
;
469 ctrl
|= PHY_CT_DUP_MD
;
470 } else if (sky2
->speed
< SPEED_1000
)
471 sky2
->flow_mode
= FC_NONE
;
474 if (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
) {
475 if (sky2_is_copper(hw
))
476 adv
|= copper_fc_adv
[sky2
->flow_mode
];
478 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
480 reg
|= GM_GPCR_AU_FCT_DIS
;
481 reg
|= gm_fc_disable
[sky2
->flow_mode
];
483 /* Forward pause packets to GMAC? */
484 if (sky2
->flow_mode
& FC_RX
)
485 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
487 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
490 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
492 if (hw
->flags
& SKY2_HW_GIGABIT
)
493 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
495 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
496 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
498 /* Setup Phy LED's */
499 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
502 switch (hw
->chip_id
) {
503 case CHIP_ID_YUKON_FE
:
504 /* on 88E3082 these bits are at 11..9 (shifted left) */
505 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
507 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
509 /* delete ACT LED control bits */
510 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
511 /* change ACT LED control to blink mode */
512 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
513 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
516 case CHIP_ID_YUKON_FE_P
:
517 /* Enable Link Partner Next Page */
518 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
519 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
521 /* disable Energy Detect and enable scrambler */
522 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
523 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
525 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
526 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
527 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
528 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
530 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
533 case CHIP_ID_YUKON_XL
:
534 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
536 /* select page 3 to access LED control register */
537 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
539 /* set LED Function Control register */
540 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
541 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
542 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
543 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
544 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
546 /* set Polarity Control register */
547 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
548 (PHY_M_POLC_LS1_P_MIX(4) |
549 PHY_M_POLC_IS0_P_MIX(4) |
550 PHY_M_POLC_LOS_CTRL(2) |
551 PHY_M_POLC_INIT_CTRL(2) |
552 PHY_M_POLC_STA1_CTRL(2) |
553 PHY_M_POLC_STA0_CTRL(2)));
555 /* restore page register */
556 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
559 case CHIP_ID_YUKON_EC_U
:
560 case CHIP_ID_YUKON_EX
:
561 case CHIP_ID_YUKON_SUPR
:
562 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
564 /* select page 3 to access LED control register */
565 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
567 /* set LED Function Control register */
568 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
569 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
570 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
571 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
572 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
574 /* set Blink Rate in LED Timer Control Register */
575 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
576 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
577 /* restore page register */
578 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
582 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
583 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
585 /* turn off the Rx LED (LED_RX) */
586 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
589 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
590 /* apply fixes in PHY AFE */
591 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
593 /* increase differential signal amplitude in 10BASE-T */
594 gm_phy_write(hw
, port
, 0x18, 0xaa99);
595 gm_phy_write(hw
, port
, 0x17, 0x2011);
597 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
598 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
599 gm_phy_write(hw
, port
, 0x18, 0xa204);
600 gm_phy_write(hw
, port
, 0x17, 0x2002);
603 /* set page register to 0 */
604 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
605 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
606 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
607 /* apply workaround for integrated resistors calibration */
608 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
609 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
610 } else if (hw
->chip_id
== CHIP_ID_YUKON_OPT
&& hw
->chip_rev
== 0) {
611 /* apply fixes in PHY AFE */
612 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00ff);
614 /* apply RDAC termination workaround */
615 gm_phy_write(hw
, port
, 24, 0x2800);
616 gm_phy_write(hw
, port
, 23, 0x2001);
618 /* set page register back to 0 */
619 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
620 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
621 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
622 /* no effect on Yukon-XL */
623 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
625 if (!(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) ||
626 sky2
->speed
== SPEED_100
) {
627 /* turn on 100 Mbps LED (LED_LINK100) */
628 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
632 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
636 /* Enable phy interrupt on auto-negotiation complete (or link up) */
637 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
638 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
640 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
643 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
644 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
646 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
650 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
651 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
652 reg1
&= ~phy_power
[port
];
654 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
655 reg1
|= coma_mode
[port
];
657 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
658 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
659 sky2_pci_read32(hw
, PCI_DEV_REG1
);
661 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
662 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
663 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
664 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
667 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
672 /* release GPHY Control reset */
673 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
675 /* release GMAC reset */
676 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
678 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
679 /* select page 2 to access MAC control register */
680 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
682 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
683 /* allow GMII Power Down */
684 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
685 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
687 /* set page register back to 0 */
688 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
691 /* setup General Purpose Control Register */
692 gma_write16(hw
, port
, GM_GP_CTRL
,
693 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
|
694 GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_FCT_DIS
|
697 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
698 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
699 /* select page 2 to access MAC control register */
700 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
702 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
703 /* enable Power Down */
704 ctrl
|= PHY_M_PC_POW_D_ENA
;
705 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
707 /* set page register back to 0 */
708 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
711 /* set IEEE compatible Power Down Mode (dev. #4.99) */
712 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
715 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
716 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
717 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
718 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
719 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
722 /* Force a renegotiation */
723 static void sky2_phy_reinit(struct sky2_port
*sky2
)
725 spin_lock_bh(&sky2
->phy_lock
);
726 sky2_phy_init(sky2
->hw
, sky2
->port
);
727 spin_unlock_bh(&sky2
->phy_lock
);
730 /* Put device in state to listen for Wake On Lan */
731 static void sky2_wol_init(struct sky2_port
*sky2
)
733 struct sky2_hw
*hw
= sky2
->hw
;
734 unsigned port
= sky2
->port
;
735 enum flow_control save_mode
;
738 /* Bring hardware out of reset */
739 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
740 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
742 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
743 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
746 * sky2_reset will re-enable on resume
748 save_mode
= sky2
->flow_mode
;
749 ctrl
= sky2
->advertising
;
751 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
752 sky2
->flow_mode
= FC_NONE
;
754 spin_lock_bh(&sky2
->phy_lock
);
755 sky2_phy_power_up(hw
, port
);
756 sky2_phy_init(hw
, port
);
757 spin_unlock_bh(&sky2
->phy_lock
);
759 sky2
->flow_mode
= save_mode
;
760 sky2
->advertising
= ctrl
;
762 /* Set GMAC to no flow control and auto update for speed/duplex */
763 gma_write16(hw
, port
, GM_GP_CTRL
,
764 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
765 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
767 /* Set WOL address */
768 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
769 sky2
->netdev
->dev_addr
, ETH_ALEN
);
771 /* Turn on appropriate WOL control bits */
772 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
774 if (sky2
->wol
& WAKE_PHY
)
775 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
777 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
779 if (sky2
->wol
& WAKE_MAGIC
)
780 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
782 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;
784 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
785 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
787 /* Disable PiG firmware */
788 sky2_write16(hw
, B0_CTST
, Y2_HW_WOL_OFF
);
791 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
794 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
796 struct net_device
*dev
= hw
->dev
[port
];
798 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
799 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
800 hw
->chip_id
>= CHIP_ID_YUKON_FE_P
) {
801 /* Yukon-Extreme B0 and further Extreme devices */
802 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
803 } else if (dev
->mtu
> ETH_DATA_LEN
) {
804 /* set Tx GMAC FIFO Almost Empty Threshold */
805 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
806 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
808 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
810 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
813 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
815 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
819 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
821 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
822 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
824 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
826 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
827 /* WA DEV_472 -- looks like crossed wires on port 2 */
828 /* clear GMAC 1 Control reset */
829 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
831 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
832 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
833 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
834 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
835 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
838 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
840 /* Enable Transmit FIFO Underrun */
841 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
843 spin_lock_bh(&sky2
->phy_lock
);
844 sky2_phy_power_up(hw
, port
);
845 sky2_phy_init(hw
, port
);
846 spin_unlock_bh(&sky2
->phy_lock
);
849 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
850 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
852 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
853 gma_read16(hw
, port
, i
);
854 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
856 /* transmit control */
857 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
859 /* receive control reg: unicast + multicast + no FCS */
860 gma_write16(hw
, port
, GM_RX_CTRL
,
861 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
863 /* transmit flow control */
864 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
866 /* transmit parameter */
867 gma_write16(hw
, port
, GM_TX_PARAM
,
868 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
869 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
870 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
871 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
873 /* serial mode register */
874 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
875 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
877 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
878 reg
|= GM_SMOD_JUMBO_ENA
;
880 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
882 /* virtual address for data */
883 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
885 /* physical address: used for pause frames */
886 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
888 /* ignore counter overflows */
889 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
890 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
891 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
893 /* Configure Rx MAC FIFO */
894 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
895 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
896 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
897 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
898 rx_reg
|= GMF_RX_OVER_ON
;
900 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
902 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
903 /* Hardware errata - clear flush mask */
904 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
906 /* Flush Rx MAC FIFO on any flow control or error */
907 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
910 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
911 reg
= RX_GMF_FL_THR_DEF
+ 1;
912 /* Another magic mystery workaround from sk98lin */
913 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
914 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
916 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
918 /* Configure Tx MAC FIFO */
919 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
920 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
922 /* On chips without ram buffer, pause is controled by MAC level */
923 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
924 /* Pause threshold is scaled by 8 in bytes */
925 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
926 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
930 sky2_write16(hw
, SK_REG(port
, RX_GMF_UP_THR
), reg
);
931 sky2_write16(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768 / 8);
933 sky2_set_tx_stfwd(hw
, port
);
936 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
937 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
938 /* disable dynamic watermark */
939 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
940 reg
&= ~TX_DYN_WM_ENA
;
941 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
945 /* Assign Ram Buffer allocation to queue */
946 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
950 /* convert from K bytes to qwords used for hw register */
953 end
= start
+ space
- 1;
955 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
956 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
957 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
958 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
959 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
961 if (q
== Q_R1
|| q
== Q_R2
) {
962 u32 tp
= space
- space
/4;
964 /* On receive queue's set the thresholds
965 * give receiver priority when > 3/4 full
966 * send pause when down to 2K
968 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
969 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
972 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
973 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
975 /* Enable store & forward on Tx queue's because
976 * Tx FIFO is only 1K on Yukon
978 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
981 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
982 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
985 /* Setup Bus Memory Interface */
986 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
988 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
989 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
990 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
991 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
994 /* Setup prefetch unit registers. This is the interface between
995 * hardware and driver list elements
997 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
998 dma_addr_t addr
, u32 last
)
1000 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1001 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
1002 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), upper_32_bits(addr
));
1003 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), lower_32_bits(addr
));
1004 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
1005 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
1007 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
1010 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
, u16
*slot
)
1012 struct sky2_tx_le
*le
= sky2
->tx_le
+ *slot
;
1014 *slot
= RING_NEXT(*slot
, sky2
->tx_ring_size
);
1019 static void tx_init(struct sky2_port
*sky2
)
1021 struct sky2_tx_le
*le
;
1023 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1024 sky2
->tx_tcpsum
= 0;
1025 sky2
->tx_last_mss
= 0;
1027 le
= get_tx_le(sky2
, &sky2
->tx_prod
);
1029 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1030 sky2
->tx_last_upper
= 0;
1033 /* Update chip's next pointer */
1034 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1036 /* Make sure write' to descriptors are complete before we tell hardware */
1038 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1040 /* Synchronize I/O on since next processor may write to tail */
1045 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1047 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1048 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1053 static unsigned sky2_get_rx_threshold(struct sky2_port
* sky2
)
1057 /* Space needed for frame data + headers rounded up */
1058 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1060 /* Stopping point for hardware truncation */
1061 return (size
- 8) / sizeof(u32
);
1064 static unsigned sky2_get_rx_data_size(struct sky2_port
* sky2
)
1066 struct rx_ring_info
*re
;
1069 /* Space needed for frame data + headers rounded up */
1070 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1072 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1073 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1075 /* Compute residue after pages */
1076 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1078 /* Optimize to handle small packets and headers */
1079 if (size
< copybreak
)
1081 if (size
< ETH_HLEN
)
1087 /* Build description to hardware for one receive segment */
1088 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1089 dma_addr_t map
, unsigned len
)
1091 struct sky2_rx_le
*le
;
1093 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1094 le
= sky2_next_rx(sky2
);
1095 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1096 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1099 le
= sky2_next_rx(sky2
);
1100 le
->addr
= cpu_to_le32(lower_32_bits(map
));
1101 le
->length
= cpu_to_le16(len
);
1102 le
->opcode
= op
| HW_OWNER
;
1105 /* Build description to hardware for one possibly fragmented skb */
1106 static void sky2_rx_submit(struct sky2_port
*sky2
,
1107 const struct rx_ring_info
*re
)
1111 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1113 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1114 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1118 static int sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1121 struct sk_buff
*skb
= re
->skb
;
1124 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1125 if (pci_dma_mapping_error(pdev
, re
->data_addr
))
1128 pci_unmap_len_set(re
, data_size
, size
);
1130 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1131 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1133 re
->frag_addr
[i
] = pci_map_page(pdev
, frag
->page
,
1136 PCI_DMA_FROMDEVICE
);
1138 if (pci_dma_mapping_error(pdev
, re
->frag_addr
[i
]))
1139 goto map_page_error
;
1145 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1146 skb_shinfo(skb
)->frags
[i
].size
,
1147 PCI_DMA_FROMDEVICE
);
1150 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1151 PCI_DMA_FROMDEVICE
);
1154 if (net_ratelimit())
1155 dev_warn(&pdev
->dev
, "%s: rx mapping error\n",
1160 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1162 struct sk_buff
*skb
= re
->skb
;
1165 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1166 PCI_DMA_FROMDEVICE
);
1168 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1169 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1170 skb_shinfo(skb
)->frags
[i
].size
,
1171 PCI_DMA_FROMDEVICE
);
1174 /* Tell chip where to start receive checksum.
1175 * Actually has two checksums, but set both same to avoid possible byte
1178 static void rx_set_checksum(struct sky2_port
*sky2
)
1180 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1182 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1184 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1186 sky2_write32(sky2
->hw
,
1187 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1188 (sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
)
1189 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1193 * The RX Stop command will not work for Yukon-2 if the BMU does not
1194 * reach the end of packet and since we can't make sure that we have
1195 * incoming data, we must reset the BMU while it is not doing a DMA
1196 * transfer. Since it is possible that the RX path is still active,
1197 * the RX RAM buffer will be stopped first, so any possible incoming
1198 * data will not trigger a DMA. After the RAM buffer is stopped, the
1199 * BMU is polled until any DMA in progress is ended and only then it
1202 static void sky2_rx_stop(struct sky2_port
*sky2
)
1204 struct sky2_hw
*hw
= sky2
->hw
;
1205 unsigned rxq
= rxqaddr
[sky2
->port
];
1208 /* disable the RAM Buffer receive queue */
1209 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1211 for (i
= 0; i
< 0xffff; i
++)
1212 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1213 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1216 netdev_warn(sky2
->netdev
, "receiver stop failed\n");
1218 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1220 /* reset the Rx prefetch unit */
1221 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1225 /* Clean out receive buffer area, assumes receiver hardware stopped */
1226 static void sky2_rx_clean(struct sky2_port
*sky2
)
1230 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1231 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1232 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1235 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1242 /* Basic MII support */
1243 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1245 struct mii_ioctl_data
*data
= if_mii(ifr
);
1246 struct sky2_port
*sky2
= netdev_priv(dev
);
1247 struct sky2_hw
*hw
= sky2
->hw
;
1248 int err
= -EOPNOTSUPP
;
1250 if (!netif_running(dev
))
1251 return -ENODEV
; /* Phy still in reset */
1255 data
->phy_id
= PHY_ADDR_MARV
;
1261 spin_lock_bh(&sky2
->phy_lock
);
1262 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1263 spin_unlock_bh(&sky2
->phy_lock
);
1265 data
->val_out
= val
;
1270 spin_lock_bh(&sky2
->phy_lock
);
1271 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1273 spin_unlock_bh(&sky2
->phy_lock
);
1279 #ifdef SKY2_VLAN_TAG_USED
1280 static void sky2_set_vlan_mode(struct sky2_hw
*hw
, u16 port
, bool onoff
)
1283 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1285 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1288 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1290 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1295 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1297 struct sky2_port
*sky2
= netdev_priv(dev
);
1298 struct sky2_hw
*hw
= sky2
->hw
;
1299 u16 port
= sky2
->port
;
1301 netif_tx_lock_bh(dev
);
1302 napi_disable(&hw
->napi
);
1305 sky2_set_vlan_mode(hw
, port
, grp
!= NULL
);
1307 sky2_read32(hw
, B0_Y2_SP_LISR
);
1308 napi_enable(&hw
->napi
);
1309 netif_tx_unlock_bh(dev
);
1313 /* Amount of required worst case padding in rx buffer */
1314 static inline unsigned sky2_rx_pad(const struct sky2_hw
*hw
)
1316 return (hw
->flags
& SKY2_HW_RAM_BUFFER
) ? 8 : 2;
1320 * Allocate an skb for receiving. If the MTU is large enough
1321 * make the skb non-linear with a fragment list of pages.
1323 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1325 struct sk_buff
*skb
;
1328 skb
= netdev_alloc_skb(sky2
->netdev
,
1329 sky2
->rx_data_size
+ sky2_rx_pad(sky2
->hw
));
1333 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1334 unsigned char *start
;
1336 * Workaround for a bug in FIFO that cause hang
1337 * if the FIFO if the receive buffer is not 64 byte aligned.
1338 * The buffer returned from netdev_alloc_skb is
1339 * aligned except if slab debugging is enabled.
1341 start
= PTR_ALIGN(skb
->data
, 8);
1342 skb_reserve(skb
, start
- skb
->data
);
1344 skb_reserve(skb
, NET_IP_ALIGN
);
1346 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1347 struct page
*page
= alloc_page(GFP_ATOMIC
);
1351 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1361 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1363 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1366 static int sky2_alloc_rx_skbs(struct sky2_port
*sky2
)
1368 struct sky2_hw
*hw
= sky2
->hw
;
1371 sky2
->rx_data_size
= sky2_get_rx_data_size(sky2
);
1374 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1375 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1377 re
->skb
= sky2_rx_alloc(sky2
);
1381 if (sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
)) {
1382 dev_kfree_skb(re
->skb
);
1391 * Setup receiver buffer pool.
1392 * Normal case this ends up creating one list element for skb
1393 * in the receive ring. Worst case if using large MTU and each
1394 * allocation falls on a different 64 bit region, that results
1395 * in 6 list elements per ring entry.
1396 * One element is used for checksum enable/disable, and one
1397 * extra to avoid wrap.
1399 static void sky2_rx_start(struct sky2_port
*sky2
)
1401 struct sky2_hw
*hw
= sky2
->hw
;
1402 struct rx_ring_info
*re
;
1403 unsigned rxq
= rxqaddr
[sky2
->port
];
1406 sky2
->rx_put
= sky2
->rx_next
= 0;
1409 /* On PCI express lowering the watermark gives better performance */
1410 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1411 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1413 /* These chips have no ram buffer?
1414 * MAC Rx RAM Read is controlled by hardware */
1415 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1416 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
||
1417 hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1418 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1420 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1422 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1423 rx_set_checksum(sky2
);
1425 /* submit Rx ring */
1426 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1427 re
= sky2
->rx_ring
+ i
;
1428 sky2_rx_submit(sky2
, re
);
1432 * The receiver hangs if it receives frames larger than the
1433 * packet buffer. As a workaround, truncate oversize frames, but
1434 * the register is limited to 9 bits, so if you do frames > 2052
1435 * you better get the MTU right!
1437 thresh
= sky2_get_rx_threshold(sky2
);
1439 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1441 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1442 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1445 /* Tell chip about available buffers */
1446 sky2_rx_update(sky2
, rxq
);
1448 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
1449 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
1451 * Disable flushing of non ASF packets;
1452 * must be done after initializing the BMUs;
1453 * drivers without ASF support should do this too, otherwise
1454 * it may happen that they cannot run on ASF devices;
1455 * remember that the MAC FIFO isn't reset during initialization.
1457 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_MACSEC_FLUSH_OFF
);
1460 if (hw
->chip_id
>= CHIP_ID_YUKON_SUPR
) {
1461 /* Enable RX Home Address & Routing Header checksum fix */
1462 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_FL_CTRL
),
1463 RX_IPV6_SA_MOB_ENA
| RX_IPV6_DA_MOB_ENA
);
1465 /* Enable TX Home Address & Routing Header checksum fix */
1466 sky2_write32(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_TEST
),
1467 TBMU_TEST_HOME_ADD_FIX_EN
| TBMU_TEST_ROUTING_ADD_FIX_EN
);
1471 static int sky2_alloc_buffers(struct sky2_port
*sky2
)
1473 struct sky2_hw
*hw
= sky2
->hw
;
1475 /* must be power of 2 */
1476 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1477 sky2
->tx_ring_size
*
1478 sizeof(struct sky2_tx_le
),
1483 sky2
->tx_ring
= kcalloc(sky2
->tx_ring_size
, sizeof(struct tx_ring_info
),
1488 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1492 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1494 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1499 return sky2_alloc_rx_skbs(sky2
);
1504 static void sky2_free_buffers(struct sky2_port
*sky2
)
1506 struct sky2_hw
*hw
= sky2
->hw
;
1508 sky2_rx_clean(sky2
);
1511 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1512 sky2
->rx_le
, sky2
->rx_le_map
);
1516 pci_free_consistent(hw
->pdev
,
1517 sky2
->tx_ring_size
* sizeof(struct sky2_tx_le
),
1518 sky2
->tx_le
, sky2
->tx_le_map
);
1521 kfree(sky2
->tx_ring
);
1522 kfree(sky2
->rx_ring
);
1524 sky2
->tx_ring
= NULL
;
1525 sky2
->rx_ring
= NULL
;
1528 static void sky2_hw_up(struct sky2_port
*sky2
)
1530 struct sky2_hw
*hw
= sky2
->hw
;
1531 unsigned port
= sky2
->port
;
1534 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1539 * On dual port PCI-X card, there is an problem where status
1540 * can be received out of order due to split transactions
1542 if (otherdev
&& netif_running(otherdev
) &&
1543 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1546 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1547 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1548 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1551 sky2_mac_init(hw
, port
);
1553 /* Register is number of 4K blocks on internal RAM buffer. */
1554 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1558 netdev_dbg(sky2
->netdev
, "ram buffer %dK\n", ramsize
);
1560 rxspace
= ramsize
/ 2;
1562 rxspace
= 8 + (2*(ramsize
- 16))/3;
1564 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1565 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1567 /* Make sure SyncQ is disabled */
1568 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1572 sky2_qset(hw
, txqaddr
[port
]);
1574 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1575 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1576 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1578 /* Set almost empty threshold */
1579 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1580 hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1581 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1583 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1584 sky2
->tx_ring_size
- 1);
1586 #ifdef SKY2_VLAN_TAG_USED
1587 sky2_set_vlan_mode(hw
, port
, sky2
->vlgrp
!= NULL
);
1590 sky2_rx_start(sky2
);
1593 /* Bring up network interface. */
1594 static int sky2_up(struct net_device
*dev
)
1596 struct sky2_port
*sky2
= netdev_priv(dev
);
1597 struct sky2_hw
*hw
= sky2
->hw
;
1598 unsigned port
= sky2
->port
;
1602 netif_carrier_off(dev
);
1604 err
= sky2_alloc_buffers(sky2
);
1610 /* Enable interrupts from phy/mac for port */
1611 imask
= sky2_read32(hw
, B0_IMSK
);
1612 imask
|= portirq_msk
[port
];
1613 sky2_write32(hw
, B0_IMSK
, imask
);
1614 sky2_read32(hw
, B0_IMSK
);
1616 netif_info(sky2
, ifup
, dev
, "enabling interface\n");
1621 sky2_free_buffers(sky2
);
1625 /* Modular subtraction in ring */
1626 static inline int tx_inuse(const struct sky2_port
*sky2
)
1628 return (sky2
->tx_prod
- sky2
->tx_cons
) & (sky2
->tx_ring_size
- 1);
1631 /* Number of list elements available for next tx */
1632 static inline int tx_avail(const struct sky2_port
*sky2
)
1634 return sky2
->tx_pending
- tx_inuse(sky2
);
1637 /* Estimate of number of transmit list elements required */
1638 static unsigned tx_le_req(const struct sk_buff
*skb
)
1642 count
= (skb_shinfo(skb
)->nr_frags
+ 1)
1643 * (sizeof(dma_addr_t
) / sizeof(u32
));
1645 if (skb_is_gso(skb
))
1647 else if (sizeof(dma_addr_t
) == sizeof(u32
))
1648 ++count
; /* possible vlan */
1650 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1656 static void sky2_tx_unmap(struct pci_dev
*pdev
, struct tx_ring_info
*re
)
1658 if (re
->flags
& TX_MAP_SINGLE
)
1659 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1660 pci_unmap_len(re
, maplen
),
1662 else if (re
->flags
& TX_MAP_PAGE
)
1663 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1664 pci_unmap_len(re
, maplen
),
1670 * Put one packet in ring for transmit.
1671 * A single packet can generate multiple list elements, and
1672 * the number of ring elements will probably be less than the number
1673 * of list elements used.
1675 static netdev_tx_t
sky2_xmit_frame(struct sk_buff
*skb
,
1676 struct net_device
*dev
)
1678 struct sky2_port
*sky2
= netdev_priv(dev
);
1679 struct sky2_hw
*hw
= sky2
->hw
;
1680 struct sky2_tx_le
*le
= NULL
;
1681 struct tx_ring_info
*re
;
1689 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1690 return NETDEV_TX_BUSY
;
1692 len
= skb_headlen(skb
);
1693 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1695 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1698 slot
= sky2
->tx_prod
;
1699 netif_printk(sky2
, tx_queued
, KERN_DEBUG
, dev
,
1700 "tx queued, slot %u, len %d\n", slot
, skb
->len
);
1702 /* Send high bits if needed */
1703 upper
= upper_32_bits(mapping
);
1704 if (upper
!= sky2
->tx_last_upper
) {
1705 le
= get_tx_le(sky2
, &slot
);
1706 le
->addr
= cpu_to_le32(upper
);
1707 sky2
->tx_last_upper
= upper
;
1708 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1711 /* Check for TCP Segmentation Offload */
1712 mss
= skb_shinfo(skb
)->gso_size
;
1715 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1716 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1718 if (mss
!= sky2
->tx_last_mss
) {
1719 le
= get_tx_le(sky2
, &slot
);
1720 le
->addr
= cpu_to_le32(mss
);
1722 if (hw
->flags
& SKY2_HW_NEW_LE
)
1723 le
->opcode
= OP_MSS
| HW_OWNER
;
1725 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1726 sky2
->tx_last_mss
= mss
;
1731 #ifdef SKY2_VLAN_TAG_USED
1732 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1733 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1735 le
= get_tx_le(sky2
, &slot
);
1737 le
->opcode
= OP_VLAN
|HW_OWNER
;
1739 le
->opcode
|= OP_VLAN
;
1740 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1745 /* Handle TCP checksum offload */
1746 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1747 /* On Yukon EX (some versions) encoding change. */
1748 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1749 ctrl
|= CALSUM
; /* auto checksum */
1751 const unsigned offset
= skb_transport_offset(skb
);
1754 tcpsum
= offset
<< 16; /* sum start */
1755 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1757 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1758 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1761 if (tcpsum
!= sky2
->tx_tcpsum
) {
1762 sky2
->tx_tcpsum
= tcpsum
;
1764 le
= get_tx_le(sky2
, &slot
);
1765 le
->addr
= cpu_to_le32(tcpsum
);
1766 le
->length
= 0; /* initial checksum value */
1767 le
->ctrl
= 1; /* one packet */
1768 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1773 re
= sky2
->tx_ring
+ slot
;
1774 re
->flags
= TX_MAP_SINGLE
;
1775 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1776 pci_unmap_len_set(re
, maplen
, len
);
1778 le
= get_tx_le(sky2
, &slot
);
1779 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1780 le
->length
= cpu_to_le16(len
);
1782 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1785 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1786 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1788 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1789 frag
->size
, PCI_DMA_TODEVICE
);
1791 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1792 goto mapping_unwind
;
1794 upper
= upper_32_bits(mapping
);
1795 if (upper
!= sky2
->tx_last_upper
) {
1796 le
= get_tx_le(sky2
, &slot
);
1797 le
->addr
= cpu_to_le32(upper
);
1798 sky2
->tx_last_upper
= upper
;
1799 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1802 re
= sky2
->tx_ring
+ slot
;
1803 re
->flags
= TX_MAP_PAGE
;
1804 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1805 pci_unmap_len_set(re
, maplen
, frag
->size
);
1807 le
= get_tx_le(sky2
, &slot
);
1808 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1809 le
->length
= cpu_to_le16(frag
->size
);
1811 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1817 sky2
->tx_prod
= slot
;
1819 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1820 netif_stop_queue(dev
);
1822 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1824 return NETDEV_TX_OK
;
1827 for (i
= sky2
->tx_prod
; i
!= slot
; i
= RING_NEXT(i
, sky2
->tx_ring_size
)) {
1828 re
= sky2
->tx_ring
+ i
;
1830 sky2_tx_unmap(hw
->pdev
, re
);
1834 if (net_ratelimit())
1835 dev_warn(&hw
->pdev
->dev
, "%s: tx mapping error\n", dev
->name
);
1837 return NETDEV_TX_OK
;
1841 * Free ring elements from starting at tx_cons until "done"
1844 * 1. The hardware will tell us about partial completion of multi-part
1845 * buffers so make sure not to free skb to early.
1846 * 2. This may run in parallel start_xmit because the it only
1847 * looks at the tail of the queue of FIFO (tx_cons), not
1848 * the head (tx_prod)
1850 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1852 struct net_device
*dev
= sky2
->netdev
;
1855 BUG_ON(done
>= sky2
->tx_ring_size
);
1857 for (idx
= sky2
->tx_cons
; idx
!= done
;
1858 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
1859 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1860 struct sk_buff
*skb
= re
->skb
;
1862 sky2_tx_unmap(sky2
->hw
->pdev
, re
);
1865 netif_printk(sky2
, tx_done
, KERN_DEBUG
, dev
,
1866 "tx done %u\n", idx
);
1868 dev
->stats
.tx_packets
++;
1869 dev
->stats
.tx_bytes
+= skb
->len
;
1872 dev_kfree_skb_any(skb
);
1874 sky2
->tx_next
= RING_NEXT(idx
, sky2
->tx_ring_size
);
1878 sky2
->tx_cons
= idx
;
1882 static void sky2_tx_reset(struct sky2_hw
*hw
, unsigned port
)
1884 /* Disable Force Sync bit and Enable Alloc bit */
1885 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1886 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1888 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1889 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1890 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1892 /* Reset the PCI FIFO of the async Tx queue */
1893 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1894 BMU_RST_SET
| BMU_FIFO_RST
);
1896 /* Reset the Tx prefetch units */
1897 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1900 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1901 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1904 static void sky2_hw_down(struct sky2_port
*sky2
)
1906 struct sky2_hw
*hw
= sky2
->hw
;
1907 unsigned port
= sky2
->port
;
1910 /* Force flow control off */
1911 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1913 /* Stop transmitter */
1914 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1915 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1917 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1918 RB_RST_SET
| RB_DIS_OP_MD
);
1920 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1921 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1922 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1924 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1926 /* Workaround shared GMAC reset */
1927 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 &&
1928 port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1929 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1931 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1933 /* Force any delayed status interrrupt and NAPI */
1934 sky2_write32(hw
, STAT_LEV_TIMER_CNT
, 0);
1935 sky2_write32(hw
, STAT_TX_TIMER_CNT
, 0);
1936 sky2_write32(hw
, STAT_ISR_TIMER_CNT
, 0);
1937 sky2_read8(hw
, STAT_ISR_TIMER_CTRL
);
1941 spin_lock_bh(&sky2
->phy_lock
);
1942 sky2_phy_power_down(hw
, port
);
1943 spin_unlock_bh(&sky2
->phy_lock
);
1945 sky2_tx_reset(hw
, port
);
1947 /* Free any pending frames stuck in HW queue */
1948 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1951 /* Network shutdown */
1952 static int sky2_down(struct net_device
*dev
)
1954 struct sky2_port
*sky2
= netdev_priv(dev
);
1955 struct sky2_hw
*hw
= sky2
->hw
;
1957 /* Never really got started! */
1961 netif_info(sky2
, ifdown
, dev
, "disabling interface\n");
1963 /* Disable port IRQ */
1964 sky2_write32(hw
, B0_IMSK
,
1965 sky2_read32(hw
, B0_IMSK
) & ~portirq_msk
[sky2
->port
]);
1966 sky2_read32(hw
, B0_IMSK
);
1968 synchronize_irq(hw
->pdev
->irq
);
1969 napi_synchronize(&hw
->napi
);
1973 sky2_free_buffers(sky2
);
1978 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1980 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1983 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1984 if (aux
& PHY_M_PS_SPEED_100
)
1990 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1991 case PHY_M_PS_SPEED_1000
:
1993 case PHY_M_PS_SPEED_100
:
2000 static void sky2_link_up(struct sky2_port
*sky2
)
2002 struct sky2_hw
*hw
= sky2
->hw
;
2003 unsigned port
= sky2
->port
;
2005 static const char *fc_name
[] = {
2013 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2014 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
2015 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2017 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
2019 netif_carrier_on(sky2
->netdev
);
2021 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
2023 /* Turn on link LED */
2024 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
2025 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
2027 netif_info(sky2
, link
, sky2
->netdev
,
2028 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2030 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
2031 fc_name
[sky2
->flow_status
]);
2034 static void sky2_link_down(struct sky2_port
*sky2
)
2036 struct sky2_hw
*hw
= sky2
->hw
;
2037 unsigned port
= sky2
->port
;
2040 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
2042 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2043 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2044 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2046 netif_carrier_off(sky2
->netdev
);
2048 /* Turn off link LED */
2049 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
2051 netif_info(sky2
, link
, sky2
->netdev
, "Link is down\n");
2053 sky2_phy_init(hw
, port
);
2056 static enum flow_control
sky2_flow(int rx
, int tx
)
2059 return tx
? FC_BOTH
: FC_RX
;
2061 return tx
? FC_TX
: FC_NONE
;
2064 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
2066 struct sky2_hw
*hw
= sky2
->hw
;
2067 unsigned port
= sky2
->port
;
2070 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2071 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
2072 if (lpa
& PHY_M_AN_RF
) {
2073 netdev_err(sky2
->netdev
, "remote fault\n");
2077 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
2078 netdev_err(sky2
->netdev
, "speed/duplex mismatch\n");
2082 sky2
->speed
= sky2_phy_speed(hw
, aux
);
2083 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2085 /* Since the pause result bits seem to in different positions on
2086 * different chips. look at registers.
2088 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
2089 /* Shift for bits in fiber PHY */
2090 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
2091 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
2093 if (advert
& ADVERTISE_1000XPAUSE
)
2094 advert
|= ADVERTISE_PAUSE_CAP
;
2095 if (advert
& ADVERTISE_1000XPSE_ASYM
)
2096 advert
|= ADVERTISE_PAUSE_ASYM
;
2097 if (lpa
& LPA_1000XPAUSE
)
2098 lpa
|= LPA_PAUSE_CAP
;
2099 if (lpa
& LPA_1000XPAUSE_ASYM
)
2100 lpa
|= LPA_PAUSE_ASYM
;
2103 sky2
->flow_status
= FC_NONE
;
2104 if (advert
& ADVERTISE_PAUSE_CAP
) {
2105 if (lpa
& LPA_PAUSE_CAP
)
2106 sky2
->flow_status
= FC_BOTH
;
2107 else if (advert
& ADVERTISE_PAUSE_ASYM
)
2108 sky2
->flow_status
= FC_RX
;
2109 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
2110 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
2111 sky2
->flow_status
= FC_TX
;
2114 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
&&
2115 !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
2116 sky2
->flow_status
= FC_NONE
;
2118 if (sky2
->flow_status
& FC_TX
)
2119 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2121 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2126 /* Interrupt from PHY */
2127 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2129 struct net_device
*dev
= hw
->dev
[port
];
2130 struct sky2_port
*sky2
= netdev_priv(dev
);
2131 u16 istatus
, phystat
;
2133 if (!netif_running(dev
))
2136 spin_lock(&sky2
->phy_lock
);
2137 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2138 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2140 netif_info(sky2
, intr
, sky2
->netdev
, "phy interrupt status 0x%x 0x%x\n",
2143 if (istatus
& PHY_M_IS_AN_COMPL
) {
2144 if (sky2_autoneg_done(sky2
, phystat
) == 0)
2149 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2150 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2152 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2154 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2156 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2157 if (phystat
& PHY_M_PS_LINK_UP
)
2160 sky2_link_down(sky2
);
2163 spin_unlock(&sky2
->phy_lock
);
2166 /* Special quick link interrupt (Yukon-2 Optima only) */
2167 static void sky2_qlink_intr(struct sky2_hw
*hw
)
2169 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[0]);
2174 imask
= sky2_read32(hw
, B0_IMSK
);
2175 imask
&= ~Y2_IS_PHY_QLNK
;
2176 sky2_write32(hw
, B0_IMSK
, imask
);
2178 /* reset PHY Link Detect */
2179 phy
= sky2_pci_read16(hw
, PSM_CONFIG_REG4
);
2180 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2181 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, phy
| 1);
2182 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2187 /* Transmit timeout is only called if we are running, carrier is up
2188 * and tx queue is full (stopped).
2190 static void sky2_tx_timeout(struct net_device
*dev
)
2192 struct sky2_port
*sky2
= netdev_priv(dev
);
2193 struct sky2_hw
*hw
= sky2
->hw
;
2195 netif_err(sky2
, timer
, dev
, "tx timeout\n");
2197 netdev_printk(KERN_DEBUG
, dev
, "transmit ring %u .. %u report=%u done=%u\n",
2198 sky2
->tx_cons
, sky2
->tx_prod
,
2199 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2200 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2202 /* can't restart safely under softirq */
2203 schedule_work(&hw
->restart_work
);
2206 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2208 struct sky2_port
*sky2
= netdev_priv(dev
);
2209 struct sky2_hw
*hw
= sky2
->hw
;
2210 unsigned port
= sky2
->port
;
2215 /* MTU size outside the spec */
2216 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2219 /* MTU > 1500 on yukon FE and FE+ not allowed */
2220 if (new_mtu
> ETH_DATA_LEN
&&
2221 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2222 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2225 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2226 if (new_mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2227 dev
->features
&= ~(NETIF_F_TSO
|NETIF_F_SG
|NETIF_F_ALL_CSUM
);
2229 if (!netif_running(dev
)) {
2234 imask
= sky2_read32(hw
, B0_IMSK
);
2235 sky2_write32(hw
, B0_IMSK
, 0);
2237 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2238 netif_stop_queue(dev
);
2239 napi_disable(&hw
->napi
);
2241 synchronize_irq(hw
->pdev
->irq
);
2243 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2244 sky2_set_tx_stfwd(hw
, port
);
2246 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2247 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2249 sky2_rx_clean(sky2
);
2253 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2254 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2256 if (dev
->mtu
> ETH_DATA_LEN
)
2257 mode
|= GM_SMOD_JUMBO_ENA
;
2259 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2261 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2263 err
= sky2_alloc_rx_skbs(sky2
);
2265 sky2_rx_start(sky2
);
2267 sky2_rx_clean(sky2
);
2268 sky2_write32(hw
, B0_IMSK
, imask
);
2270 sky2_read32(hw
, B0_Y2_SP_LISR
);
2271 napi_enable(&hw
->napi
);
2276 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2278 netif_wake_queue(dev
);
2284 /* For small just reuse existing skb for next receive */
2285 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2286 const struct rx_ring_info
*re
,
2289 struct sk_buff
*skb
;
2291 skb
= netdev_alloc_skb_ip_align(sky2
->netdev
, length
);
2293 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2294 length
, PCI_DMA_FROMDEVICE
);
2295 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2296 skb
->ip_summed
= re
->skb
->ip_summed
;
2297 skb
->csum
= re
->skb
->csum
;
2298 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2299 length
, PCI_DMA_FROMDEVICE
);
2300 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2301 skb_put(skb
, length
);
2306 /* Adjust length of skb with fragments to match received data */
2307 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2308 unsigned int length
)
2313 /* put header into skb */
2314 size
= min(length
, hdr_space
);
2319 num_frags
= skb_shinfo(skb
)->nr_frags
;
2320 for (i
= 0; i
< num_frags
; i
++) {
2321 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2324 /* don't need this page */
2325 __free_page(frag
->page
);
2326 --skb_shinfo(skb
)->nr_frags
;
2328 size
= min(length
, (unsigned) PAGE_SIZE
);
2331 skb
->data_len
+= size
;
2332 skb
->truesize
+= size
;
2339 /* Normal packet - take skb from ring element and put in a new one */
2340 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2341 struct rx_ring_info
*re
,
2342 unsigned int length
)
2344 struct sk_buff
*skb
;
2345 struct rx_ring_info nre
;
2346 unsigned hdr_space
= sky2
->rx_data_size
;
2348 nre
.skb
= sky2_rx_alloc(sky2
);
2349 if (unlikely(!nre
.skb
))
2352 if (sky2_rx_map_skb(sky2
->hw
->pdev
, &nre
, hdr_space
))
2356 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2357 prefetch(skb
->data
);
2360 if (skb_shinfo(skb
)->nr_frags
)
2361 skb_put_frags(skb
, hdr_space
, length
);
2363 skb_put(skb
, length
);
2367 dev_kfree_skb(nre
.skb
);
2373 * Receive one packet.
2374 * For larger packets, get new buffer.
2376 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2377 u16 length
, u32 status
)
2379 struct sky2_port
*sky2
= netdev_priv(dev
);
2380 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2381 struct sk_buff
*skb
= NULL
;
2382 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2384 #ifdef SKY2_VLAN_TAG_USED
2385 /* Account for vlan tag */
2386 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2390 netif_printk(sky2
, rx_status
, KERN_DEBUG
, dev
,
2391 "rx slot %u status 0x%x len %d\n",
2392 sky2
->rx_next
, status
, length
);
2394 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2395 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2397 /* This chip has hardware problems that generates bogus status.
2398 * So do only marginal checking and expect higher level protocols
2399 * to handle crap frames.
2401 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2402 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2406 if (status
& GMR_FS_ANY_ERR
)
2409 if (!(status
& GMR_FS_RX_OK
))
2412 /* if length reported by DMA does not match PHY, packet was truncated */
2413 if (length
!= count
)
2417 if (length
< copybreak
)
2418 skb
= receive_copy(sky2
, re
, length
);
2420 skb
= receive_new(sky2
, re
, length
);
2422 dev
->stats
.rx_dropped
+= (skb
== NULL
);
2425 sky2_rx_submit(sky2
, re
);
2430 /* Truncation of overlength packets
2431 causes PHY length to not match MAC length */
2432 ++dev
->stats
.rx_length_errors
;
2433 if (net_ratelimit())
2434 netif_info(sky2
, rx_err
, dev
,
2435 "rx length error: status %#x length %d\n",
2440 ++dev
->stats
.rx_errors
;
2441 if (status
& GMR_FS_RX_FF_OV
) {
2442 dev
->stats
.rx_over_errors
++;
2446 if (net_ratelimit())
2447 netif_info(sky2
, rx_err
, dev
,
2448 "rx error, status 0x%x length %d\n", status
, length
);
2450 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2451 dev
->stats
.rx_length_errors
++;
2452 if (status
& GMR_FS_FRAGMENT
)
2453 dev
->stats
.rx_frame_errors
++;
2454 if (status
& GMR_FS_CRC_ERR
)
2455 dev
->stats
.rx_crc_errors
++;
2460 /* Transmit complete */
2461 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2463 struct sky2_port
*sky2
= netdev_priv(dev
);
2465 if (netif_running(dev
)) {
2466 sky2_tx_complete(sky2
, last
);
2468 /* Wake unless it's detached, and called e.g. from sky2_down() */
2469 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
2470 netif_wake_queue(dev
);
2474 static inline void sky2_skb_rx(const struct sky2_port
*sky2
,
2475 u32 status
, struct sk_buff
*skb
)
2477 #ifdef SKY2_VLAN_TAG_USED
2478 u16 vlan_tag
= be16_to_cpu(sky2
->rx_tag
);
2479 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2480 if (skb
->ip_summed
== CHECKSUM_NONE
)
2481 vlan_hwaccel_receive_skb(skb
, sky2
->vlgrp
, vlan_tag
);
2483 vlan_gro_receive(&sky2
->hw
->napi
, sky2
->vlgrp
,
2488 if (skb
->ip_summed
== CHECKSUM_NONE
)
2489 netif_receive_skb(skb
);
2491 napi_gro_receive(&sky2
->hw
->napi
, skb
);
2494 static inline void sky2_rx_done(struct sky2_hw
*hw
, unsigned port
,
2495 unsigned packets
, unsigned bytes
)
2498 struct net_device
*dev
= hw
->dev
[port
];
2500 dev
->stats
.rx_packets
+= packets
;
2501 dev
->stats
.rx_bytes
+= bytes
;
2502 dev
->last_rx
= jiffies
;
2503 sky2_rx_update(netdev_priv(dev
), rxqaddr
[port
]);
2507 static void sky2_rx_checksum(struct sky2_port
*sky2
, u32 status
)
2509 /* If this happens then driver assuming wrong format for chip type */
2510 BUG_ON(sky2
->hw
->flags
& SKY2_HW_NEW_LE
);
2512 /* Both checksum counters are programmed to start at
2513 * the same offset, so unless there is a problem they
2514 * should match. This failure is an early indication that
2515 * hardware receive checksumming won't work.
2517 if (likely((u16
)(status
>> 16) == (u16
)status
)) {
2518 struct sk_buff
*skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2519 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2520 skb
->csum
= le16_to_cpu(status
);
2522 dev_notice(&sky2
->hw
->pdev
->dev
,
2523 "%s: receive checksum problem (status = %#x)\n",
2524 sky2
->netdev
->name
, status
);
2526 /* Disable checksum offload */
2527 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
2528 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2533 /* Process status response ring */
2534 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2537 unsigned int total_bytes
[2] = { 0 };
2538 unsigned int total_packets
[2] = { 0 };
2542 struct sky2_port
*sky2
;
2543 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2545 struct net_device
*dev
;
2546 struct sk_buff
*skb
;
2549 u8 opcode
= le
->opcode
;
2551 if (!(opcode
& HW_OWNER
))
2554 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2556 port
= le
->css
& CSS_LINK_BIT
;
2557 dev
= hw
->dev
[port
];
2558 sky2
= netdev_priv(dev
);
2559 length
= le16_to_cpu(le
->length
);
2560 status
= le32_to_cpu(le
->status
);
2563 switch (opcode
& ~HW_OWNER
) {
2565 total_packets
[port
]++;
2566 total_bytes
[port
] += length
;
2568 skb
= sky2_receive(dev
, length
, status
);
2572 /* This chip reports checksum status differently */
2573 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2574 if ((sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
) &&
2575 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2576 (le
->css
& CSS_TCPUDPCSOK
))
2577 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2579 skb
->ip_summed
= CHECKSUM_NONE
;
2582 skb
->protocol
= eth_type_trans(skb
, dev
);
2584 sky2_skb_rx(sky2
, status
, skb
);
2586 /* Stop after net poll weight */
2587 if (++work_done
>= to_do
)
2591 #ifdef SKY2_VLAN_TAG_USED
2593 sky2
->rx_tag
= length
;
2597 sky2
->rx_tag
= length
;
2601 if (likely(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
))
2602 sky2_rx_checksum(sky2
, status
);
2606 /* TX index reports status for both ports */
2607 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2609 sky2_tx_done(hw
->dev
[1],
2610 ((status
>> 24) & 0xff)
2611 | (u16
)(length
& 0xf) << 8);
2615 if (net_ratelimit())
2616 pr_warning("unknown status opcode 0x%x\n", opcode
);
2618 } while (hw
->st_idx
!= idx
);
2620 /* Fully processed status ring so clear irq */
2621 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2624 sky2_rx_done(hw
, 0, total_packets
[0], total_bytes
[0]);
2625 sky2_rx_done(hw
, 1, total_packets
[1], total_bytes
[1]);
2630 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2632 struct net_device
*dev
= hw
->dev
[port
];
2634 if (net_ratelimit())
2635 netdev_info(dev
, "hw error interrupt status 0x%x\n", status
);
2637 if (status
& Y2_IS_PAR_RD1
) {
2638 if (net_ratelimit())
2639 netdev_err(dev
, "ram data read parity error\n");
2641 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2644 if (status
& Y2_IS_PAR_WR1
) {
2645 if (net_ratelimit())
2646 netdev_err(dev
, "ram data write parity error\n");
2648 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2651 if (status
& Y2_IS_PAR_MAC1
) {
2652 if (net_ratelimit())
2653 netdev_err(dev
, "MAC parity error\n");
2654 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2657 if (status
& Y2_IS_PAR_RX1
) {
2658 if (net_ratelimit())
2659 netdev_err(dev
, "RX parity error\n");
2660 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2663 if (status
& Y2_IS_TCP_TXA1
) {
2664 if (net_ratelimit())
2665 netdev_err(dev
, "TCP segmentation error\n");
2666 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2670 static void sky2_hw_intr(struct sky2_hw
*hw
)
2672 struct pci_dev
*pdev
= hw
->pdev
;
2673 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2674 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2678 if (status
& Y2_IS_TIST_OV
)
2679 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2681 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2684 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2685 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2686 if (net_ratelimit())
2687 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2690 sky2_pci_write16(hw
, PCI_STATUS
,
2691 pci_err
| PCI_STATUS_ERROR_BITS
);
2692 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2695 if (status
& Y2_IS_PCI_EXP
) {
2696 /* PCI-Express uncorrectable Error occurred */
2699 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2700 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2701 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2703 if (net_ratelimit())
2704 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2706 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2707 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2710 if (status
& Y2_HWE_L1_MASK
)
2711 sky2_hw_error(hw
, 0, status
);
2713 if (status
& Y2_HWE_L1_MASK
)
2714 sky2_hw_error(hw
, 1, status
);
2717 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2719 struct net_device
*dev
= hw
->dev
[port
];
2720 struct sky2_port
*sky2
= netdev_priv(dev
);
2721 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2723 netif_info(sky2
, intr
, dev
, "mac interrupt status 0x%x\n", status
);
2725 if (status
& GM_IS_RX_CO_OV
)
2726 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2728 if (status
& GM_IS_TX_CO_OV
)
2729 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2731 if (status
& GM_IS_RX_FF_OR
) {
2732 ++dev
->stats
.rx_fifo_errors
;
2733 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2736 if (status
& GM_IS_TX_FF_UR
) {
2737 ++dev
->stats
.tx_fifo_errors
;
2738 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2742 /* This should never happen it is a bug. */
2743 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
, u16 q
)
2745 struct net_device
*dev
= hw
->dev
[port
];
2746 u16 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2748 dev_err(&hw
->pdev
->dev
, "%s: descriptor error q=%#x get=%u put=%u\n",
2749 dev
->name
, (unsigned) q
, (unsigned) idx
,
2750 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2752 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2755 static int sky2_rx_hung(struct net_device
*dev
)
2757 struct sky2_port
*sky2
= netdev_priv(dev
);
2758 struct sky2_hw
*hw
= sky2
->hw
;
2759 unsigned port
= sky2
->port
;
2760 unsigned rxq
= rxqaddr
[port
];
2761 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2762 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2763 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2764 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2766 /* If idle and MAC or PCI is stuck */
2767 if (sky2
->check
.last
== dev
->last_rx
&&
2768 ((mac_rp
== sky2
->check
.mac_rp
&&
2769 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2770 /* Check if the PCI RX hang */
2771 (fifo_rp
== sky2
->check
.fifo_rp
&&
2772 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2773 netdev_printk(KERN_DEBUG
, dev
,
2774 "hung mac %d:%d fifo %d (%d:%d)\n",
2775 mac_lev
, mac_rp
, fifo_lev
,
2776 fifo_rp
, sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2779 sky2
->check
.last
= dev
->last_rx
;
2780 sky2
->check
.mac_rp
= mac_rp
;
2781 sky2
->check
.mac_lev
= mac_lev
;
2782 sky2
->check
.fifo_rp
= fifo_rp
;
2783 sky2
->check
.fifo_lev
= fifo_lev
;
2788 static void sky2_watchdog(unsigned long arg
)
2790 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2792 /* Check for lost IRQ once a second */
2793 if (sky2_read32(hw
, B0_ISRC
)) {
2794 napi_schedule(&hw
->napi
);
2798 for (i
= 0; i
< hw
->ports
; i
++) {
2799 struct net_device
*dev
= hw
->dev
[i
];
2800 if (!netif_running(dev
))
2804 /* For chips with Rx FIFO, check if stuck */
2805 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
2806 sky2_rx_hung(dev
)) {
2807 netdev_info(dev
, "receiver hang detected\n");
2808 schedule_work(&hw
->restart_work
);
2817 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2820 /* Hardware/software error handling */
2821 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2823 if (net_ratelimit())
2824 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2826 if (status
& Y2_IS_HW_ERR
)
2829 if (status
& Y2_IS_IRQ_MAC1
)
2830 sky2_mac_intr(hw
, 0);
2832 if (status
& Y2_IS_IRQ_MAC2
)
2833 sky2_mac_intr(hw
, 1);
2835 if (status
& Y2_IS_CHK_RX1
)
2836 sky2_le_error(hw
, 0, Q_R1
);
2838 if (status
& Y2_IS_CHK_RX2
)
2839 sky2_le_error(hw
, 1, Q_R2
);
2841 if (status
& Y2_IS_CHK_TXA1
)
2842 sky2_le_error(hw
, 0, Q_XA1
);
2844 if (status
& Y2_IS_CHK_TXA2
)
2845 sky2_le_error(hw
, 1, Q_XA2
);
2848 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
2850 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
2851 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2855 if (unlikely(status
& Y2_IS_ERROR
))
2856 sky2_err_intr(hw
, status
);
2858 if (status
& Y2_IS_IRQ_PHY1
)
2859 sky2_phy_intr(hw
, 0);
2861 if (status
& Y2_IS_IRQ_PHY2
)
2862 sky2_phy_intr(hw
, 1);
2864 if (status
& Y2_IS_PHY_QLNK
)
2865 sky2_qlink_intr(hw
);
2867 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
2868 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
2870 if (work_done
>= work_limit
)
2874 napi_complete(napi
);
2875 sky2_read32(hw
, B0_Y2_SP_LISR
);
2881 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2883 struct sky2_hw
*hw
= dev_id
;
2886 /* Reading this mask interrupts as side effect */
2887 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2888 if (status
== 0 || status
== ~0)
2891 prefetch(&hw
->st_le
[hw
->st_idx
]);
2893 napi_schedule(&hw
->napi
);
2898 #ifdef CONFIG_NET_POLL_CONTROLLER
2899 static void sky2_netpoll(struct net_device
*dev
)
2901 struct sky2_port
*sky2
= netdev_priv(dev
);
2903 napi_schedule(&sky2
->hw
->napi
);
2907 /* Chip internal frequency for clock calculations */
2908 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2910 switch (hw
->chip_id
) {
2911 case CHIP_ID_YUKON_EC
:
2912 case CHIP_ID_YUKON_EC_U
:
2913 case CHIP_ID_YUKON_EX
:
2914 case CHIP_ID_YUKON_SUPR
:
2915 case CHIP_ID_YUKON_UL_2
:
2916 case CHIP_ID_YUKON_OPT
:
2919 case CHIP_ID_YUKON_FE
:
2922 case CHIP_ID_YUKON_FE_P
:
2925 case CHIP_ID_YUKON_XL
:
2933 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2935 return sky2_mhz(hw
) * us
;
2938 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2940 return clk
/ sky2_mhz(hw
);
2944 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2948 /* Enable all clocks and check for bad PCI access */
2949 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2951 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2953 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2954 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2956 switch(hw
->chip_id
) {
2957 case CHIP_ID_YUKON_XL
:
2958 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
2961 case CHIP_ID_YUKON_EC_U
:
2962 hw
->flags
= SKY2_HW_GIGABIT
2964 | SKY2_HW_ADV_POWER_CTL
;
2967 case CHIP_ID_YUKON_EX
:
2968 hw
->flags
= SKY2_HW_GIGABIT
2971 | SKY2_HW_ADV_POWER_CTL
;
2973 /* New transmit checksum */
2974 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2975 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2978 case CHIP_ID_YUKON_EC
:
2979 /* This rev is really old, and requires untested workarounds */
2980 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2981 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2984 hw
->flags
= SKY2_HW_GIGABIT
;
2987 case CHIP_ID_YUKON_FE
:
2990 case CHIP_ID_YUKON_FE_P
:
2991 hw
->flags
= SKY2_HW_NEWER_PHY
2993 | SKY2_HW_AUTO_TX_SUM
2994 | SKY2_HW_ADV_POWER_CTL
;
2997 case CHIP_ID_YUKON_SUPR
:
2998 hw
->flags
= SKY2_HW_GIGABIT
3001 | SKY2_HW_AUTO_TX_SUM
3002 | SKY2_HW_ADV_POWER_CTL
;
3005 case CHIP_ID_YUKON_UL_2
:
3006 hw
->flags
= SKY2_HW_GIGABIT
3007 | SKY2_HW_ADV_POWER_CTL
;
3010 case CHIP_ID_YUKON_OPT
:
3011 hw
->flags
= SKY2_HW_GIGABIT
3013 | SKY2_HW_ADV_POWER_CTL
;
3017 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
3022 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
3023 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
3024 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
3027 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
3028 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
3029 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
3033 if (sky2_read8(hw
, B2_E_0
))
3034 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
3039 static void sky2_reset(struct sky2_hw
*hw
)
3041 struct pci_dev
*pdev
= hw
->pdev
;
3044 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
3047 if (hw
->chip_id
== CHIP_ID_YUKON_EX
3048 || hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3049 sky2_write32(hw
, CPU_WDOG
, 0);
3050 status
= sky2_read16(hw
, HCU_CCSR
);
3051 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
3052 HCU_CCSR_UC_STATE_MSK
);
3054 * CPU clock divider shouldn't be used because
3055 * - ASF firmware may malfunction
3056 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3058 status
&= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK
;
3059 sky2_write16(hw
, HCU_CCSR
, status
);
3060 sky2_write32(hw
, CPU_WDOG
, 0);
3062 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
3063 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
3066 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3067 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
3069 /* allow writes to PCI config */
3070 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3072 /* clear PCI errors, if any */
3073 status
= sky2_pci_read16(hw
, PCI_STATUS
);
3074 status
|= PCI_STATUS_ERROR_BITS
;
3075 sky2_pci_write16(hw
, PCI_STATUS
, status
);
3077 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3079 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3081 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
3084 /* If error bit is stuck on ignore it */
3085 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
3086 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
3088 hwe_mask
|= Y2_IS_PCI_EXP
;
3092 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3094 for (i
= 0; i
< hw
->ports
; i
++) {
3095 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3096 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3098 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
3099 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
3100 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
3101 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
3106 if (hw
->chip_id
== CHIP_ID_YUKON_SUPR
&& hw
->chip_rev
> CHIP_REV_YU_SU_B0
) {
3107 /* enable MACSec clock gating */
3108 sky2_pci_write32(hw
, PCI_DEV_REG3
, P_CLK_MACSEC_DIS
);
3111 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
) {
3115 if (hw
->chip_rev
== 0) {
3116 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3117 sky2_write32(hw
, Y2_PEX_PHY_DATA
, (0x80UL
<< 16) | (1 << 7));
3119 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3122 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3126 reg
<<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE
;
3128 /* reset PHY Link Detect */
3129 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3130 sky2_pci_write16(hw
, PSM_CONFIG_REG4
,
3131 reg
| PSM_CONFIG_REG4_RST_PHY_LINK_DETECT
);
3132 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, reg
);
3135 /* enable PHY Quick Link */
3136 msk
= sky2_read32(hw
, B0_IMSK
);
3137 msk
|= Y2_IS_PHY_QLNK
;
3138 sky2_write32(hw
, B0_IMSK
, msk
);
3140 /* check if PSMv2 was running before */
3141 reg
= sky2_pci_read16(hw
, PSM_CONFIG_REG3
);
3142 if (reg
& PCI_EXP_LNKCTL_ASPMC
) {
3143 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3144 /* restore the PCIe Link Control register */
3145 sky2_pci_write16(hw
, cap
+ PCI_EXP_LNKCTL
, reg
);
3147 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3149 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3150 sky2_write32(hw
, Y2_PEX_PHY_DATA
, PEX_DB_ACCESS
| (0x08UL
<< 16));
3153 /* Clear I2C IRQ noise */
3154 sky2_write32(hw
, B2_I2C_IRQ
, 1);
3156 /* turn off hardware timer (unused) */
3157 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3158 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3160 /* Turn off descriptor polling */
3161 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
3163 /* Turn off receive timestamp */
3164 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
3165 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3167 /* enable the Tx Arbiters */
3168 for (i
= 0; i
< hw
->ports
; i
++)
3169 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3171 /* Initialize ram interface */
3172 for (i
= 0; i
< hw
->ports
; i
++) {
3173 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
3175 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
3176 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
3177 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
3178 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
3179 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
3180 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
3181 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
3182 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
3183 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
3184 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
3185 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
3186 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
3189 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
3191 for (i
= 0; i
< hw
->ports
; i
++)
3192 sky2_gmac_reset(hw
, i
);
3194 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
3197 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
3198 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
3200 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
3201 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
3203 /* Set the list last index */
3204 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
3206 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
3207 sky2_write8(hw
, STAT_FIFO_WM
, 16);
3209 /* set Status-FIFO ISR watermark */
3210 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
3211 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
3213 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
3215 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
3216 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
3217 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
3219 /* enable status unit */
3220 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
3222 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3223 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3224 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3227 /* Take device down (offline).
3228 * Equivalent to doing dev_stop() but this does not
3229 * inform upper layers of the transistion.
3231 static void sky2_detach(struct net_device
*dev
)
3233 if (netif_running(dev
)) {
3235 netif_device_detach(dev
); /* stop txq */
3236 netif_tx_unlock(dev
);
3241 /* Bring device back after doing sky2_detach */
3242 static int sky2_reattach(struct net_device
*dev
)
3246 if (netif_running(dev
)) {
3249 netdev_info(dev
, "could not restart %d\n", err
);
3252 netif_device_attach(dev
);
3253 sky2_set_multicast(dev
);
3260 static void sky2_restart(struct work_struct
*work
)
3262 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
3268 napi_disable(&hw
->napi
);
3269 synchronize_irq(hw
->pdev
->irq
);
3270 imask
= sky2_read32(hw
, B0_IMSK
);
3271 sky2_write32(hw
, B0_IMSK
, 0);
3273 for (i
= 0; i
< hw
->ports
; i
++) {
3274 struct net_device
*dev
= hw
->dev
[i
];
3275 struct sky2_port
*sky2
= netdev_priv(dev
);
3277 if (!netif_running(dev
))
3280 netif_carrier_off(dev
);
3281 netif_tx_disable(dev
);
3287 for (i
= 0; i
< hw
->ports
; i
++) {
3288 struct net_device
*dev
= hw
->dev
[i
];
3289 struct sky2_port
*sky2
= netdev_priv(dev
);
3291 if (!netif_running(dev
))
3295 netif_wake_queue(dev
);
3298 sky2_write32(hw
, B0_IMSK
, imask
);
3299 sky2_read32(hw
, B0_IMSK
);
3301 sky2_read32(hw
, B0_Y2_SP_LISR
);
3302 napi_enable(&hw
->napi
);
3307 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3309 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3312 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3314 const struct sky2_port
*sky2
= netdev_priv(dev
);
3316 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3317 wol
->wolopts
= sky2
->wol
;
3320 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3322 struct sky2_port
*sky2
= netdev_priv(dev
);
3323 struct sky2_hw
*hw
= sky2
->hw
;
3325 if ((wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
)) ||
3326 !device_can_wakeup(&hw
->pdev
->dev
))
3329 sky2
->wol
= wol
->wolopts
;
3333 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3335 if (sky2_is_copper(hw
)) {
3336 u32 modes
= SUPPORTED_10baseT_Half
3337 | SUPPORTED_10baseT_Full
3338 | SUPPORTED_100baseT_Half
3339 | SUPPORTED_100baseT_Full
3340 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
3342 if (hw
->flags
& SKY2_HW_GIGABIT
)
3343 modes
|= SUPPORTED_1000baseT_Half
3344 | SUPPORTED_1000baseT_Full
;
3347 return SUPPORTED_1000baseT_Half
3348 | SUPPORTED_1000baseT_Full
3353 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3355 struct sky2_port
*sky2
= netdev_priv(dev
);
3356 struct sky2_hw
*hw
= sky2
->hw
;
3358 ecmd
->transceiver
= XCVR_INTERNAL
;
3359 ecmd
->supported
= sky2_supported_modes(hw
);
3360 ecmd
->phy_address
= PHY_ADDR_MARV
;
3361 if (sky2_is_copper(hw
)) {
3362 ecmd
->port
= PORT_TP
;
3363 ecmd
->speed
= sky2
->speed
;
3365 ecmd
->speed
= SPEED_1000
;
3366 ecmd
->port
= PORT_FIBRE
;
3369 ecmd
->advertising
= sky2
->advertising
;
3370 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
3371 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3372 ecmd
->duplex
= sky2
->duplex
;
3376 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3378 struct sky2_port
*sky2
= netdev_priv(dev
);
3379 const struct sky2_hw
*hw
= sky2
->hw
;
3380 u32 supported
= sky2_supported_modes(hw
);
3382 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3383 sky2
->flags
|= SKY2_FLAG_AUTO_SPEED
;
3384 ecmd
->advertising
= supported
;
3390 switch (ecmd
->speed
) {
3392 if (ecmd
->duplex
== DUPLEX_FULL
)
3393 setting
= SUPPORTED_1000baseT_Full
;
3394 else if (ecmd
->duplex
== DUPLEX_HALF
)
3395 setting
= SUPPORTED_1000baseT_Half
;
3400 if (ecmd
->duplex
== DUPLEX_FULL
)
3401 setting
= SUPPORTED_100baseT_Full
;
3402 else if (ecmd
->duplex
== DUPLEX_HALF
)
3403 setting
= SUPPORTED_100baseT_Half
;
3409 if (ecmd
->duplex
== DUPLEX_FULL
)
3410 setting
= SUPPORTED_10baseT_Full
;
3411 else if (ecmd
->duplex
== DUPLEX_HALF
)
3412 setting
= SUPPORTED_10baseT_Half
;
3420 if ((setting
& supported
) == 0)
3423 sky2
->speed
= ecmd
->speed
;
3424 sky2
->duplex
= ecmd
->duplex
;
3425 sky2
->flags
&= ~SKY2_FLAG_AUTO_SPEED
;
3428 sky2
->advertising
= ecmd
->advertising
;
3430 if (netif_running(dev
)) {
3431 sky2_phy_reinit(sky2
);
3432 sky2_set_multicast(dev
);
3438 static void sky2_get_drvinfo(struct net_device
*dev
,
3439 struct ethtool_drvinfo
*info
)
3441 struct sky2_port
*sky2
= netdev_priv(dev
);
3443 strcpy(info
->driver
, DRV_NAME
);
3444 strcpy(info
->version
, DRV_VERSION
);
3445 strcpy(info
->fw_version
, "N/A");
3446 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3449 static const struct sky2_stat
{
3450 char name
[ETH_GSTRING_LEN
];
3453 { "tx_bytes", GM_TXO_OK_HI
},
3454 { "rx_bytes", GM_RXO_OK_HI
},
3455 { "tx_broadcast", GM_TXF_BC_OK
},
3456 { "rx_broadcast", GM_RXF_BC_OK
},
3457 { "tx_multicast", GM_TXF_MC_OK
},
3458 { "rx_multicast", GM_RXF_MC_OK
},
3459 { "tx_unicast", GM_TXF_UC_OK
},
3460 { "rx_unicast", GM_RXF_UC_OK
},
3461 { "tx_mac_pause", GM_TXF_MPAUSE
},
3462 { "rx_mac_pause", GM_RXF_MPAUSE
},
3463 { "collisions", GM_TXF_COL
},
3464 { "late_collision",GM_TXF_LAT_COL
},
3465 { "aborted", GM_TXF_ABO_COL
},
3466 { "single_collisions", GM_TXF_SNG_COL
},
3467 { "multi_collisions", GM_TXF_MUL_COL
},
3469 { "rx_short", GM_RXF_SHT
},
3470 { "rx_runt", GM_RXE_FRAG
},
3471 { "rx_64_byte_packets", GM_RXF_64B
},
3472 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3473 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3474 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3475 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3476 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3477 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3478 { "rx_too_long", GM_RXF_LNG_ERR
},
3479 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3480 { "rx_jabber", GM_RXF_JAB_PKT
},
3481 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3483 { "tx_64_byte_packets", GM_TXF_64B
},
3484 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3485 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3486 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3487 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3488 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3489 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3490 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3493 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3495 struct sky2_port
*sky2
= netdev_priv(dev
);
3497 return !!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
);
3500 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3502 struct sky2_port
*sky2
= netdev_priv(dev
);
3505 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
3507 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
3509 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3510 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3515 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3517 struct sky2_port
*sky2
= netdev_priv(netdev
);
3518 return sky2
->msg_enable
;
3521 static int sky2_nway_reset(struct net_device
*dev
)
3523 struct sky2_port
*sky2
= netdev_priv(dev
);
3525 if (!netif_running(dev
) || !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
))
3528 sky2_phy_reinit(sky2
);
3529 sky2_set_multicast(dev
);
3534 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3536 struct sky2_hw
*hw
= sky2
->hw
;
3537 unsigned port
= sky2
->port
;
3540 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3541 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3542 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3543 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3545 for (i
= 2; i
< count
; i
++)
3546 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3549 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3551 struct sky2_port
*sky2
= netdev_priv(netdev
);
3552 sky2
->msg_enable
= value
;
3555 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3559 return ARRAY_SIZE(sky2_stats
);
3565 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3566 struct ethtool_stats
*stats
, u64
* data
)
3568 struct sky2_port
*sky2
= netdev_priv(dev
);
3570 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3573 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3577 switch (stringset
) {
3579 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3580 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3581 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3586 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3588 struct sky2_port
*sky2
= netdev_priv(dev
);
3589 struct sky2_hw
*hw
= sky2
->hw
;
3590 unsigned port
= sky2
->port
;
3591 const struct sockaddr
*addr
= p
;
3593 if (!is_valid_ether_addr(addr
->sa_data
))
3594 return -EADDRNOTAVAIL
;
3596 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3597 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3598 dev
->dev_addr
, ETH_ALEN
);
3599 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3600 dev
->dev_addr
, ETH_ALEN
);
3602 /* virtual address for data */
3603 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3605 /* physical address: used for pause frames */
3606 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3611 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3615 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3616 filter
[bit
>> 3] |= 1 << (bit
& 7);
3619 static void sky2_set_multicast(struct net_device
*dev
)
3621 struct sky2_port
*sky2
= netdev_priv(dev
);
3622 struct sky2_hw
*hw
= sky2
->hw
;
3623 unsigned port
= sky2
->port
;
3624 struct dev_mc_list
*list
;
3628 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3630 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3631 memset(filter
, 0, sizeof(filter
));
3633 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3634 reg
|= GM_RXCR_UCF_ENA
;
3636 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3637 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3638 else if (dev
->flags
& IFF_ALLMULTI
)
3639 memset(filter
, 0xff, sizeof(filter
));
3640 else if (netdev_mc_empty(dev
) && !rx_pause
)
3641 reg
&= ~GM_RXCR_MCF_ENA
;
3643 reg
|= GM_RXCR_MCF_ENA
;
3646 sky2_add_filter(filter
, pause_mc_addr
);
3648 netdev_for_each_mc_addr(list
, dev
)
3649 sky2_add_filter(filter
, list
->dmi_addr
);
3652 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3653 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3654 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3655 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3656 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3657 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3658 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3659 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3661 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3664 /* Can have one global because blinking is controlled by
3665 * ethtool and that is always under RTNL mutex
3667 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3669 struct sky2_hw
*hw
= sky2
->hw
;
3670 unsigned port
= sky2
->port
;
3672 spin_lock_bh(&sky2
->phy_lock
);
3673 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3674 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3675 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3677 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3678 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3682 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3683 PHY_M_LEDC_LOS_CTRL(8) |
3684 PHY_M_LEDC_INIT_CTRL(8) |
3685 PHY_M_LEDC_STA1_CTRL(8) |
3686 PHY_M_LEDC_STA0_CTRL(8));
3689 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3690 PHY_M_LEDC_LOS_CTRL(9) |
3691 PHY_M_LEDC_INIT_CTRL(9) |
3692 PHY_M_LEDC_STA1_CTRL(9) |
3693 PHY_M_LEDC_STA0_CTRL(9));
3696 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3697 PHY_M_LEDC_LOS_CTRL(0xa) |
3698 PHY_M_LEDC_INIT_CTRL(0xa) |
3699 PHY_M_LEDC_STA1_CTRL(0xa) |
3700 PHY_M_LEDC_STA0_CTRL(0xa));
3703 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3704 PHY_M_LEDC_LOS_CTRL(1) |
3705 PHY_M_LEDC_INIT_CTRL(8) |
3706 PHY_M_LEDC_STA1_CTRL(7) |
3707 PHY_M_LEDC_STA0_CTRL(7));
3710 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3712 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3713 PHY_M_LED_MO_DUP(mode
) |
3714 PHY_M_LED_MO_10(mode
) |
3715 PHY_M_LED_MO_100(mode
) |
3716 PHY_M_LED_MO_1000(mode
) |
3717 PHY_M_LED_MO_RX(mode
) |
3718 PHY_M_LED_MO_TX(mode
));
3720 spin_unlock_bh(&sky2
->phy_lock
);
3723 /* blink LED's for finding board */
3724 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3726 struct sky2_port
*sky2
= netdev_priv(dev
);
3732 for (i
= 0; i
< data
; i
++) {
3733 sky2_led(sky2
, MO_LED_ON
);
3734 if (msleep_interruptible(500))
3736 sky2_led(sky2
, MO_LED_OFF
);
3737 if (msleep_interruptible(500))
3740 sky2_led(sky2
, MO_LED_NORM
);
3745 static void sky2_get_pauseparam(struct net_device
*dev
,
3746 struct ethtool_pauseparam
*ecmd
)
3748 struct sky2_port
*sky2
= netdev_priv(dev
);
3750 switch (sky2
->flow_mode
) {
3752 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3755 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3758 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3761 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3764 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
)
3765 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3768 static int sky2_set_pauseparam(struct net_device
*dev
,
3769 struct ethtool_pauseparam
*ecmd
)
3771 struct sky2_port
*sky2
= netdev_priv(dev
);
3773 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
3774 sky2
->flags
|= SKY2_FLAG_AUTO_PAUSE
;
3776 sky2
->flags
&= ~SKY2_FLAG_AUTO_PAUSE
;
3778 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3780 if (netif_running(dev
))
3781 sky2_phy_reinit(sky2
);
3786 static int sky2_get_coalesce(struct net_device
*dev
,
3787 struct ethtool_coalesce
*ecmd
)
3789 struct sky2_port
*sky2
= netdev_priv(dev
);
3790 struct sky2_hw
*hw
= sky2
->hw
;
3792 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3793 ecmd
->tx_coalesce_usecs
= 0;
3795 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3796 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3798 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3800 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3801 ecmd
->rx_coalesce_usecs
= 0;
3803 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3804 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3806 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3808 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3809 ecmd
->rx_coalesce_usecs_irq
= 0;
3811 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3812 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3815 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3820 /* Note: this affect both ports */
3821 static int sky2_set_coalesce(struct net_device
*dev
,
3822 struct ethtool_coalesce
*ecmd
)
3824 struct sky2_port
*sky2
= netdev_priv(dev
);
3825 struct sky2_hw
*hw
= sky2
->hw
;
3826 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3828 if (ecmd
->tx_coalesce_usecs
> tmax
||
3829 ecmd
->rx_coalesce_usecs
> tmax
||
3830 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3833 if (ecmd
->tx_max_coalesced_frames
>= sky2
->tx_ring_size
-1)
3835 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3837 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3840 if (ecmd
->tx_coalesce_usecs
== 0)
3841 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3843 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3844 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3845 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3847 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3849 if (ecmd
->rx_coalesce_usecs
== 0)
3850 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3852 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3853 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3854 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3856 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3858 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3859 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3861 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3862 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3863 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3865 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3869 static void sky2_get_ringparam(struct net_device
*dev
,
3870 struct ethtool_ringparam
*ering
)
3872 struct sky2_port
*sky2
= netdev_priv(dev
);
3874 ering
->rx_max_pending
= RX_MAX_PENDING
;
3875 ering
->rx_mini_max_pending
= 0;
3876 ering
->rx_jumbo_max_pending
= 0;
3877 ering
->tx_max_pending
= TX_MAX_PENDING
;
3879 ering
->rx_pending
= sky2
->rx_pending
;
3880 ering
->rx_mini_pending
= 0;
3881 ering
->rx_jumbo_pending
= 0;
3882 ering
->tx_pending
= sky2
->tx_pending
;
3885 static int sky2_set_ringparam(struct net_device
*dev
,
3886 struct ethtool_ringparam
*ering
)
3888 struct sky2_port
*sky2
= netdev_priv(dev
);
3890 if (ering
->rx_pending
> RX_MAX_PENDING
||
3891 ering
->rx_pending
< 8 ||
3892 ering
->tx_pending
< TX_MIN_PENDING
||
3893 ering
->tx_pending
> TX_MAX_PENDING
)
3898 sky2
->rx_pending
= ering
->rx_pending
;
3899 sky2
->tx_pending
= ering
->tx_pending
;
3900 sky2
->tx_ring_size
= roundup_pow_of_two(sky2
->tx_pending
+1);
3902 return sky2_reattach(dev
);
3905 static int sky2_get_regs_len(struct net_device
*dev
)
3910 static int sky2_reg_access_ok(struct sky2_hw
*hw
, unsigned int b
)
3912 /* This complicated switch statement is to make sure and
3913 * only access regions that are unreserved.
3914 * Some blocks are only valid on dual port cards.
3918 case 5: /* Tx Arbiter 2 */
3920 case 14 ... 15: /* TX2 */
3921 case 17: case 19: /* Ram Buffer 2 */
3922 case 22 ... 23: /* Tx Ram Buffer 2 */
3923 case 25: /* Rx MAC Fifo 1 */
3924 case 27: /* Tx MAC Fifo 2 */
3925 case 31: /* GPHY 2 */
3926 case 40 ... 47: /* Pattern Ram 2 */
3927 case 52: case 54: /* TCP Segmentation 2 */
3928 case 112 ... 116: /* GMAC 2 */
3929 return hw
->ports
> 1;
3931 case 0: /* Control */
3932 case 2: /* Mac address */
3933 case 4: /* Tx Arbiter 1 */
3934 case 7: /* PCI express reg */
3936 case 12 ... 13: /* TX1 */
3937 case 16: case 18:/* Rx Ram Buffer 1 */
3938 case 20 ... 21: /* Tx Ram Buffer 1 */
3939 case 24: /* Rx MAC Fifo 1 */
3940 case 26: /* Tx MAC Fifo 1 */
3941 case 28 ... 29: /* Descriptor and status unit */
3942 case 30: /* GPHY 1*/
3943 case 32 ... 39: /* Pattern Ram 1 */
3944 case 48: case 50: /* TCP Segmentation 1 */
3945 case 56 ... 60: /* PCI space */
3946 case 80 ... 84: /* GMAC 1 */
3955 * Returns copy of control register region
3956 * Note: ethtool_get_regs always provides full size (16k) buffer
3958 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3961 const struct sky2_port
*sky2
= netdev_priv(dev
);
3962 const void __iomem
*io
= sky2
->hw
->regs
;
3967 for (b
= 0; b
< 128; b
++) {
3968 /* skip poisonous diagnostic ram region in block 3 */
3970 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
3971 else if (sky2_reg_access_ok(sky2
->hw
, b
))
3972 memcpy_fromio(p
, io
, 128);
3981 /* In order to do Jumbo packets on these chips, need to turn off the
3982 * transmit store/forward. Therefore checksum offload won't work.
3984 static int no_tx_offload(struct net_device
*dev
)
3986 const struct sky2_port
*sky2
= netdev_priv(dev
);
3987 const struct sky2_hw
*hw
= sky2
->hw
;
3989 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3992 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3994 if (data
&& no_tx_offload(dev
))
3997 return ethtool_op_set_tx_csum(dev
, data
);
4001 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
4003 if (data
&& no_tx_offload(dev
))
4006 return ethtool_op_set_tso(dev
, data
);
4009 static int sky2_get_eeprom_len(struct net_device
*dev
)
4011 struct sky2_port
*sky2
= netdev_priv(dev
);
4012 struct sky2_hw
*hw
= sky2
->hw
;
4015 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4016 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4019 static int sky2_vpd_wait(const struct sky2_hw
*hw
, int cap
, u16 busy
)
4021 unsigned long start
= jiffies
;
4023 while ( (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
) == busy
) {
4024 /* Can take up to 10.6 ms for write */
4025 if (time_after(jiffies
, start
+ HZ
/4)) {
4026 dev_err(&hw
->pdev
->dev
, "VPD cycle timed out\n");
4035 static int sky2_vpd_read(struct sky2_hw
*hw
, int cap
, void *data
,
4036 u16 offset
, size_t length
)
4040 while (length
> 0) {
4043 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
4044 rc
= sky2_vpd_wait(hw
, cap
, 0);
4048 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
4050 memcpy(data
, &val
, min(sizeof(val
), length
));
4051 offset
+= sizeof(u32
);
4052 data
+= sizeof(u32
);
4053 length
-= sizeof(u32
);
4059 static int sky2_vpd_write(struct sky2_hw
*hw
, int cap
, const void *data
,
4060 u16 offset
, unsigned int length
)
4065 for (i
= 0; i
< length
; i
+= sizeof(u32
)) {
4066 u32 val
= *(u32
*)(data
+ i
);
4068 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
4069 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
4071 rc
= sky2_vpd_wait(hw
, cap
, PCI_VPD_ADDR_F
);
4078 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4081 struct sky2_port
*sky2
= netdev_priv(dev
);
4082 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4087 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
4089 return sky2_vpd_read(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4092 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4095 struct sky2_port
*sky2
= netdev_priv(dev
);
4096 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4101 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
4104 /* Partial writes not supported */
4105 if ((eeprom
->offset
& 3) || (eeprom
->len
& 3))
4108 return sky2_vpd_write(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4112 static const struct ethtool_ops sky2_ethtool_ops
= {
4113 .get_settings
= sky2_get_settings
,
4114 .set_settings
= sky2_set_settings
,
4115 .get_drvinfo
= sky2_get_drvinfo
,
4116 .get_wol
= sky2_get_wol
,
4117 .set_wol
= sky2_set_wol
,
4118 .get_msglevel
= sky2_get_msglevel
,
4119 .set_msglevel
= sky2_set_msglevel
,
4120 .nway_reset
= sky2_nway_reset
,
4121 .get_regs_len
= sky2_get_regs_len
,
4122 .get_regs
= sky2_get_regs
,
4123 .get_link
= ethtool_op_get_link
,
4124 .get_eeprom_len
= sky2_get_eeprom_len
,
4125 .get_eeprom
= sky2_get_eeprom
,
4126 .set_eeprom
= sky2_set_eeprom
,
4127 .set_sg
= ethtool_op_set_sg
,
4128 .set_tx_csum
= sky2_set_tx_csum
,
4129 .set_tso
= sky2_set_tso
,
4130 .get_rx_csum
= sky2_get_rx_csum
,
4131 .set_rx_csum
= sky2_set_rx_csum
,
4132 .get_strings
= sky2_get_strings
,
4133 .get_coalesce
= sky2_get_coalesce
,
4134 .set_coalesce
= sky2_set_coalesce
,
4135 .get_ringparam
= sky2_get_ringparam
,
4136 .set_ringparam
= sky2_set_ringparam
,
4137 .get_pauseparam
= sky2_get_pauseparam
,
4138 .set_pauseparam
= sky2_set_pauseparam
,
4139 .phys_id
= sky2_phys_id
,
4140 .get_sset_count
= sky2_get_sset_count
,
4141 .get_ethtool_stats
= sky2_get_ethtool_stats
,
4144 #ifdef CONFIG_SKY2_DEBUG
4146 static struct dentry
*sky2_debug
;
4150 * Read and parse the first part of Vital Product Data
4152 #define VPD_SIZE 128
4153 #define VPD_MAGIC 0x82
4155 static const struct vpd_tag
{
4159 { "PN", "Part Number" },
4160 { "EC", "Engineering Level" },
4161 { "MN", "Manufacturer" },
4162 { "SN", "Serial Number" },
4163 { "YA", "Asset Tag" },
4164 { "VL", "First Error Log Message" },
4165 { "VF", "Second Error Log Message" },
4166 { "VB", "Boot Agent ROM Configuration" },
4167 { "VE", "EFI UNDI Configuration" },
4170 static void sky2_show_vpd(struct seq_file
*seq
, struct sky2_hw
*hw
)
4178 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4179 vpd_size
= 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4181 seq_printf(seq
, "%s Product Data\n", pci_name(hw
->pdev
));
4182 buf
= kmalloc(vpd_size
, GFP_KERNEL
);
4184 seq_puts(seq
, "no memory!\n");
4188 if (pci_read_vpd(hw
->pdev
, 0, vpd_size
, buf
) < 0) {
4189 seq_puts(seq
, "VPD read failed\n");
4193 if (buf
[0] != VPD_MAGIC
) {
4194 seq_printf(seq
, "VPD tag mismatch: %#x\n", buf
[0]);
4198 if (len
== 0 || len
> vpd_size
- 4) {
4199 seq_printf(seq
, "Invalid id length: %d\n", len
);
4203 seq_printf(seq
, "%.*s\n", len
, buf
+ 3);
4206 while (offs
< vpd_size
- 4) {
4209 if (!memcmp("RW", buf
+ offs
, 2)) /* end marker */
4211 len
= buf
[offs
+ 2];
4212 if (offs
+ len
+ 3 >= vpd_size
)
4215 for (i
= 0; i
< ARRAY_SIZE(vpd_tags
); i
++) {
4216 if (!memcmp(vpd_tags
[i
].tag
, buf
+ offs
, 2)) {
4217 seq_printf(seq
, " %s: %.*s\n",
4218 vpd_tags
[i
].label
, len
, buf
+ offs
+ 3);
4228 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
4230 struct net_device
*dev
= seq
->private;
4231 const struct sky2_port
*sky2
= netdev_priv(dev
);
4232 struct sky2_hw
*hw
= sky2
->hw
;
4233 unsigned port
= sky2
->port
;
4237 sky2_show_vpd(seq
, hw
);
4239 seq_printf(seq
, "\nIRQ src=%x mask=%x control=%x\n",
4240 sky2_read32(hw
, B0_ISRC
),
4241 sky2_read32(hw
, B0_IMSK
),
4242 sky2_read32(hw
, B0_Y2_SP_ICR
));
4244 if (!netif_running(dev
)) {
4245 seq_printf(seq
, "network not running\n");
4249 napi_disable(&hw
->napi
);
4250 last
= sky2_read16(hw
, STAT_PUT_IDX
);
4252 if (hw
->st_idx
== last
)
4253 seq_puts(seq
, "Status ring (empty)\n");
4255 seq_puts(seq
, "Status ring\n");
4256 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
4257 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
4258 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
4259 seq_printf(seq
, "[%d] %#x %d %#x\n",
4260 idx
, le
->opcode
, le
->length
, le
->status
);
4262 seq_puts(seq
, "\n");
4265 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
4266 sky2
->tx_cons
, sky2
->tx_prod
,
4267 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
4268 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
4270 /* Dump contents of tx ring */
4272 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< sky2
->tx_ring_size
;
4273 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
4274 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
4275 u32 a
= le32_to_cpu(le
->addr
);
4278 seq_printf(seq
, "%u:", idx
);
4281 switch(le
->opcode
& ~HW_OWNER
) {
4283 seq_printf(seq
, " %#x:", a
);
4286 seq_printf(seq
, " mtu=%d", a
);
4289 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
4292 seq_printf(seq
, " csum=%#x", a
);
4295 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
4298 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
4301 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
4304 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
4305 a
, le16_to_cpu(le
->length
));
4308 if (le
->ctrl
& EOP
) {
4309 seq_putc(seq
, '\n');
4314 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
4315 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
4316 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
4317 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
4319 sky2_read32(hw
, B0_Y2_SP_LISR
);
4320 napi_enable(&hw
->napi
);
4324 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
4326 return single_open(file
, sky2_debug_show
, inode
->i_private
);
4329 static const struct file_operations sky2_debug_fops
= {
4330 .owner
= THIS_MODULE
,
4331 .open
= sky2_debug_open
,
4333 .llseek
= seq_lseek
,
4334 .release
= single_release
,
4338 * Use network device events to create/remove/rename
4339 * debugfs file entries
4341 static int sky2_device_event(struct notifier_block
*unused
,
4342 unsigned long event
, void *ptr
)
4344 struct net_device
*dev
= ptr
;
4345 struct sky2_port
*sky2
= netdev_priv(dev
);
4347 if (dev
->netdev_ops
->ndo_open
!= sky2_up
|| !sky2_debug
)
4351 case NETDEV_CHANGENAME
:
4352 if (sky2
->debugfs
) {
4353 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
4354 sky2_debug
, dev
->name
);
4358 case NETDEV_GOING_DOWN
:
4359 if (sky2
->debugfs
) {
4360 netdev_printk(KERN_DEBUG
, dev
, "remove debugfs\n");
4361 debugfs_remove(sky2
->debugfs
);
4362 sky2
->debugfs
= NULL
;
4367 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
4370 if (IS_ERR(sky2
->debugfs
))
4371 sky2
->debugfs
= NULL
;
4377 static struct notifier_block sky2_notifier
= {
4378 .notifier_call
= sky2_device_event
,
4382 static __init
void sky2_debug_init(void)
4386 ent
= debugfs_create_dir("sky2", NULL
);
4387 if (!ent
|| IS_ERR(ent
))
4391 register_netdevice_notifier(&sky2_notifier
);
4394 static __exit
void sky2_debug_cleanup(void)
4397 unregister_netdevice_notifier(&sky2_notifier
);
4398 debugfs_remove(sky2_debug
);
4404 #define sky2_debug_init()
4405 #define sky2_debug_cleanup()
4408 /* Two copies of network device operations to handle special case of
4409 not allowing netpoll on second port */
4410 static const struct net_device_ops sky2_netdev_ops
[2] = {
4412 .ndo_open
= sky2_up
,
4413 .ndo_stop
= sky2_down
,
4414 .ndo_start_xmit
= sky2_xmit_frame
,
4415 .ndo_do_ioctl
= sky2_ioctl
,
4416 .ndo_validate_addr
= eth_validate_addr
,
4417 .ndo_set_mac_address
= sky2_set_mac_address
,
4418 .ndo_set_multicast_list
= sky2_set_multicast
,
4419 .ndo_change_mtu
= sky2_change_mtu
,
4420 .ndo_tx_timeout
= sky2_tx_timeout
,
4421 #ifdef SKY2_VLAN_TAG_USED
4422 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4424 #ifdef CONFIG_NET_POLL_CONTROLLER
4425 .ndo_poll_controller
= sky2_netpoll
,
4429 .ndo_open
= sky2_up
,
4430 .ndo_stop
= sky2_down
,
4431 .ndo_start_xmit
= sky2_xmit_frame
,
4432 .ndo_do_ioctl
= sky2_ioctl
,
4433 .ndo_validate_addr
= eth_validate_addr
,
4434 .ndo_set_mac_address
= sky2_set_mac_address
,
4435 .ndo_set_multicast_list
= sky2_set_multicast
,
4436 .ndo_change_mtu
= sky2_change_mtu
,
4437 .ndo_tx_timeout
= sky2_tx_timeout
,
4438 #ifdef SKY2_VLAN_TAG_USED
4439 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4444 /* Initialize network device */
4445 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
4447 int highmem
, int wol
)
4449 struct sky2_port
*sky2
;
4450 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4453 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
4457 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4458 dev
->irq
= hw
->pdev
->irq
;
4459 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4460 dev
->watchdog_timeo
= TX_WATCHDOG
;
4461 dev
->netdev_ops
= &sky2_netdev_ops
[port
];
4463 sky2
= netdev_priv(dev
);
4466 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4468 /* Auto speed and flow control */
4469 sky2
->flags
= SKY2_FLAG_AUTO_SPEED
| SKY2_FLAG_AUTO_PAUSE
;
4470 if (hw
->chip_id
!= CHIP_ID_YUKON_XL
)
4471 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
4473 sky2
->flow_mode
= FC_BOTH
;
4477 sky2
->advertising
= sky2_supported_modes(hw
);
4480 spin_lock_init(&sky2
->phy_lock
);
4482 sky2
->tx_pending
= TX_DEF_PENDING
;
4483 sky2
->tx_ring_size
= roundup_pow_of_two(TX_DEF_PENDING
+1);
4484 sky2
->rx_pending
= RX_DEF_PENDING
;
4486 hw
->dev
[port
] = dev
;
4490 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
4492 dev
->features
|= NETIF_F_HIGHDMA
;
4494 #ifdef SKY2_VLAN_TAG_USED
4495 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4496 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
4497 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
4498 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4502 /* read the mac address */
4503 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4504 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4509 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4511 const struct sky2_port
*sky2
= netdev_priv(dev
);
4513 netif_info(sky2
, probe
, dev
, "addr %pM\n", dev
->dev_addr
);
4516 /* Handle software interrupt used during MSI test */
4517 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4519 struct sky2_hw
*hw
= dev_id
;
4520 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4525 if (status
& Y2_IS_IRQ_SW
) {
4526 hw
->flags
|= SKY2_HW_USE_MSI
;
4527 wake_up(&hw
->msi_wait
);
4528 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4530 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4535 /* Test interrupt path by forcing a a software IRQ */
4536 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4538 struct pci_dev
*pdev
= hw
->pdev
;
4541 init_waitqueue_head (&hw
->msi_wait
);
4543 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4545 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4547 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4551 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4552 sky2_read8(hw
, B0_CTST
);
4554 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4556 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4557 /* MSI test failed, go back to INTx mode */
4558 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4559 "switching to INTx mode.\n");
4562 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4565 sky2_write32(hw
, B0_IMSK
, 0);
4566 sky2_read32(hw
, B0_IMSK
);
4568 free_irq(pdev
->irq
, hw
);
4573 /* This driver supports yukon2 chipset only */
4574 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4576 const char *name
[] = {
4578 "EC Ultra", /* 0xb4 */
4579 "Extreme", /* 0xb5 */
4583 "Supreme", /* 0xb9 */
4585 "Unknown", /* 0xbb */
4586 "Optima", /* 0xbc */
4589 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
<= CHIP_ID_YUKON_OPT
)
4590 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4592 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4596 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4597 const struct pci_device_id
*ent
)
4599 struct net_device
*dev
;
4601 int err
, using_dac
= 0, wol_default
;
4605 err
= pci_enable_device(pdev
);
4607 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4611 /* Get configuration information
4612 * Note: only regular PCI config access once to test for HW issues
4613 * other PCI access through shared memory for speed and to
4614 * avoid MMCONFIG problems.
4616 err
= pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
4618 dev_err(&pdev
->dev
, "PCI read config failed\n");
4623 dev_err(&pdev
->dev
, "PCI configuration read error\n");
4627 err
= pci_request_regions(pdev
, DRV_NAME
);
4629 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4630 goto err_out_disable
;
4633 pci_set_master(pdev
);
4635 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4636 !(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
4638 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4640 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4641 "for consistent allocations\n");
4642 goto err_out_free_regions
;
4645 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4647 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4648 goto err_out_free_regions
;
4654 /* The sk98lin vendor driver uses hardware byte swapping but
4655 * this driver uses software swapping.
4657 reg
&= ~PCI_REV_DESC
;
4658 err
= pci_write_config_dword(pdev
,PCI_DEV_REG2
, reg
);
4660 dev_err(&pdev
->dev
, "PCI write config failed\n");
4661 goto err_out_free_regions
;
4665 wol_default
= device_may_wakeup(&pdev
->dev
) ? WAKE_MAGIC
: 0;
4669 hw
= kzalloc(sizeof(*hw
) + strlen(DRV_NAME
"@pci:")
4670 + strlen(pci_name(pdev
)) + 1, GFP_KERNEL
);
4672 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4673 goto err_out_free_regions
;
4677 sprintf(hw
->irq_name
, DRV_NAME
"@pci:%s", pci_name(pdev
));
4679 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4681 dev_err(&pdev
->dev
, "cannot map device registers\n");
4682 goto err_out_free_hw
;
4685 /* ring for status responses */
4686 hw
->st_le
= pci_alloc_consistent(pdev
, STATUS_LE_BYTES
, &hw
->st_dma
);
4688 goto err_out_iounmap
;
4690 err
= sky2_init(hw
);
4692 goto err_out_iounmap
;
4694 dev_info(&pdev
->dev
, "Yukon-2 %s chip revision %d\n",
4695 sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)), hw
->chip_rev
);
4699 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4702 goto err_out_free_pci
;
4705 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4706 err
= sky2_test_msi(hw
);
4707 if (err
== -EOPNOTSUPP
)
4708 pci_disable_msi(pdev
);
4710 goto err_out_free_netdev
;
4713 err
= register_netdev(dev
);
4715 dev_err(&pdev
->dev
, "cannot register net device\n");
4716 goto err_out_free_netdev
;
4719 netif_carrier_off(dev
);
4721 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
4723 err
= request_irq(pdev
->irq
, sky2_intr
,
4724 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4727 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4728 goto err_out_unregister
;
4730 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4731 napi_enable(&hw
->napi
);
4733 sky2_show_addr(dev
);
4735 if (hw
->ports
> 1) {
4736 struct net_device
*dev1
;
4739 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4740 if (dev1
&& (err
= register_netdev(dev1
)) == 0)
4741 sky2_show_addr(dev1
);
4743 dev_warn(&pdev
->dev
,
4744 "register of second port failed (%d)\n", err
);
4752 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4753 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4755 pci_set_drvdata(pdev
, hw
);
4756 pdev
->d3_delay
= 150;
4761 if (hw
->flags
& SKY2_HW_USE_MSI
)
4762 pci_disable_msi(pdev
);
4763 unregister_netdev(dev
);
4764 err_out_free_netdev
:
4767 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4768 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4773 err_out_free_regions
:
4774 pci_release_regions(pdev
);
4776 pci_disable_device(pdev
);
4778 pci_set_drvdata(pdev
, NULL
);
4782 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4784 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4790 del_timer_sync(&hw
->watchdog_timer
);
4791 cancel_work_sync(&hw
->restart_work
);
4793 for (i
= hw
->ports
-1; i
>= 0; --i
)
4794 unregister_netdev(hw
->dev
[i
]);
4796 sky2_write32(hw
, B0_IMSK
, 0);
4800 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4801 sky2_read8(hw
, B0_CTST
);
4803 free_irq(pdev
->irq
, hw
);
4804 if (hw
->flags
& SKY2_HW_USE_MSI
)
4805 pci_disable_msi(pdev
);
4806 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4807 pci_release_regions(pdev
);
4808 pci_disable_device(pdev
);
4810 for (i
= hw
->ports
-1; i
>= 0; --i
)
4811 free_netdev(hw
->dev
[i
]);
4816 pci_set_drvdata(pdev
, NULL
);
4819 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4821 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4827 del_timer_sync(&hw
->watchdog_timer
);
4828 cancel_work_sync(&hw
->restart_work
);
4831 for (i
= 0; i
< hw
->ports
; i
++) {
4832 struct net_device
*dev
= hw
->dev
[i
];
4833 struct sky2_port
*sky2
= netdev_priv(dev
);
4838 sky2_wol_init(sky2
);
4843 device_set_wakeup_enable(&pdev
->dev
, wol
!= 0);
4845 sky2_write32(hw
, B0_IMSK
, 0);
4846 napi_disable(&hw
->napi
);
4850 pci_save_state(pdev
);
4851 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4852 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4858 static int sky2_resume(struct pci_dev
*pdev
)
4860 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4866 err
= pci_set_power_state(pdev
, PCI_D0
);
4870 err
= pci_restore_state(pdev
);
4874 pci_enable_wake(pdev
, PCI_D0
, 0);
4876 /* Re-enable all clocks */
4877 err
= pci_write_config_dword(pdev
, PCI_DEV_REG3
, 0);
4879 dev_err(&pdev
->dev
, "PCI write config failed\n");
4884 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4885 napi_enable(&hw
->napi
);
4888 for (i
= 0; i
< hw
->ports
; i
++) {
4889 err
= sky2_reattach(hw
->dev
[i
]);
4899 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4900 pci_disable_device(pdev
);
4905 static void sky2_shutdown(struct pci_dev
*pdev
)
4907 sky2_suspend(pdev
, PMSG_SUSPEND
);
4910 static struct pci_driver sky2_driver
= {
4912 .id_table
= sky2_id_table
,
4913 .probe
= sky2_probe
,
4914 .remove
= __devexit_p(sky2_remove
),
4916 .suspend
= sky2_suspend
,
4917 .resume
= sky2_resume
,
4919 .shutdown
= sky2_shutdown
,
4922 static int __init
sky2_init_module(void)
4924 pr_info("driver version " DRV_VERSION
"\n");
4927 return pci_register_driver(&sky2_driver
);
4930 static void __exit
sky2_cleanup_module(void)
4932 pci_unregister_driver(&sky2_driver
);
4933 sky2_debug_cleanup();
4936 module_init(sky2_init_module
);
4937 module_exit(sky2_cleanup_module
);
4939 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4940 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4941 MODULE_LICENSE("GPL");
4942 MODULE_VERSION(DRV_VERSION
);