2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
38 #include <linux/string.h>
39 #include <linux/slab.h>
40 #include <linux/sched.h>
44 #include <rdma/ib_verbs.h>
45 #include <rdma/ib_cache.h>
46 #include <rdma/ib_pack.h>
48 #include "mthca_dev.h"
49 #include "mthca_cmd.h"
50 #include "mthca_memfree.h"
51 #include "mthca_wqe.h"
54 MTHCA_MAX_DIRECT_QP_SIZE
= 4 * PAGE_SIZE
,
55 MTHCA_ACK_REQ_FREQ
= 10,
56 MTHCA_FLIGHT_LIMIT
= 9,
57 MTHCA_UD_HEADER_SIZE
= 72, /* largest UD header possible */
58 MTHCA_INLINE_HEADER_SIZE
= 4, /* data segment overhead for inline */
59 MTHCA_INLINE_CHUNK_SIZE
= 16 /* inline data segment chunk */
63 MTHCA_QP_STATE_RST
= 0,
64 MTHCA_QP_STATE_INIT
= 1,
65 MTHCA_QP_STATE_RTR
= 2,
66 MTHCA_QP_STATE_RTS
= 3,
67 MTHCA_QP_STATE_SQE
= 4,
68 MTHCA_QP_STATE_SQD
= 5,
69 MTHCA_QP_STATE_ERR
= 6,
70 MTHCA_QP_STATE_DRAINING
= 7
82 MTHCA_QP_PM_MIGRATED
= 0x3,
83 MTHCA_QP_PM_ARMED
= 0x0,
84 MTHCA_QP_PM_REARM
= 0x1
88 /* qp_context flags */
89 MTHCA_QP_BIT_DE
= 1 << 8,
91 MTHCA_QP_BIT_SRE
= 1 << 15,
92 MTHCA_QP_BIT_SWE
= 1 << 14,
93 MTHCA_QP_BIT_SAE
= 1 << 13,
94 MTHCA_QP_BIT_SIC
= 1 << 4,
95 MTHCA_QP_BIT_SSC
= 1 << 3,
97 MTHCA_QP_BIT_RRE
= 1 << 15,
98 MTHCA_QP_BIT_RWE
= 1 << 14,
99 MTHCA_QP_BIT_RAE
= 1 << 13,
100 MTHCA_QP_BIT_RIC
= 1 << 4,
101 MTHCA_QP_BIT_RSC
= 1 << 3
105 MTHCA_SEND_DOORBELL_FENCE
= 1 << 5
108 struct mthca_qp_path
{
117 __be32 sl_tclass_flowlabel
;
119 } __attribute__((packed
));
121 struct mthca_qp_context
{
123 __be32 tavor_sched_queue
; /* Reserved on Arbel */
125 u8 rq_size_stride
; /* Reserved on Tavor */
126 u8 sq_size_stride
; /* Reserved on Tavor */
127 u8 rlkey_arbel_sched_queue
; /* Reserved on Tavor */
132 struct mthca_qp_path pri_path
;
133 struct mthca_qp_path alt_path
;
140 __be32 next_send_psn
;
142 __be32 snd_wqe_base_l
; /* Next send WQE on Tavor */
143 __be32 snd_db_index
; /* (debugging only entries) */
144 __be32 last_acked_psn
;
147 __be32 rnr_nextrecvpsn
;
150 __be32 rcv_wqe_base_l
; /* Next recv WQE on Tavor */
151 __be32 rcv_db_index
; /* (debugging only entries) */
155 __be16 rq_wqe_counter
; /* reserved on Tavor */
156 __be16 sq_wqe_counter
; /* reserved on Tavor */
158 } __attribute__((packed
));
160 struct mthca_qp_param
{
161 __be32 opt_param_mask
;
163 struct mthca_qp_context context
;
165 } __attribute__((packed
));
168 MTHCA_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
169 MTHCA_QP_OPTPAR_RRE
= 1 << 1,
170 MTHCA_QP_OPTPAR_RAE
= 1 << 2,
171 MTHCA_QP_OPTPAR_RWE
= 1 << 3,
172 MTHCA_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
173 MTHCA_QP_OPTPAR_Q_KEY
= 1 << 5,
174 MTHCA_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
175 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
176 MTHCA_QP_OPTPAR_SRA_MAX
= 1 << 8,
177 MTHCA_QP_OPTPAR_RRA_MAX
= 1 << 9,
178 MTHCA_QP_OPTPAR_PM_STATE
= 1 << 10,
179 MTHCA_QP_OPTPAR_PORT_NUM
= 1 << 11,
180 MTHCA_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
181 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
= 1 << 13,
182 MTHCA_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
183 MTHCA_QP_OPTPAR_RNR_RETRY
= 1 << 15,
184 MTHCA_QP_OPTPAR_SCHED_QUEUE
= 1 << 16
187 static const u8 mthca_opcode
[] = {
188 [IB_WR_SEND
] = MTHCA_OPCODE_SEND
,
189 [IB_WR_SEND_WITH_IMM
] = MTHCA_OPCODE_SEND_IMM
,
190 [IB_WR_RDMA_WRITE
] = MTHCA_OPCODE_RDMA_WRITE
,
191 [IB_WR_RDMA_WRITE_WITH_IMM
] = MTHCA_OPCODE_RDMA_WRITE_IMM
,
192 [IB_WR_RDMA_READ
] = MTHCA_OPCODE_RDMA_READ
,
193 [IB_WR_ATOMIC_CMP_AND_SWP
] = MTHCA_OPCODE_ATOMIC_CS
,
194 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MTHCA_OPCODE_ATOMIC_FA
,
197 static int is_sqp(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
199 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
200 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 3;
203 static int is_qp0(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
205 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
206 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 1;
209 static void *get_recv_wqe(struct mthca_qp
*qp
, int n
)
212 return qp
->queue
.direct
.buf
+ (n
<< qp
->rq
.wqe_shift
);
214 return qp
->queue
.page_list
[(n
<< qp
->rq
.wqe_shift
) >> PAGE_SHIFT
].buf
+
215 ((n
<< qp
->rq
.wqe_shift
) & (PAGE_SIZE
- 1));
218 static void *get_send_wqe(struct mthca_qp
*qp
, int n
)
221 return qp
->queue
.direct
.buf
+ qp
->send_wqe_offset
+
222 (n
<< qp
->sq
.wqe_shift
);
224 return qp
->queue
.page_list
[(qp
->send_wqe_offset
+
225 (n
<< qp
->sq
.wqe_shift
)) >>
227 ((qp
->send_wqe_offset
+ (n
<< qp
->sq
.wqe_shift
)) &
231 static void mthca_wq_reset(struct mthca_wq
*wq
)
234 wq
->last_comp
= wq
->max
- 1;
239 void mthca_qp_event(struct mthca_dev
*dev
, u32 qpn
,
240 enum ib_event_type event_type
)
243 struct ib_event event
;
245 spin_lock(&dev
->qp_table
.lock
);
246 qp
= mthca_array_get(&dev
->qp_table
.qp
, qpn
& (dev
->limits
.num_qps
- 1));
249 spin_unlock(&dev
->qp_table
.lock
);
252 mthca_warn(dev
, "Async event for bogus QP %08x\n", qpn
);
256 if (event_type
== IB_EVENT_PATH_MIG
)
257 qp
->port
= qp
->alt_port
;
259 event
.device
= &dev
->ib_dev
;
260 event
.event
= event_type
;
261 event
.element
.qp
= &qp
->ibqp
;
262 if (qp
->ibqp
.event_handler
)
263 qp
->ibqp
.event_handler(&event
, qp
->ibqp
.qp_context
);
265 spin_lock(&dev
->qp_table
.lock
);
268 spin_unlock(&dev
->qp_table
.lock
);
271 static int to_mthca_state(enum ib_qp_state ib_state
)
274 case IB_QPS_RESET
: return MTHCA_QP_STATE_RST
;
275 case IB_QPS_INIT
: return MTHCA_QP_STATE_INIT
;
276 case IB_QPS_RTR
: return MTHCA_QP_STATE_RTR
;
277 case IB_QPS_RTS
: return MTHCA_QP_STATE_RTS
;
278 case IB_QPS_SQD
: return MTHCA_QP_STATE_SQD
;
279 case IB_QPS_SQE
: return MTHCA_QP_STATE_SQE
;
280 case IB_QPS_ERR
: return MTHCA_QP_STATE_ERR
;
285 enum { RC
, UC
, UD
, RD
, RDEE
, MLX
, NUM_TRANS
};
287 static int to_mthca_st(int transport
)
290 case RC
: return MTHCA_QP_ST_RC
;
291 case UC
: return MTHCA_QP_ST_UC
;
292 case UD
: return MTHCA_QP_ST_UD
;
293 case RD
: return MTHCA_QP_ST_RD
;
294 case MLX
: return MTHCA_QP_ST_MLX
;
299 static void store_attrs(struct mthca_sqp
*sqp
, const struct ib_qp_attr
*attr
,
302 if (attr_mask
& IB_QP_PKEY_INDEX
)
303 sqp
->pkey_index
= attr
->pkey_index
;
304 if (attr_mask
& IB_QP_QKEY
)
305 sqp
->qkey
= attr
->qkey
;
306 if (attr_mask
& IB_QP_SQ_PSN
)
307 sqp
->send_psn
= attr
->sq_psn
;
310 static void init_port(struct mthca_dev
*dev
, int port
)
314 struct mthca_init_ib_param param
;
316 memset(¶m
, 0, sizeof param
);
318 param
.port_width
= dev
->limits
.port_width_cap
;
319 param
.vl_cap
= dev
->limits
.vl_cap
;
320 param
.mtu_cap
= dev
->limits
.mtu_cap
;
321 param
.gid_cap
= dev
->limits
.gid_table_len
;
322 param
.pkey_cap
= dev
->limits
.pkey_table_len
;
324 err
= mthca_INIT_IB(dev
, ¶m
, port
, &status
);
326 mthca_warn(dev
, "INIT_IB failed, return code %d.\n", err
);
328 mthca_warn(dev
, "INIT_IB returned status %02x.\n", status
);
331 static __be32
get_hw_access_flags(struct mthca_qp
*qp
, const struct ib_qp_attr
*attr
,
336 u32 hw_access_flags
= 0;
338 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
339 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
341 dest_rd_atomic
= qp
->resp_depth
;
343 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
344 access_flags
= attr
->qp_access_flags
;
346 access_flags
= qp
->atomic_rd_en
;
349 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
351 if (access_flags
& IB_ACCESS_REMOTE_READ
)
352 hw_access_flags
|= MTHCA_QP_BIT_RRE
;
353 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
354 hw_access_flags
|= MTHCA_QP_BIT_RAE
;
355 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
356 hw_access_flags
|= MTHCA_QP_BIT_RWE
;
358 return cpu_to_be32(hw_access_flags
);
361 static inline enum ib_qp_state
to_ib_qp_state(int mthca_state
)
363 switch (mthca_state
) {
364 case MTHCA_QP_STATE_RST
: return IB_QPS_RESET
;
365 case MTHCA_QP_STATE_INIT
: return IB_QPS_INIT
;
366 case MTHCA_QP_STATE_RTR
: return IB_QPS_RTR
;
367 case MTHCA_QP_STATE_RTS
: return IB_QPS_RTS
;
368 case MTHCA_QP_STATE_DRAINING
:
369 case MTHCA_QP_STATE_SQD
: return IB_QPS_SQD
;
370 case MTHCA_QP_STATE_SQE
: return IB_QPS_SQE
;
371 case MTHCA_QP_STATE_ERR
: return IB_QPS_ERR
;
376 static inline enum ib_mig_state
to_ib_mig_state(int mthca_mig_state
)
378 switch (mthca_mig_state
) {
379 case 0: return IB_MIG_ARMED
;
380 case 1: return IB_MIG_REARM
;
381 case 3: return IB_MIG_MIGRATED
;
386 static int to_ib_qp_access_flags(int mthca_flags
)
390 if (mthca_flags
& MTHCA_QP_BIT_RRE
)
391 ib_flags
|= IB_ACCESS_REMOTE_READ
;
392 if (mthca_flags
& MTHCA_QP_BIT_RWE
)
393 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
394 if (mthca_flags
& MTHCA_QP_BIT_RAE
)
395 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
400 static void to_ib_ah_attr(struct mthca_dev
*dev
, struct ib_ah_attr
*ib_ah_attr
,
401 struct mthca_qp_path
*path
)
403 memset(ib_ah_attr
, 0, sizeof *ib_ah_attr
);
404 ib_ah_attr
->port_num
= (be32_to_cpu(path
->port_pkey
) >> 24) & 0x3;
406 if (ib_ah_attr
->port_num
== 0 || ib_ah_attr
->port_num
> dev
->limits
.num_ports
)
409 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
410 ib_ah_attr
->sl
= be32_to_cpu(path
->sl_tclass_flowlabel
) >> 28;
411 ib_ah_attr
->src_path_bits
= path
->g_mylmc
& 0x7f;
412 ib_ah_attr
->static_rate
= mthca_rate_to_ib(dev
,
413 path
->static_rate
& 0xf,
414 ib_ah_attr
->port_num
);
415 ib_ah_attr
->ah_flags
= (path
->g_mylmc
& (1 << 7)) ? IB_AH_GRH
: 0;
416 if (ib_ah_attr
->ah_flags
) {
417 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
& (dev
->limits
.gid_table_len
- 1);
418 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
419 ib_ah_attr
->grh
.traffic_class
=
420 (be32_to_cpu(path
->sl_tclass_flowlabel
) >> 20) & 0xff;
421 ib_ah_attr
->grh
.flow_label
=
422 be32_to_cpu(path
->sl_tclass_flowlabel
) & 0xfffff;
423 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
424 path
->rgid
, sizeof ib_ah_attr
->grh
.dgid
.raw
);
428 int mthca_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
429 struct ib_qp_init_attr
*qp_init_attr
)
431 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
432 struct mthca_qp
*qp
= to_mqp(ibqp
);
434 struct mthca_mailbox
*mailbox
= NULL
;
435 struct mthca_qp_param
*qp_param
;
436 struct mthca_qp_context
*context
;
440 if (qp
->state
== IB_QPS_RESET
) {
441 qp_attr
->qp_state
= IB_QPS_RESET
;
445 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
447 return PTR_ERR(mailbox
);
449 err
= mthca_QUERY_QP(dev
, qp
->qpn
, 0, mailbox
, &status
);
453 mthca_warn(dev
, "QUERY_QP returned status %02x\n", status
);
458 qp_param
= mailbox
->buf
;
459 context
= &qp_param
->context
;
460 mthca_state
= be32_to_cpu(context
->flags
) >> 28;
462 qp_attr
->qp_state
= to_ib_qp_state(mthca_state
);
463 qp_attr
->path_mtu
= context
->mtu_msgmax
>> 5;
464 qp_attr
->path_mig_state
=
465 to_ib_mig_state((be32_to_cpu(context
->flags
) >> 11) & 0x3);
466 qp_attr
->qkey
= be32_to_cpu(context
->qkey
);
467 qp_attr
->rq_psn
= be32_to_cpu(context
->rnr_nextrecvpsn
) & 0xffffff;
468 qp_attr
->sq_psn
= be32_to_cpu(context
->next_send_psn
) & 0xffffff;
469 qp_attr
->dest_qp_num
= be32_to_cpu(context
->remote_qpn
) & 0xffffff;
470 qp_attr
->qp_access_flags
=
471 to_ib_qp_access_flags(be32_to_cpu(context
->params2
));
473 if (qp
->transport
== RC
|| qp
->transport
== UC
) {
474 to_ib_ah_attr(dev
, &qp_attr
->ah_attr
, &context
->pri_path
);
475 to_ib_ah_attr(dev
, &qp_attr
->alt_ah_attr
, &context
->alt_path
);
476 qp_attr
->alt_pkey_index
=
477 be32_to_cpu(context
->alt_path
.port_pkey
) & 0x7f;
478 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
481 qp_attr
->pkey_index
= be32_to_cpu(context
->pri_path
.port_pkey
) & 0x7f;
483 (be32_to_cpu(context
->pri_path
.port_pkey
) >> 24) & 0x3;
485 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
486 qp_attr
->sq_draining
= mthca_state
== MTHCA_QP_STATE_DRAINING
;
488 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
->params1
) >> 21) & 0x7);
490 qp_attr
->max_dest_rd_atomic
=
491 1 << ((be32_to_cpu(context
->params2
) >> 21) & 0x7);
492 qp_attr
->min_rnr_timer
=
493 (be32_to_cpu(context
->rnr_nextrecvpsn
) >> 24) & 0x1f;
494 qp_attr
->timeout
= context
->pri_path
.ackto
>> 3;
495 qp_attr
->retry_cnt
= (be32_to_cpu(context
->params1
) >> 16) & 0x7;
496 qp_attr
->rnr_retry
= context
->pri_path
.rnr_retry
>> 5;
497 qp_attr
->alt_timeout
= context
->alt_path
.ackto
>> 3;
500 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
501 qp_attr
->cap
.max_send_wr
= qp
->sq
.max
;
502 qp_attr
->cap
.max_recv_wr
= qp
->rq
.max
;
503 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
504 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
505 qp_attr
->cap
.max_inline_data
= qp
->max_inline_data
;
507 qp_init_attr
->cap
= qp_attr
->cap
;
510 mthca_free_mailbox(dev
, mailbox
);
514 static int mthca_path_set(struct mthca_dev
*dev
, const struct ib_ah_attr
*ah
,
515 struct mthca_qp_path
*path
, u8 port
)
517 path
->g_mylmc
= ah
->src_path_bits
& 0x7f;
518 path
->rlid
= cpu_to_be16(ah
->dlid
);
519 path
->static_rate
= mthca_get_rate(dev
, ah
->static_rate
, port
);
521 if (ah
->ah_flags
& IB_AH_GRH
) {
522 if (ah
->grh
.sgid_index
>= dev
->limits
.gid_table_len
) {
523 mthca_dbg(dev
, "sgid_index (%u) too large. max is %d\n",
524 ah
->grh
.sgid_index
, dev
->limits
.gid_table_len
-1);
528 path
->g_mylmc
|= 1 << 7;
529 path
->mgid_index
= ah
->grh
.sgid_index
;
530 path
->hop_limit
= ah
->grh
.hop_limit
;
531 path
->sl_tclass_flowlabel
=
532 cpu_to_be32((ah
->sl
<< 28) |
533 (ah
->grh
.traffic_class
<< 20) |
534 (ah
->grh
.flow_label
));
535 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
537 path
->sl_tclass_flowlabel
= cpu_to_be32(ah
->sl
<< 28);
542 static int __mthca_modify_qp(struct ib_qp
*ibqp
,
543 const struct ib_qp_attr
*attr
, int attr_mask
,
544 enum ib_qp_state cur_state
, enum ib_qp_state new_state
)
546 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
547 struct mthca_qp
*qp
= to_mqp(ibqp
);
548 struct mthca_mailbox
*mailbox
;
549 struct mthca_qp_param
*qp_param
;
550 struct mthca_qp_context
*qp_context
;
555 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
556 if (IS_ERR(mailbox
)) {
557 err
= PTR_ERR(mailbox
);
560 qp_param
= mailbox
->buf
;
561 qp_context
= &qp_param
->context
;
562 memset(qp_param
, 0, sizeof *qp_param
);
564 qp_context
->flags
= cpu_to_be32((to_mthca_state(new_state
) << 28) |
565 (to_mthca_st(qp
->transport
) << 16));
566 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_BIT_DE
);
567 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
568 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
570 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE
);
571 switch (attr
->path_mig_state
) {
572 case IB_MIG_MIGRATED
:
573 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
576 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_REARM
<< 11);
579 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_ARMED
<< 11);
584 /* leave tavor_sched_queue as 0 */
586 if (qp
->transport
== MLX
|| qp
->transport
== UD
)
587 qp_context
->mtu_msgmax
= (IB_MTU_2048
<< 5) | 11;
588 else if (attr_mask
& IB_QP_PATH_MTU
) {
589 if (attr
->path_mtu
< IB_MTU_256
|| attr
->path_mtu
> IB_MTU_2048
) {
590 mthca_dbg(dev
, "path MTU (%u) is invalid\n",
594 qp_context
->mtu_msgmax
= (attr
->path_mtu
<< 5) | 31;
597 if (mthca_is_memfree(dev
)) {
599 qp_context
->rq_size_stride
= ilog2(qp
->rq
.max
) << 3;
600 qp_context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
603 qp_context
->sq_size_stride
= ilog2(qp
->sq
.max
) << 3;
604 qp_context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
607 /* leave arbel_sched_queue as 0 */
609 if (qp
->ibqp
.uobject
)
610 qp_context
->usr_page
=
611 cpu_to_be32(to_mucontext(qp
->ibqp
.uobject
->context
)->uar
.index
);
613 qp_context
->usr_page
= cpu_to_be32(dev
->driver_uar
.index
);
614 qp_context
->local_qpn
= cpu_to_be32(qp
->qpn
);
615 if (attr_mask
& IB_QP_DEST_QPN
) {
616 qp_context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
619 if (qp
->transport
== MLX
)
620 qp_context
->pri_path
.port_pkey
|=
621 cpu_to_be32(qp
->port
<< 24);
623 if (attr_mask
& IB_QP_PORT
) {
624 qp_context
->pri_path
.port_pkey
|=
625 cpu_to_be32(attr
->port_num
<< 24);
626 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM
);
630 if (attr_mask
& IB_QP_PKEY_INDEX
) {
631 qp_context
->pri_path
.port_pkey
|=
632 cpu_to_be32(attr
->pkey_index
);
633 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX
);
636 if (attr_mask
& IB_QP_RNR_RETRY
) {
637 qp_context
->alt_path
.rnr_retry
= qp_context
->pri_path
.rnr_retry
=
638 attr
->rnr_retry
<< 5;
639 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY
|
640 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
);
643 if (attr_mask
& IB_QP_AV
) {
644 if (mthca_path_set(dev
, &attr
->ah_attr
, &qp_context
->pri_path
,
645 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
))
648 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
);
651 if (ibqp
->qp_type
== IB_QPT_RC
&&
652 cur_state
== IB_QPS_INIT
&& new_state
== IB_QPS_RTR
) {
653 u8 sched_queue
= ibqp
->uobject
? 0x2 : 0x1;
655 if (mthca_is_memfree(dev
))
656 qp_context
->rlkey_arbel_sched_queue
|= sched_queue
;
658 qp_context
->tavor_sched_queue
|= cpu_to_be32(sched_queue
);
660 qp_param
->opt_param_mask
|=
661 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE
);
664 if (attr_mask
& IB_QP_TIMEOUT
) {
665 qp_context
->pri_path
.ackto
= attr
->timeout
<< 3;
666 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT
);
669 if (attr_mask
& IB_QP_ALT_PATH
) {
670 if (attr
->alt_pkey_index
>= dev
->limits
.pkey_table_len
) {
671 mthca_dbg(dev
, "Alternate P_Key index (%u) too large. max is %d\n",
672 attr
->alt_pkey_index
, dev
->limits
.pkey_table_len
-1);
676 if (attr
->alt_port_num
== 0 || attr
->alt_port_num
> dev
->limits
.num_ports
) {
677 mthca_dbg(dev
, "Alternate port number (%u) is invalid\n",
682 if (mthca_path_set(dev
, &attr
->alt_ah_attr
, &qp_context
->alt_path
,
683 attr
->alt_ah_attr
.port_num
))
686 qp_context
->alt_path
.port_pkey
|= cpu_to_be32(attr
->alt_pkey_index
|
687 attr
->alt_port_num
<< 24);
688 qp_context
->alt_path
.ackto
= attr
->alt_timeout
<< 3;
689 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH
);
693 qp_context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pd_num
);
694 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
695 qp_context
->wqe_lkey
= cpu_to_be32(qp
->mr
.ibmr
.lkey
);
696 qp_context
->params1
= cpu_to_be32((MTHCA_ACK_REQ_FREQ
<< 28) |
697 (MTHCA_FLIGHT_LIMIT
<< 24) |
699 if (qp
->sq_policy
== IB_SIGNAL_ALL_WR
)
700 qp_context
->params1
|= cpu_to_be32(MTHCA_QP_BIT_SSC
);
701 if (attr_mask
& IB_QP_RETRY_CNT
) {
702 qp_context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
703 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT
);
706 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
707 if (attr
->max_rd_atomic
) {
708 qp_context
->params1
|=
709 cpu_to_be32(MTHCA_QP_BIT_SRE
|
711 qp_context
->params1
|=
712 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
714 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX
);
717 if (attr_mask
& IB_QP_SQ_PSN
)
718 qp_context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
719 qp_context
->cqn_snd
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->cqn
);
721 if (mthca_is_memfree(dev
)) {
722 qp_context
->snd_wqe_base_l
= cpu_to_be32(qp
->send_wqe_offset
);
723 qp_context
->snd_db_index
= cpu_to_be32(qp
->sq
.db_index
);
726 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
727 if (attr
->max_dest_rd_atomic
)
728 qp_context
->params2
|=
729 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
731 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX
);
734 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
)) {
735 qp_context
->params2
|= get_hw_access_flags(qp
, attr
, attr_mask
);
736 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
737 MTHCA_QP_OPTPAR_RRE
|
738 MTHCA_QP_OPTPAR_RAE
);
741 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RSC
);
744 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RIC
);
746 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
747 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
748 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT
);
750 if (attr_mask
& IB_QP_RQ_PSN
)
751 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
753 qp_context
->ra_buff_indx
=
754 cpu_to_be32(dev
->qp_table
.rdb_base
+
755 ((qp
->qpn
& (dev
->limits
.num_qps
- 1)) * MTHCA_RDB_ENTRY_SIZE
<<
756 dev
->qp_table
.rdb_shift
));
758 qp_context
->cqn_rcv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->cqn
);
760 if (mthca_is_memfree(dev
))
761 qp_context
->rcv_db_index
= cpu_to_be32(qp
->rq
.db_index
);
763 if (attr_mask
& IB_QP_QKEY
) {
764 qp_context
->qkey
= cpu_to_be32(attr
->qkey
);
765 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY
);
769 qp_context
->srqn
= cpu_to_be32(1 << 24 |
770 to_msrq(ibqp
->srq
)->srqn
);
772 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
773 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&&
774 attr
->en_sqd_async_notify
)
777 err
= mthca_MODIFY_QP(dev
, cur_state
, new_state
, qp
->qpn
, 0,
778 mailbox
, sqd_event
, &status
);
782 mthca_warn(dev
, "modify QP %d->%d returned status %02x.\n",
783 cur_state
, new_state
, status
);
788 qp
->state
= new_state
;
789 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
790 qp
->atomic_rd_en
= attr
->qp_access_flags
;
791 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
792 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
793 if (attr_mask
& IB_QP_PORT
)
794 qp
->port
= attr
->port_num
;
795 if (attr_mask
& IB_QP_ALT_PATH
)
796 qp
->alt_port
= attr
->alt_port_num
;
799 store_attrs(to_msqp(qp
), attr
, attr_mask
);
802 * If we moved QP0 to RTR, bring the IB link up; if we moved
803 * QP0 to RESET or ERROR, bring the link back down.
805 if (is_qp0(dev
, qp
)) {
806 if (cur_state
!= IB_QPS_RTR
&&
807 new_state
== IB_QPS_RTR
)
808 init_port(dev
, qp
->port
);
810 if (cur_state
!= IB_QPS_RESET
&&
811 cur_state
!= IB_QPS_ERR
&&
812 (new_state
== IB_QPS_RESET
||
813 new_state
== IB_QPS_ERR
))
814 mthca_CLOSE_IB(dev
, qp
->port
, &status
);
818 * If we moved a kernel QP to RESET, clean up all old CQ
819 * entries and reinitialize the QP.
821 if (new_state
== IB_QPS_RESET
&& !qp
->ibqp
.uobject
) {
822 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
), qp
->qpn
,
823 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
824 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
825 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
), qp
->qpn
, NULL
);
827 mthca_wq_reset(&qp
->sq
);
828 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
830 mthca_wq_reset(&qp
->rq
);
831 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
833 if (mthca_is_memfree(dev
)) {
840 mthca_free_mailbox(dev
, mailbox
);
845 static const struct ib_qp_attr dummy_init_attr
= { .port_num
= 1 };
846 static const int dummy_init_attr_mask
[] = {
847 [IB_QPT_UD
] = (IB_QP_PKEY_INDEX
|
850 [IB_QPT_UC
] = (IB_QP_PKEY_INDEX
|
853 [IB_QPT_RC
] = (IB_QP_PKEY_INDEX
|
856 [IB_QPT_SMI
] = (IB_QP_PKEY_INDEX
|
858 [IB_QPT_GSI
] = (IB_QP_PKEY_INDEX
|
862 int mthca_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
, int attr_mask
,
863 struct ib_udata
*udata
)
865 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
866 struct mthca_qp
*qp
= to_mqp(ibqp
);
867 enum ib_qp_state cur_state
, new_state
;
870 mutex_lock(&qp
->mutex
);
871 if (attr_mask
& IB_QP_CUR_STATE
) {
872 cur_state
= attr
->cur_qp_state
;
874 spin_lock_irq(&qp
->sq
.lock
);
875 spin_lock(&qp
->rq
.lock
);
876 cur_state
= qp
->state
;
877 spin_unlock(&qp
->rq
.lock
);
878 spin_unlock_irq(&qp
->sq
.lock
);
881 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
883 if (!ib_modify_qp_is_ok(cur_state
, new_state
, ibqp
->qp_type
, attr_mask
)) {
884 mthca_dbg(dev
, "Bad QP transition (transport %d) "
885 "%d->%d with attr 0x%08x\n",
886 qp
->transport
, cur_state
, new_state
,
891 if ((attr_mask
& IB_QP_PKEY_INDEX
) &&
892 attr
->pkey_index
>= dev
->limits
.pkey_table_len
) {
893 mthca_dbg(dev
, "P_Key index (%u) too large. max is %d\n",
894 attr
->pkey_index
, dev
->limits
.pkey_table_len
-1);
898 if ((attr_mask
& IB_QP_PORT
) &&
899 (attr
->port_num
== 0 || attr
->port_num
> dev
->limits
.num_ports
)) {
900 mthca_dbg(dev
, "Port number (%u) is invalid\n", attr
->port_num
);
904 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
905 attr
->max_rd_atomic
> dev
->limits
.max_qp_init_rdma
) {
906 mthca_dbg(dev
, "Max rdma_atomic as initiator %u too large (max is %d)\n",
907 attr
->max_rd_atomic
, dev
->limits
.max_qp_init_rdma
);
911 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
912 attr
->max_dest_rd_atomic
> 1 << dev
->qp_table
.rdb_shift
) {
913 mthca_dbg(dev
, "Max rdma_atomic as responder %u too large (max %d)\n",
914 attr
->max_dest_rd_atomic
, 1 << dev
->qp_table
.rdb_shift
);
918 if (cur_state
== new_state
&& cur_state
== IB_QPS_RESET
) {
923 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_ERR
) {
924 err
= __mthca_modify_qp(ibqp
, &dummy_init_attr
,
925 dummy_init_attr_mask
[ibqp
->qp_type
],
926 IB_QPS_RESET
, IB_QPS_INIT
);
929 cur_state
= IB_QPS_INIT
;
932 err
= __mthca_modify_qp(ibqp
, attr
, attr_mask
, cur_state
, new_state
);
935 mutex_unlock(&qp
->mutex
);
939 static int mthca_max_data_size(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int desc_sz
)
942 * Calculate the maximum size of WQE s/g segments, excluding
943 * the next segment and other non-data segments.
945 int max_data_size
= desc_sz
- sizeof (struct mthca_next_seg
);
947 switch (qp
->transport
) {
949 max_data_size
-= 2 * sizeof (struct mthca_data_seg
);
953 if (mthca_is_memfree(dev
))
954 max_data_size
-= sizeof (struct mthca_arbel_ud_seg
);
956 max_data_size
-= sizeof (struct mthca_tavor_ud_seg
);
960 max_data_size
-= sizeof (struct mthca_raddr_seg
);
964 return max_data_size
;
967 static inline int mthca_max_inline_data(struct mthca_pd
*pd
, int max_data_size
)
969 /* We don't support inline data for kernel QPs (yet). */
970 return pd
->ibpd
.uobject
? max_data_size
- MTHCA_INLINE_HEADER_SIZE
: 0;
973 static void mthca_adjust_qp_caps(struct mthca_dev
*dev
,
977 int max_data_size
= mthca_max_data_size(dev
, qp
,
978 min(dev
->limits
.max_desc_sz
,
979 1 << qp
->sq
.wqe_shift
));
981 qp
->max_inline_data
= mthca_max_inline_data(pd
, max_data_size
);
983 qp
->sq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
984 max_data_size
/ sizeof (struct mthca_data_seg
));
985 qp
->rq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
986 (min(dev
->limits
.max_desc_sz
, 1 << qp
->rq
.wqe_shift
) -
987 sizeof (struct mthca_next_seg
)) /
988 sizeof (struct mthca_data_seg
));
992 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
993 * rq.max_gs and sq.max_gs must all be assigned.
994 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
995 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
998 static int mthca_alloc_wqe_buf(struct mthca_dev
*dev
,
1000 struct mthca_qp
*qp
)
1005 size
= sizeof (struct mthca_next_seg
) +
1006 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
);
1008 if (size
> dev
->limits
.max_desc_sz
)
1011 for (qp
->rq
.wqe_shift
= 6; 1 << qp
->rq
.wqe_shift
< size
;
1015 size
= qp
->sq
.max_gs
* sizeof (struct mthca_data_seg
);
1016 switch (qp
->transport
) {
1018 size
+= 2 * sizeof (struct mthca_data_seg
);
1022 size
+= mthca_is_memfree(dev
) ?
1023 sizeof (struct mthca_arbel_ud_seg
) :
1024 sizeof (struct mthca_tavor_ud_seg
);
1028 size
+= sizeof (struct mthca_raddr_seg
);
1032 size
+= sizeof (struct mthca_raddr_seg
);
1034 * An atomic op will require an atomic segment, a
1035 * remote address segment and one scatter entry.
1037 size
= max_t(int, size
,
1038 sizeof (struct mthca_atomic_seg
) +
1039 sizeof (struct mthca_raddr_seg
) +
1040 sizeof (struct mthca_data_seg
));
1047 /* Make sure that we have enough space for a bind request */
1048 size
= max_t(int, size
, sizeof (struct mthca_bind_seg
));
1050 size
+= sizeof (struct mthca_next_seg
);
1052 if (size
> dev
->limits
.max_desc_sz
)
1055 for (qp
->sq
.wqe_shift
= 6; 1 << qp
->sq
.wqe_shift
< size
;
1059 qp
->send_wqe_offset
= ALIGN(qp
->rq
.max
<< qp
->rq
.wqe_shift
,
1060 1 << qp
->sq
.wqe_shift
);
1063 * If this is a userspace QP, we don't actually have to
1064 * allocate anything. All we need is to calculate the WQE
1065 * sizes and the send_wqe_offset, so we're done now.
1067 if (pd
->ibpd
.uobject
)
1070 size
= PAGE_ALIGN(qp
->send_wqe_offset
+
1071 (qp
->sq
.max
<< qp
->sq
.wqe_shift
));
1073 qp
->wrid
= kmalloc((qp
->rq
.max
+ qp
->sq
.max
) * sizeof (u64
),
1078 err
= mthca_buf_alloc(dev
, size
, MTHCA_MAX_DIRECT_QP_SIZE
,
1079 &qp
->queue
, &qp
->is_direct
, pd
, 0, &qp
->mr
);
1090 static void mthca_free_wqe_buf(struct mthca_dev
*dev
,
1091 struct mthca_qp
*qp
)
1093 mthca_buf_free(dev
, PAGE_ALIGN(qp
->send_wqe_offset
+
1094 (qp
->sq
.max
<< qp
->sq
.wqe_shift
)),
1095 &qp
->queue
, qp
->is_direct
, &qp
->mr
);
1099 static int mthca_map_memfree(struct mthca_dev
*dev
,
1100 struct mthca_qp
*qp
)
1104 if (mthca_is_memfree(dev
)) {
1105 ret
= mthca_table_get(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1109 ret
= mthca_table_get(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1113 ret
= mthca_table_get(dev
, dev
->qp_table
.rdb_table
,
1114 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1123 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1126 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1131 static void mthca_unmap_memfree(struct mthca_dev
*dev
,
1132 struct mthca_qp
*qp
)
1134 mthca_table_put(dev
, dev
->qp_table
.rdb_table
,
1135 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1136 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1137 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1140 static int mthca_alloc_memfree(struct mthca_dev
*dev
,
1141 struct mthca_qp
*qp
)
1143 if (mthca_is_memfree(dev
)) {
1144 qp
->rq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_RQ
,
1145 qp
->qpn
, &qp
->rq
.db
);
1146 if (qp
->rq
.db_index
< 0)
1149 qp
->sq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_SQ
,
1150 qp
->qpn
, &qp
->sq
.db
);
1151 if (qp
->sq
.db_index
< 0) {
1152 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1160 static void mthca_free_memfree(struct mthca_dev
*dev
,
1161 struct mthca_qp
*qp
)
1163 if (mthca_is_memfree(dev
)) {
1164 mthca_free_db(dev
, MTHCA_DB_TYPE_SQ
, qp
->sq
.db_index
);
1165 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1169 static int mthca_alloc_qp_common(struct mthca_dev
*dev
,
1170 struct mthca_pd
*pd
,
1171 struct mthca_cq
*send_cq
,
1172 struct mthca_cq
*recv_cq
,
1173 enum ib_sig_type send_policy
,
1174 struct mthca_qp
*qp
)
1180 init_waitqueue_head(&qp
->wait
);
1181 mutex_init(&qp
->mutex
);
1182 qp
->state
= IB_QPS_RESET
;
1183 qp
->atomic_rd_en
= 0;
1185 qp
->sq_policy
= send_policy
;
1186 mthca_wq_reset(&qp
->sq
);
1187 mthca_wq_reset(&qp
->rq
);
1189 spin_lock_init(&qp
->sq
.lock
);
1190 spin_lock_init(&qp
->rq
.lock
);
1192 ret
= mthca_map_memfree(dev
, qp
);
1196 ret
= mthca_alloc_wqe_buf(dev
, pd
, qp
);
1198 mthca_unmap_memfree(dev
, qp
);
1202 mthca_adjust_qp_caps(dev
, pd
, qp
);
1205 * If this is a userspace QP, we're done now. The doorbells
1206 * will be allocated and buffers will be initialized in
1209 if (pd
->ibpd
.uobject
)
1212 ret
= mthca_alloc_memfree(dev
, qp
);
1214 mthca_free_wqe_buf(dev
, qp
);
1215 mthca_unmap_memfree(dev
, qp
);
1219 if (mthca_is_memfree(dev
)) {
1220 struct mthca_next_seg
*next
;
1221 struct mthca_data_seg
*scatter
;
1222 int size
= (sizeof (struct mthca_next_seg
) +
1223 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
)) / 16;
1225 for (i
= 0; i
< qp
->rq
.max
; ++i
) {
1226 next
= get_recv_wqe(qp
, i
);
1227 next
->nda_op
= cpu_to_be32(((i
+ 1) & (qp
->rq
.max
- 1)) <<
1229 next
->ee_nds
= cpu_to_be32(size
);
1231 for (scatter
= (void *) (next
+ 1);
1232 (void *) scatter
< (void *) next
+ (1 << qp
->rq
.wqe_shift
);
1234 scatter
->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
1237 for (i
= 0; i
< qp
->sq
.max
; ++i
) {
1238 next
= get_send_wqe(qp
, i
);
1239 next
->nda_op
= cpu_to_be32((((i
+ 1) & (qp
->sq
.max
- 1)) <<
1241 qp
->send_wqe_offset
);
1245 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
1246 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
1251 static int mthca_set_qp_size(struct mthca_dev
*dev
, struct ib_qp_cap
*cap
,
1252 struct mthca_pd
*pd
, struct mthca_qp
*qp
)
1254 int max_data_size
= mthca_max_data_size(dev
, qp
, dev
->limits
.max_desc_sz
);
1256 /* Sanity check QP size before proceeding */
1257 if (cap
->max_send_wr
> dev
->limits
.max_wqes
||
1258 cap
->max_recv_wr
> dev
->limits
.max_wqes
||
1259 cap
->max_send_sge
> dev
->limits
.max_sg
||
1260 cap
->max_recv_sge
> dev
->limits
.max_sg
||
1261 cap
->max_inline_data
> mthca_max_inline_data(pd
, max_data_size
))
1265 * For MLX transport we need 2 extra S/G entries:
1266 * one for the header and one for the checksum at the end
1268 if (qp
->transport
== MLX
&& cap
->max_recv_sge
+ 2 > dev
->limits
.max_sg
)
1271 if (mthca_is_memfree(dev
)) {
1272 qp
->rq
.max
= cap
->max_recv_wr
?
1273 roundup_pow_of_two(cap
->max_recv_wr
) : 0;
1274 qp
->sq
.max
= cap
->max_send_wr
?
1275 roundup_pow_of_two(cap
->max_send_wr
) : 0;
1277 qp
->rq
.max
= cap
->max_recv_wr
;
1278 qp
->sq
.max
= cap
->max_send_wr
;
1281 qp
->rq
.max_gs
= cap
->max_recv_sge
;
1282 qp
->sq
.max_gs
= max_t(int, cap
->max_send_sge
,
1283 ALIGN(cap
->max_inline_data
+ MTHCA_INLINE_HEADER_SIZE
,
1284 MTHCA_INLINE_CHUNK_SIZE
) /
1285 sizeof (struct mthca_data_seg
));
1290 int mthca_alloc_qp(struct mthca_dev
*dev
,
1291 struct mthca_pd
*pd
,
1292 struct mthca_cq
*send_cq
,
1293 struct mthca_cq
*recv_cq
,
1294 enum ib_qp_type type
,
1295 enum ib_sig_type send_policy
,
1296 struct ib_qp_cap
*cap
,
1297 struct mthca_qp
*qp
)
1302 case IB_QPT_RC
: qp
->transport
= RC
; break;
1303 case IB_QPT_UC
: qp
->transport
= UC
; break;
1304 case IB_QPT_UD
: qp
->transport
= UD
; break;
1305 default: return -EINVAL
;
1308 err
= mthca_set_qp_size(dev
, cap
, pd
, qp
);
1312 qp
->qpn
= mthca_alloc(&dev
->qp_table
.alloc
);
1316 /* initialize port to zero for error-catching. */
1319 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1322 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1326 spin_lock_irq(&dev
->qp_table
.lock
);
1327 mthca_array_set(&dev
->qp_table
.qp
,
1328 qp
->qpn
& (dev
->limits
.num_qps
- 1), qp
);
1329 spin_unlock_irq(&dev
->qp_table
.lock
);
1334 static void mthca_lock_cqs(struct mthca_cq
*send_cq
, struct mthca_cq
*recv_cq
)
1336 if (send_cq
== recv_cq
)
1337 spin_lock_irq(&send_cq
->lock
);
1338 else if (send_cq
->cqn
< recv_cq
->cqn
) {
1339 spin_lock_irq(&send_cq
->lock
);
1340 spin_lock_nested(&recv_cq
->lock
, SINGLE_DEPTH_NESTING
);
1342 spin_lock_irq(&recv_cq
->lock
);
1343 spin_lock_nested(&send_cq
->lock
, SINGLE_DEPTH_NESTING
);
1347 static void mthca_unlock_cqs(struct mthca_cq
*send_cq
, struct mthca_cq
*recv_cq
)
1349 if (send_cq
== recv_cq
)
1350 spin_unlock_irq(&send_cq
->lock
);
1351 else if (send_cq
->cqn
< recv_cq
->cqn
) {
1352 spin_unlock(&recv_cq
->lock
);
1353 spin_unlock_irq(&send_cq
->lock
);
1355 spin_unlock(&send_cq
->lock
);
1356 spin_unlock_irq(&recv_cq
->lock
);
1360 int mthca_alloc_sqp(struct mthca_dev
*dev
,
1361 struct mthca_pd
*pd
,
1362 struct mthca_cq
*send_cq
,
1363 struct mthca_cq
*recv_cq
,
1364 enum ib_sig_type send_policy
,
1365 struct ib_qp_cap
*cap
,
1368 struct mthca_sqp
*sqp
)
1370 u32 mqpn
= qpn
* 2 + dev
->qp_table
.sqp_start
+ port
- 1;
1373 sqp
->qp
.transport
= MLX
;
1374 err
= mthca_set_qp_size(dev
, cap
, pd
, &sqp
->qp
);
1378 sqp
->header_buf_size
= sqp
->qp
.sq
.max
* MTHCA_UD_HEADER_SIZE
;
1379 sqp
->header_buf
= dma_alloc_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1380 &sqp
->header_dma
, GFP_KERNEL
);
1381 if (!sqp
->header_buf
)
1384 spin_lock_irq(&dev
->qp_table
.lock
);
1385 if (mthca_array_get(&dev
->qp_table
.qp
, mqpn
))
1388 mthca_array_set(&dev
->qp_table
.qp
, mqpn
, sqp
);
1389 spin_unlock_irq(&dev
->qp_table
.lock
);
1394 sqp
->qp
.port
= port
;
1396 sqp
->qp
.transport
= MLX
;
1398 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1399 send_policy
, &sqp
->qp
);
1403 atomic_inc(&pd
->sqp_count
);
1409 * Lock CQs here, so that CQ polling code can do QP lookup
1410 * without taking a lock.
1412 mthca_lock_cqs(send_cq
, recv_cq
);
1414 spin_lock(&dev
->qp_table
.lock
);
1415 mthca_array_clear(&dev
->qp_table
.qp
, mqpn
);
1416 spin_unlock(&dev
->qp_table
.lock
);
1418 mthca_unlock_cqs(send_cq
, recv_cq
);
1421 dma_free_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1422 sqp
->header_buf
, sqp
->header_dma
);
1427 static inline int get_qp_refcount(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
1431 spin_lock_irq(&dev
->qp_table
.lock
);
1433 spin_unlock_irq(&dev
->qp_table
.lock
);
1438 void mthca_free_qp(struct mthca_dev
*dev
,
1439 struct mthca_qp
*qp
)
1442 struct mthca_cq
*send_cq
;
1443 struct mthca_cq
*recv_cq
;
1445 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1446 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
1449 * Lock CQs here, so that CQ polling code can do QP lookup
1450 * without taking a lock.
1452 mthca_lock_cqs(send_cq
, recv_cq
);
1454 spin_lock(&dev
->qp_table
.lock
);
1455 mthca_array_clear(&dev
->qp_table
.qp
,
1456 qp
->qpn
& (dev
->limits
.num_qps
- 1));
1458 spin_unlock(&dev
->qp_table
.lock
);
1460 mthca_unlock_cqs(send_cq
, recv_cq
);
1462 wait_event(qp
->wait
, !get_qp_refcount(dev
, qp
));
1464 if (qp
->state
!= IB_QPS_RESET
)
1465 mthca_MODIFY_QP(dev
, qp
->state
, IB_QPS_RESET
, qp
->qpn
, 0,
1469 * If this is a userspace QP, the buffers, MR, CQs and so on
1470 * will be cleaned up in userspace, so all we have to do is
1471 * unref the mem-free tables and free the QPN in our table.
1473 if (!qp
->ibqp
.uobject
) {
1474 mthca_cq_clean(dev
, recv_cq
, qp
->qpn
,
1475 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1476 if (send_cq
!= recv_cq
)
1477 mthca_cq_clean(dev
, send_cq
, qp
->qpn
, NULL
);
1479 mthca_free_memfree(dev
, qp
);
1480 mthca_free_wqe_buf(dev
, qp
);
1483 mthca_unmap_memfree(dev
, qp
);
1485 if (is_sqp(dev
, qp
)) {
1486 atomic_dec(&(to_mpd(qp
->ibqp
.pd
)->sqp_count
));
1487 dma_free_coherent(&dev
->pdev
->dev
,
1488 to_msqp(qp
)->header_buf_size
,
1489 to_msqp(qp
)->header_buf
,
1490 to_msqp(qp
)->header_dma
);
1492 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1495 /* Create UD header for an MLX send and build a data segment for it */
1496 static int build_mlx_header(struct mthca_dev
*dev
, struct mthca_sqp
*sqp
,
1497 int ind
, struct ib_send_wr
*wr
,
1498 struct mthca_mlx_seg
*mlx
,
1499 struct mthca_data_seg
*data
)
1505 ib_ud_header_init(256, /* assume a MAD */
1506 mthca_ah_grh_present(to_mah(wr
->wr
.ud
.ah
)),
1509 err
= mthca_read_ah(dev
, to_mah(wr
->wr
.ud
.ah
), &sqp
->ud_header
);
1512 mlx
->flags
&= ~cpu_to_be32(MTHCA_NEXT_SOLICIT
| 1);
1513 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MTHCA_MLX_VL15
: 0) |
1514 (sqp
->ud_header
.lrh
.destination_lid
==
1515 IB_LID_PERMISSIVE
? MTHCA_MLX_SLR
: 0) |
1516 (sqp
->ud_header
.lrh
.service_level
<< 8));
1517 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1520 switch (wr
->opcode
) {
1522 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1523 sqp
->ud_header
.immediate_present
= 0;
1525 case IB_WR_SEND_WITH_IMM
:
1526 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1527 sqp
->ud_header
.immediate_present
= 1;
1528 sqp
->ud_header
.immediate_data
= wr
->imm_data
;
1534 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1535 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1536 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1537 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1538 if (!sqp
->qp
.ibqp
.qp_num
)
1539 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->qp
.port
,
1540 sqp
->pkey_index
, &pkey
);
1542 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->qp
.port
,
1543 wr
->wr
.ud
.pkey_index
, &pkey
);
1544 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1545 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1546 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1547 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1548 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1549 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1551 header_size
= ib_ud_header_pack(&sqp
->ud_header
,
1553 ind
* MTHCA_UD_HEADER_SIZE
);
1555 data
->byte_count
= cpu_to_be32(header_size
);
1556 data
->lkey
= cpu_to_be32(to_mpd(sqp
->qp
.ibqp
.pd
)->ntmr
.ibmr
.lkey
);
1557 data
->addr
= cpu_to_be64(sqp
->header_dma
+
1558 ind
* MTHCA_UD_HEADER_SIZE
);
1563 static inline int mthca_wq_overflow(struct mthca_wq
*wq
, int nreq
,
1564 struct ib_cq
*ib_cq
)
1567 struct mthca_cq
*cq
;
1569 cur
= wq
->head
- wq
->tail
;
1570 if (likely(cur
+ nreq
< wq
->max
))
1574 spin_lock(&cq
->lock
);
1575 cur
= wq
->head
- wq
->tail
;
1576 spin_unlock(&cq
->lock
);
1578 return cur
+ nreq
>= wq
->max
;
1581 int mthca_tavor_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1582 struct ib_send_wr
**bad_wr
)
1584 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1585 struct mthca_qp
*qp
= to_mqp(ibqp
);
1588 unsigned long flags
;
1598 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1600 /* XXX check that state is OK to post send */
1602 ind
= qp
->sq
.next_ind
;
1604 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1605 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1606 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1607 " %d max, %d nreq)\n", qp
->qpn
,
1608 qp
->sq
.head
, qp
->sq
.tail
,
1615 wqe
= get_send_wqe(qp
, ind
);
1616 prev_wqe
= qp
->sq
.last
;
1619 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1620 ((struct mthca_next_seg
*) wqe
)->ee_nds
= 0;
1621 ((struct mthca_next_seg
*) wqe
)->flags
=
1622 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1623 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1624 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1625 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1627 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1628 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1629 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1631 wqe
+= sizeof (struct mthca_next_seg
);
1632 size
= sizeof (struct mthca_next_seg
) / 16;
1634 switch (qp
->transport
) {
1636 switch (wr
->opcode
) {
1637 case IB_WR_ATOMIC_CMP_AND_SWP
:
1638 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1639 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1640 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1641 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1642 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1643 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1645 wqe
+= sizeof (struct mthca_raddr_seg
);
1647 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1648 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1649 cpu_to_be64(wr
->wr
.atomic
.swap
);
1650 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1651 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1653 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1654 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1655 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1658 wqe
+= sizeof (struct mthca_atomic_seg
);
1659 size
+= (sizeof (struct mthca_raddr_seg
) +
1660 sizeof (struct mthca_atomic_seg
)) / 16;
1663 case IB_WR_RDMA_WRITE
:
1664 case IB_WR_RDMA_WRITE_WITH_IMM
:
1665 case IB_WR_RDMA_READ
:
1666 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1667 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1668 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1669 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1670 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1671 wqe
+= sizeof (struct mthca_raddr_seg
);
1672 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1676 /* No extra segments required for sends */
1683 switch (wr
->opcode
) {
1684 case IB_WR_RDMA_WRITE
:
1685 case IB_WR_RDMA_WRITE_WITH_IMM
:
1686 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1687 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1688 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1689 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1690 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1691 wqe
+= sizeof (struct mthca_raddr_seg
);
1692 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1696 /* No extra segments required for sends */
1703 ((struct mthca_tavor_ud_seg
*) wqe
)->lkey
=
1704 cpu_to_be32(to_mah(wr
->wr
.ud
.ah
)->key
);
1705 ((struct mthca_tavor_ud_seg
*) wqe
)->av_addr
=
1706 cpu_to_be64(to_mah(wr
->wr
.ud
.ah
)->avdma
);
1707 ((struct mthca_tavor_ud_seg
*) wqe
)->dqpn
=
1708 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1709 ((struct mthca_tavor_ud_seg
*) wqe
)->qkey
=
1710 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1712 wqe
+= sizeof (struct mthca_tavor_ud_seg
);
1713 size
+= sizeof (struct mthca_tavor_ud_seg
) / 16;
1717 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1718 wqe
- sizeof (struct mthca_next_seg
),
1724 wqe
+= sizeof (struct mthca_data_seg
);
1725 size
+= sizeof (struct mthca_data_seg
) / 16;
1729 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1730 mthca_err(dev
, "too many gathers\n");
1736 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1737 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1738 cpu_to_be32(wr
->sg_list
[i
].length
);
1739 ((struct mthca_data_seg
*) wqe
)->lkey
=
1740 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1741 ((struct mthca_data_seg
*) wqe
)->addr
=
1742 cpu_to_be64(wr
->sg_list
[i
].addr
);
1743 wqe
+= sizeof (struct mthca_data_seg
);
1744 size
+= sizeof (struct mthca_data_seg
) / 16;
1747 /* Add one more inline data segment for ICRC */
1748 if (qp
->transport
== MLX
) {
1749 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1750 cpu_to_be32((1 << 31) | 4);
1751 ((u32
*) wqe
)[1] = 0;
1752 wqe
+= sizeof (struct mthca_data_seg
);
1753 size
+= sizeof (struct mthca_data_seg
) / 16;
1756 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1758 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1759 mthca_err(dev
, "opcode invalid\n");
1765 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1766 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1767 qp
->send_wqe_offset
) |
1768 mthca_opcode
[wr
->opcode
]);
1770 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1771 cpu_to_be32((size0
? 0 : MTHCA_NEXT_DBD
) | size
|
1772 ((wr
->send_flags
& IB_SEND_FENCE
) ?
1773 MTHCA_NEXT_FENCE
: 0));
1777 op0
= mthca_opcode
[wr
->opcode
];
1778 f0
= wr
->send_flags
& IB_SEND_FENCE
?
1779 MTHCA_SEND_DOORBELL_FENCE
: 0;
1783 if (unlikely(ind
>= qp
->sq
.max
))
1791 doorbell
[0] = cpu_to_be32(((qp
->sq
.next_ind
<< qp
->sq
.wqe_shift
) +
1792 qp
->send_wqe_offset
) | f0
| op0
);
1793 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1797 mthca_write64(doorbell
,
1798 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1799 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1801 * Make sure doorbells don't leak out of SQ spinlock
1802 * and reach the HCA out of order:
1807 qp
->sq
.next_ind
= ind
;
1808 qp
->sq
.head
+= nreq
;
1810 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1814 int mthca_tavor_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1815 struct ib_recv_wr
**bad_wr
)
1817 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1818 struct mthca_qp
*qp
= to_mqp(ibqp
);
1820 unsigned long flags
;
1830 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1832 /* XXX check that state is OK to post receive */
1834 ind
= qp
->rq
.next_ind
;
1836 for (nreq
= 0; wr
; wr
= wr
->next
) {
1837 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1838 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
1839 " %d max, %d nreq)\n", qp
->qpn
,
1840 qp
->rq
.head
, qp
->rq
.tail
,
1847 wqe
= get_recv_wqe(qp
, ind
);
1848 prev_wqe
= qp
->rq
.last
;
1851 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1852 ((struct mthca_next_seg
*) wqe
)->ee_nds
=
1853 cpu_to_be32(MTHCA_NEXT_DBD
);
1854 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
1856 wqe
+= sizeof (struct mthca_next_seg
);
1857 size
= sizeof (struct mthca_next_seg
) / 16;
1859 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1865 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1866 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1867 cpu_to_be32(wr
->sg_list
[i
].length
);
1868 ((struct mthca_data_seg
*) wqe
)->lkey
=
1869 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1870 ((struct mthca_data_seg
*) wqe
)->addr
=
1871 cpu_to_be64(wr
->sg_list
[i
].addr
);
1872 wqe
+= sizeof (struct mthca_data_seg
);
1873 size
+= sizeof (struct mthca_data_seg
) / 16;
1876 qp
->wrid
[ind
] = wr
->wr_id
;
1878 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1879 cpu_to_be32((ind
<< qp
->rq
.wqe_shift
) | 1);
1881 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1882 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
1888 if (unlikely(ind
>= qp
->rq
.max
))
1892 if (unlikely(nreq
== MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
)) {
1895 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1896 doorbell
[1] = cpu_to_be32(qp
->qpn
<< 8);
1900 mthca_write64(doorbell
,
1901 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1902 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1904 qp
->rq
.next_ind
= ind
;
1905 qp
->rq
.head
+= MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
;
1912 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1913 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | nreq
);
1917 mthca_write64(doorbell
,
1918 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1919 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1922 qp
->rq
.next_ind
= ind
;
1923 qp
->rq
.head
+= nreq
;
1926 * Make sure doorbells don't leak out of RQ spinlock and reach
1927 * the HCA out of order:
1931 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1935 int mthca_arbel_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1936 struct ib_send_wr
**bad_wr
)
1938 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1939 struct mthca_qp
*qp
= to_mqp(ibqp
);
1943 unsigned long flags
;
1953 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1955 /* XXX check that state is OK to post send */
1957 ind
= qp
->sq
.head
& (qp
->sq
.max
- 1);
1959 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1960 if (unlikely(nreq
== MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
)) {
1963 doorbell
[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
<< 24) |
1964 ((qp
->sq
.head
& 0xffff) << 8) |
1966 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1968 qp
->sq
.head
+= MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
;
1972 * Make sure that descriptors are written before
1976 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
1979 * Make sure doorbell record is written before we
1980 * write MMIO send doorbell.
1983 mthca_write64(doorbell
,
1984 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1985 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1988 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1989 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1990 " %d max, %d nreq)\n", qp
->qpn
,
1991 qp
->sq
.head
, qp
->sq
.tail
,
1998 wqe
= get_send_wqe(qp
, ind
);
1999 prev_wqe
= qp
->sq
.last
;
2002 ((struct mthca_next_seg
*) wqe
)->flags
=
2003 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
2004 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
2005 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
2006 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
2008 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
2009 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
2010 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
2012 wqe
+= sizeof (struct mthca_next_seg
);
2013 size
= sizeof (struct mthca_next_seg
) / 16;
2015 switch (qp
->transport
) {
2017 switch (wr
->opcode
) {
2018 case IB_WR_ATOMIC_CMP_AND_SWP
:
2019 case IB_WR_ATOMIC_FETCH_AND_ADD
:
2020 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
2021 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
2022 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
2023 cpu_to_be32(wr
->wr
.atomic
.rkey
);
2024 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
2026 wqe
+= sizeof (struct mthca_raddr_seg
);
2028 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
2029 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
2030 cpu_to_be64(wr
->wr
.atomic
.swap
);
2031 ((struct mthca_atomic_seg
*) wqe
)->compare
=
2032 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
2034 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
2035 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
2036 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
2039 wqe
+= sizeof (struct mthca_atomic_seg
);
2040 size
+= (sizeof (struct mthca_raddr_seg
) +
2041 sizeof (struct mthca_atomic_seg
)) / 16;
2044 case IB_WR_RDMA_READ
:
2045 case IB_WR_RDMA_WRITE
:
2046 case IB_WR_RDMA_WRITE_WITH_IMM
:
2047 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
2048 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
2049 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
2050 cpu_to_be32(wr
->wr
.rdma
.rkey
);
2051 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
2052 wqe
+= sizeof (struct mthca_raddr_seg
);
2053 size
+= sizeof (struct mthca_raddr_seg
) / 16;
2057 /* No extra segments required for sends */
2064 switch (wr
->opcode
) {
2065 case IB_WR_RDMA_WRITE
:
2066 case IB_WR_RDMA_WRITE_WITH_IMM
:
2067 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
2068 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
2069 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
2070 cpu_to_be32(wr
->wr
.rdma
.rkey
);
2071 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
2072 wqe
+= sizeof (struct mthca_raddr_seg
);
2073 size
+= sizeof (struct mthca_raddr_seg
) / 16;
2077 /* No extra segments required for sends */
2084 memcpy(((struct mthca_arbel_ud_seg
*) wqe
)->av
,
2085 to_mah(wr
->wr
.ud
.ah
)->av
, MTHCA_AV_SIZE
);
2086 ((struct mthca_arbel_ud_seg
*) wqe
)->dqpn
=
2087 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
2088 ((struct mthca_arbel_ud_seg
*) wqe
)->qkey
=
2089 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
2091 wqe
+= sizeof (struct mthca_arbel_ud_seg
);
2092 size
+= sizeof (struct mthca_arbel_ud_seg
) / 16;
2096 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
2097 wqe
- sizeof (struct mthca_next_seg
),
2103 wqe
+= sizeof (struct mthca_data_seg
);
2104 size
+= sizeof (struct mthca_data_seg
) / 16;
2108 if (wr
->num_sge
> qp
->sq
.max_gs
) {
2109 mthca_err(dev
, "too many gathers\n");
2115 for (i
= 0; i
< wr
->num_sge
; ++i
) {
2116 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2117 cpu_to_be32(wr
->sg_list
[i
].length
);
2118 ((struct mthca_data_seg
*) wqe
)->lkey
=
2119 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2120 ((struct mthca_data_seg
*) wqe
)->addr
=
2121 cpu_to_be64(wr
->sg_list
[i
].addr
);
2122 wqe
+= sizeof (struct mthca_data_seg
);
2123 size
+= sizeof (struct mthca_data_seg
) / 16;
2126 /* Add one more inline data segment for ICRC */
2127 if (qp
->transport
== MLX
) {
2128 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2129 cpu_to_be32((1 << 31) | 4);
2130 ((u32
*) wqe
)[1] = 0;
2131 wqe
+= sizeof (struct mthca_data_seg
);
2132 size
+= sizeof (struct mthca_data_seg
) / 16;
2135 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
2137 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
2138 mthca_err(dev
, "opcode invalid\n");
2144 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
2145 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
2146 qp
->send_wqe_offset
) |
2147 mthca_opcode
[wr
->opcode
]);
2149 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
2150 cpu_to_be32(MTHCA_NEXT_DBD
| size
|
2151 ((wr
->send_flags
& IB_SEND_FENCE
) ?
2152 MTHCA_NEXT_FENCE
: 0));
2156 op0
= mthca_opcode
[wr
->opcode
];
2157 f0
= wr
->send_flags
& IB_SEND_FENCE
?
2158 MTHCA_SEND_DOORBELL_FENCE
: 0;
2162 if (unlikely(ind
>= qp
->sq
.max
))
2168 doorbell
[0] = cpu_to_be32((nreq
<< 24) |
2169 ((qp
->sq
.head
& 0xffff) << 8) |
2171 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
2173 qp
->sq
.head
+= nreq
;
2176 * Make sure that descriptors are written before
2180 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
2183 * Make sure doorbell record is written before we
2184 * write MMIO send doorbell.
2187 mthca_write64(doorbell
,
2188 dev
->kar
+ MTHCA_SEND_DOORBELL
,
2189 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
2193 * Make sure doorbells don't leak out of SQ spinlock and reach
2194 * the HCA out of order:
2198 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
2202 int mthca_arbel_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
2203 struct ib_recv_wr
**bad_wr
)
2205 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
2206 struct mthca_qp
*qp
= to_mqp(ibqp
);
2207 unsigned long flags
;
2214 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
2216 /* XXX check that state is OK to post receive */
2218 ind
= qp
->rq
.head
& (qp
->rq
.max
- 1);
2220 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
2221 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
2222 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
2223 " %d max, %d nreq)\n", qp
->qpn
,
2224 qp
->rq
.head
, qp
->rq
.tail
,
2231 wqe
= get_recv_wqe(qp
, ind
);
2233 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
2235 wqe
+= sizeof (struct mthca_next_seg
);
2237 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
2243 for (i
= 0; i
< wr
->num_sge
; ++i
) {
2244 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2245 cpu_to_be32(wr
->sg_list
[i
].length
);
2246 ((struct mthca_data_seg
*) wqe
)->lkey
=
2247 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2248 ((struct mthca_data_seg
*) wqe
)->addr
=
2249 cpu_to_be64(wr
->sg_list
[i
].addr
);
2250 wqe
+= sizeof (struct mthca_data_seg
);
2253 if (i
< qp
->rq
.max_gs
) {
2254 ((struct mthca_data_seg
*) wqe
)->byte_count
= 0;
2255 ((struct mthca_data_seg
*) wqe
)->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
2256 ((struct mthca_data_seg
*) wqe
)->addr
= 0;
2259 qp
->wrid
[ind
] = wr
->wr_id
;
2262 if (unlikely(ind
>= qp
->rq
.max
))
2267 qp
->rq
.head
+= nreq
;
2270 * Make sure that descriptors are written before
2274 *qp
->rq
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
2277 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
2281 void mthca_free_err_wqe(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int is_send
,
2282 int index
, int *dbd
, __be32
*new_wqe
)
2284 struct mthca_next_seg
*next
;
2287 * For SRQs, all receive WQEs generate a CQE, so we're always
2288 * at the end of the doorbell chain.
2290 if (qp
->ibqp
.srq
&& !is_send
) {
2296 next
= get_send_wqe(qp
, index
);
2298 next
= get_recv_wqe(qp
, index
);
2300 *dbd
= !!(next
->ee_nds
& cpu_to_be32(MTHCA_NEXT_DBD
));
2301 if (next
->ee_nds
& cpu_to_be32(0x3f))
2302 *new_wqe
= (next
->nda_op
& cpu_to_be32(~0x3f)) |
2303 (next
->ee_nds
& cpu_to_be32(0x3f));
2308 int mthca_init_qp_table(struct mthca_dev
*dev
)
2314 spin_lock_init(&dev
->qp_table
.lock
);
2317 * We reserve 2 extra QPs per port for the special QPs. The
2318 * special QP for port 1 has to be even, so round up.
2320 dev
->qp_table
.sqp_start
= (dev
->limits
.reserved_qps
+ 1) & ~1UL;
2321 err
= mthca_alloc_init(&dev
->qp_table
.alloc
,
2322 dev
->limits
.num_qps
,
2324 dev
->qp_table
.sqp_start
+
2325 MTHCA_MAX_PORTS
* 2);
2329 err
= mthca_array_init(&dev
->qp_table
.qp
,
2330 dev
->limits
.num_qps
);
2332 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2336 for (i
= 0; i
< 2; ++i
) {
2337 err
= mthca_CONF_SPECIAL_QP(dev
, i
? IB_QPT_GSI
: IB_QPT_SMI
,
2338 dev
->qp_table
.sqp_start
+ i
* 2,
2343 mthca_warn(dev
, "CONF_SPECIAL_QP returned "
2344 "status %02x, aborting.\n",
2353 for (i
= 0; i
< 2; ++i
)
2354 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2356 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2357 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2362 void mthca_cleanup_qp_table(struct mthca_dev
*dev
)
2367 for (i
= 0; i
< 2; ++i
)
2368 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2370 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2371 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);