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net: Remove unnecessary driver assignments of ethtool_ringparam fields to zero
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
blob18520cef3e947da88c82cfb727613f38b5522fd5
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/interrupt.h>
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/ethtool.h>
37 #include <linux/vmalloc.h>
38 #include <linux/uaccess.h>
39
40 #include "ixgbe.h"
41
42
43 #define IXGBE_ALL_RAR_ENTRIES 16
44
45 enum {NETDEV_STATS, IXGBE_STATS};
46
47 struct ixgbe_stats {
48 char stat_string[ETH_GSTRING_LEN];
49 int type;
50 int sizeof_stat;
51 int stat_offset;
52 };
53
54 #define IXGBE_STAT(m) IXGBE_STATS, \
55 sizeof(((struct ixgbe_adapter *)0)->m), \
56 offsetof(struct ixgbe_adapter, m)
57 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
58 sizeof(((struct rtnl_link_stats64 *)0)->m), \
59 offsetof(struct rtnl_link_stats64, m)
60
61 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
62 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
63 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
64 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
65 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
66 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
67 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
68 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
69 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
70 {"lsc_int", IXGBE_STAT(lsc_int)},
71 {"tx_busy", IXGBE_STAT(tx_busy)},
72 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
73 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
74 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
75 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
76 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
77 {"multicast", IXGBE_NETDEV_STAT(multicast)},
78 {"broadcast", IXGBE_STAT(stats.bprc)},
79 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
80 {"collisions", IXGBE_NETDEV_STAT(collisions)},
81 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
82 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
83 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
84 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
85 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
86 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
87 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
88 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
89 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
90 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
91 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
92 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
93 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
94 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
95 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
96 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
97 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
98 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
99 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
100 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
101 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
102 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
103 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
104 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
105 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
106 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
107 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
108 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
109 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
110 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
111 #ifdef IXGBE_FCOE
112 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
113 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
114 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
115 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
116 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
117 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
118 #endif /* IXGBE_FCOE */
119 };
120
121 #define IXGBE_QUEUE_STATS_LEN \
122 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
123 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
124 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
125 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
126 #define IXGBE_PB_STATS_LEN ( \
127 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
128 IXGBE_FLAG_DCB_ENABLED) ? \
129 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
130 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
131 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
132 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
133 / sizeof(u64) : 0)
134 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
135 IXGBE_PB_STATS_LEN + \
136 IXGBE_QUEUE_STATS_LEN)
137
138 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
139 "Register test (offline)", "Eeprom test (offline)",
140 "Interrupt test (offline)", "Loopback test (offline)",
141 "Link test (on/offline)"
142 };
143 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
144
145 static int ixgbe_get_settings(struct net_device *netdev,
146 struct ethtool_cmd *ecmd)
147 {
148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
149 struct ixgbe_hw *hw = &adapter->hw;
150 u32 link_speed = 0;
151 bool link_up;
152
153 ecmd->supported = SUPPORTED_10000baseT_Full;
154 ecmd->autoneg = AUTONEG_ENABLE;
155 ecmd->transceiver = XCVR_EXTERNAL;
156 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
157 (hw->phy.multispeed_fiber)) {
158 ecmd->supported |= (SUPPORTED_1000baseT_Full |
159 SUPPORTED_Autoneg);
160
161 switch (hw->mac.type) {
162 case ixgbe_mac_X540:
163 ecmd->supported |= SUPPORTED_100baseT_Full;
164 break;
165 default:
166 break;
167 }
168
169 ecmd->advertising = ADVERTISED_Autoneg;
170 if (hw->phy.autoneg_advertised) {
171 if (hw->phy.autoneg_advertised &
172 IXGBE_LINK_SPEED_100_FULL)
173 ecmd->advertising |= ADVERTISED_100baseT_Full;
174 if (hw->phy.autoneg_advertised &
175 IXGBE_LINK_SPEED_10GB_FULL)
176 ecmd->advertising |= ADVERTISED_10000baseT_Full;
177 if (hw->phy.autoneg_advertised &
178 IXGBE_LINK_SPEED_1GB_FULL)
179 ecmd->advertising |= ADVERTISED_1000baseT_Full;
180 } else {
181 /*
182 * Default advertised modes in case
183 * phy.autoneg_advertised isn't set.
184 */
185 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
186 ADVERTISED_1000baseT_Full);
187 if (hw->mac.type == ixgbe_mac_X540)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
189 }
190
191 if (hw->phy.media_type == ixgbe_media_type_copper) {
192 ecmd->supported |= SUPPORTED_TP;
193 ecmd->advertising |= ADVERTISED_TP;
194 ecmd->port = PORT_TP;
195 } else {
196 ecmd->supported |= SUPPORTED_FIBRE;
197 ecmd->advertising |= ADVERTISED_FIBRE;
198 ecmd->port = PORT_FIBRE;
199 }
200 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
201 /* Set as FIBRE until SERDES defined in kernel */
202 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
203 ecmd->supported = (SUPPORTED_1000baseT_Full |
204 SUPPORTED_FIBRE);
205 ecmd->advertising = (ADVERTISED_1000baseT_Full |
206 ADVERTISED_FIBRE);
207 ecmd->port = PORT_FIBRE;
208 ecmd->autoneg = AUTONEG_DISABLE;
209 } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) ||
210 (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {
211 ecmd->supported |= (SUPPORTED_1000baseT_Full |
212 SUPPORTED_Autoneg |
213 SUPPORTED_FIBRE);
214 ecmd->advertising = (ADVERTISED_10000baseT_Full |
215 ADVERTISED_1000baseT_Full |
216 ADVERTISED_Autoneg |
217 ADVERTISED_FIBRE);
218 ecmd->port = PORT_FIBRE;
219 } else {
220 ecmd->supported |= (SUPPORTED_1000baseT_Full |
221 SUPPORTED_FIBRE);
222 ecmd->advertising = (ADVERTISED_10000baseT_Full |
223 ADVERTISED_1000baseT_Full |
224 ADVERTISED_FIBRE);
225 ecmd->port = PORT_FIBRE;
226 }
227 } else {
228 ecmd->supported |= SUPPORTED_FIBRE;
229 ecmd->advertising = (ADVERTISED_10000baseT_Full |
230 ADVERTISED_FIBRE);
231 ecmd->port = PORT_FIBRE;
232 ecmd->autoneg = AUTONEG_DISABLE;
233 }
234
235 /* Get PHY type */
236 switch (adapter->hw.phy.type) {
237 case ixgbe_phy_tn:
238 case ixgbe_phy_aq:
239 case ixgbe_phy_cu_unknown:
240 /* Copper 10G-BASET */
241 ecmd->port = PORT_TP;
242 break;
243 case ixgbe_phy_qt:
244 ecmd->port = PORT_FIBRE;
245 break;
246 case ixgbe_phy_nl:
247 case ixgbe_phy_sfp_passive_tyco:
248 case ixgbe_phy_sfp_passive_unknown:
249 case ixgbe_phy_sfp_ftl:
250 case ixgbe_phy_sfp_avago:
251 case ixgbe_phy_sfp_intel:
252 case ixgbe_phy_sfp_unknown:
253 switch (adapter->hw.phy.sfp_type) {
254 /* SFP+ devices, further checking needed */
255 case ixgbe_sfp_type_da_cu:
256 case ixgbe_sfp_type_da_cu_core0:
257 case ixgbe_sfp_type_da_cu_core1:
258 ecmd->port = PORT_DA;
259 break;
260 case ixgbe_sfp_type_sr:
261 case ixgbe_sfp_type_lr:
262 case ixgbe_sfp_type_srlr_core0:
263 case ixgbe_sfp_type_srlr_core1:
264 ecmd->port = PORT_FIBRE;
265 break;
266 case ixgbe_sfp_type_not_present:
267 ecmd->port = PORT_NONE;
268 break;
269 case ixgbe_sfp_type_1g_cu_core0:
270 case ixgbe_sfp_type_1g_cu_core1:
271 ecmd->port = PORT_TP;
272 ecmd->supported = SUPPORTED_TP;
273 ecmd->advertising = (ADVERTISED_1000baseT_Full |
274 ADVERTISED_TP);
275 break;
276 case ixgbe_sfp_type_unknown:
277 default:
278 ecmd->port = PORT_OTHER;
279 break;
280 }
281 break;
282 case ixgbe_phy_xaui:
283 ecmd->port = PORT_NONE;
284 break;
285 case ixgbe_phy_unknown:
286 case ixgbe_phy_generic:
287 case ixgbe_phy_sfp_unsupported:
288 default:
289 ecmd->port = PORT_OTHER;
290 break;
291 }
292
293 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
294 if (link_up) {
295 switch (link_speed) {
296 case IXGBE_LINK_SPEED_10GB_FULL:
297 ethtool_cmd_speed_set(ecmd, SPEED_10000);
298 break;
299 case IXGBE_LINK_SPEED_1GB_FULL:
300 ethtool_cmd_speed_set(ecmd, SPEED_1000);
301 break;
302 case IXGBE_LINK_SPEED_100_FULL:
303 ethtool_cmd_speed_set(ecmd, SPEED_100);
304 break;
305 default:
306 break;
307 }
308 ecmd->duplex = DUPLEX_FULL;
309 } else {
310 ethtool_cmd_speed_set(ecmd, -1);
311 ecmd->duplex = -1;
312 }
313
314 return 0;
315 }
316
317 static int ixgbe_set_settings(struct net_device *netdev,
318 struct ethtool_cmd *ecmd)
319 {
320 struct ixgbe_adapter *adapter = netdev_priv(netdev);
321 struct ixgbe_hw *hw = &adapter->hw;
322 u32 advertised, old;
323 s32 err = 0;
324
325 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
326 (hw->phy.multispeed_fiber)) {
327 /*
328 * this function does not support duplex forcing, but can
329 * limit the advertising of the adapter to the specified speed
330 */
331 if (ecmd->autoneg == AUTONEG_DISABLE)
332 return -EINVAL;
333
334 if (ecmd->advertising & ~ecmd->supported)
335 return -EINVAL;
336
337 old = hw->phy.autoneg_advertised;
338 advertised = 0;
339 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
340 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
341
342 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
343 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
344
345 if (ecmd->advertising & ADVERTISED_100baseT_Full)
346 advertised |= IXGBE_LINK_SPEED_100_FULL;
347
348 if (old == advertised)
349 return err;
350 /* this sets the link speed and restarts auto-neg */
351 hw->mac.autotry_restart = true;
352 err = hw->mac.ops.setup_link(hw, advertised, true, true);
353 if (err) {
354 e_info(probe, "setup link failed with code %d\n", err);
355 hw->mac.ops.setup_link(hw, old, true, true);
356 }
357 } else {
358 /* in this case we currently only support 10Gb/FULL */
359 u32 speed = ethtool_cmd_speed(ecmd);
360 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
361 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
362 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
363 return -EINVAL;
364 }
365
366 return err;
367 }
368
369 static void ixgbe_get_pauseparam(struct net_device *netdev,
370 struct ethtool_pauseparam *pause)
371 {
372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
373 struct ixgbe_hw *hw = &adapter->hw;
374
375 if (hw->fc.disable_fc_autoneg)
376 pause->autoneg = 0;
377 else
378 pause->autoneg = 1;
379
380 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
381 pause->rx_pause = 1;
382 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
383 pause->tx_pause = 1;
384 } else if (hw->fc.current_mode == ixgbe_fc_full) {
385 pause->rx_pause = 1;
386 pause->tx_pause = 1;
387 #ifdef CONFIG_DCB
388 } else if (hw->fc.current_mode == ixgbe_fc_pfc) {
389 pause->rx_pause = 0;
390 pause->tx_pause = 0;
391 #endif
392 }
393 }
394
395 static int ixgbe_set_pauseparam(struct net_device *netdev,
396 struct ethtool_pauseparam *pause)
397 {
398 struct ixgbe_adapter *adapter = netdev_priv(netdev);
399 struct ixgbe_hw *hw = &adapter->hw;
400 struct ixgbe_fc_info fc;
401
402 #ifdef CONFIG_DCB
403 if (adapter->dcb_cfg.pfc_mode_enable ||
404 ((hw->mac.type == ixgbe_mac_82598EB) &&
405 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
406 return -EINVAL;
407
408 #endif
409 fc = hw->fc;
410
411 if (pause->autoneg != AUTONEG_ENABLE)
412 fc.disable_fc_autoneg = true;
413 else
414 fc.disable_fc_autoneg = false;
415
416 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
417 fc.requested_mode = ixgbe_fc_full;
418 else if (pause->rx_pause && !pause->tx_pause)
419 fc.requested_mode = ixgbe_fc_rx_pause;
420 else if (!pause->rx_pause && pause->tx_pause)
421 fc.requested_mode = ixgbe_fc_tx_pause;
422 else if (!pause->rx_pause && !pause->tx_pause)
423 fc.requested_mode = ixgbe_fc_none;
424 else
425 return -EINVAL;
426
427 #ifdef CONFIG_DCB
428 adapter->last_lfc_mode = fc.requested_mode;
429 #endif
430
431 /* if the thing changed then we'll update and use new autoneg */
432 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
433 hw->fc = fc;
434 if (netif_running(netdev))
435 ixgbe_reinit_locked(adapter);
436 else
437 ixgbe_reset(adapter);
438 }
439
440 return 0;
441 }
442
443 static u32 ixgbe_get_msglevel(struct net_device *netdev)
444 {
445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
446 return adapter->msg_enable;
447 }
448
449 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
450 {
451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
452 adapter->msg_enable = data;
453 }
454
455 static int ixgbe_get_regs_len(struct net_device *netdev)
456 {
457 #define IXGBE_REGS_LEN 1129
458 return IXGBE_REGS_LEN * sizeof(u32);
459 }
460
461 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
462
463 static void ixgbe_get_regs(struct net_device *netdev,
464 struct ethtool_regs *regs, void *p)
465 {
466 struct ixgbe_adapter *adapter = netdev_priv(netdev);
467 struct ixgbe_hw *hw = &adapter->hw;
468 u32 *regs_buff = p;
469 u8 i;
470
471 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
472
473 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
474
475 /* General Registers */
476 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
477 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
478 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
479 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
480 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
481 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
482 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
483 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
484
485 /* NVM Register */
486 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
487 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
488 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
489 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
490 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
491 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
492 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
493 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
494 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
495 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
496
497 /* Interrupt */
498 /* don't read EICR because it can clear interrupt causes, instead
499 * read EICS which is a shadow but doesn't clear EICR */
500 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
501 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
502 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
503 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
504 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
505 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
506 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
507 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
508 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
509 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
510 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
511 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
512
513 /* Flow Control */
514 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
515 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
516 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
517 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
518 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
519 for (i = 0; i < 8; i++) {
520 switch (hw->mac.type) {
521 case ixgbe_mac_82598EB:
522 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
523 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
524 break;
525 case ixgbe_mac_82599EB:
526 case ixgbe_mac_X540:
527 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
528 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
529 break;
530 default:
531 break;
532 }
533 }
534 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
535 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
536
537 /* Receive DMA */
538 for (i = 0; i < 64; i++)
539 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
540 for (i = 0; i < 64; i++)
541 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
542 for (i = 0; i < 64; i++)
543 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
544 for (i = 0; i < 64; i++)
545 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
546 for (i = 0; i < 64; i++)
547 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
548 for (i = 0; i < 64; i++)
549 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
550 for (i = 0; i < 16; i++)
551 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
552 for (i = 0; i < 16; i++)
553 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
554 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
555 for (i = 0; i < 8; i++)
556 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
557 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
558 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
559
560 /* Receive */
561 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
562 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
563 for (i = 0; i < 16; i++)
564 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
565 for (i = 0; i < 16; i++)
566 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
567 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
568 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
569 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
570 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
571 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
572 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
573 for (i = 0; i < 8; i++)
574 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
575 for (i = 0; i < 8; i++)
576 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
577 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
578
579 /* Transmit */
580 for (i = 0; i < 32; i++)
581 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
582 for (i = 0; i < 32; i++)
583 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
584 for (i = 0; i < 32; i++)
585 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
586 for (i = 0; i < 32; i++)
587 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
588 for (i = 0; i < 32; i++)
589 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
590 for (i = 0; i < 32; i++)
591 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
592 for (i = 0; i < 32; i++)
593 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
594 for (i = 0; i < 32; i++)
595 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
596 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
597 for (i = 0; i < 16; i++)
598 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
599 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
600 for (i = 0; i < 8; i++)
601 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
602 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
603
604 /* Wake Up */
605 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
606 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
607 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
608 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
609 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
610 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
611 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
612 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
613 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
614
615 /* DCB */
616 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
617 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
618 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
619 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
620 for (i = 0; i < 8; i++)
621 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
622 for (i = 0; i < 8; i++)
623 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
624 for (i = 0; i < 8; i++)
625 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
626 for (i = 0; i < 8; i++)
627 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
628 for (i = 0; i < 8; i++)
629 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
630 for (i = 0; i < 8; i++)
631 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
632
633 /* Statistics */
634 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
635 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
636 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
637 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
638 for (i = 0; i < 8; i++)
639 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
640 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
641 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
642 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
643 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
644 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
645 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
646 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
647 for (i = 0; i < 8; i++)
648 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
649 for (i = 0; i < 8; i++)
650 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
651 for (i = 0; i < 8; i++)
652 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
653 for (i = 0; i < 8; i++)
654 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
655 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
656 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
657 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
658 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
659 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
660 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
661 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
662 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
663 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
664 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
665 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
666 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
667 for (i = 0; i < 8; i++)
668 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
669 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
670 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
671 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
672 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
673 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
674 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
675 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
676 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
677 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
678 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
679 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
680 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
681 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
682 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
683 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
684 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
685 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
686 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
687 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
688 for (i = 0; i < 16; i++)
689 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
690 for (i = 0; i < 16; i++)
691 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
692 for (i = 0; i < 16; i++)
693 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
694 for (i = 0; i < 16; i++)
695 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
696
697 /* MAC */
698 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
699 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
700 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
701 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
702 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
703 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
704 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
705 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
706 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
707 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
708 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
709 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
710 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
711 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
712 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
713 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
714 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
715 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
716 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
717 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
718 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
719 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
720 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
721 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
722 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
723 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
724 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
725 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
726 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
727 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
728 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
729 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
730 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
731
732 /* Diagnostic */
733 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
734 for (i = 0; i < 8; i++)
735 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
736 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
737 for (i = 0; i < 4; i++)
738 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
739 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
740 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
741 for (i = 0; i < 8; i++)
742 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
743 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
744 for (i = 0; i < 4; i++)
745 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
746 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
747 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
748 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
749 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
750 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
751 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
752 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
753 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
754 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
755 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
756 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
757 for (i = 0; i < 8; i++)
758 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
759 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
760 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
761 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
762 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
763 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
764 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
765 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
766 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
767 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
768
769 /* 82599 X540 specific registers */
770 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
771 }
772
773 static int ixgbe_get_eeprom_len(struct net_device *netdev)
774 {
775 struct ixgbe_adapter *adapter = netdev_priv(netdev);
776 return adapter->hw.eeprom.word_size * 2;
777 }
778
779 static int ixgbe_get_eeprom(struct net_device *netdev,
780 struct ethtool_eeprom *eeprom, u8 *bytes)
781 {
782 struct ixgbe_adapter *adapter = netdev_priv(netdev);
783 struct ixgbe_hw *hw = &adapter->hw;
784 u16 *eeprom_buff;
785 int first_word, last_word, eeprom_len;
786 int ret_val = 0;
787 u16 i;
788
789 if (eeprom->len == 0)
790 return -EINVAL;
791
792 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
793
794 first_word = eeprom->offset >> 1;
795 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
796 eeprom_len = last_word - first_word + 1;
797
798 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
799 if (!eeprom_buff)
800 return -ENOMEM;
801
802 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
803 eeprom_buff);
804
805 /* Device's eeprom is always little-endian, word addressable */
806 for (i = 0; i < eeprom_len; i++)
807 le16_to_cpus(&eeprom_buff[i]);
808
809 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
810 kfree(eeprom_buff);
811
812 return ret_val;
813 }
814
815 static void ixgbe_get_drvinfo(struct net_device *netdev,
816 struct ethtool_drvinfo *drvinfo)
817 {
818 struct ixgbe_adapter *adapter = netdev_priv(netdev);
819 char firmware_version[32];
820
821 strncpy(drvinfo->driver, ixgbe_driver_name,
822 sizeof(drvinfo->driver) - 1);
823 strncpy(drvinfo->version, ixgbe_driver_version,
824 sizeof(drvinfo->version) - 1);
825
826 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
827 (adapter->eeprom_version & 0xF000) >> 12,
828 (adapter->eeprom_version & 0x0FF0) >> 4,
829 adapter->eeprom_version & 0x000F);
830
831 strncpy(drvinfo->fw_version, firmware_version,
832 sizeof(drvinfo->fw_version));
833 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
834 sizeof(drvinfo->bus_info));
835 drvinfo->n_stats = IXGBE_STATS_LEN;
836 drvinfo->testinfo_len = IXGBE_TEST_LEN;
837 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
838 }
839
840 static void ixgbe_get_ringparam(struct net_device *netdev,
841 struct ethtool_ringparam *ring)
842 {
843 struct ixgbe_adapter *adapter = netdev_priv(netdev);
844 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
845 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
846
847 ring->rx_max_pending = IXGBE_MAX_RXD;
848 ring->tx_max_pending = IXGBE_MAX_TXD;
849 ring->rx_pending = rx_ring->count;
850 ring->tx_pending = tx_ring->count;
851 }
852
853 static int ixgbe_set_ringparam(struct net_device *netdev,
854 struct ethtool_ringparam *ring)
855 {
856 struct ixgbe_adapter *adapter = netdev_priv(netdev);
857 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
858 int i, err = 0;
859 u32 new_rx_count, new_tx_count;
860 bool need_update = false;
861
862 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
863 return -EINVAL;
864
865 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
866 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
867 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
868
869 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
870 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
871 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
872
873 if ((new_tx_count == adapter->tx_ring[0]->count) &&
874 (new_rx_count == adapter->rx_ring[0]->count)) {
875 /* nothing to do */
876 return 0;
877 }
878
879 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
880 usleep_range(1000, 2000);
881
882 if (!netif_running(adapter->netdev)) {
883 for (i = 0; i < adapter->num_tx_queues; i++)
884 adapter->tx_ring[i]->count = new_tx_count;
885 for (i = 0; i < adapter->num_rx_queues; i++)
886 adapter->rx_ring[i]->count = new_rx_count;
887 adapter->tx_ring_count = new_tx_count;
888 adapter->rx_ring_count = new_rx_count;
889 goto clear_reset;
890 }
891
892 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
893 if (!temp_tx_ring) {
894 err = -ENOMEM;
895 goto clear_reset;
896 }
897
898 if (new_tx_count != adapter->tx_ring_count) {
899 for (i = 0; i < adapter->num_tx_queues; i++) {
900 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
901 sizeof(struct ixgbe_ring));
902 temp_tx_ring[i].count = new_tx_count;
903 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
904 if (err) {
905 while (i) {
906 i--;
907 ixgbe_free_tx_resources(&temp_tx_ring[i]);
908 }
909 goto clear_reset;
910 }
911 }
912 need_update = true;
913 }
914
915 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
916 if (!temp_rx_ring) {
917 err = -ENOMEM;
918 goto err_setup;
919 }
920
921 if (new_rx_count != adapter->rx_ring_count) {
922 for (i = 0; i < adapter->num_rx_queues; i++) {
923 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
924 sizeof(struct ixgbe_ring));
925 temp_rx_ring[i].count = new_rx_count;
926 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
927 if (err) {
928 while (i) {
929 i--;
930 ixgbe_free_rx_resources(&temp_rx_ring[i]);
931 }
932 goto err_setup;
933 }
934 }
935 need_update = true;
936 }
937
938 /* if rings need to be updated, here's the place to do it in one shot */
939 if (need_update) {
940 ixgbe_down(adapter);
941
942 /* tx */
943 if (new_tx_count != adapter->tx_ring_count) {
944 for (i = 0; i < adapter->num_tx_queues; i++) {
945 ixgbe_free_tx_resources(adapter->tx_ring[i]);
946 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
947 sizeof(struct ixgbe_ring));
948 }
949 adapter->tx_ring_count = new_tx_count;
950 }
951
952 /* rx */
953 if (new_rx_count != adapter->rx_ring_count) {
954 for (i = 0; i < adapter->num_rx_queues; i++) {
955 ixgbe_free_rx_resources(adapter->rx_ring[i]);
956 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
957 sizeof(struct ixgbe_ring));
958 }
959 adapter->rx_ring_count = new_rx_count;
960 }
961 ixgbe_up(adapter);
962 }
963
964 vfree(temp_rx_ring);
965 err_setup:
966 vfree(temp_tx_ring);
967 clear_reset:
968 clear_bit(__IXGBE_RESETTING, &adapter->state);
969 return err;
970 }
971
972 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
973 {
974 switch (sset) {
975 case ETH_SS_TEST:
976 return IXGBE_TEST_LEN;
977 case ETH_SS_STATS:
978 return IXGBE_STATS_LEN;
979 default:
980 return -EOPNOTSUPP;
981 }
982 }
983
984 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
985 struct ethtool_stats *stats, u64 *data)
986 {
987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
988 struct rtnl_link_stats64 temp;
989 const struct rtnl_link_stats64 *net_stats;
990 unsigned int start;
991 struct ixgbe_ring *ring;
992 int i, j;
993 char *p = NULL;
994
995 ixgbe_update_stats(adapter);
996 net_stats = dev_get_stats(netdev, &temp);
997 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
998 switch (ixgbe_gstrings_stats[i].type) {
999 case NETDEV_STATS:
1000 p = (char *) net_stats +
1001 ixgbe_gstrings_stats[i].stat_offset;
1002 break;
1003 case IXGBE_STATS:
1004 p = (char *) adapter +
1005 ixgbe_gstrings_stats[i].stat_offset;
1006 break;
1007 }
1008
1009 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1010 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1011 }
1012 for (j = 0; j < adapter->num_tx_queues; j++) {
1013 ring = adapter->tx_ring[j];
1014 do {
1015 start = u64_stats_fetch_begin_bh(&ring->syncp);
1016 data[i] = ring->stats.packets;
1017 data[i+1] = ring->stats.bytes;
1018 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1019 i += 2;
1020 }
1021 for (j = 0; j < adapter->num_rx_queues; j++) {
1022 ring = adapter->rx_ring[j];
1023 do {
1024 start = u64_stats_fetch_begin_bh(&ring->syncp);
1025 data[i] = ring->stats.packets;
1026 data[i+1] = ring->stats.bytes;
1027 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1028 i += 2;
1029 }
1030 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1031 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1032 data[i++] = adapter->stats.pxontxc[j];
1033 data[i++] = adapter->stats.pxofftxc[j];
1034 }
1035 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1036 data[i++] = adapter->stats.pxonrxc[j];
1037 data[i++] = adapter->stats.pxoffrxc[j];
1038 }
1039 }
1040 }
1041
1042 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1043 u8 *data)
1044 {
1045 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1046 char *p = (char *)data;
1047 int i;
1048
1049 switch (stringset) {
1050 case ETH_SS_TEST:
1051 memcpy(data, *ixgbe_gstrings_test,
1052 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1053 break;
1054 case ETH_SS_STATS:
1055 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1056 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1057 ETH_GSTRING_LEN);
1058 p += ETH_GSTRING_LEN;
1059 }
1060 for (i = 0; i < adapter->num_tx_queues; i++) {
1061 sprintf(p, "tx_queue_%u_packets", i);
1062 p += ETH_GSTRING_LEN;
1063 sprintf(p, "tx_queue_%u_bytes", i);
1064 p += ETH_GSTRING_LEN;
1065 }
1066 for (i = 0; i < adapter->num_rx_queues; i++) {
1067 sprintf(p, "rx_queue_%u_packets", i);
1068 p += ETH_GSTRING_LEN;
1069 sprintf(p, "rx_queue_%u_bytes", i);
1070 p += ETH_GSTRING_LEN;
1071 }
1072 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1073 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1074 sprintf(p, "tx_pb_%u_pxon", i);
1075 p += ETH_GSTRING_LEN;
1076 sprintf(p, "tx_pb_%u_pxoff", i);
1077 p += ETH_GSTRING_LEN;
1078 }
1079 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1080 sprintf(p, "rx_pb_%u_pxon", i);
1081 p += ETH_GSTRING_LEN;
1082 sprintf(p, "rx_pb_%u_pxoff", i);
1083 p += ETH_GSTRING_LEN;
1084 }
1085 }
1086 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1087 break;
1088 }
1089 }
1090
1091 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1092 {
1093 struct ixgbe_hw *hw = &adapter->hw;
1094 bool link_up;
1095 u32 link_speed = 0;
1096 *data = 0;
1097
1098 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1099 if (link_up)
1100 return *data;
1101 else
1102 *data = 1;
1103 return *data;
1104 }
1105
1106 /* ethtool register test data */
1107 struct ixgbe_reg_test {
1108 u16 reg;
1109 u8 array_len;
1110 u8 test_type;
1111 u32 mask;
1112 u32 write;
1113 };
1114
1115 /* In the hardware, registers are laid out either singly, in arrays
1116 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1117 * most tests take place on arrays or single registers (handled
1118 * as a single-element array) and special-case the tables.
1119 * Table tests are always pattern tests.
1120 *
1121 * We also make provision for some required setup steps by specifying
1122 * registers to be written without any read-back testing.
1123 */
1124
1125 #define PATTERN_TEST 1
1126 #define SET_READ_TEST 2
1127 #define WRITE_NO_TEST 3
1128 #define TABLE32_TEST 4
1129 #define TABLE64_TEST_LO 5
1130 #define TABLE64_TEST_HI 6
1131
1132 /* default 82599 register test */
1133 static const struct ixgbe_reg_test reg_test_82599[] = {
1134 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1135 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1136 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1137 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1138 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1139 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1140 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1141 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1142 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1143 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1144 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1145 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1146 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1147 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1149 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1150 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1152 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1153 { 0, 0, 0, 0 }
1154 };
1155
1156 /* default 82598 register test */
1157 static const struct ixgbe_reg_test reg_test_82598[] = {
1158 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1159 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1160 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1161 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1162 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1163 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1164 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1165 /* Enable all four RX queues before testing. */
1166 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1167 /* RDH is read-only for 82598, only test RDT. */
1168 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1169 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1170 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1171 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1172 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1173 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1174 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1175 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1176 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1177 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1178 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1179 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1180 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1181 { 0, 0, 0, 0 }
1182 };
1183
1184 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1185 u32 mask, u32 write)
1186 {
1187 u32 pat, val, before;
1188 static const u32 test_pattern[] = {
1189 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1190
1191 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1192 before = readl(adapter->hw.hw_addr + reg);
1193 writel((test_pattern[pat] & write),
1194 (adapter->hw.hw_addr + reg));
1195 val = readl(adapter->hw.hw_addr + reg);
1196 if (val != (test_pattern[pat] & write & mask)) {
1197 e_err(drv, "pattern test reg %04X failed: got "
1198 "0x%08X expected 0x%08X\n",
1199 reg, val, (test_pattern[pat] & write & mask));
1200 *data = reg;
1201 writel(before, adapter->hw.hw_addr + reg);
1202 return 1;
1203 }
1204 writel(before, adapter->hw.hw_addr + reg);
1205 }
1206 return 0;
1207 }
1208
1209 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1210 u32 mask, u32 write)
1211 {
1212 u32 val, before;
1213 before = readl(adapter->hw.hw_addr + reg);
1214 writel((write & mask), (adapter->hw.hw_addr + reg));
1215 val = readl(adapter->hw.hw_addr + reg);
1216 if ((write & mask) != (val & mask)) {
1217 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1218 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1219 *data = reg;
1220 writel(before, (adapter->hw.hw_addr + reg));
1221 return 1;
1222 }
1223 writel(before, (adapter->hw.hw_addr + reg));
1224 return 0;
1225 }
1226
1227 #define REG_PATTERN_TEST(reg, mask, write) \
1228 do { \
1229 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1230 return 1; \
1231 } while (0) \
1232
1233
1234 #define REG_SET_AND_CHECK(reg, mask, write) \
1235 do { \
1236 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1237 return 1; \
1238 } while (0) \
1239
1240 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1241 {
1242 const struct ixgbe_reg_test *test;
1243 u32 value, before, after;
1244 u32 i, toggle;
1245
1246 switch (adapter->hw.mac.type) {
1247 case ixgbe_mac_82598EB:
1248 toggle = 0x7FFFF3FF;
1249 test = reg_test_82598;
1250 break;
1251 case ixgbe_mac_82599EB:
1252 case ixgbe_mac_X540:
1253 toggle = 0x7FFFF30F;
1254 test = reg_test_82599;
1255 break;
1256 default:
1257 *data = 1;
1258 return 1;
1259 break;
1260 }
1261
1262 /*
1263 * Because the status register is such a special case,
1264 * we handle it separately from the rest of the register
1265 * tests. Some bits are read-only, some toggle, and some
1266 * are writeable on newer MACs.
1267 */
1268 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1269 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1271 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1272 if (value != after) {
1273 e_err(drv, "failed STATUS register test got: 0x%08X "
1274 "expected: 0x%08X\n", after, value);
1275 *data = 1;
1276 return 1;
1277 }
1278 /* restore previous status */
1279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1280
1281 /*
1282 * Perform the remainder of the register test, looping through
1283 * the test table until we either fail or reach the null entry.
1284 */
1285 while (test->reg) {
1286 for (i = 0; i < test->array_len; i++) {
1287 switch (test->test_type) {
1288 case PATTERN_TEST:
1289 REG_PATTERN_TEST(test->reg + (i * 0x40),
1290 test->mask,
1291 test->write);
1292 break;
1293 case SET_READ_TEST:
1294 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1295 test->mask,
1296 test->write);
1297 break;
1298 case WRITE_NO_TEST:
1299 writel(test->write,
1300 (adapter->hw.hw_addr + test->reg)
1301 + (i * 0x40));
1302 break;
1303 case TABLE32_TEST:
1304 REG_PATTERN_TEST(test->reg + (i * 4),
1305 test->mask,
1306 test->write);
1307 break;
1308 case TABLE64_TEST_LO:
1309 REG_PATTERN_TEST(test->reg + (i * 8),
1310 test->mask,
1311 test->write);
1312 break;
1313 case TABLE64_TEST_HI:
1314 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1315 test->mask,
1316 test->write);
1317 break;
1318 }
1319 }
1320 test++;
1321 }
1322
1323 *data = 0;
1324 return 0;
1325 }
1326
1327 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1328 {
1329 struct ixgbe_hw *hw = &adapter->hw;
1330 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1331 *data = 1;
1332 else
1333 *data = 0;
1334 return *data;
1335 }
1336
1337 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1338 {
1339 struct net_device *netdev = (struct net_device *) data;
1340 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1341
1342 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1343
1344 return IRQ_HANDLED;
1345 }
1346
1347 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1348 {
1349 struct net_device *netdev = adapter->netdev;
1350 u32 mask, i = 0, shared_int = true;
1351 u32 irq = adapter->pdev->irq;
1352
1353 *data = 0;
1354
1355 /* Hook up test interrupt handler just for this test */
1356 if (adapter->msix_entries) {
1357 /* NOTE: we don't test MSI-X interrupts here, yet */
1358 return 0;
1359 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1360 shared_int = false;
1361 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1362 netdev)) {
1363 *data = 1;
1364 return -1;
1365 }
1366 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1367 netdev->name, netdev)) {
1368 shared_int = false;
1369 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1370 netdev->name, netdev)) {
1371 *data = 1;
1372 return -1;
1373 }
1374 e_info(hw, "testing %s interrupt\n", shared_int ?
1375 "shared" : "unshared");
1376
1377 /* Disable all the interrupts */
1378 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1379 IXGBE_WRITE_FLUSH(&adapter->hw);
1380 usleep_range(10000, 20000);
1381
1382 /* Test each interrupt */
1383 for (; i < 10; i++) {
1384 /* Interrupt to test */
1385 mask = 1 << i;
1386
1387 if (!shared_int) {
1388 /*
1389 * Disable the interrupts to be reported in
1390 * the cause register and then force the same
1391 * interrupt and see if one gets posted. If
1392 * an interrupt was posted to the bus, the
1393 * test failed.
1394 */
1395 adapter->test_icr = 0;
1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1397 ~mask & 0x00007FFF);
1398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1399 ~mask & 0x00007FFF);
1400 IXGBE_WRITE_FLUSH(&adapter->hw);
1401 usleep_range(10000, 20000);
1402
1403 if (adapter->test_icr & mask) {
1404 *data = 3;
1405 break;
1406 }
1407 }
1408
1409 /*
1410 * Enable the interrupt to be reported in the cause
1411 * register and then force the same interrupt and see
1412 * if one gets posted. If an interrupt was not posted
1413 * to the bus, the test failed.
1414 */
1415 adapter->test_icr = 0;
1416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1418 IXGBE_WRITE_FLUSH(&adapter->hw);
1419 usleep_range(10000, 20000);
1420
1421 if (!(adapter->test_icr &mask)) {
1422 *data = 4;
1423 break;
1424 }
1425
1426 if (!shared_int) {
1427 /*
1428 * Disable the other interrupts to be reported in
1429 * the cause register and then force the other
1430 * interrupts and see if any get posted. If
1431 * an interrupt was posted to the bus, the
1432 * test failed.
1433 */
1434 adapter->test_icr = 0;
1435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1436 ~mask & 0x00007FFF);
1437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1438 ~mask & 0x00007FFF);
1439 IXGBE_WRITE_FLUSH(&adapter->hw);
1440 usleep_range(10000, 20000);
1441
1442 if (adapter->test_icr) {
1443 *data = 5;
1444 break;
1445 }
1446 }
1447 }
1448
1449 /* Disable all the interrupts */
1450 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1451 IXGBE_WRITE_FLUSH(&adapter->hw);
1452 usleep_range(10000, 20000);
1453
1454 /* Unhook test interrupt handler */
1455 free_irq(irq, netdev);
1456
1457 return *data;
1458 }
1459
1460 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1461 {
1462 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1463 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1464 struct ixgbe_hw *hw = &adapter->hw;
1465 u32 reg_ctl;
1466
1467 /* shut down the DMA engines now so they can be reinitialized later */
1468
1469 /* first Rx */
1470 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1471 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1472 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1473 ixgbe_disable_rx_queue(adapter, rx_ring);
1474
1475 /* now Tx */
1476 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1477 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1478 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1479
1480 switch (hw->mac.type) {
1481 case ixgbe_mac_82599EB:
1482 case ixgbe_mac_X540:
1483 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1484 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1485 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1486 break;
1487 default:
1488 break;
1489 }
1490
1491 ixgbe_reset(adapter);
1492
1493 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1494 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1495 }
1496
1497 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1498 {
1499 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1500 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1501 u32 rctl, reg_data;
1502 int ret_val;
1503 int err;
1504
1505 /* Setup Tx descriptor ring and Tx buffers */
1506 tx_ring->count = IXGBE_DEFAULT_TXD;
1507 tx_ring->queue_index = 0;
1508 tx_ring->dev = &adapter->pdev->dev;
1509 tx_ring->netdev = adapter->netdev;
1510 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1511 tx_ring->numa_node = adapter->node;
1512
1513 err = ixgbe_setup_tx_resources(tx_ring);
1514 if (err)
1515 return 1;
1516
1517 switch (adapter->hw.mac.type) {
1518 case ixgbe_mac_82599EB:
1519 case ixgbe_mac_X540:
1520 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1521 reg_data |= IXGBE_DMATXCTL_TE;
1522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1523 break;
1524 default:
1525 break;
1526 }
1527
1528 ixgbe_configure_tx_ring(adapter, tx_ring);
1529
1530 /* Setup Rx Descriptor ring and Rx buffers */
1531 rx_ring->count = IXGBE_DEFAULT_RXD;
1532 rx_ring->queue_index = 0;
1533 rx_ring->dev = &adapter->pdev->dev;
1534 rx_ring->netdev = adapter->netdev;
1535 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1536 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2K;
1537 rx_ring->numa_node = adapter->node;
1538
1539 err = ixgbe_setup_rx_resources(rx_ring);
1540 if (err) {
1541 ret_val = 4;
1542 goto err_nomem;
1543 }
1544
1545 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1546 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1547
1548 ixgbe_configure_rx_ring(adapter, rx_ring);
1549
1550 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1551 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1552
1553 return 0;
1554
1555 err_nomem:
1556 ixgbe_free_desc_rings(adapter);
1557 return ret_val;
1558 }
1559
1560 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1561 {
1562 struct ixgbe_hw *hw = &adapter->hw;
1563 u32 reg_data;
1564
1565 /* X540 needs to set the MACC.FLU bit to force link up */
1566 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1567 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1568 reg_data |= IXGBE_MACC_FLU;
1569 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1570 }
1571
1572 /* right now we only support MAC loopback in the driver */
1573 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1574 /* Setup MAC loopback */
1575 reg_data |= IXGBE_HLREG0_LPBK;
1576 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1577
1578 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1579 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1580 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1581
1582 reg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1583 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1584 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1585 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1586 IXGBE_WRITE_FLUSH(hw);
1587 usleep_range(10000, 20000);
1588
1589 /* Disable Atlas Tx lanes; re-enabled in reset path */
1590 if (hw->mac.type == ixgbe_mac_82598EB) {
1591 u8 atlas;
1592
1593 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1594 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1595 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1596
1597 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1598 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1599 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1600
1601 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1602 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1603 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1604
1605 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1606 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1607 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1608 }
1609
1610 return 0;
1611 }
1612
1613 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1614 {
1615 u32 reg_data;
1616
1617 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1618 reg_data &= ~IXGBE_HLREG0_LPBK;
1619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1620 }
1621
1622 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1623 unsigned int frame_size)
1624 {
1625 memset(skb->data, 0xFF, frame_size);
1626 frame_size &= ~1;
1627 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1628 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1629 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1630 }
1631
1632 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1633 unsigned int frame_size)
1634 {
1635 frame_size &= ~1;
1636 if (*(skb->data + 3) == 0xFF) {
1637 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1638 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1639 return 0;
1640 }
1641 }
1642 return 13;
1643 }
1644
1645 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1646 struct ixgbe_ring *tx_ring,
1647 unsigned int size)
1648 {
1649 union ixgbe_adv_rx_desc *rx_desc;
1650 struct ixgbe_rx_buffer *rx_buffer_info;
1651 struct ixgbe_tx_buffer *tx_buffer_info;
1652 const int bufsz = rx_ring->rx_buf_len;
1653 u32 staterr;
1654 u16 rx_ntc, tx_ntc, count = 0;
1655
1656 /* initialize next to clean and descriptor values */
1657 rx_ntc = rx_ring->next_to_clean;
1658 tx_ntc = tx_ring->next_to_clean;
1659 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1660 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1661
1662 while (staterr & IXGBE_RXD_STAT_DD) {
1663 /* check Rx buffer */
1664 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1665
1666 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
1667 dma_unmap_single(rx_ring->dev,
1668 rx_buffer_info->dma,
1669 bufsz,
1670 DMA_FROM_DEVICE);
1671 rx_buffer_info->dma = 0;
1672
1673 /* verify contents of skb */
1674 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1675 count++;
1676
1677 /* unmap buffer on Tx side */
1678 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1679 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1680
1681 /* increment Rx/Tx next to clean counters */
1682 rx_ntc++;
1683 if (rx_ntc == rx_ring->count)
1684 rx_ntc = 0;
1685 tx_ntc++;
1686 if (tx_ntc == tx_ring->count)
1687 tx_ntc = 0;
1688
1689 /* fetch next descriptor */
1690 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1691 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1692 }
1693
1694 /* re-map buffers to ring, store next to clean values */
1695 ixgbe_alloc_rx_buffers(rx_ring, count);
1696 rx_ring->next_to_clean = rx_ntc;
1697 tx_ring->next_to_clean = tx_ntc;
1698
1699 return count;
1700 }
1701
1702 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1703 {
1704 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1705 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1706 int i, j, lc, good_cnt, ret_val = 0;
1707 unsigned int size = 1024;
1708 netdev_tx_t tx_ret_val;
1709 struct sk_buff *skb;
1710
1711 /* allocate test skb */
1712 skb = alloc_skb(size, GFP_KERNEL);
1713 if (!skb)
1714 return 11;
1715
1716 /* place data into test skb */
1717 ixgbe_create_lbtest_frame(skb, size);
1718 skb_put(skb, size);
1719
1720 /*
1721 * Calculate the loop count based on the largest descriptor ring
1722 * The idea is to wrap the largest ring a number of times using 64
1723 * send/receive pairs during each loop
1724 */
1725
1726 if (rx_ring->count <= tx_ring->count)
1727 lc = ((tx_ring->count / 64) * 2) + 1;
1728 else
1729 lc = ((rx_ring->count / 64) * 2) + 1;
1730
1731 for (j = 0; j <= lc; j++) {
1732 /* reset count of good packets */
1733 good_cnt = 0;
1734
1735 /* place 64 packets on the transmit queue*/
1736 for (i = 0; i < 64; i++) {
1737 skb_get(skb);
1738 tx_ret_val = ixgbe_xmit_frame_ring(skb,
1739 adapter,
1740 tx_ring);
1741 if (tx_ret_val == NETDEV_TX_OK)
1742 good_cnt++;
1743 }
1744
1745 if (good_cnt != 64) {
1746 ret_val = 12;
1747 break;
1748 }
1749
1750 /* allow 200 milliseconds for packets to go from Tx to Rx */
1751 msleep(200);
1752
1753 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
1754 if (good_cnt != 64) {
1755 ret_val = 13;
1756 break;
1757 }
1758 }
1759
1760 /* free the original skb */
1761 kfree_skb(skb);
1762
1763 return ret_val;
1764 }
1765
1766 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1767 {
1768 *data = ixgbe_setup_desc_rings(adapter);
1769 if (*data)
1770 goto out;
1771 *data = ixgbe_setup_loopback_test(adapter);
1772 if (*data)
1773 goto err_loopback;
1774 *data = ixgbe_run_loopback_test(adapter);
1775 ixgbe_loopback_cleanup(adapter);
1776
1777 err_loopback:
1778 ixgbe_free_desc_rings(adapter);
1779 out:
1780 return *data;
1781 }
1782
1783 static void ixgbe_diag_test(struct net_device *netdev,
1784 struct ethtool_test *eth_test, u64 *data)
1785 {
1786 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1787 bool if_running = netif_running(netdev);
1788
1789 set_bit(__IXGBE_TESTING, &adapter->state);
1790 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1791 /* Offline tests */
1792
1793 e_info(hw, "offline testing starting\n");
1794
1795 /* Link test performed before hardware reset so autoneg doesn't
1796 * interfere with test result */
1797 if (ixgbe_link_test(adapter, &data[4]))
1798 eth_test->flags |= ETH_TEST_FL_FAILED;
1799
1800 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1801 int i;
1802 for (i = 0; i < adapter->num_vfs; i++) {
1803 if (adapter->vfinfo[i].clear_to_send) {
1804 netdev_warn(netdev, "%s",
1805 "offline diagnostic is not "
1806 "supported when VFs are "
1807 "present\n");
1808 data[0] = 1;
1809 data[1] = 1;
1810 data[2] = 1;
1811 data[3] = 1;
1812 eth_test->flags |= ETH_TEST_FL_FAILED;
1813 clear_bit(__IXGBE_TESTING,
1814 &adapter->state);
1815 goto skip_ol_tests;
1816 }
1817 }
1818 }
1819
1820 if (if_running)
1821 /* indicate we're in test mode */
1822 dev_close(netdev);
1823 else
1824 ixgbe_reset(adapter);
1825
1826 e_info(hw, "register testing starting\n");
1827 if (ixgbe_reg_test(adapter, &data[0]))
1828 eth_test->flags |= ETH_TEST_FL_FAILED;
1829
1830 ixgbe_reset(adapter);
1831 e_info(hw, "eeprom testing starting\n");
1832 if (ixgbe_eeprom_test(adapter, &data[1]))
1833 eth_test->flags |= ETH_TEST_FL_FAILED;
1834
1835 ixgbe_reset(adapter);
1836 e_info(hw, "interrupt testing starting\n");
1837 if (ixgbe_intr_test(adapter, &data[2]))
1838 eth_test->flags |= ETH_TEST_FL_FAILED;
1839
1840 /* If SRIOV or VMDq is enabled then skip MAC
1841 * loopback diagnostic. */
1842 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1843 IXGBE_FLAG_VMDQ_ENABLED)) {
1844 e_info(hw, "Skip MAC loopback diagnostic in VT "
1845 "mode\n");
1846 data[3] = 0;
1847 goto skip_loopback;
1848 }
1849
1850 ixgbe_reset(adapter);
1851 e_info(hw, "loopback testing starting\n");
1852 if (ixgbe_loopback_test(adapter, &data[3]))
1853 eth_test->flags |= ETH_TEST_FL_FAILED;
1854
1855 skip_loopback:
1856 ixgbe_reset(adapter);
1857
1858 clear_bit(__IXGBE_TESTING, &adapter->state);
1859 if (if_running)
1860 dev_open(netdev);
1861 } else {
1862 e_info(hw, "online testing starting\n");
1863 /* Online tests */
1864 if (ixgbe_link_test(adapter, &data[4]))
1865 eth_test->flags |= ETH_TEST_FL_FAILED;
1866
1867 /* Online tests aren't run; pass by default */
1868 data[0] = 0;
1869 data[1] = 0;
1870 data[2] = 0;
1871 data[3] = 0;
1872
1873 clear_bit(__IXGBE_TESTING, &adapter->state);
1874 }
1875 skip_ol_tests:
1876 msleep_interruptible(4 * 1000);
1877 }
1878
1879 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1880 struct ethtool_wolinfo *wol)
1881 {
1882 struct ixgbe_hw *hw = &adapter->hw;
1883 int retval = 1;
1884 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
1885
1886 /* WOL not supported except for the following */
1887 switch(hw->device_id) {
1888 case IXGBE_DEV_ID_82599_SFP:
1889 /* Only this subdevice supports WOL */
1890 if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) {
1891 wol->supported = 0;
1892 break;
1893 }
1894 retval = 0;
1895 break;
1896 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1897 /* All except this subdevice support WOL */
1898 if (hw->subsystem_device_id ==
1899 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
1900 wol->supported = 0;
1901 break;
1902 }
1903 retval = 0;
1904 break;
1905 case IXGBE_DEV_ID_82599_KX4:
1906 retval = 0;
1907 break;
1908 case IXGBE_DEV_ID_X540T:
1909 /* check eeprom to see if enabled wol */
1910 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
1911 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
1912 (hw->bus.func == 0))) {
1913 retval = 0;
1914 break;
1915 }
1916
1917 /* All others not supported */
1918 wol->supported = 0;
1919 break;
1920 default:
1921 wol->supported = 0;
1922 }
1923
1924 return retval;
1925 }
1926
1927 static void ixgbe_get_wol(struct net_device *netdev,
1928 struct ethtool_wolinfo *wol)
1929 {
1930 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1931
1932 wol->supported = WAKE_UCAST | WAKE_MCAST |
1933 WAKE_BCAST | WAKE_MAGIC;
1934 wol->wolopts = 0;
1935
1936 if (ixgbe_wol_exclusion(adapter, wol) ||
1937 !device_can_wakeup(&adapter->pdev->dev))
1938 return;
1939
1940 if (adapter->wol & IXGBE_WUFC_EX)
1941 wol->wolopts |= WAKE_UCAST;
1942 if (adapter->wol & IXGBE_WUFC_MC)
1943 wol->wolopts |= WAKE_MCAST;
1944 if (adapter->wol & IXGBE_WUFC_BC)
1945 wol->wolopts |= WAKE_BCAST;
1946 if (adapter->wol & IXGBE_WUFC_MAG)
1947 wol->wolopts |= WAKE_MAGIC;
1948 }
1949
1950 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1951 {
1952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1953
1954 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1955 return -EOPNOTSUPP;
1956
1957 if (ixgbe_wol_exclusion(adapter, wol))
1958 return wol->wolopts ? -EOPNOTSUPP : 0;
1959
1960 adapter->wol = 0;
1961
1962 if (wol->wolopts & WAKE_UCAST)
1963 adapter->wol |= IXGBE_WUFC_EX;
1964 if (wol->wolopts & WAKE_MCAST)
1965 adapter->wol |= IXGBE_WUFC_MC;
1966 if (wol->wolopts & WAKE_BCAST)
1967 adapter->wol |= IXGBE_WUFC_BC;
1968 if (wol->wolopts & WAKE_MAGIC)
1969 adapter->wol |= IXGBE_WUFC_MAG;
1970
1971 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1972
1973 return 0;
1974 }
1975
1976 static int ixgbe_nway_reset(struct net_device *netdev)
1977 {
1978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1979
1980 if (netif_running(netdev))
1981 ixgbe_reinit_locked(adapter);
1982
1983 return 0;
1984 }
1985
1986 static int ixgbe_set_phys_id(struct net_device *netdev,
1987 enum ethtool_phys_id_state state)
1988 {
1989 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1990 struct ixgbe_hw *hw = &adapter->hw;
1991
1992 switch (state) {
1993 case ETHTOOL_ID_ACTIVE:
1994 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1995 return 2;
1996
1997 case ETHTOOL_ID_ON:
1998 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1999 break;
2000
2001 case ETHTOOL_ID_OFF:
2002 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2003 break;
2004
2005 case ETHTOOL_ID_INACTIVE:
2006 /* Restore LED settings */
2007 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2008 break;
2009 }
2010
2011 return 0;
2012 }
2013
2014 static int ixgbe_get_coalesce(struct net_device *netdev,
2015 struct ethtool_coalesce *ec)
2016 {
2017 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2018
2019 ec->tx_max_coalesced_frames_irq = adapter->tx_work_limit;
2020
2021 /* only valid if in constant ITR mode */
2022 if (adapter->rx_itr_setting <= 1)
2023 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2024 else
2025 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2026
2027 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2028 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2029 return 0;
2030
2031 /* only valid if in constant ITR mode */
2032 if (adapter->tx_itr_setting <= 1)
2033 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2034 else
2035 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2036
2037 return 0;
2038 }
2039
2040 /*
2041 * this function must be called before setting the new value of
2042 * rx_itr_setting
2043 */
2044 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
2045 struct ethtool_coalesce *ec)
2046 {
2047 struct net_device *netdev = adapter->netdev;
2048
2049 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2050 return false;
2051
2052 /* if interrupt rate is too high then disable RSC */
2053 if (ec->rx_coalesce_usecs != 1 &&
2054 ec->rx_coalesce_usecs <= (IXGBE_MIN_RSC_ITR >> 2)) {
2055 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2056 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2057 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2058 return true;
2059 }
2060 } else {
2061 /* check the feature flag value and enable RSC if necessary */
2062 if ((netdev->features & NETIF_F_LRO) &&
2063 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2064 e_info(probe, "rx-usecs set to %d, re-enabling RSC\n",
2065 ec->rx_coalesce_usecs);
2066 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2067 return true;
2068 }
2069 }
2070 return false;
2071 }
2072
2073 static int ixgbe_set_coalesce(struct net_device *netdev,
2074 struct ethtool_coalesce *ec)
2075 {
2076 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2077 struct ixgbe_q_vector *q_vector;
2078 int i;
2079 int num_vectors;
2080 u16 tx_itr_param, rx_itr_param;
2081 bool need_reset = false;
2082
2083 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2084 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count
2085 && ec->tx_coalesce_usecs)
2086 return -EINVAL;
2087
2088 if (ec->tx_max_coalesced_frames_irq)
2089 adapter->tx_work_limit = ec->tx_max_coalesced_frames_irq;
2090
2091 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2092 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2093 return -EINVAL;
2094
2095 /* check the old value and enable RSC if necessary */
2096 need_reset = ixgbe_update_rsc(adapter, ec);
2097
2098 if (ec->rx_coalesce_usecs > 1)
2099 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2100 else
2101 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2102
2103 if (adapter->rx_itr_setting == 1)
2104 rx_itr_param = IXGBE_20K_ITR;
2105 else
2106 rx_itr_param = adapter->rx_itr_setting;
2107
2108 if (ec->tx_coalesce_usecs > 1)
2109 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2110 else
2111 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2112
2113 if (adapter->tx_itr_setting == 1)
2114 tx_itr_param = IXGBE_10K_ITR;
2115 else
2116 tx_itr_param = adapter->tx_itr_setting;
2117
2118 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2119 num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2120 else
2121 num_vectors = 1;
2122
2123 for (i = 0; i < num_vectors; i++) {
2124 q_vector = adapter->q_vector[i];
2125 q_vector->tx.work_limit = adapter->tx_work_limit;
2126 if (q_vector->tx.count && !q_vector->rx.count)
2127 /* tx only */
2128 q_vector->itr = tx_itr_param;
2129 else
2130 /* rx only or mixed */
2131 q_vector->itr = rx_itr_param;
2132 ixgbe_write_eitr(q_vector);
2133 }
2134
2135 /*
2136 * do reset here at the end to make sure EITR==0 case is handled
2137 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2138 * also locks in RSC enable/disable which requires reset
2139 */
2140 if (need_reset)
2141 ixgbe_do_reset(netdev);
2142
2143 return 0;
2144 }
2145
2146 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2147 struct ethtool_rxnfc *cmd)
2148 {
2149 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2150 struct ethtool_rx_flow_spec *fsp =
2151 (struct ethtool_rx_flow_spec *)&cmd->fs;
2152 struct hlist_node *node, *node2;
2153 struct ixgbe_fdir_filter *rule = NULL;
2154
2155 /* report total rule count */
2156 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2157
2158 hlist_for_each_entry_safe(rule, node, node2,
2159 &adapter->fdir_filter_list, fdir_node) {
2160 if (fsp->location <= rule->sw_idx)
2161 break;
2162 }
2163
2164 if (!rule || fsp->location != rule->sw_idx)
2165 return -EINVAL;
2166
2167 /* fill out the flow spec entry */
2168
2169 /* set flow type field */
2170 switch (rule->filter.formatted.flow_type) {
2171 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2172 fsp->flow_type = TCP_V4_FLOW;
2173 break;
2174 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2175 fsp->flow_type = UDP_V4_FLOW;
2176 break;
2177 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2178 fsp->flow_type = SCTP_V4_FLOW;
2179 break;
2180 case IXGBE_ATR_FLOW_TYPE_IPV4:
2181 fsp->flow_type = IP_USER_FLOW;
2182 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2183 fsp->h_u.usr_ip4_spec.proto = 0;
2184 fsp->m_u.usr_ip4_spec.proto = 0;
2185 break;
2186 default:
2187 return -EINVAL;
2188 }
2189
2190 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2191 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2192 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2193 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2194 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2195 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2196 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2197 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2198 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2199 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2200 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2201 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2202 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2203 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2204 fsp->flow_type |= FLOW_EXT;
2205
2206 /* record action */
2207 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2208 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2209 else
2210 fsp->ring_cookie = rule->action;
2211
2212 return 0;
2213 }
2214
2215 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2216 struct ethtool_rxnfc *cmd,
2217 u32 *rule_locs)
2218 {
2219 struct hlist_node *node, *node2;
2220 struct ixgbe_fdir_filter *rule;
2221 int cnt = 0;
2222
2223 /* report total rule count */
2224 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2225
2226 hlist_for_each_entry_safe(rule, node, node2,
2227 &adapter->fdir_filter_list, fdir_node) {
2228 if (cnt == cmd->rule_cnt)
2229 return -EMSGSIZE;
2230 rule_locs[cnt] = rule->sw_idx;
2231 cnt++;
2232 }
2233
2234 cmd->rule_cnt = cnt;
2235
2236 return 0;
2237 }
2238
2239 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2240 u32 *rule_locs)
2241 {
2242 struct ixgbe_adapter *adapter = netdev_priv(dev);
2243 int ret = -EOPNOTSUPP;
2244
2245 switch (cmd->cmd) {
2246 case ETHTOOL_GRXRINGS:
2247 cmd->data = adapter->num_rx_queues;
2248 ret = 0;
2249 break;
2250 case ETHTOOL_GRXCLSRLCNT:
2251 cmd->rule_cnt = adapter->fdir_filter_count;
2252 ret = 0;
2253 break;
2254 case ETHTOOL_GRXCLSRULE:
2255 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2256 break;
2257 case ETHTOOL_GRXCLSRLALL:
2258 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2259 break;
2260 default:
2261 break;
2262 }
2263
2264 return ret;
2265 }
2266
2267 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2268 struct ixgbe_fdir_filter *input,
2269 u16 sw_idx)
2270 {
2271 struct ixgbe_hw *hw = &adapter->hw;
2272 struct hlist_node *node, *node2, *parent;
2273 struct ixgbe_fdir_filter *rule;
2274 int err = -EINVAL;
2275
2276 parent = NULL;
2277 rule = NULL;
2278
2279 hlist_for_each_entry_safe(rule, node, node2,
2280 &adapter->fdir_filter_list, fdir_node) {
2281 /* hash found, or no matching entry */
2282 if (rule->sw_idx >= sw_idx)
2283 break;
2284 parent = node;
2285 }
2286
2287 /* if there is an old rule occupying our place remove it */
2288 if (rule && (rule->sw_idx == sw_idx)) {
2289 if (!input || (rule->filter.formatted.bkt_hash !=
2290 input->filter.formatted.bkt_hash)) {
2291 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2292 &rule->filter,
2293 sw_idx);
2294 }
2295
2296 hlist_del(&rule->fdir_node);
2297 kfree(rule);
2298 adapter->fdir_filter_count--;
2299 }
2300
2301 /*
2302 * If no input this was a delete, err should be 0 if a rule was
2303 * successfully found and removed from the list else -EINVAL
2304 */
2305 if (!input)
2306 return err;
2307
2308 /* initialize node and set software index */
2309 INIT_HLIST_NODE(&input->fdir_node);
2310
2311 /* add filter to the list */
2312 if (parent)
2313 hlist_add_after(parent, &input->fdir_node);
2314 else
2315 hlist_add_head(&input->fdir_node,
2316 &adapter->fdir_filter_list);
2317
2318 /* update counts */
2319 adapter->fdir_filter_count++;
2320
2321 return 0;
2322 }
2323
2324 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2325 u8 *flow_type)
2326 {
2327 switch (fsp->flow_type & ~FLOW_EXT) {
2328 case TCP_V4_FLOW:
2329 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2330 break;
2331 case UDP_V4_FLOW:
2332 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2333 break;
2334 case SCTP_V4_FLOW:
2335 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2336 break;
2337 case IP_USER_FLOW:
2338 switch (fsp->h_u.usr_ip4_spec.proto) {
2339 case IPPROTO_TCP:
2340 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2341 break;
2342 case IPPROTO_UDP:
2343 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2344 break;
2345 case IPPROTO_SCTP:
2346 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2347 break;
2348 case 0:
2349 if (!fsp->m_u.usr_ip4_spec.proto) {
2350 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2351 break;
2352 }
2353 default:
2354 return 0;
2355 }
2356 break;
2357 default:
2358 return 0;
2359 }
2360
2361 return 1;
2362 }
2363
2364 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2365 struct ethtool_rxnfc *cmd)
2366 {
2367 struct ethtool_rx_flow_spec *fsp =
2368 (struct ethtool_rx_flow_spec *)&cmd->fs;
2369 struct ixgbe_hw *hw = &adapter->hw;
2370 struct ixgbe_fdir_filter *input;
2371 union ixgbe_atr_input mask;
2372 int err;
2373
2374 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2375 return -EOPNOTSUPP;
2376
2377 /*
2378 * Don't allow programming if the action is a queue greater than
2379 * the number of online Rx queues.
2380 */
2381 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2382 (fsp->ring_cookie >= adapter->num_rx_queues))
2383 return -EINVAL;
2384
2385 /* Don't allow indexes to exist outside of available space */
2386 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2387 e_err(drv, "Location out of range\n");
2388 return -EINVAL;
2389 }
2390
2391 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2392 if (!input)
2393 return -ENOMEM;
2394
2395 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2396
2397 /* set SW index */
2398 input->sw_idx = fsp->location;
2399
2400 /* record flow type */
2401 if (!ixgbe_flowspec_to_flow_type(fsp,
2402 &input->filter.formatted.flow_type)) {
2403 e_err(drv, "Unrecognized flow type\n");
2404 goto err_out;
2405 }
2406
2407 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2408 IXGBE_ATR_L4TYPE_MASK;
2409
2410 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2411 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2412
2413 /* Copy input into formatted structures */
2414 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2415 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2416 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2417 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2418 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2419 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2420 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2421 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2422
2423 if (fsp->flow_type & FLOW_EXT) {
2424 input->filter.formatted.vm_pool =
2425 (unsigned char)ntohl(fsp->h_ext.data[1]);
2426 mask.formatted.vm_pool =
2427 (unsigned char)ntohl(fsp->m_ext.data[1]);
2428 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2429 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2430 input->filter.formatted.flex_bytes =
2431 fsp->h_ext.vlan_etype;
2432 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2433 }
2434
2435 /* determine if we need to drop or route the packet */
2436 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2437 input->action = IXGBE_FDIR_DROP_QUEUE;
2438 else
2439 input->action = fsp->ring_cookie;
2440
2441 spin_lock(&adapter->fdir_perfect_lock);
2442
2443 if (hlist_empty(&adapter->fdir_filter_list)) {
2444 /* save mask and program input mask into HW */
2445 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2446 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2447 if (err) {
2448 e_err(drv, "Error writing mask\n");
2449 goto err_out_w_lock;
2450 }
2451 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2452 e_err(drv, "Only one mask supported per port\n");
2453 goto err_out_w_lock;
2454 }
2455
2456 /* apply mask and compute/store hash */
2457 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2458
2459 /* program filters to filter memory */
2460 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2461 &input->filter, input->sw_idx,
2462 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2463 IXGBE_FDIR_DROP_QUEUE :
2464 adapter->rx_ring[input->action]->reg_idx);
2465 if (err)
2466 goto err_out_w_lock;
2467
2468 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2469
2470 spin_unlock(&adapter->fdir_perfect_lock);
2471
2472 return err;
2473 err_out_w_lock:
2474 spin_unlock(&adapter->fdir_perfect_lock);
2475 err_out:
2476 kfree(input);
2477 return -EINVAL;
2478 }
2479
2480 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2481 struct ethtool_rxnfc *cmd)
2482 {
2483 struct ethtool_rx_flow_spec *fsp =
2484 (struct ethtool_rx_flow_spec *)&cmd->fs;
2485 int err;
2486
2487 spin_lock(&adapter->fdir_perfect_lock);
2488 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2489 spin_unlock(&adapter->fdir_perfect_lock);
2490
2491 return err;
2492 }
2493
2494 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2495 {
2496 struct ixgbe_adapter *adapter = netdev_priv(dev);
2497 int ret = -EOPNOTSUPP;
2498
2499 switch (cmd->cmd) {
2500 case ETHTOOL_SRXCLSRLINS:
2501 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2502 break;
2503 case ETHTOOL_SRXCLSRLDEL:
2504 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2505 break;
2506 default:
2507 break;
2508 }
2509
2510 return ret;
2511 }
2512
2513 static const struct ethtool_ops ixgbe_ethtool_ops = {
2514 .get_settings = ixgbe_get_settings,
2515 .set_settings = ixgbe_set_settings,
2516 .get_drvinfo = ixgbe_get_drvinfo,
2517 .get_regs_len = ixgbe_get_regs_len,
2518 .get_regs = ixgbe_get_regs,
2519 .get_wol = ixgbe_get_wol,
2520 .set_wol = ixgbe_set_wol,
2521 .nway_reset = ixgbe_nway_reset,
2522 .get_link = ethtool_op_get_link,
2523 .get_eeprom_len = ixgbe_get_eeprom_len,
2524 .get_eeprom = ixgbe_get_eeprom,
2525 .get_ringparam = ixgbe_get_ringparam,
2526 .set_ringparam = ixgbe_set_ringparam,
2527 .get_pauseparam = ixgbe_get_pauseparam,
2528 .set_pauseparam = ixgbe_set_pauseparam,
2529 .get_msglevel = ixgbe_get_msglevel,
2530 .set_msglevel = ixgbe_set_msglevel,
2531 .self_test = ixgbe_diag_test,
2532 .get_strings = ixgbe_get_strings,
2533 .set_phys_id = ixgbe_set_phys_id,
2534 .get_sset_count = ixgbe_get_sset_count,
2535 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2536 .get_coalesce = ixgbe_get_coalesce,
2537 .set_coalesce = ixgbe_set_coalesce,
2538 .get_rxnfc = ixgbe_get_rxnfc,
2539 .set_rxnfc = ixgbe_set_rxnfc,
2540 };
2541
2542 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2543 {
2544 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2545 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree