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net: Remove unnecessary driver assignments of ethtool_ringparam fields to zero
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / broadcom / bnx2.c
blob3c221be9d1e28526fc3d7f8ca4f7474f252df535
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33 #include <linux/delay.h>
34 #include <asm/byteorder.h>
35 #include <asm/page.h>
36 #include <linux/time.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
39 #include <linux/if.h>
40 #include <linux/if_vlan.h>
41 #include <net/ip.h>
42 #include <net/tcp.h>
43 #include <net/checksum.h>
44 #include <linux/workqueue.h>
45 #include <linux/crc32.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/firmware.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51
52 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
53 #define BCM_CNIC 1
54 #include "cnic_if.h"
55 #endif
56 #include "bnx2.h"
57 #include "bnx2_fw.h"
58
59 #define DRV_MODULE_NAME "bnx2"
60 #define DRV_MODULE_VERSION "2.1.11"
61 #define DRV_MODULE_RELDATE "July 20, 2011"
62 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.1.fw"
63 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
64 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1a.fw"
65 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
66 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
67
68 #define RUN_AT(x) (jiffies + (x))
69
70 /* Time in jiffies before concluding the transmitter is hung. */
71 #define TX_TIMEOUT (5*HZ)
72
73 static char version[] __devinitdata =
74 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
75
76 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
77 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
78 MODULE_LICENSE("GPL");
79 MODULE_VERSION(DRV_MODULE_VERSION);
80 MODULE_FIRMWARE(FW_MIPS_FILE_06);
81 MODULE_FIRMWARE(FW_RV2P_FILE_06);
82 MODULE_FIRMWARE(FW_MIPS_FILE_09);
83 MODULE_FIRMWARE(FW_RV2P_FILE_09);
84 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
85
86 static int disable_msi = 0;
87
88 module_param(disable_msi, int, 0);
89 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
90
91 typedef enum {
92 BCM5706 = 0,
93 NC370T,
94 NC370I,
95 BCM5706S,
96 NC370F,
97 BCM5708,
98 BCM5708S,
99 BCM5709,
100 BCM5709S,
101 BCM5716,
102 BCM5716S,
103 } board_t;
104
105 /* indexed by board_t, above */
106 static struct {
107 char *name;
108 } board_info[] __devinitdata = {
109 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
110 { "HP NC370T Multifunction Gigabit Server Adapter" },
111 { "HP NC370i Multifunction Gigabit Server Adapter" },
112 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
113 { "HP NC370F Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
116 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
118 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
119 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
120 };
121
122 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
124 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
132 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
141 { PCI_VENDOR_ID_BROADCOM, 0x163b,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
143 { PCI_VENDOR_ID_BROADCOM, 0x163c,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
145 { 0, }
146 };
147
148 static const struct flash_spec flash_table[] =
149 {
150 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
151 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
152 /* Slow EEPROM */
153 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
154 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
155 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
156 "EEPROM - slow"},
157 /* Expansion entry 0001 */
158 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
159 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
160 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
161 "Entry 0001"},
162 /* Saifun SA25F010 (non-buffered flash) */
163 /* strap, cfg1, & write1 need updates */
164 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
165 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
166 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
167 "Non-buffered flash (128kB)"},
168 /* Saifun SA25F020 (non-buffered flash) */
169 /* strap, cfg1, & write1 need updates */
170 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
172 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
173 "Non-buffered flash (256kB)"},
174 /* Expansion entry 0100 */
175 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
178 "Entry 0100"},
179 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
180 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
181 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
182 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
183 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
184 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
185 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
186 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
187 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
188 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
189 /* Saifun SA25F005 (non-buffered flash) */
190 /* strap, cfg1, & write1 need updates */
191 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
194 "Non-buffered flash (64kB)"},
195 /* Fast EEPROM */
196 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
197 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
198 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
199 "EEPROM - fast"},
200 /* Expansion entry 1001 */
201 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204 "Entry 1001"},
205 /* Expansion entry 1010 */
206 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
208 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
209 "Entry 1010"},
210 /* ATMEL AT45DB011B (buffered flash) */
211 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
212 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
213 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
214 "Buffered flash (128kB)"},
215 /* Expansion entry 1100 */
216 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
217 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1100"},
220 /* Expansion entry 1101 */
221 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
224 "Entry 1101"},
225 /* Ateml Expansion entry 1110 */
226 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
227 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
228 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
229 "Entry 1110 (Atmel)"},
230 /* ATMEL AT45DB021B (buffered flash) */
231 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
232 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
233 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
234 "Buffered flash (256kB)"},
235 };
236
237 static const struct flash_spec flash_5709 = {
238 .flags = BNX2_NV_BUFFERED,
239 .page_bits = BCM5709_FLASH_PAGE_BITS,
240 .page_size = BCM5709_FLASH_PAGE_SIZE,
241 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
242 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
243 .name = "5709 Buffered flash (256kB)",
244 };
245
246 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
247
248 static void bnx2_init_napi(struct bnx2 *bp);
249 static void bnx2_del_napi(struct bnx2 *bp);
250
251 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
252 {
253 u32 diff;
254
255 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
256 barrier();
257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
261 diff = txr->tx_prod - txr->tx_cons;
262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
267 return bp->tx_ring_size - diff;
268 }
269
270 static u32
271 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272 {
273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
280 }
281
282 static void
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284 {
285 spin_lock_bh(&bp->indirect_lock);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
288 spin_unlock_bh(&bp->indirect_lock);
289 }
290
291 static void
292 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293 {
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295 }
296
297 static u32
298 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299 {
300 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
301 }
302
303 static void
304 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305 {
306 offset += cid_addr;
307 spin_lock_bh(&bp->indirect_lock);
308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
324 spin_unlock_bh(&bp->indirect_lock);
325 }
326
327 #ifdef BCM_CNIC
328 static int
329 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330 {
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348 }
349
350 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351 {
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375 }
376
377 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379 {
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
389 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
390 return -ENODEV;
391
392 bp->cnic_data = data;
393 rcu_assign_pointer(bp->cnic_ops, ops);
394
395 cp->num_irq = 0;
396 cp->drv_state = CNIC_DRV_STATE_REGD;
397
398 bnx2_setup_cnic_irq_info(bp);
399
400 return 0;
401 }
402
403 static int bnx2_unregister_cnic(struct net_device *dev)
404 {
405 struct bnx2 *bp = netdev_priv(dev);
406 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
407 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
408
409 mutex_lock(&bp->cnic_lock);
410 cp->drv_state = 0;
411 bnapi->cnic_present = 0;
412 rcu_assign_pointer(bp->cnic_ops, NULL);
413 mutex_unlock(&bp->cnic_lock);
414 synchronize_rcu();
415 return 0;
416 }
417
418 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
419 {
420 struct bnx2 *bp = netdev_priv(dev);
421 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
422
423 if (!cp->max_iscsi_conn)
424 return NULL;
425
426 cp->drv_owner = THIS_MODULE;
427 cp->chip_id = bp->chip_id;
428 cp->pdev = bp->pdev;
429 cp->io_base = bp->regview;
430 cp->drv_ctl = bnx2_drv_ctl;
431 cp->drv_register_cnic = bnx2_register_cnic;
432 cp->drv_unregister_cnic = bnx2_unregister_cnic;
433
434 return cp;
435 }
436 EXPORT_SYMBOL(bnx2_cnic_probe);
437
438 static void
439 bnx2_cnic_stop(struct bnx2 *bp)
440 {
441 struct cnic_ops *c_ops;
442 struct cnic_ctl_info info;
443
444 mutex_lock(&bp->cnic_lock);
445 c_ops = rcu_dereference_protected(bp->cnic_ops,
446 lockdep_is_held(&bp->cnic_lock));
447 if (c_ops) {
448 info.cmd = CNIC_CTL_STOP_CMD;
449 c_ops->cnic_ctl(bp->cnic_data, &info);
450 }
451 mutex_unlock(&bp->cnic_lock);
452 }
453
454 static void
455 bnx2_cnic_start(struct bnx2 *bp)
456 {
457 struct cnic_ops *c_ops;
458 struct cnic_ctl_info info;
459
460 mutex_lock(&bp->cnic_lock);
461 c_ops = rcu_dereference_protected(bp->cnic_ops,
462 lockdep_is_held(&bp->cnic_lock));
463 if (c_ops) {
464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
466
467 bnapi->cnic_tag = bnapi->last_status_idx;
468 }
469 info.cmd = CNIC_CTL_START_CMD;
470 c_ops->cnic_ctl(bp->cnic_data, &info);
471 }
472 mutex_unlock(&bp->cnic_lock);
473 }
474
475 #else
476
477 static void
478 bnx2_cnic_stop(struct bnx2 *bp)
479 {
480 }
481
482 static void
483 bnx2_cnic_start(struct bnx2 *bp)
484 {
485 }
486
487 #endif
488
489 static int
490 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
491 {
492 u32 val1;
493 int i, ret;
494
495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
496 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
498
499 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
500 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
501
502 udelay(40);
503 }
504
505 val1 = (bp->phy_addr << 21) | (reg << 16) |
506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
507 BNX2_EMAC_MDIO_COMM_START_BUSY;
508 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
509
510 for (i = 0; i < 50; i++) {
511 udelay(10);
512
513 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
515 udelay(5);
516
517 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
518 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
519
520 break;
521 }
522 }
523
524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
525 *val = 0x0;
526 ret = -EBUSY;
527 }
528 else {
529 *val = val1;
530 ret = 0;
531 }
532
533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
534 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
536
537 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
538 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
539
540 udelay(40);
541 }
542
543 return ret;
544 }
545
546 static int
547 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
548 {
549 u32 val1;
550 int i, ret;
551
552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
553 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
555
556 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
557 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
558
559 udelay(40);
560 }
561
562 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
565 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
566
567 for (i = 0; i < 50; i++) {
568 udelay(10);
569
570 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
572 udelay(5);
573 break;
574 }
575 }
576
577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
578 ret = -EBUSY;
579 else
580 ret = 0;
581
582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
583 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
585
586 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
587 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
588
589 udelay(40);
590 }
591
592 return ret;
593 }
594
595 static void
596 bnx2_disable_int(struct bnx2 *bp)
597 {
598 int i;
599 struct bnx2_napi *bnapi;
600
601 for (i = 0; i < bp->irq_nvecs; i++) {
602 bnapi = &bp->bnx2_napi[i];
603 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
605 }
606 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
607 }
608
609 static void
610 bnx2_enable_int(struct bnx2 *bp)
611 {
612 int i;
613 struct bnx2_napi *bnapi;
614
615 for (i = 0; i < bp->irq_nvecs; i++) {
616 bnapi = &bp->bnx2_napi[i];
617
618 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
621 bnapi->last_status_idx);
622
623 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
625 bnapi->last_status_idx);
626 }
627 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
628 }
629
630 static void
631 bnx2_disable_int_sync(struct bnx2 *bp)
632 {
633 int i;
634
635 atomic_inc(&bp->intr_sem);
636 if (!netif_running(bp->dev))
637 return;
638
639 bnx2_disable_int(bp);
640 for (i = 0; i < bp->irq_nvecs; i++)
641 synchronize_irq(bp->irq_tbl[i].vector);
642 }
643
644 static void
645 bnx2_napi_disable(struct bnx2 *bp)
646 {
647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_disable(&bp->bnx2_napi[i].napi);
651 }
652
653 static void
654 bnx2_napi_enable(struct bnx2 *bp)
655 {
656 int i;
657
658 for (i = 0; i < bp->irq_nvecs; i++)
659 napi_enable(&bp->bnx2_napi[i].napi);
660 }
661
662 static void
663 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
664 {
665 if (stop_cnic)
666 bnx2_cnic_stop(bp);
667 if (netif_running(bp->dev)) {
668 bnx2_napi_disable(bp);
669 netif_tx_disable(bp->dev);
670 }
671 bnx2_disable_int_sync(bp);
672 netif_carrier_off(bp->dev); /* prevent tx timeout */
673 }
674
675 static void
676 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
677 {
678 if (atomic_dec_and_test(&bp->intr_sem)) {
679 if (netif_running(bp->dev)) {
680 netif_tx_wake_all_queues(bp->dev);
681 spin_lock_bh(&bp->phy_lock);
682 if (bp->link_up)
683 netif_carrier_on(bp->dev);
684 spin_unlock_bh(&bp->phy_lock);
685 bnx2_napi_enable(bp);
686 bnx2_enable_int(bp);
687 if (start_cnic)
688 bnx2_cnic_start(bp);
689 }
690 }
691 }
692
693 static void
694 bnx2_free_tx_mem(struct bnx2 *bp)
695 {
696 int i;
697
698 for (i = 0; i < bp->num_tx_rings; i++) {
699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
701
702 if (txr->tx_desc_ring) {
703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
704 txr->tx_desc_ring,
705 txr->tx_desc_mapping);
706 txr->tx_desc_ring = NULL;
707 }
708 kfree(txr->tx_buf_ring);
709 txr->tx_buf_ring = NULL;
710 }
711 }
712
713 static void
714 bnx2_free_rx_mem(struct bnx2 *bp)
715 {
716 int i;
717
718 for (i = 0; i < bp->num_rx_rings; i++) {
719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
721 int j;
722
723 for (j = 0; j < bp->rx_max_ring; j++) {
724 if (rxr->rx_desc_ring[j])
725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
726 rxr->rx_desc_ring[j],
727 rxr->rx_desc_mapping[j]);
728 rxr->rx_desc_ring[j] = NULL;
729 }
730 vfree(rxr->rx_buf_ring);
731 rxr->rx_buf_ring = NULL;
732
733 for (j = 0; j < bp->rx_max_pg_ring; j++) {
734 if (rxr->rx_pg_desc_ring[j])
735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
736 rxr->rx_pg_desc_ring[j],
737 rxr->rx_pg_desc_mapping[j]);
738 rxr->rx_pg_desc_ring[j] = NULL;
739 }
740 vfree(rxr->rx_pg_ring);
741 rxr->rx_pg_ring = NULL;
742 }
743 }
744
745 static int
746 bnx2_alloc_tx_mem(struct bnx2 *bp)
747 {
748 int i;
749
750 for (i = 0; i < bp->num_tx_rings; i++) {
751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
753
754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
755 if (txr->tx_buf_ring == NULL)
756 return -ENOMEM;
757
758 txr->tx_desc_ring =
759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
760 &txr->tx_desc_mapping, GFP_KERNEL);
761 if (txr->tx_desc_ring == NULL)
762 return -ENOMEM;
763 }
764 return 0;
765 }
766
767 static int
768 bnx2_alloc_rx_mem(struct bnx2 *bp)
769 {
770 int i;
771
772 for (i = 0; i < bp->num_rx_rings; i++) {
773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
775 int j;
776
777 rxr->rx_buf_ring =
778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
779 if (rxr->rx_buf_ring == NULL)
780 return -ENOMEM;
781
782 for (j = 0; j < bp->rx_max_ring; j++) {
783 rxr->rx_desc_ring[j] =
784 dma_alloc_coherent(&bp->pdev->dev,
785 RXBD_RING_SIZE,
786 &rxr->rx_desc_mapping[j],
787 GFP_KERNEL);
788 if (rxr->rx_desc_ring[j] == NULL)
789 return -ENOMEM;
790
791 }
792
793 if (bp->rx_pg_ring_size) {
794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
795 bp->rx_max_pg_ring);
796 if (rxr->rx_pg_ring == NULL)
797 return -ENOMEM;
798
799 }
800
801 for (j = 0; j < bp->rx_max_pg_ring; j++) {
802 rxr->rx_pg_desc_ring[j] =
803 dma_alloc_coherent(&bp->pdev->dev,
804 RXBD_RING_SIZE,
805 &rxr->rx_pg_desc_mapping[j],
806 GFP_KERNEL);
807 if (rxr->rx_pg_desc_ring[j] == NULL)
808 return -ENOMEM;
809
810 }
811 }
812 return 0;
813 }
814
815 static void
816 bnx2_free_mem(struct bnx2 *bp)
817 {
818 int i;
819 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
820
821 bnx2_free_tx_mem(bp);
822 bnx2_free_rx_mem(bp);
823
824 for (i = 0; i < bp->ctx_pages; i++) {
825 if (bp->ctx_blk[i]) {
826 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
827 bp->ctx_blk[i],
828 bp->ctx_blk_mapping[i]);
829 bp->ctx_blk[i] = NULL;
830 }
831 }
832 if (bnapi->status_blk.msi) {
833 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
834 bnapi->status_blk.msi,
835 bp->status_blk_mapping);
836 bnapi->status_blk.msi = NULL;
837 bp->stats_blk = NULL;
838 }
839 }
840
841 static int
842 bnx2_alloc_mem(struct bnx2 *bp)
843 {
844 int i, status_blk_size, err;
845 struct bnx2_napi *bnapi;
846 void *status_blk;
847
848 /* Combine status and statistics blocks into one allocation. */
849 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
850 if (bp->flags & BNX2_FLAG_MSIX_CAP)
851 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
852 BNX2_SBLK_MSIX_ALIGN_SIZE);
853 bp->status_stats_size = status_blk_size +
854 sizeof(struct statistics_block);
855
856 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
857 &bp->status_blk_mapping, GFP_KERNEL);
858 if (status_blk == NULL)
859 goto alloc_mem_err;
860
861 memset(status_blk, 0, bp->status_stats_size);
862
863 bnapi = &bp->bnx2_napi[0];
864 bnapi->status_blk.msi = status_blk;
865 bnapi->hw_tx_cons_ptr =
866 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
867 bnapi->hw_rx_cons_ptr =
868 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
869 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
870 for (i = 1; i < bp->irq_nvecs; i++) {
871 struct status_block_msix *sblk;
872
873 bnapi = &bp->bnx2_napi[i];
874
875 sblk = (void *) (status_blk +
876 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
877 bnapi->status_blk.msix = sblk;
878 bnapi->hw_tx_cons_ptr =
879 &sblk->status_tx_quick_consumer_index;
880 bnapi->hw_rx_cons_ptr =
881 &sblk->status_rx_quick_consumer_index;
882 bnapi->int_num = i << 24;
883 }
884 }
885
886 bp->stats_blk = status_blk + status_blk_size;
887
888 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
889
890 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
891 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
892 if (bp->ctx_pages == 0)
893 bp->ctx_pages = 1;
894 for (i = 0; i < bp->ctx_pages; i++) {
895 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
896 BCM_PAGE_SIZE,
897 &bp->ctx_blk_mapping[i],
898 GFP_KERNEL);
899 if (bp->ctx_blk[i] == NULL)
900 goto alloc_mem_err;
901 }
902 }
903
904 err = bnx2_alloc_rx_mem(bp);
905 if (err)
906 goto alloc_mem_err;
907
908 err = bnx2_alloc_tx_mem(bp);
909 if (err)
910 goto alloc_mem_err;
911
912 return 0;
913
914 alloc_mem_err:
915 bnx2_free_mem(bp);
916 return -ENOMEM;
917 }
918
919 static void
920 bnx2_report_fw_link(struct bnx2 *bp)
921 {
922 u32 fw_link_status = 0;
923
924 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
925 return;
926
927 if (bp->link_up) {
928 u32 bmsr;
929
930 switch (bp->line_speed) {
931 case SPEED_10:
932 if (bp->duplex == DUPLEX_HALF)
933 fw_link_status = BNX2_LINK_STATUS_10HALF;
934 else
935 fw_link_status = BNX2_LINK_STATUS_10FULL;
936 break;
937 case SPEED_100:
938 if (bp->duplex == DUPLEX_HALF)
939 fw_link_status = BNX2_LINK_STATUS_100HALF;
940 else
941 fw_link_status = BNX2_LINK_STATUS_100FULL;
942 break;
943 case SPEED_1000:
944 if (bp->duplex == DUPLEX_HALF)
945 fw_link_status = BNX2_LINK_STATUS_1000HALF;
946 else
947 fw_link_status = BNX2_LINK_STATUS_1000FULL;
948 break;
949 case SPEED_2500:
950 if (bp->duplex == DUPLEX_HALF)
951 fw_link_status = BNX2_LINK_STATUS_2500HALF;
952 else
953 fw_link_status = BNX2_LINK_STATUS_2500FULL;
954 break;
955 }
956
957 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
958
959 if (bp->autoneg) {
960 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
961
962 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
963 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
964
965 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
966 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
967 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
968 else
969 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
970 }
971 }
972 else
973 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
974
975 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
976 }
977
978 static char *
979 bnx2_xceiver_str(struct bnx2 *bp)
980 {
981 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
982 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
983 "Copper");
984 }
985
986 static void
987 bnx2_report_link(struct bnx2 *bp)
988 {
989 if (bp->link_up) {
990 netif_carrier_on(bp->dev);
991 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
992 bnx2_xceiver_str(bp),
993 bp->line_speed,
994 bp->duplex == DUPLEX_FULL ? "full" : "half");
995
996 if (bp->flow_ctrl) {
997 if (bp->flow_ctrl & FLOW_CTRL_RX) {
998 pr_cont(", receive ");
999 if (bp->flow_ctrl & FLOW_CTRL_TX)
1000 pr_cont("& transmit ");
1001 }
1002 else {
1003 pr_cont(", transmit ");
1004 }
1005 pr_cont("flow control ON");
1006 }
1007 pr_cont("\n");
1008 } else {
1009 netif_carrier_off(bp->dev);
1010 netdev_err(bp->dev, "NIC %s Link is Down\n",
1011 bnx2_xceiver_str(bp));
1012 }
1013
1014 bnx2_report_fw_link(bp);
1015 }
1016
1017 static void
1018 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1019 {
1020 u32 local_adv, remote_adv;
1021
1022 bp->flow_ctrl = 0;
1023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1025
1026 if (bp->duplex == DUPLEX_FULL) {
1027 bp->flow_ctrl = bp->req_flow_ctrl;
1028 }
1029 return;
1030 }
1031
1032 if (bp->duplex != DUPLEX_FULL) {
1033 return;
1034 }
1035
1036 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1037 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1038 u32 val;
1039
1040 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1041 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_TX;
1043 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1044 bp->flow_ctrl |= FLOW_CTRL_RX;
1045 return;
1046 }
1047
1048 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1049 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1050
1051 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1052 u32 new_local_adv = 0;
1053 u32 new_remote_adv = 0;
1054
1055 if (local_adv & ADVERTISE_1000XPAUSE)
1056 new_local_adv |= ADVERTISE_PAUSE_CAP;
1057 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1058 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1059 if (remote_adv & ADVERTISE_1000XPAUSE)
1060 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1061 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1062 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1063
1064 local_adv = new_local_adv;
1065 remote_adv = new_remote_adv;
1066 }
1067
1068 /* See Table 28B-3 of 802.3ab-1999 spec. */
1069 if (local_adv & ADVERTISE_PAUSE_CAP) {
1070 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1075 bp->flow_ctrl = FLOW_CTRL_RX;
1076 }
1077 }
1078 else {
1079 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1080 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1081 }
1082 }
1083 }
1084 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1085 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1086 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1087
1088 bp->flow_ctrl = FLOW_CTRL_TX;
1089 }
1090 }
1091 }
1092
1093 static int
1094 bnx2_5709s_linkup(struct bnx2 *bp)
1095 {
1096 u32 val, speed;
1097
1098 bp->link_up = 1;
1099
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1101 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1103
1104 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1105 bp->line_speed = bp->req_line_speed;
1106 bp->duplex = bp->req_duplex;
1107 return 0;
1108 }
1109 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1110 switch (speed) {
1111 case MII_BNX2_GP_TOP_AN_SPEED_10:
1112 bp->line_speed = SPEED_10;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_100:
1115 bp->line_speed = SPEED_100;
1116 break;
1117 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1118 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1119 bp->line_speed = SPEED_1000;
1120 break;
1121 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1122 bp->line_speed = SPEED_2500;
1123 break;
1124 }
1125 if (val & MII_BNX2_GP_TOP_AN_FD)
1126 bp->duplex = DUPLEX_FULL;
1127 else
1128 bp->duplex = DUPLEX_HALF;
1129 return 0;
1130 }
1131
1132 static int
1133 bnx2_5708s_linkup(struct bnx2 *bp)
1134 {
1135 u32 val;
1136
1137 bp->link_up = 1;
1138 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1139 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1140 case BCM5708S_1000X_STAT1_SPEED_10:
1141 bp->line_speed = SPEED_10;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_100:
1144 bp->line_speed = SPEED_100;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_1G:
1147 bp->line_speed = SPEED_1000;
1148 break;
1149 case BCM5708S_1000X_STAT1_SPEED_2G5:
1150 bp->line_speed = SPEED_2500;
1151 break;
1152 }
1153 if (val & BCM5708S_1000X_STAT1_FD)
1154 bp->duplex = DUPLEX_FULL;
1155 else
1156 bp->duplex = DUPLEX_HALF;
1157
1158 return 0;
1159 }
1160
1161 static int
1162 bnx2_5706s_linkup(struct bnx2 *bp)
1163 {
1164 u32 bmcr, local_adv, remote_adv, common;
1165
1166 bp->link_up = 1;
1167 bp->line_speed = SPEED_1000;
1168
1169 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1170 if (bmcr & BMCR_FULLDPLX) {
1171 bp->duplex = DUPLEX_FULL;
1172 }
1173 else {
1174 bp->duplex = DUPLEX_HALF;
1175 }
1176
1177 if (!(bmcr & BMCR_ANENABLE)) {
1178 return 0;
1179 }
1180
1181 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1182 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1183
1184 common = local_adv & remote_adv;
1185 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1186
1187 if (common & ADVERTISE_1000XFULL) {
1188 bp->duplex = DUPLEX_FULL;
1189 }
1190 else {
1191 bp->duplex = DUPLEX_HALF;
1192 }
1193 }
1194
1195 return 0;
1196 }
1197
1198 static int
1199 bnx2_copper_linkup(struct bnx2 *bp)
1200 {
1201 u32 bmcr;
1202
1203 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1204 if (bmcr & BMCR_ANENABLE) {
1205 u32 local_adv, remote_adv, common;
1206
1207 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1208 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1209
1210 common = local_adv & (remote_adv >> 2);
1211 if (common & ADVERTISE_1000FULL) {
1212 bp->line_speed = SPEED_1000;
1213 bp->duplex = DUPLEX_FULL;
1214 }
1215 else if (common & ADVERTISE_1000HALF) {
1216 bp->line_speed = SPEED_1000;
1217 bp->duplex = DUPLEX_HALF;
1218 }
1219 else {
1220 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1221 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1222
1223 common = local_adv & remote_adv;
1224 if (common & ADVERTISE_100FULL) {
1225 bp->line_speed = SPEED_100;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_100HALF) {
1229 bp->line_speed = SPEED_100;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else if (common & ADVERTISE_10FULL) {
1233 bp->line_speed = SPEED_10;
1234 bp->duplex = DUPLEX_FULL;
1235 }
1236 else if (common & ADVERTISE_10HALF) {
1237 bp->line_speed = SPEED_10;
1238 bp->duplex = DUPLEX_HALF;
1239 }
1240 else {
1241 bp->line_speed = 0;
1242 bp->link_up = 0;
1243 }
1244 }
1245 }
1246 else {
1247 if (bmcr & BMCR_SPEED100) {
1248 bp->line_speed = SPEED_100;
1249 }
1250 else {
1251 bp->line_speed = SPEED_10;
1252 }
1253 if (bmcr & BMCR_FULLDPLX) {
1254 bp->duplex = DUPLEX_FULL;
1255 }
1256 else {
1257 bp->duplex = DUPLEX_HALF;
1258 }
1259 }
1260
1261 return 0;
1262 }
1263
1264 static void
1265 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1266 {
1267 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1268
1269 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1270 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1271 val |= 0x02 << 8;
1272
1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
1275
1276 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1277 }
1278
1279 static void
1280 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1281 {
1282 int i;
1283 u32 cid;
1284
1285 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1286 if (i == 1)
1287 cid = RX_RSS_CID;
1288 bnx2_init_rx_context(bp, cid);
1289 }
1290 }
1291
1292 static void
1293 bnx2_set_mac_link(struct bnx2 *bp)
1294 {
1295 u32 val;
1296
1297 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1298 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1299 (bp->duplex == DUPLEX_HALF)) {
1300 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1301 }
1302
1303 /* Configure the EMAC mode register. */
1304 val = REG_RD(bp, BNX2_EMAC_MODE);
1305
1306 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1307 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1308 BNX2_EMAC_MODE_25G_MODE);
1309
1310 if (bp->link_up) {
1311 switch (bp->line_speed) {
1312 case SPEED_10:
1313 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1314 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1315 break;
1316 }
1317 /* fall through */
1318 case SPEED_100:
1319 val |= BNX2_EMAC_MODE_PORT_MII;
1320 break;
1321 case SPEED_2500:
1322 val |= BNX2_EMAC_MODE_25G_MODE;
1323 /* fall through */
1324 case SPEED_1000:
1325 val |= BNX2_EMAC_MODE_PORT_GMII;
1326 break;
1327 }
1328 }
1329 else {
1330 val |= BNX2_EMAC_MODE_PORT_GMII;
1331 }
1332
1333 /* Set the MAC to operate in the appropriate duplex mode. */
1334 if (bp->duplex == DUPLEX_HALF)
1335 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1336 REG_WR(bp, BNX2_EMAC_MODE, val);
1337
1338 /* Enable/disable rx PAUSE. */
1339 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1340
1341 if (bp->flow_ctrl & FLOW_CTRL_RX)
1342 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1343 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1344
1345 /* Enable/disable tx PAUSE. */
1346 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1347 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1348
1349 if (bp->flow_ctrl & FLOW_CTRL_TX)
1350 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1351 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1352
1353 /* Acknowledge the interrupt. */
1354 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1355
1356 bnx2_init_all_rx_contexts(bp);
1357 }
1358
1359 static void
1360 bnx2_enable_bmsr1(struct bnx2 *bp)
1361 {
1362 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1363 (CHIP_NUM(bp) == CHIP_NUM_5709))
1364 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1365 MII_BNX2_BLK_ADDR_GP_STATUS);
1366 }
1367
1368 static void
1369 bnx2_disable_bmsr1(struct bnx2 *bp)
1370 {
1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1372 (CHIP_NUM(bp) == CHIP_NUM_5709))
1373 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1374 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1375 }
1376
1377 static int
1378 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1379 {
1380 u32 up1;
1381 int ret = 1;
1382
1383 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1384 return 0;
1385
1386 if (bp->autoneg & AUTONEG_SPEED)
1387 bp->advertising |= ADVERTISED_2500baseX_Full;
1388
1389 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1390 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1391
1392 bnx2_read_phy(bp, bp->mii_up1, &up1);
1393 if (!(up1 & BCM5708S_UP1_2G5)) {
1394 up1 |= BCM5708S_UP1_2G5;
1395 bnx2_write_phy(bp, bp->mii_up1, up1);
1396 ret = 0;
1397 }
1398
1399 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1400 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1401 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1402
1403 return ret;
1404 }
1405
1406 static int
1407 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1408 {
1409 u32 up1;
1410 int ret = 0;
1411
1412 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1413 return 0;
1414
1415 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1416 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1417
1418 bnx2_read_phy(bp, bp->mii_up1, &up1);
1419 if (up1 & BCM5708S_UP1_2G5) {
1420 up1 &= ~BCM5708S_UP1_2G5;
1421 bnx2_write_phy(bp, bp->mii_up1, up1);
1422 ret = 1;
1423 }
1424
1425 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1426 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1427 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1428
1429 return ret;
1430 }
1431
1432 static void
1433 bnx2_enable_forced_2g5(struct bnx2 *bp)
1434 {
1435 u32 uninitialized_var(bmcr);
1436 int err;
1437
1438 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1439 return;
1440
1441 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1442 u32 val;
1443
1444 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1445 MII_BNX2_BLK_ADDR_SERDES_DIG);
1446 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1447 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1448 val |= MII_BNX2_SD_MISC1_FORCE |
1449 MII_BNX2_SD_MISC1_FORCE_2_5G;
1450 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1451 }
1452
1453 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1454 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1455 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1456
1457 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1458 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1459 if (!err)
1460 bmcr |= BCM5708S_BMCR_FORCE_2500;
1461 } else {
1462 return;
1463 }
1464
1465 if (err)
1466 return;
1467
1468 if (bp->autoneg & AUTONEG_SPEED) {
1469 bmcr &= ~BMCR_ANENABLE;
1470 if (bp->req_duplex == DUPLEX_FULL)
1471 bmcr |= BMCR_FULLDPLX;
1472 }
1473 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1474 }
1475
1476 static void
1477 bnx2_disable_forced_2g5(struct bnx2 *bp)
1478 {
1479 u32 uninitialized_var(bmcr);
1480 int err;
1481
1482 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1483 return;
1484
1485 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1486 u32 val;
1487
1488 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1489 MII_BNX2_BLK_ADDR_SERDES_DIG);
1490 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1491 val &= ~MII_BNX2_SD_MISC1_FORCE;
1492 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1493 }
1494
1495 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1496 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1498
1499 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1500 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1501 if (!err)
1502 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1503 } else {
1504 return;
1505 }
1506
1507 if (err)
1508 return;
1509
1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1513 }
1514
1515 static void
1516 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1517 {
1518 u32 val;
1519
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1522 if (start)
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1524 else
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1526 }
1527
1528 static int
1529 bnx2_set_link(struct bnx2 *bp)
1530 {
1531 u32 bmsr;
1532 u8 link_up;
1533
1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1535 bp->link_up = 1;
1536 return 0;
1537 }
1538
1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1540 return 0;
1541
1542 link_up = bp->link_up;
1543
1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
1548
1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1551 u32 val, an_dbg;
1552
1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1554 bnx2_5706s_force_link_dn(bp, 0);
1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1556 }
1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
1558
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1565 bmsr |= BMSR_LSTATUS;
1566 else
1567 bmsr &= ~BMSR_LSTATUS;
1568 }
1569
1570 if (bmsr & BMSR_LSTATUS) {
1571 bp->link_up = 1;
1572
1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
1580 }
1581 else {
1582 bnx2_copper_linkup(bp);
1583 }
1584 bnx2_resolve_flow_ctrl(bp);
1585 }
1586 else {
1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
1590
1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1592 u32 bmcr;
1593
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1597
1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1599 }
1600 bp->link_up = 0;
1601 }
1602
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1605 }
1606
1607 bnx2_set_mac_link(bp);
1608
1609 return 0;
1610 }
1611
1612 static int
1613 bnx2_reset_phy(struct bnx2 *bp)
1614 {
1615 int i;
1616 u32 reg;
1617
1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1619
1620 #define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1622 udelay(10);
1623
1624 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1625 if (!(reg & BMCR_RESET)) {
1626 udelay(20);
1627 break;
1628 }
1629 }
1630 if (i == PHY_RESET_MAX_WAIT) {
1631 return -EBUSY;
1632 }
1633 return 0;
1634 }
1635
1636 static u32
1637 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1638 {
1639 u32 adv = 0;
1640
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1643
1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1645 adv = ADVERTISE_1000XPAUSE;
1646 }
1647 else {
1648 adv = ADVERTISE_PAUSE_CAP;
1649 }
1650 }
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1653 adv = ADVERTISE_1000XPSE_ASYM;
1654 }
1655 else {
1656 adv = ADVERTISE_PAUSE_ASYM;
1657 }
1658 }
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1662 }
1663 else {
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1665 }
1666 }
1667 return adv;
1668 }
1669
1670 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1671
1672 static int
1673 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1674 __releases(&bp->phy_lock)
1675 __acquires(&bp->phy_lock)
1676 {
1677 u32 speed_arg = 0, pause_adv;
1678
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1680
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 } else {
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1703 else
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1708 else
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1710 }
1711 }
1712
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1717
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1721
1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1723
1724 spin_unlock_bh(&bp->phy_lock);
1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1726 spin_lock_bh(&bp->phy_lock);
1727
1728 return 0;
1729 }
1730
1731 static int
1732 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1733 __releases(&bp->phy_lock)
1734 __acquires(&bp->phy_lock)
1735 {
1736 u32 adv, bmcr;
1737 u32 new_adv = 0;
1738
1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1740 return bnx2_setup_remote_phy(bp, port);
1741
1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1743 u32 new_bmcr;
1744 int force_link_down = 0;
1745
1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1752 }
1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1755
1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
1758 new_bmcr |= BMCR_SPEED1000;
1759
1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1766 }
1767
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1771 else
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1773 }
1774
1775 if (bp->req_duplex == DUPLEX_FULL) {
1776 adv |= ADVERTISE_1000XFULL;
1777 new_bmcr |= BMCR_FULLDPLX;
1778 }
1779 else {
1780 adv |= ADVERTISE_1000XHALF;
1781 new_bmcr &= ~BMCR_FULLDPLX;
1782 }
1783 if ((new_bmcr != bmcr) || (force_link_down)) {
1784 /* Force a link down visible on the other side */
1785 if (bp->link_up) {
1786 bnx2_write_phy(bp, bp->mii_adv, adv &
1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1790 BMCR_ANRESTART | BMCR_ANENABLE);
1791
1792 bp->link_up = 0;
1793 netif_carrier_off(bp->dev);
1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1795 bnx2_report_link(bp);
1796 }
1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1799 } else {
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
1802 }
1803 return 0;
1804 }
1805
1806 bnx2_test_and_enable_2g5(bp);
1807
1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1810
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1812
1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1815
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1819 if (bp->link_up) {
1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1821 spin_unlock_bh(&bp->phy_lock);
1822 msleep(20);
1823 spin_lock_bh(&bp->phy_lock);
1824 }
1825
1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1828 BMCR_ANENABLE);
1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1836 */
1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
1840 } else {
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
1843 }
1844
1845 return 0;
1846 }
1847
1848 #define ETHTOOL_ALL_FIBRE_SPEED \
1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
1852
1853 #define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1857
1858 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1860
1861 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1862
1863 static void
1864 bnx2_set_default_remote_link(struct bnx2 *bp)
1865 {
1866 u32 link;
1867
1868 if (bp->phy_port == PORT_TP)
1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1870 else
1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1872
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1889 } else {
1890 bp->autoneg = 0;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1897 }
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1902 }
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1907 }
1908 }
1909
1910 static void
1911 bnx2_set_default_link(struct bnx2 *bp)
1912 {
1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1915 return;
1916 }
1917
1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1921 u32 reg;
1922
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1924
1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1928 bp->autoneg = 0;
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1931 }
1932 } else
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1934 }
1935
1936 static void
1937 bnx2_send_heart_beat(struct bnx2 *bp)
1938 {
1939 u32 msg;
1940 u32 addr;
1941
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1948 }
1949
1950 static void
1951 bnx2_remote_phy_event(struct bnx2 *bp)
1952 {
1953 u32 msg;
1954 u8 link_up = bp->link_up;
1955 u8 old_port;
1956
1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1958
1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1961
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1963
1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1965 bp->link_up = 0;
1966 else {
1967 u32 speed;
1968
1969 bp->link_up = 1;
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1972 switch (speed) {
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1977 break;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1983 break;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1988 break;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
1993 break;
1994 default:
1995 bp->line_speed = 0;
1996 break;
1997 }
1998
1999 bp->flow_ctrl = 0;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2004 } else {
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2009 }
2010
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2014 else
2015 bp->phy_port = PORT_TP;
2016
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2019
2020 }
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2023
2024 bnx2_set_mac_link(bp);
2025 }
2026
2027 static int
2028 bnx2_set_remote_link(struct bnx2 *bp)
2029 {
2030 u32 evt_code;
2031
2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2033 switch (evt_code) {
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2036 break;
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2038 default:
2039 bnx2_send_heart_beat(bp);
2040 break;
2041 }
2042 return 0;
2043 }
2044
2045 static int
2046 bnx2_setup_copper_phy(struct bnx2 *bp)
2047 __releases(&bp->phy_lock)
2048 __acquires(&bp->phy_lock)
2049 {
2050 u32 bmcr;
2051 u32 new_bmcr;
2052
2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2054
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
2057 u32 new_adv_reg = 0;
2058 u32 new_adv1000_reg = 0;
2059
2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2063
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2066
2067 if (bp->advertising & ADVERTISED_10baseT_Half)
2068 new_adv_reg |= ADVERTISE_10HALF;
2069 if (bp->advertising & ADVERTISED_10baseT_Full)
2070 new_adv_reg |= ADVERTISE_10FULL;
2071 if (bp->advertising & ADVERTISED_100baseT_Half)
2072 new_adv_reg |= ADVERTISE_100HALF;
2073 if (bp->advertising & ADVERTISED_100baseT_Full)
2074 new_adv_reg |= ADVERTISE_100FULL;
2075 if (bp->advertising & ADVERTISED_1000baseT_Full)
2076 new_adv1000_reg |= ADVERTISE_1000FULL;
2077
2078 new_adv_reg |= ADVERTISE_CSMA;
2079
2080 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2081
2082 if ((adv1000_reg != new_adv1000_reg) ||
2083 (adv_reg != new_adv_reg) ||
2084 ((bmcr & BMCR_ANENABLE) == 0)) {
2085
2086 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2087 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2088 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2089 BMCR_ANENABLE);
2090 }
2091 else if (bp->link_up) {
2092 /* Flow ctrl may have changed from auto to forced */
2093 /* or vice-versa. */
2094
2095 bnx2_resolve_flow_ctrl(bp);
2096 bnx2_set_mac_link(bp);
2097 }
2098 return 0;
2099 }
2100
2101 new_bmcr = 0;
2102 if (bp->req_line_speed == SPEED_100) {
2103 new_bmcr |= BMCR_SPEED100;
2104 }
2105 if (bp->req_duplex == DUPLEX_FULL) {
2106 new_bmcr |= BMCR_FULLDPLX;
2107 }
2108 if (new_bmcr != bmcr) {
2109 u32 bmsr;
2110
2111 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113
2114 if (bmsr & BMSR_LSTATUS) {
2115 /* Force link down */
2116 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2117 spin_unlock_bh(&bp->phy_lock);
2118 msleep(50);
2119 spin_lock_bh(&bp->phy_lock);
2120
2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2122 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2123 }
2124
2125 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2126
2127 /* Normally, the new speed is setup after the link has
2128 * gone down and up again. In some cases, link will not go
2129 * down so we need to set up the new speed here.
2130 */
2131 if (bmsr & BMSR_LSTATUS) {
2132 bp->line_speed = bp->req_line_speed;
2133 bp->duplex = bp->req_duplex;
2134 bnx2_resolve_flow_ctrl(bp);
2135 bnx2_set_mac_link(bp);
2136 }
2137 } else {
2138 bnx2_resolve_flow_ctrl(bp);
2139 bnx2_set_mac_link(bp);
2140 }
2141 return 0;
2142 }
2143
2144 static int
2145 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2146 __releases(&bp->phy_lock)
2147 __acquires(&bp->phy_lock)
2148 {
2149 if (bp->loopback == MAC_LOOPBACK)
2150 return 0;
2151
2152 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2153 return bnx2_setup_serdes_phy(bp, port);
2154 }
2155 else {
2156 return bnx2_setup_copper_phy(bp);
2157 }
2158 }
2159
2160 static int
2161 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2162 {
2163 u32 val;
2164
2165 bp->mii_bmcr = MII_BMCR + 0x10;
2166 bp->mii_bmsr = MII_BMSR + 0x10;
2167 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2168 bp->mii_adv = MII_ADVERTISE + 0x10;
2169 bp->mii_lpa = MII_LPA + 0x10;
2170 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2171
2172 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2173 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2174
2175 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2176 if (reset_phy)
2177 bnx2_reset_phy(bp);
2178
2179 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2180
2181 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2182 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2183 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2184 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2185
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2187 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2188 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2189 val |= BCM5708S_UP1_2G5;
2190 else
2191 val &= ~BCM5708S_UP1_2G5;
2192 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2193
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2195 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2196 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2197 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2198
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2200
2201 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2202 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2203 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2204
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2206
2207 return 0;
2208 }
2209
2210 static int
2211 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2212 {
2213 u32 val;
2214
2215 if (reset_phy)
2216 bnx2_reset_phy(bp);
2217
2218 bp->mii_up1 = BCM5708S_UP1;
2219
2220 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2221 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2222 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2223
2224 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2225 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2226 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2227
2228 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2229 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2230 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2231
2232 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2233 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2234 val |= BCM5708S_UP1_2G5;
2235 bnx2_write_phy(bp, BCM5708S_UP1, val);
2236 }
2237
2238 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2239 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2240 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2241 /* increase tx signal amplitude */
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2243 BCM5708S_BLK_ADDR_TX_MISC);
2244 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2245 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2246 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2247 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2248 }
2249
2250 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2251 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2252
2253 if (val) {
2254 u32 is_backplane;
2255
2256 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2257 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2258 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2259 BCM5708S_BLK_ADDR_TX_MISC);
2260 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2262 BCM5708S_BLK_ADDR_DIG);
2263 }
2264 }
2265 return 0;
2266 }
2267
2268 static int
2269 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2270 {
2271 if (reset_phy)
2272 bnx2_reset_phy(bp);
2273
2274 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2275
2276 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2277 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2278
2279 if (bp->dev->mtu > 1500) {
2280 u32 val;
2281
2282 /* Set extended packet length bit */
2283 bnx2_write_phy(bp, 0x18, 0x7);
2284 bnx2_read_phy(bp, 0x18, &val);
2285 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2286
2287 bnx2_write_phy(bp, 0x1c, 0x6c00);
2288 bnx2_read_phy(bp, 0x1c, &val);
2289 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2290 }
2291 else {
2292 u32 val;
2293
2294 bnx2_write_phy(bp, 0x18, 0x7);
2295 bnx2_read_phy(bp, 0x18, &val);
2296 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2297
2298 bnx2_write_phy(bp, 0x1c, 0x6c00);
2299 bnx2_read_phy(bp, 0x1c, &val);
2300 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2301 }
2302
2303 return 0;
2304 }
2305
2306 static int
2307 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2308 {
2309 u32 val;
2310
2311 if (reset_phy)
2312 bnx2_reset_phy(bp);
2313
2314 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2315 bnx2_write_phy(bp, 0x18, 0x0c00);
2316 bnx2_write_phy(bp, 0x17, 0x000a);
2317 bnx2_write_phy(bp, 0x15, 0x310b);
2318 bnx2_write_phy(bp, 0x17, 0x201f);
2319 bnx2_write_phy(bp, 0x15, 0x9506);
2320 bnx2_write_phy(bp, 0x17, 0x401f);
2321 bnx2_write_phy(bp, 0x15, 0x14e2);
2322 bnx2_write_phy(bp, 0x18, 0x0400);
2323 }
2324
2325 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2326 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2327 MII_BNX2_DSP_EXPAND_REG | 0x8);
2328 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2329 val &= ~(1 << 8);
2330 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2331 }
2332
2333 if (bp->dev->mtu > 1500) {
2334 /* Set extended packet length bit */
2335 bnx2_write_phy(bp, 0x18, 0x7);
2336 bnx2_read_phy(bp, 0x18, &val);
2337 bnx2_write_phy(bp, 0x18, val | 0x4000);
2338
2339 bnx2_read_phy(bp, 0x10, &val);
2340 bnx2_write_phy(bp, 0x10, val | 0x1);
2341 }
2342 else {
2343 bnx2_write_phy(bp, 0x18, 0x7);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2346
2347 bnx2_read_phy(bp, 0x10, &val);
2348 bnx2_write_phy(bp, 0x10, val & ~0x1);
2349 }
2350
2351 /* ethernet@wirespeed */
2352 bnx2_write_phy(bp, 0x18, 0x7007);
2353 bnx2_read_phy(bp, 0x18, &val);
2354 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2355 return 0;
2356 }
2357
2358
2359 static int
2360 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2361 __releases(&bp->phy_lock)
2362 __acquires(&bp->phy_lock)
2363 {
2364 u32 val;
2365 int rc = 0;
2366
2367 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2368 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2369
2370 bp->mii_bmcr = MII_BMCR;
2371 bp->mii_bmsr = MII_BMSR;
2372 bp->mii_bmsr1 = MII_BMSR;
2373 bp->mii_adv = MII_ADVERTISE;
2374 bp->mii_lpa = MII_LPA;
2375
2376 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2377
2378 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2379 goto setup_phy;
2380
2381 bnx2_read_phy(bp, MII_PHYSID1, &val);
2382 bp->phy_id = val << 16;
2383 bnx2_read_phy(bp, MII_PHYSID2, &val);
2384 bp->phy_id |= val & 0xffff;
2385
2386 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2387 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2388 rc = bnx2_init_5706s_phy(bp, reset_phy);
2389 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2390 rc = bnx2_init_5708s_phy(bp, reset_phy);
2391 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2392 rc = bnx2_init_5709s_phy(bp, reset_phy);
2393 }
2394 else {
2395 rc = bnx2_init_copper_phy(bp, reset_phy);
2396 }
2397
2398 setup_phy:
2399 if (!rc)
2400 rc = bnx2_setup_phy(bp, bp->phy_port);
2401
2402 return rc;
2403 }
2404
2405 static int
2406 bnx2_set_mac_loopback(struct bnx2 *bp)
2407 {
2408 u32 mac_mode;
2409
2410 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2411 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2412 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2413 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2414 bp->link_up = 1;
2415 return 0;
2416 }
2417
2418 static int bnx2_test_link(struct bnx2 *);
2419
2420 static int
2421 bnx2_set_phy_loopback(struct bnx2 *bp)
2422 {
2423 u32 mac_mode;
2424 int rc, i;
2425
2426 spin_lock_bh(&bp->phy_lock);
2427 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2428 BMCR_SPEED1000);
2429 spin_unlock_bh(&bp->phy_lock);
2430 if (rc)
2431 return rc;
2432
2433 for (i = 0; i < 10; i++) {
2434 if (bnx2_test_link(bp) == 0)
2435 break;
2436 msleep(100);
2437 }
2438
2439 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2440 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2441 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2442 BNX2_EMAC_MODE_25G_MODE);
2443
2444 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2445 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2446 bp->link_up = 1;
2447 return 0;
2448 }
2449
2450 static void
2451 bnx2_dump_mcp_state(struct bnx2 *bp)
2452 {
2453 struct net_device *dev = bp->dev;
2454 u32 mcp_p0, mcp_p1;
2455
2456 netdev_err(dev, "<--- start MCP states dump --->\n");
2457 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2458 mcp_p0 = BNX2_MCP_STATE_P0;
2459 mcp_p1 = BNX2_MCP_STATE_P1;
2460 } else {
2461 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2462 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2463 }
2464 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2465 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2466 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2467 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2468 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2469 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2470 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2471 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2472 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2473 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2474 netdev_err(dev, "DEBUG: shmem states:\n");
2475 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2476 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2477 bnx2_shmem_rd(bp, BNX2_FW_MB),
2478 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2479 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2480 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2481 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2482 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2483 pr_cont(" condition[%08x]\n",
2484 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2485 DP_SHMEM_LINE(bp, 0x3cc);
2486 DP_SHMEM_LINE(bp, 0x3dc);
2487 DP_SHMEM_LINE(bp, 0x3ec);
2488 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2489 netdev_err(dev, "<--- end MCP states dump --->\n");
2490 }
2491
2492 static int
2493 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2494 {
2495 int i;
2496 u32 val;
2497
2498 bp->fw_wr_seq++;
2499 msg_data |= bp->fw_wr_seq;
2500
2501 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2502
2503 if (!ack)
2504 return 0;
2505
2506 /* wait for an acknowledgement. */
2507 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2508 msleep(10);
2509
2510 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2511
2512 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2513 break;
2514 }
2515 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2516 return 0;
2517
2518 /* If we timed out, inform the firmware that this is the case. */
2519 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2520 msg_data &= ~BNX2_DRV_MSG_CODE;
2521 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2522
2523 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2524 if (!silent) {
2525 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2526 bnx2_dump_mcp_state(bp);
2527 }
2528
2529 return -EBUSY;
2530 }
2531
2532 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2533 return -EIO;
2534
2535 return 0;
2536 }
2537
2538 static int
2539 bnx2_init_5709_context(struct bnx2 *bp)
2540 {
2541 int i, ret = 0;
2542 u32 val;
2543
2544 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2545 val |= (BCM_PAGE_BITS - 8) << 16;
2546 REG_WR(bp, BNX2_CTX_COMMAND, val);
2547 for (i = 0; i < 10; i++) {
2548 val = REG_RD(bp, BNX2_CTX_COMMAND);
2549 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2550 break;
2551 udelay(2);
2552 }
2553 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2554 return -EBUSY;
2555
2556 for (i = 0; i < bp->ctx_pages; i++) {
2557 int j;
2558
2559 if (bp->ctx_blk[i])
2560 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2561 else
2562 return -ENOMEM;
2563
2564 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2565 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2566 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2567 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2568 (u64) bp->ctx_blk_mapping[i] >> 32);
2569 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2570 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2571 for (j = 0; j < 10; j++) {
2572
2573 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2574 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2575 break;
2576 udelay(5);
2577 }
2578 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2579 ret = -EBUSY;
2580 break;
2581 }
2582 }
2583 return ret;
2584 }
2585
2586 static void
2587 bnx2_init_context(struct bnx2 *bp)
2588 {
2589 u32 vcid;
2590
2591 vcid = 96;
2592 while (vcid) {
2593 u32 vcid_addr, pcid_addr, offset;
2594 int i;
2595
2596 vcid--;
2597
2598 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2599 u32 new_vcid;
2600
2601 vcid_addr = GET_PCID_ADDR(vcid);
2602 if (vcid & 0x8) {
2603 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2604 }
2605 else {
2606 new_vcid = vcid;
2607 }
2608 pcid_addr = GET_PCID_ADDR(new_vcid);
2609 }
2610 else {
2611 vcid_addr = GET_CID_ADDR(vcid);
2612 pcid_addr = vcid_addr;
2613 }
2614
2615 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2616 vcid_addr += (i << PHY_CTX_SHIFT);
2617 pcid_addr += (i << PHY_CTX_SHIFT);
2618
2619 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2620 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2621
2622 /* Zero out the context. */
2623 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2624 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2625 }
2626 }
2627 }
2628
2629 static int
2630 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2631 {
2632 u16 *good_mbuf;
2633 u32 good_mbuf_cnt;
2634 u32 val;
2635
2636 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2637 if (good_mbuf == NULL) {
2638 pr_err("Failed to allocate memory in %s\n", __func__);
2639 return -ENOMEM;
2640 }
2641
2642 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2643 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2644
2645 good_mbuf_cnt = 0;
2646
2647 /* Allocate a bunch of mbufs and save the good ones in an array. */
2648 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2649 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2650 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2651 BNX2_RBUF_COMMAND_ALLOC_REQ);
2652
2653 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2654
2655 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2656
2657 /* The addresses with Bit 9 set are bad memory blocks. */
2658 if (!(val & (1 << 9))) {
2659 good_mbuf[good_mbuf_cnt] = (u16) val;
2660 good_mbuf_cnt++;
2661 }
2662
2663 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2664 }
2665
2666 /* Free the good ones back to the mbuf pool thus discarding
2667 * all the bad ones. */
2668 while (good_mbuf_cnt) {
2669 good_mbuf_cnt--;
2670
2671 val = good_mbuf[good_mbuf_cnt];
2672 val = (val << 9) | val | 1;
2673
2674 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2675 }
2676 kfree(good_mbuf);
2677 return 0;
2678 }
2679
2680 static void
2681 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2682 {
2683 u32 val;
2684
2685 val = (mac_addr[0] << 8) | mac_addr[1];
2686
2687 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2688
2689 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2690 (mac_addr[4] << 8) | mac_addr[5];
2691
2692 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2693 }
2694
2695 static inline int
2696 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2697 {
2698 dma_addr_t mapping;
2699 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2700 struct rx_bd *rxbd =
2701 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2702 struct page *page = alloc_page(gfp);
2703
2704 if (!page)
2705 return -ENOMEM;
2706 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
2707 PCI_DMA_FROMDEVICE);
2708 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2709 __free_page(page);
2710 return -EIO;
2711 }
2712
2713 rx_pg->page = page;
2714 dma_unmap_addr_set(rx_pg, mapping, mapping);
2715 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2716 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2717 return 0;
2718 }
2719
2720 static void
2721 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2722 {
2723 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2724 struct page *page = rx_pg->page;
2725
2726 if (!page)
2727 return;
2728
2729 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2730 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2731
2732 __free_page(page);
2733 rx_pg->page = NULL;
2734 }
2735
2736 static inline int
2737 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2738 {
2739 struct sk_buff *skb;
2740 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2741 dma_addr_t mapping;
2742 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2743 unsigned long align;
2744
2745 skb = __netdev_alloc_skb(bp->dev, bp->rx_buf_size, gfp);
2746 if (skb == NULL) {
2747 return -ENOMEM;
2748 }
2749
2750 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2751 skb_reserve(skb, BNX2_RX_ALIGN - align);
2752
2753 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_use_size,
2754 PCI_DMA_FROMDEVICE);
2755 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2756 dev_kfree_skb(skb);
2757 return -EIO;
2758 }
2759
2760 rx_buf->skb = skb;
2761 rx_buf->desc = (struct l2_fhdr *) skb->data;
2762 dma_unmap_addr_set(rx_buf, mapping, mapping);
2763
2764 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2765 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2766
2767 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2768
2769 return 0;
2770 }
2771
2772 static int
2773 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2774 {
2775 struct status_block *sblk = bnapi->status_blk.msi;
2776 u32 new_link_state, old_link_state;
2777 int is_set = 1;
2778
2779 new_link_state = sblk->status_attn_bits & event;
2780 old_link_state = sblk->status_attn_bits_ack & event;
2781 if (new_link_state != old_link_state) {
2782 if (new_link_state)
2783 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2784 else
2785 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2786 } else
2787 is_set = 0;
2788
2789 return is_set;
2790 }
2791
2792 static void
2793 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2794 {
2795 spin_lock(&bp->phy_lock);
2796
2797 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2798 bnx2_set_link(bp);
2799 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2800 bnx2_set_remote_link(bp);
2801
2802 spin_unlock(&bp->phy_lock);
2803
2804 }
2805
2806 static inline u16
2807 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2808 {
2809 u16 cons;
2810
2811 /* Tell compiler that status block fields can change. */
2812 barrier();
2813 cons = *bnapi->hw_tx_cons_ptr;
2814 barrier();
2815 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2816 cons++;
2817 return cons;
2818 }
2819
2820 static int
2821 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2822 {
2823 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2824 u16 hw_cons, sw_cons, sw_ring_cons;
2825 int tx_pkt = 0, index;
2826 struct netdev_queue *txq;
2827
2828 index = (bnapi - bp->bnx2_napi);
2829 txq = netdev_get_tx_queue(bp->dev, index);
2830
2831 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2832 sw_cons = txr->tx_cons;
2833
2834 while (sw_cons != hw_cons) {
2835 struct sw_tx_bd *tx_buf;
2836 struct sk_buff *skb;
2837 int i, last;
2838
2839 sw_ring_cons = TX_RING_IDX(sw_cons);
2840
2841 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2842 skb = tx_buf->skb;
2843
2844 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2845 prefetch(&skb->end);
2846
2847 /* partial BD completions possible with TSO packets */
2848 if (tx_buf->is_gso) {
2849 u16 last_idx, last_ring_idx;
2850
2851 last_idx = sw_cons + tx_buf->nr_frags + 1;
2852 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2853 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2854 last_idx++;
2855 }
2856 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2857 break;
2858 }
2859 }
2860
2861 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
2862 skb_headlen(skb), PCI_DMA_TODEVICE);
2863
2864 tx_buf->skb = NULL;
2865 last = tx_buf->nr_frags;
2866
2867 for (i = 0; i < last; i++) {
2868 sw_cons = NEXT_TX_BD(sw_cons);
2869
2870 dma_unmap_page(&bp->pdev->dev,
2871 dma_unmap_addr(
2872 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2873 mapping),
2874 skb_shinfo(skb)->frags[i].size,
2875 PCI_DMA_TODEVICE);
2876 }
2877
2878 sw_cons = NEXT_TX_BD(sw_cons);
2879
2880 dev_kfree_skb(skb);
2881 tx_pkt++;
2882 if (tx_pkt == budget)
2883 break;
2884
2885 if (hw_cons == sw_cons)
2886 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2887 }
2888
2889 txr->hw_tx_cons = hw_cons;
2890 txr->tx_cons = sw_cons;
2891
2892 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2893 * before checking for netif_tx_queue_stopped(). Without the
2894 * memory barrier, there is a small possibility that bnx2_start_xmit()
2895 * will miss it and cause the queue to be stopped forever.
2896 */
2897 smp_mb();
2898
2899 if (unlikely(netif_tx_queue_stopped(txq)) &&
2900 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2901 __netif_tx_lock(txq, smp_processor_id());
2902 if ((netif_tx_queue_stopped(txq)) &&
2903 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2904 netif_tx_wake_queue(txq);
2905 __netif_tx_unlock(txq);
2906 }
2907
2908 return tx_pkt;
2909 }
2910
2911 static void
2912 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2913 struct sk_buff *skb, int count)
2914 {
2915 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2916 struct rx_bd *cons_bd, *prod_bd;
2917 int i;
2918 u16 hw_prod, prod;
2919 u16 cons = rxr->rx_pg_cons;
2920
2921 cons_rx_pg = &rxr->rx_pg_ring[cons];
2922
2923 /* The caller was unable to allocate a new page to replace the
2924 * last one in the frags array, so we need to recycle that page
2925 * and then free the skb.
2926 */
2927 if (skb) {
2928 struct page *page;
2929 struct skb_shared_info *shinfo;
2930
2931 shinfo = skb_shinfo(skb);
2932 shinfo->nr_frags--;
2933 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2934 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
2935
2936 cons_rx_pg->page = page;
2937 dev_kfree_skb(skb);
2938 }
2939
2940 hw_prod = rxr->rx_pg_prod;
2941
2942 for (i = 0; i < count; i++) {
2943 prod = RX_PG_RING_IDX(hw_prod);
2944
2945 prod_rx_pg = &rxr->rx_pg_ring[prod];
2946 cons_rx_pg = &rxr->rx_pg_ring[cons];
2947 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2948 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2949
2950 if (prod != cons) {
2951 prod_rx_pg->page = cons_rx_pg->page;
2952 cons_rx_pg->page = NULL;
2953 dma_unmap_addr_set(prod_rx_pg, mapping,
2954 dma_unmap_addr(cons_rx_pg, mapping));
2955
2956 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2957 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2958
2959 }
2960 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2961 hw_prod = NEXT_RX_BD(hw_prod);
2962 }
2963 rxr->rx_pg_prod = hw_prod;
2964 rxr->rx_pg_cons = cons;
2965 }
2966
2967 static inline void
2968 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2969 struct sk_buff *skb, u16 cons, u16 prod)
2970 {
2971 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2972 struct rx_bd *cons_bd, *prod_bd;
2973
2974 cons_rx_buf = &rxr->rx_buf_ring[cons];
2975 prod_rx_buf = &rxr->rx_buf_ring[prod];
2976
2977 dma_sync_single_for_device(&bp->pdev->dev,
2978 dma_unmap_addr(cons_rx_buf, mapping),
2979 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2980
2981 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2982
2983 prod_rx_buf->skb = skb;
2984 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
2985
2986 if (cons == prod)
2987 return;
2988
2989 dma_unmap_addr_set(prod_rx_buf, mapping,
2990 dma_unmap_addr(cons_rx_buf, mapping));
2991
2992 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2993 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2994 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2995 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2996 }
2997
2998 static int
2999 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
3000 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
3001 u32 ring_idx)
3002 {
3003 int err;
3004 u16 prod = ring_idx & 0xffff;
3005
3006 err = bnx2_alloc_rx_skb(bp, rxr, prod, GFP_ATOMIC);
3007 if (unlikely(err)) {
3008 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
3009 if (hdr_len) {
3010 unsigned int raw_len = len + 4;
3011 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3012
3013 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3014 }
3015 return err;
3016 }
3017
3018 skb_reserve(skb, BNX2_RX_OFFSET);
3019 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
3020 PCI_DMA_FROMDEVICE);
3021
3022 if (hdr_len == 0) {
3023 skb_put(skb, len);
3024 return 0;
3025 } else {
3026 unsigned int i, frag_len, frag_size, pages;
3027 struct sw_pg *rx_pg;
3028 u16 pg_cons = rxr->rx_pg_cons;
3029 u16 pg_prod = rxr->rx_pg_prod;
3030
3031 frag_size = len + 4 - hdr_len;
3032 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3033 skb_put(skb, hdr_len);
3034
3035 for (i = 0; i < pages; i++) {
3036 dma_addr_t mapping_old;
3037
3038 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3039 if (unlikely(frag_len <= 4)) {
3040 unsigned int tail = 4 - frag_len;
3041
3042 rxr->rx_pg_cons = pg_cons;
3043 rxr->rx_pg_prod = pg_prod;
3044 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3045 pages - i);
3046 skb->len -= tail;
3047 if (i == 0) {
3048 skb->tail -= tail;
3049 } else {
3050 skb_frag_t *frag =
3051 &skb_shinfo(skb)->frags[i - 1];
3052 frag->size -= tail;
3053 skb->data_len -= tail;
3054 skb->truesize -= tail;
3055 }
3056 return 0;
3057 }
3058 rx_pg = &rxr->rx_pg_ring[pg_cons];
3059
3060 /* Don't unmap yet. If we're unable to allocate a new
3061 * page, we need to recycle the page and the DMA addr.
3062 */
3063 mapping_old = dma_unmap_addr(rx_pg, mapping);
3064 if (i == pages - 1)
3065 frag_len -= 4;
3066
3067 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3068 rx_pg->page = NULL;
3069
3070 err = bnx2_alloc_rx_page(bp, rxr,
3071 RX_PG_RING_IDX(pg_prod),
3072 GFP_ATOMIC);
3073 if (unlikely(err)) {
3074 rxr->rx_pg_cons = pg_cons;
3075 rxr->rx_pg_prod = pg_prod;
3076 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3077 pages - i);
3078 return err;
3079 }
3080
3081 dma_unmap_page(&bp->pdev->dev, mapping_old,
3082 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3083
3084 frag_size -= frag_len;
3085 skb->data_len += frag_len;
3086 skb->truesize += frag_len;
3087 skb->len += frag_len;
3088
3089 pg_prod = NEXT_RX_BD(pg_prod);
3090 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3091 }
3092 rxr->rx_pg_prod = pg_prod;
3093 rxr->rx_pg_cons = pg_cons;
3094 }
3095 return 0;
3096 }
3097
3098 static inline u16
3099 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3100 {
3101 u16 cons;
3102
3103 /* Tell compiler that status block fields can change. */
3104 barrier();
3105 cons = *bnapi->hw_rx_cons_ptr;
3106 barrier();
3107 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3108 cons++;
3109 return cons;
3110 }
3111
3112 static int
3113 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3114 {
3115 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3116 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3117 struct l2_fhdr *rx_hdr;
3118 int rx_pkt = 0, pg_ring_used = 0;
3119
3120 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3121 sw_cons = rxr->rx_cons;
3122 sw_prod = rxr->rx_prod;
3123
3124 /* Memory barrier necessary as speculative reads of the rx
3125 * buffer can be ahead of the index in the status block
3126 */
3127 rmb();
3128 while (sw_cons != hw_cons) {
3129 unsigned int len, hdr_len;
3130 u32 status;
3131 struct sw_bd *rx_buf, *next_rx_buf;
3132 struct sk_buff *skb;
3133 dma_addr_t dma_addr;
3134
3135 sw_ring_cons = RX_RING_IDX(sw_cons);
3136 sw_ring_prod = RX_RING_IDX(sw_prod);
3137
3138 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3139 skb = rx_buf->skb;
3140 prefetchw(skb);
3141
3142 next_rx_buf =
3143 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3144 prefetch(next_rx_buf->desc);
3145
3146 rx_buf->skb = NULL;
3147
3148 dma_addr = dma_unmap_addr(rx_buf, mapping);
3149
3150 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
3151 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3152 PCI_DMA_FROMDEVICE);
3153
3154 rx_hdr = rx_buf->desc;
3155 len = rx_hdr->l2_fhdr_pkt_len;
3156 status = rx_hdr->l2_fhdr_status;
3157
3158 hdr_len = 0;
3159 if (status & L2_FHDR_STATUS_SPLIT) {
3160 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3161 pg_ring_used = 1;
3162 } else if (len > bp->rx_jumbo_thresh) {
3163 hdr_len = bp->rx_jumbo_thresh;
3164 pg_ring_used = 1;
3165 }
3166
3167 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3168 L2_FHDR_ERRORS_PHY_DECODE |
3169 L2_FHDR_ERRORS_ALIGNMENT |
3170 L2_FHDR_ERRORS_TOO_SHORT |
3171 L2_FHDR_ERRORS_GIANT_FRAME))) {
3172
3173 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3174 sw_ring_prod);
3175 if (pg_ring_used) {
3176 int pages;
3177
3178 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3179
3180 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3181 }
3182 goto next_rx;
3183 }
3184
3185 len -= 4;
3186
3187 if (len <= bp->rx_copy_thresh) {
3188 struct sk_buff *new_skb;
3189
3190 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3191 if (new_skb == NULL) {
3192 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3193 sw_ring_prod);
3194 goto next_rx;
3195 }
3196
3197 /* aligned copy */
3198 skb_copy_from_linear_data_offset(skb,
3199 BNX2_RX_OFFSET - 6,
3200 new_skb->data, len + 6);
3201 skb_reserve(new_skb, 6);
3202 skb_put(new_skb, len);
3203
3204 bnx2_reuse_rx_skb(bp, rxr, skb,
3205 sw_ring_cons, sw_ring_prod);
3206
3207 skb = new_skb;
3208 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3209 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3210 goto next_rx;
3211
3212 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3213 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3214 __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag);
3215
3216 skb->protocol = eth_type_trans(skb, bp->dev);
3217
3218 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3219 (ntohs(skb->protocol) != 0x8100)) {
3220
3221 dev_kfree_skb(skb);
3222 goto next_rx;
3223
3224 }
3225
3226 skb_checksum_none_assert(skb);
3227 if ((bp->dev->features & NETIF_F_RXCSUM) &&
3228 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3229 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3230
3231 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3232 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3233 skb->ip_summed = CHECKSUM_UNNECESSARY;
3234 }
3235 if ((bp->dev->features & NETIF_F_RXHASH) &&
3236 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3237 L2_FHDR_STATUS_USE_RXHASH))
3238 skb->rxhash = rx_hdr->l2_fhdr_hash;
3239
3240 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3241 napi_gro_receive(&bnapi->napi, skb);
3242 rx_pkt++;
3243
3244 next_rx:
3245 sw_cons = NEXT_RX_BD(sw_cons);
3246 sw_prod = NEXT_RX_BD(sw_prod);
3247
3248 if ((rx_pkt == budget))
3249 break;
3250
3251 /* Refresh hw_cons to see if there is new work */
3252 if (sw_cons == hw_cons) {
3253 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3254 rmb();
3255 }
3256 }
3257 rxr->rx_cons = sw_cons;
3258 rxr->rx_prod = sw_prod;
3259
3260 if (pg_ring_used)
3261 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3262
3263 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3264
3265 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3266
3267 mmiowb();
3268
3269 return rx_pkt;
3270
3271 }
3272
3273 /* MSI ISR - The only difference between this and the INTx ISR
3274 * is that the MSI interrupt is always serviced.
3275 */
3276 static irqreturn_t
3277 bnx2_msi(int irq, void *dev_instance)
3278 {
3279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
3281
3282 prefetch(bnapi->status_blk.msi);
3283 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3284 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3285 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3286
3287 /* Return here if interrupt is disabled. */
3288 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3289 return IRQ_HANDLED;
3290
3291 napi_schedule(&bnapi->napi);
3292
3293 return IRQ_HANDLED;
3294 }
3295
3296 static irqreturn_t
3297 bnx2_msi_1shot(int irq, void *dev_instance)
3298 {
3299 struct bnx2_napi *bnapi = dev_instance;
3300 struct bnx2 *bp = bnapi->bp;
3301
3302 prefetch(bnapi->status_blk.msi);
3303
3304 /* Return here if interrupt is disabled. */
3305 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3306 return IRQ_HANDLED;
3307
3308 napi_schedule(&bnapi->napi);
3309
3310 return IRQ_HANDLED;
3311 }
3312
3313 static irqreturn_t
3314 bnx2_interrupt(int irq, void *dev_instance)
3315 {
3316 struct bnx2_napi *bnapi = dev_instance;
3317 struct bnx2 *bp = bnapi->bp;
3318 struct status_block *sblk = bnapi->status_blk.msi;
3319
3320 /* When using INTx, it is possible for the interrupt to arrive
3321 * at the CPU before the status block posted prior to the
3322 * interrupt. Reading a register will flush the status block.
3323 * When using MSI, the MSI message will always complete after
3324 * the status block write.
3325 */
3326 if ((sblk->status_idx == bnapi->last_status_idx) &&
3327 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3328 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3329 return IRQ_NONE;
3330
3331 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3332 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3333 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3334
3335 /* Read back to deassert IRQ immediately to avoid too many
3336 * spurious interrupts.
3337 */
3338 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3339
3340 /* Return here if interrupt is shared and is disabled. */
3341 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3342 return IRQ_HANDLED;
3343
3344 if (napi_schedule_prep(&bnapi->napi)) {
3345 bnapi->last_status_idx = sblk->status_idx;
3346 __napi_schedule(&bnapi->napi);
3347 }
3348
3349 return IRQ_HANDLED;
3350 }
3351
3352 static inline int
3353 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3354 {
3355 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3356 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3357
3358 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3359 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3360 return 1;
3361 return 0;
3362 }
3363
3364 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3365 STATUS_ATTN_BITS_TIMER_ABORT)
3366
3367 static inline int
3368 bnx2_has_work(struct bnx2_napi *bnapi)
3369 {
3370 struct status_block *sblk = bnapi->status_blk.msi;
3371
3372 if (bnx2_has_fast_work(bnapi))
3373 return 1;
3374
3375 #ifdef BCM_CNIC
3376 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3377 return 1;
3378 #endif
3379
3380 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3381 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3382 return 1;
3383
3384 return 0;
3385 }
3386
3387 static void
3388 bnx2_chk_missed_msi(struct bnx2 *bp)
3389 {
3390 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3391 u32 msi_ctrl;
3392
3393 if (bnx2_has_work(bnapi)) {
3394 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3395 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3396 return;
3397
3398 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3399 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3400 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3401 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3402 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3403 }
3404 }
3405
3406 bp->idle_chk_status_idx = bnapi->last_status_idx;
3407 }
3408
3409 #ifdef BCM_CNIC
3410 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3411 {
3412 struct cnic_ops *c_ops;
3413
3414 if (!bnapi->cnic_present)
3415 return;
3416
3417 rcu_read_lock();
3418 c_ops = rcu_dereference(bp->cnic_ops);
3419 if (c_ops)
3420 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3421 bnapi->status_blk.msi);
3422 rcu_read_unlock();
3423 }
3424 #endif
3425
3426 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3427 {
3428 struct status_block *sblk = bnapi->status_blk.msi;
3429 u32 status_attn_bits = sblk->status_attn_bits;
3430 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3431
3432 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3433 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3434
3435 bnx2_phy_int(bp, bnapi);
3436
3437 /* This is needed to take care of transient status
3438 * during link changes.
3439 */
3440 REG_WR(bp, BNX2_HC_COMMAND,
3441 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3442 REG_RD(bp, BNX2_HC_COMMAND);
3443 }
3444 }
3445
3446 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3447 int work_done, int budget)
3448 {
3449 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3450 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3451
3452 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3453 bnx2_tx_int(bp, bnapi, 0);
3454
3455 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3456 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3457
3458 return work_done;
3459 }
3460
3461 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3462 {
3463 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3464 struct bnx2 *bp = bnapi->bp;
3465 int work_done = 0;
3466 struct status_block_msix *sblk = bnapi->status_blk.msix;
3467
3468 while (1) {
3469 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3470 if (unlikely(work_done >= budget))
3471 break;
3472
3473 bnapi->last_status_idx = sblk->status_idx;
3474 /* status idx must be read before checking for more work. */
3475 rmb();
3476 if (likely(!bnx2_has_fast_work(bnapi))) {
3477
3478 napi_complete(napi);
3479 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3480 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3481 bnapi->last_status_idx);
3482 break;
3483 }
3484 }
3485 return work_done;
3486 }
3487
3488 static int bnx2_poll(struct napi_struct *napi, int budget)
3489 {
3490 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3491 struct bnx2 *bp = bnapi->bp;
3492 int work_done = 0;
3493 struct status_block *sblk = bnapi->status_blk.msi;
3494
3495 while (1) {
3496 bnx2_poll_link(bp, bnapi);
3497
3498 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3499
3500 #ifdef BCM_CNIC
3501 bnx2_poll_cnic(bp, bnapi);
3502 #endif
3503
3504 /* bnapi->last_status_idx is used below to tell the hw how
3505 * much work has been processed, so we must read it before
3506 * checking for more work.
3507 */
3508 bnapi->last_status_idx = sblk->status_idx;
3509
3510 if (unlikely(work_done >= budget))
3511 break;
3512
3513 rmb();
3514 if (likely(!bnx2_has_work(bnapi))) {
3515 napi_complete(napi);
3516 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3517 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3518 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3519 bnapi->last_status_idx);
3520 break;
3521 }
3522 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3523 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3524 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3525 bnapi->last_status_idx);
3526
3527 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3528 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3529 bnapi->last_status_idx);
3530 break;
3531 }
3532 }
3533
3534 return work_done;
3535 }
3536
3537 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3538 * from set_multicast.
3539 */
3540 static void
3541 bnx2_set_rx_mode(struct net_device *dev)
3542 {
3543 struct bnx2 *bp = netdev_priv(dev);
3544 u32 rx_mode, sort_mode;
3545 struct netdev_hw_addr *ha;
3546 int i;
3547
3548 if (!netif_running(dev))
3549 return;
3550
3551 spin_lock_bh(&bp->phy_lock);
3552
3553 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3554 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3555 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3556 if (!(dev->features & NETIF_F_HW_VLAN_RX) &&
3557 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3558 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3559 if (dev->flags & IFF_PROMISC) {
3560 /* Promiscuous mode. */
3561 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3562 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3563 BNX2_RPM_SORT_USER0_PROM_VLAN;
3564 }
3565 else if (dev->flags & IFF_ALLMULTI) {
3566 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3567 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3568 0xffffffff);
3569 }
3570 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3571 }
3572 else {
3573 /* Accept one or more multicast(s). */
3574 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3575 u32 regidx;
3576 u32 bit;
3577 u32 crc;
3578
3579 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3580
3581 netdev_for_each_mc_addr(ha, dev) {
3582 crc = ether_crc_le(ETH_ALEN, ha->addr);
3583 bit = crc & 0xff;
3584 regidx = (bit & 0xe0) >> 5;
3585 bit &= 0x1f;
3586 mc_filter[regidx] |= (1 << bit);
3587 }
3588
3589 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3590 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3591 mc_filter[i]);
3592 }
3593
3594 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3595 }
3596
3597 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3598 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3599 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3600 BNX2_RPM_SORT_USER0_PROM_VLAN;
3601 } else if (!(dev->flags & IFF_PROMISC)) {
3602 /* Add all entries into to the match filter list */
3603 i = 0;
3604 netdev_for_each_uc_addr(ha, dev) {
3605 bnx2_set_mac_addr(bp, ha->addr,
3606 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3607 sort_mode |= (1 <<
3608 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3609 i++;
3610 }
3611
3612 }
3613
3614 if (rx_mode != bp->rx_mode) {
3615 bp->rx_mode = rx_mode;
3616 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3617 }
3618
3619 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3620 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3621 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3622
3623 spin_unlock_bh(&bp->phy_lock);
3624 }
3625
3626 static int
3627 check_fw_section(const struct firmware *fw,
3628 const struct bnx2_fw_file_section *section,
3629 u32 alignment, bool non_empty)
3630 {
3631 u32 offset = be32_to_cpu(section->offset);
3632 u32 len = be32_to_cpu(section->len);
3633
3634 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3635 return -EINVAL;
3636 if ((non_empty && len == 0) || len > fw->size - offset ||
3637 len & (alignment - 1))
3638 return -EINVAL;
3639 return 0;
3640 }
3641
3642 static int
3643 check_mips_fw_entry(const struct firmware *fw,
3644 const struct bnx2_mips_fw_file_entry *entry)
3645 {
3646 if (check_fw_section(fw, &entry->text, 4, true) ||
3647 check_fw_section(fw, &entry->data, 4, false) ||
3648 check_fw_section(fw, &entry->rodata, 4, false))
3649 return -EINVAL;
3650 return 0;
3651 }
3652
3653 static void bnx2_release_firmware(struct bnx2 *bp)
3654 {
3655 if (bp->rv2p_firmware) {
3656 release_firmware(bp->mips_firmware);
3657 release_firmware(bp->rv2p_firmware);
3658 bp->rv2p_firmware = NULL;
3659 }
3660 }
3661
3662 static int bnx2_request_uncached_firmware(struct bnx2 *bp)
3663 {
3664 const char *mips_fw_file, *rv2p_fw_file;
3665 const struct bnx2_mips_fw_file *mips_fw;
3666 const struct bnx2_rv2p_fw_file *rv2p_fw;
3667 int rc;
3668
3669 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3670 mips_fw_file = FW_MIPS_FILE_09;
3671 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3672 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3673 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3674 else
3675 rv2p_fw_file = FW_RV2P_FILE_09;
3676 } else {
3677 mips_fw_file = FW_MIPS_FILE_06;
3678 rv2p_fw_file = FW_RV2P_FILE_06;
3679 }
3680
3681 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3682 if (rc) {
3683 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3684 goto out;
3685 }
3686
3687 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3688 if (rc) {
3689 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3690 goto err_release_mips_firmware;
3691 }
3692 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3693 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3694 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3695 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3696 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3697 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3698 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3699 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3700 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3701 rc = -EINVAL;
3702 goto err_release_firmware;
3703 }
3704 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3705 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3706 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3707 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3708 rc = -EINVAL;
3709 goto err_release_firmware;
3710 }
3711 out:
3712 return rc;
3713
3714 err_release_firmware:
3715 release_firmware(bp->rv2p_firmware);
3716 bp->rv2p_firmware = NULL;
3717 err_release_mips_firmware:
3718 release_firmware(bp->mips_firmware);
3719 goto out;
3720 }
3721
3722 static int bnx2_request_firmware(struct bnx2 *bp)
3723 {
3724 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
3725 }
3726
3727 static u32
3728 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3729 {
3730 switch (idx) {
3731 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3732 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3733 rv2p_code |= RV2P_BD_PAGE_SIZE;
3734 break;
3735 }
3736 return rv2p_code;
3737 }
3738
3739 static int
3740 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3741 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3742 {
3743 u32 rv2p_code_len, file_offset;
3744 __be32 *rv2p_code;
3745 int i;
3746 u32 val, cmd, addr;
3747
3748 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3749 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3750
3751 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3752
3753 if (rv2p_proc == RV2P_PROC1) {
3754 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3755 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3756 } else {
3757 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3758 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3759 }
3760
3761 for (i = 0; i < rv2p_code_len; i += 8) {
3762 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3763 rv2p_code++;
3764 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3765 rv2p_code++;
3766
3767 val = (i / 8) | cmd;
3768 REG_WR(bp, addr, val);
3769 }
3770
3771 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3772 for (i = 0; i < 8; i++) {
3773 u32 loc, code;
3774
3775 loc = be32_to_cpu(fw_entry->fixup[i]);
3776 if (loc && ((loc * 4) < rv2p_code_len)) {
3777 code = be32_to_cpu(*(rv2p_code + loc - 1));
3778 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3779 code = be32_to_cpu(*(rv2p_code + loc));
3780 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3781 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3782
3783 val = (loc / 2) | cmd;
3784 REG_WR(bp, addr, val);
3785 }
3786 }
3787
3788 /* Reset the processor, un-stall is done later. */
3789 if (rv2p_proc == RV2P_PROC1) {
3790 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3791 }
3792 else {
3793 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3794 }
3795
3796 return 0;
3797 }
3798
3799 static int
3800 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3801 const struct bnx2_mips_fw_file_entry *fw_entry)
3802 {
3803 u32 addr, len, file_offset;
3804 __be32 *data;
3805 u32 offset;
3806 u32 val;
3807
3808 /* Halt the CPU. */
3809 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3810 val |= cpu_reg->mode_value_halt;
3811 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3812 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3813
3814 /* Load the Text area. */
3815 addr = be32_to_cpu(fw_entry->text.addr);
3816 len = be32_to_cpu(fw_entry->text.len);
3817 file_offset = be32_to_cpu(fw_entry->text.offset);
3818 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3819
3820 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3821 if (len) {
3822 int j;
3823
3824 for (j = 0; j < (len / 4); j++, offset += 4)
3825 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3826 }
3827
3828 /* Load the Data area. */
3829 addr = be32_to_cpu(fw_entry->data.addr);
3830 len = be32_to_cpu(fw_entry->data.len);
3831 file_offset = be32_to_cpu(fw_entry->data.offset);
3832 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3833
3834 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3835 if (len) {
3836 int j;
3837
3838 for (j = 0; j < (len / 4); j++, offset += 4)
3839 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3840 }
3841
3842 /* Load the Read-Only area. */
3843 addr = be32_to_cpu(fw_entry->rodata.addr);
3844 len = be32_to_cpu(fw_entry->rodata.len);
3845 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3846 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3847
3848 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3849 if (len) {
3850 int j;
3851
3852 for (j = 0; j < (len / 4); j++, offset += 4)
3853 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3854 }
3855
3856 /* Clear the pre-fetch instruction. */
3857 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3858
3859 val = be32_to_cpu(fw_entry->start_addr);
3860 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3861
3862 /* Start the CPU. */
3863 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3864 val &= ~cpu_reg->mode_value_halt;
3865 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3866 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3867
3868 return 0;
3869 }
3870
3871 static int
3872 bnx2_init_cpus(struct bnx2 *bp)
3873 {
3874 const struct bnx2_mips_fw_file *mips_fw =
3875 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3876 const struct bnx2_rv2p_fw_file *rv2p_fw =
3877 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3878 int rc;
3879
3880 /* Initialize the RV2P processor. */
3881 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3882 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3883
3884 /* Initialize the RX Processor. */
3885 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3886 if (rc)
3887 goto init_cpu_err;
3888
3889 /* Initialize the TX Processor. */
3890 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3891 if (rc)
3892 goto init_cpu_err;
3893
3894 /* Initialize the TX Patch-up Processor. */
3895 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3896 if (rc)
3897 goto init_cpu_err;
3898
3899 /* Initialize the Completion Processor. */
3900 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3901 if (rc)
3902 goto init_cpu_err;
3903
3904 /* Initialize the Command Processor. */
3905 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3906
3907 init_cpu_err:
3908 return rc;
3909 }
3910
3911 static int
3912 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3913 {
3914 u16 pmcsr;
3915
3916 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3917
3918 switch (state) {
3919 case PCI_D0: {
3920 u32 val;
3921
3922 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3923 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3924 PCI_PM_CTRL_PME_STATUS);
3925
3926 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3927 /* delay required during transition out of D3hot */
3928 msleep(20);
3929
3930 val = REG_RD(bp, BNX2_EMAC_MODE);
3931 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3932 val &= ~BNX2_EMAC_MODE_MPKT;
3933 REG_WR(bp, BNX2_EMAC_MODE, val);
3934
3935 val = REG_RD(bp, BNX2_RPM_CONFIG);
3936 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3937 REG_WR(bp, BNX2_RPM_CONFIG, val);
3938 break;
3939 }
3940 case PCI_D3hot: {
3941 int i;
3942 u32 val, wol_msg;
3943
3944 if (bp->wol) {
3945 u32 advertising;
3946 u8 autoneg;
3947
3948 autoneg = bp->autoneg;
3949 advertising = bp->advertising;
3950
3951 if (bp->phy_port == PORT_TP) {
3952 bp->autoneg = AUTONEG_SPEED;
3953 bp->advertising = ADVERTISED_10baseT_Half |
3954 ADVERTISED_10baseT_Full |
3955 ADVERTISED_100baseT_Half |
3956 ADVERTISED_100baseT_Full |
3957 ADVERTISED_Autoneg;
3958 }
3959
3960 spin_lock_bh(&bp->phy_lock);
3961 bnx2_setup_phy(bp, bp->phy_port);
3962 spin_unlock_bh(&bp->phy_lock);
3963
3964 bp->autoneg = autoneg;
3965 bp->advertising = advertising;
3966
3967 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3968
3969 val = REG_RD(bp, BNX2_EMAC_MODE);
3970
3971 /* Enable port mode. */
3972 val &= ~BNX2_EMAC_MODE_PORT;
3973 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3974 BNX2_EMAC_MODE_ACPI_RCVD |
3975 BNX2_EMAC_MODE_MPKT;
3976 if (bp->phy_port == PORT_TP)
3977 val |= BNX2_EMAC_MODE_PORT_MII;
3978 else {
3979 val |= BNX2_EMAC_MODE_PORT_GMII;
3980 if (bp->line_speed == SPEED_2500)
3981 val |= BNX2_EMAC_MODE_25G_MODE;
3982 }
3983
3984 REG_WR(bp, BNX2_EMAC_MODE, val);
3985
3986 /* receive all multicast */
3987 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3988 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3989 0xffffffff);
3990 }
3991 REG_WR(bp, BNX2_EMAC_RX_MODE,
3992 BNX2_EMAC_RX_MODE_SORT_MODE);
3993
3994 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3995 BNX2_RPM_SORT_USER0_MC_EN;
3996 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3997 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3998 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3999 BNX2_RPM_SORT_USER0_ENA);
4000
4001 /* Need to enable EMAC and RPM for WOL. */
4002 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4003 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
4004 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
4005 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
4006
4007 val = REG_RD(bp, BNX2_RPM_CONFIG);
4008 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4009 REG_WR(bp, BNX2_RPM_CONFIG, val);
4010
4011 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4012 }
4013 else {
4014 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4015 }
4016
4017 if (!(bp->flags & BNX2_FLAG_NO_WOL))
4018 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
4019 1, 0);
4020
4021 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4022 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4023 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4024
4025 if (bp->wol)
4026 pmcsr |= 3;
4027 }
4028 else {
4029 pmcsr |= 3;
4030 }
4031 if (bp->wol) {
4032 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4033 }
4034 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4035 pmcsr);
4036
4037 /* No more memory access after this point until
4038 * device is brought back to D0.
4039 */
4040 udelay(50);
4041 break;
4042 }
4043 default:
4044 return -EINVAL;
4045 }
4046 return 0;
4047 }
4048
4049 static int
4050 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4051 {
4052 u32 val;
4053 int j;
4054
4055 /* Request access to the flash interface. */
4056 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4057 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4058 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4059 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4060 break;
4061
4062 udelay(5);
4063 }
4064
4065 if (j >= NVRAM_TIMEOUT_COUNT)
4066 return -EBUSY;
4067
4068 return 0;
4069 }
4070
4071 static int
4072 bnx2_release_nvram_lock(struct bnx2 *bp)
4073 {
4074 int j;
4075 u32 val;
4076
4077 /* Relinquish nvram interface. */
4078 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4079
4080 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4081 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4082 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4083 break;
4084
4085 udelay(5);
4086 }
4087
4088 if (j >= NVRAM_TIMEOUT_COUNT)
4089 return -EBUSY;
4090
4091 return 0;
4092 }
4093
4094
4095 static int
4096 bnx2_enable_nvram_write(struct bnx2 *bp)
4097 {
4098 u32 val;
4099
4100 val = REG_RD(bp, BNX2_MISC_CFG);
4101 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4102
4103 if (bp->flash_info->flags & BNX2_NV_WREN) {
4104 int j;
4105
4106 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4107 REG_WR(bp, BNX2_NVM_COMMAND,
4108 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4109
4110 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4111 udelay(5);
4112
4113 val = REG_RD(bp, BNX2_NVM_COMMAND);
4114 if (val & BNX2_NVM_COMMAND_DONE)
4115 break;
4116 }
4117
4118 if (j >= NVRAM_TIMEOUT_COUNT)
4119 return -EBUSY;
4120 }
4121 return 0;
4122 }
4123
4124 static void
4125 bnx2_disable_nvram_write(struct bnx2 *bp)
4126 {
4127 u32 val;
4128
4129 val = REG_RD(bp, BNX2_MISC_CFG);
4130 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4131 }
4132
4133
4134 static void
4135 bnx2_enable_nvram_access(struct bnx2 *bp)
4136 {
4137 u32 val;
4138
4139 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4140 /* Enable both bits, even on read. */
4141 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4142 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4143 }
4144
4145 static void
4146 bnx2_disable_nvram_access(struct bnx2 *bp)
4147 {
4148 u32 val;
4149
4150 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4151 /* Disable both bits, even after read. */
4152 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4153 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4154 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4155 }
4156
4157 static int
4158 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4159 {
4160 u32 cmd;
4161 int j;
4162
4163 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4164 /* Buffered flash, no erase needed */
4165 return 0;
4166
4167 /* Build an erase command */
4168 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4169 BNX2_NVM_COMMAND_DOIT;
4170
4171 /* Need to clear DONE bit separately. */
4172 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4173
4174 /* Address of the NVRAM to read from. */
4175 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4176
4177 /* Issue an erase command. */
4178 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4179
4180 /* Wait for completion. */
4181 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4182 u32 val;
4183
4184 udelay(5);
4185
4186 val = REG_RD(bp, BNX2_NVM_COMMAND);
4187 if (val & BNX2_NVM_COMMAND_DONE)
4188 break;
4189 }
4190
4191 if (j >= NVRAM_TIMEOUT_COUNT)
4192 return -EBUSY;
4193
4194 return 0;
4195 }
4196
4197 static int
4198 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4199 {
4200 u32 cmd;
4201 int j;
4202
4203 /* Build the command word. */
4204 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4205
4206 /* Calculate an offset of a buffered flash, not needed for 5709. */
4207 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4208 offset = ((offset / bp->flash_info->page_size) <<
4209 bp->flash_info->page_bits) +
4210 (offset % bp->flash_info->page_size);
4211 }
4212
4213 /* Need to clear DONE bit separately. */
4214 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4215
4216 /* Address of the NVRAM to read from. */
4217 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4218
4219 /* Issue a read command. */
4220 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4221
4222 /* Wait for completion. */
4223 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4224 u32 val;
4225
4226 udelay(5);
4227
4228 val = REG_RD(bp, BNX2_NVM_COMMAND);
4229 if (val & BNX2_NVM_COMMAND_DONE) {
4230 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4231 memcpy(ret_val, &v, 4);
4232 break;
4233 }
4234 }
4235 if (j >= NVRAM_TIMEOUT_COUNT)
4236 return -EBUSY;
4237
4238 return 0;
4239 }
4240
4241
4242 static int
4243 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4244 {
4245 u32 cmd;
4246 __be32 val32;
4247 int j;
4248
4249 /* Build the command word. */
4250 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4251
4252 /* Calculate an offset of a buffered flash, not needed for 5709. */
4253 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4254 offset = ((offset / bp->flash_info->page_size) <<
4255 bp->flash_info->page_bits) +
4256 (offset % bp->flash_info->page_size);
4257 }
4258
4259 /* Need to clear DONE bit separately. */
4260 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4261
4262 memcpy(&val32, val, 4);
4263
4264 /* Write the data. */
4265 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4266
4267 /* Address of the NVRAM to write to. */
4268 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4269
4270 /* Issue the write command. */
4271 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4272
4273 /* Wait for completion. */
4274 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4275 udelay(5);
4276
4277 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4278 break;
4279 }
4280 if (j >= NVRAM_TIMEOUT_COUNT)
4281 return -EBUSY;
4282
4283 return 0;
4284 }
4285
4286 static int
4287 bnx2_init_nvram(struct bnx2 *bp)
4288 {
4289 u32 val;
4290 int j, entry_count, rc = 0;
4291 const struct flash_spec *flash;
4292
4293 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4294 bp->flash_info = &flash_5709;
4295 goto get_flash_size;
4296 }
4297
4298 /* Determine the selected interface. */
4299 val = REG_RD(bp, BNX2_NVM_CFG1);
4300
4301 entry_count = ARRAY_SIZE(flash_table);
4302
4303 if (val & 0x40000000) {
4304
4305 /* Flash interface has been reconfigured */
4306 for (j = 0, flash = &flash_table[0]; j < entry_count;
4307 j++, flash++) {
4308 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4309 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4310 bp->flash_info = flash;
4311 break;
4312 }
4313 }
4314 }
4315 else {
4316 u32 mask;
4317 /* Not yet been reconfigured */
4318
4319 if (val & (1 << 23))
4320 mask = FLASH_BACKUP_STRAP_MASK;
4321 else
4322 mask = FLASH_STRAP_MASK;
4323
4324 for (j = 0, flash = &flash_table[0]; j < entry_count;
4325 j++, flash++) {
4326
4327 if ((val & mask) == (flash->strapping & mask)) {
4328 bp->flash_info = flash;
4329
4330 /* Request access to the flash interface. */
4331 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4332 return rc;
4333
4334 /* Enable access to flash interface */
4335 bnx2_enable_nvram_access(bp);
4336
4337 /* Reconfigure the flash interface */
4338 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4339 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4340 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4341 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4342
4343 /* Disable access to flash interface */
4344 bnx2_disable_nvram_access(bp);
4345 bnx2_release_nvram_lock(bp);
4346
4347 break;
4348 }
4349 }
4350 } /* if (val & 0x40000000) */
4351
4352 if (j == entry_count) {
4353 bp->flash_info = NULL;
4354 pr_alert("Unknown flash/EEPROM type\n");
4355 return -ENODEV;
4356 }
4357
4358 get_flash_size:
4359 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4360 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4361 if (val)
4362 bp->flash_size = val;
4363 else
4364 bp->flash_size = bp->flash_info->total_size;
4365
4366 return rc;
4367 }
4368
4369 static int
4370 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4371 int buf_size)
4372 {
4373 int rc = 0;
4374 u32 cmd_flags, offset32, len32, extra;
4375
4376 if (buf_size == 0)
4377 return 0;
4378
4379 /* Request access to the flash interface. */
4380 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4381 return rc;
4382
4383 /* Enable access to flash interface */
4384 bnx2_enable_nvram_access(bp);
4385
4386 len32 = buf_size;
4387 offset32 = offset;
4388 extra = 0;
4389
4390 cmd_flags = 0;
4391
4392 if (offset32 & 3) {
4393 u8 buf[4];
4394 u32 pre_len;
4395
4396 offset32 &= ~3;
4397 pre_len = 4 - (offset & 3);
4398
4399 if (pre_len >= len32) {
4400 pre_len = len32;
4401 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4402 BNX2_NVM_COMMAND_LAST;
4403 }
4404 else {
4405 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4406 }
4407
4408 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4409
4410 if (rc)
4411 return rc;
4412
4413 memcpy(ret_buf, buf + (offset & 3), pre_len);
4414
4415 offset32 += 4;
4416 ret_buf += pre_len;
4417 len32 -= pre_len;
4418 }
4419 if (len32 & 3) {
4420 extra = 4 - (len32 & 3);
4421 len32 = (len32 + 4) & ~3;
4422 }
4423
4424 if (len32 == 4) {
4425 u8 buf[4];
4426
4427 if (cmd_flags)
4428 cmd_flags = BNX2_NVM_COMMAND_LAST;
4429 else
4430 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4431 BNX2_NVM_COMMAND_LAST;
4432
4433 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4434
4435 memcpy(ret_buf, buf, 4 - extra);
4436 }
4437 else if (len32 > 0) {
4438 u8 buf[4];
4439
4440 /* Read the first word. */
4441 if (cmd_flags)
4442 cmd_flags = 0;
4443 else
4444 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4445
4446 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4447
4448 /* Advance to the next dword. */
4449 offset32 += 4;
4450 ret_buf += 4;
4451 len32 -= 4;
4452
4453 while (len32 > 4 && rc == 0) {
4454 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4455
4456 /* Advance to the next dword. */
4457 offset32 += 4;
4458 ret_buf += 4;
4459 len32 -= 4;
4460 }
4461
4462 if (rc)
4463 return rc;
4464
4465 cmd_flags = BNX2_NVM_COMMAND_LAST;
4466 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4467
4468 memcpy(ret_buf, buf, 4 - extra);
4469 }
4470
4471 /* Disable access to flash interface */
4472 bnx2_disable_nvram_access(bp);
4473
4474 bnx2_release_nvram_lock(bp);
4475
4476 return rc;
4477 }
4478
4479 static int
4480 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4481 int buf_size)
4482 {
4483 u32 written, offset32, len32;
4484 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4485 int rc = 0;
4486 int align_start, align_end;
4487
4488 buf = data_buf;
4489 offset32 = offset;
4490 len32 = buf_size;
4491 align_start = align_end = 0;
4492
4493 if ((align_start = (offset32 & 3))) {
4494 offset32 &= ~3;
4495 len32 += align_start;
4496 if (len32 < 4)
4497 len32 = 4;
4498 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4499 return rc;
4500 }
4501
4502 if (len32 & 3) {
4503 align_end = 4 - (len32 & 3);
4504 len32 += align_end;
4505 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4506 return rc;
4507 }
4508
4509 if (align_start || align_end) {
4510 align_buf = kmalloc(len32, GFP_KERNEL);
4511 if (align_buf == NULL)
4512 return -ENOMEM;
4513 if (align_start) {
4514 memcpy(align_buf, start, 4);
4515 }
4516 if (align_end) {
4517 memcpy(align_buf + len32 - 4, end, 4);
4518 }
4519 memcpy(align_buf + align_start, data_buf, buf_size);
4520 buf = align_buf;
4521 }
4522
4523 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4524 flash_buffer = kmalloc(264, GFP_KERNEL);
4525 if (flash_buffer == NULL) {
4526 rc = -ENOMEM;
4527 goto nvram_write_end;
4528 }
4529 }
4530
4531 written = 0;
4532 while ((written < len32) && (rc == 0)) {
4533 u32 page_start, page_end, data_start, data_end;
4534 u32 addr, cmd_flags;
4535 int i;
4536
4537 /* Find the page_start addr */
4538 page_start = offset32 + written;
4539 page_start -= (page_start % bp->flash_info->page_size);
4540 /* Find the page_end addr */
4541 page_end = page_start + bp->flash_info->page_size;
4542 /* Find the data_start addr */
4543 data_start = (written == 0) ? offset32 : page_start;
4544 /* Find the data_end addr */
4545 data_end = (page_end > offset32 + len32) ?
4546 (offset32 + len32) : page_end;
4547
4548 /* Request access to the flash interface. */
4549 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4550 goto nvram_write_end;
4551
4552 /* Enable access to flash interface */
4553 bnx2_enable_nvram_access(bp);
4554
4555 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4556 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4557 int j;
4558
4559 /* Read the whole page into the buffer
4560 * (non-buffer flash only) */
4561 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4562 if (j == (bp->flash_info->page_size - 4)) {
4563 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4564 }
4565 rc = bnx2_nvram_read_dword(bp,
4566 page_start + j,
4567 &flash_buffer[j],
4568 cmd_flags);
4569
4570 if (rc)
4571 goto nvram_write_end;
4572
4573 cmd_flags = 0;
4574 }
4575 }
4576
4577 /* Enable writes to flash interface (unlock write-protect) */
4578 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4579 goto nvram_write_end;
4580
4581 /* Loop to write back the buffer data from page_start to
4582 * data_start */
4583 i = 0;
4584 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4585 /* Erase the page */
4586 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4587 goto nvram_write_end;
4588
4589 /* Re-enable the write again for the actual write */
4590 bnx2_enable_nvram_write(bp);
4591
4592 for (addr = page_start; addr < data_start;
4593 addr += 4, i += 4) {
4594
4595 rc = bnx2_nvram_write_dword(bp, addr,
4596 &flash_buffer[i], cmd_flags);
4597
4598 if (rc != 0)
4599 goto nvram_write_end;
4600
4601 cmd_flags = 0;
4602 }
4603 }
4604
4605 /* Loop to write the new data from data_start to data_end */
4606 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4607 if ((addr == page_end - 4) ||
4608 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4609 (addr == data_end - 4))) {
4610
4611 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4612 }
4613 rc = bnx2_nvram_write_dword(bp, addr, buf,
4614 cmd_flags);
4615
4616 if (rc != 0)
4617 goto nvram_write_end;
4618
4619 cmd_flags = 0;
4620 buf += 4;
4621 }
4622
4623 /* Loop to write back the buffer data from data_end
4624 * to page_end */
4625 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4626 for (addr = data_end; addr < page_end;
4627 addr += 4, i += 4) {
4628
4629 if (addr == page_end-4) {
4630 cmd_flags = BNX2_NVM_COMMAND_LAST;
4631 }
4632 rc = bnx2_nvram_write_dword(bp, addr,
4633 &flash_buffer[i], cmd_flags);
4634
4635 if (rc != 0)
4636 goto nvram_write_end;
4637
4638 cmd_flags = 0;
4639 }
4640 }
4641
4642 /* Disable writes to flash interface (lock write-protect) */
4643 bnx2_disable_nvram_write(bp);
4644
4645 /* Disable access to flash interface */
4646 bnx2_disable_nvram_access(bp);
4647 bnx2_release_nvram_lock(bp);
4648
4649 /* Increment written */
4650 written += data_end - data_start;
4651 }
4652
4653 nvram_write_end:
4654 kfree(flash_buffer);
4655 kfree(align_buf);
4656 return rc;
4657 }
4658
4659 static void
4660 bnx2_init_fw_cap(struct bnx2 *bp)
4661 {
4662 u32 val, sig = 0;
4663
4664 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4665 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4666
4667 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4668 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4669
4670 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4671 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4672 return;
4673
4674 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4675 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4676 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4677 }
4678
4679 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4680 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4681 u32 link;
4682
4683 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4684
4685 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4686 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4687 bp->phy_port = PORT_FIBRE;
4688 else
4689 bp->phy_port = PORT_TP;
4690
4691 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4692 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4693 }
4694
4695 if (netif_running(bp->dev) && sig)
4696 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4697 }
4698
4699 static void
4700 bnx2_setup_msix_tbl(struct bnx2 *bp)
4701 {
4702 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4703
4704 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4705 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4706 }
4707
4708 static int
4709 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4710 {
4711 u32 val;
4712 int i, rc = 0;
4713 u8 old_port;
4714
4715 /* Wait for the current PCI transaction to complete before
4716 * issuing a reset. */
4717 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4718 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
4719 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4720 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4721 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4722 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4723 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4724 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4725 udelay(5);
4726 } else { /* 5709 */
4727 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4728 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4729 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4730 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4731
4732 for (i = 0; i < 100; i++) {
4733 msleep(1);
4734 val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4735 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4736 break;
4737 }
4738 }
4739
4740 /* Wait for the firmware to tell us it is ok to issue a reset. */
4741 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4742
4743 /* Deposit a driver reset signature so the firmware knows that
4744 * this is a soft reset. */
4745 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4746 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4747
4748 /* Do a dummy read to force the chip to complete all current transaction
4749 * before we issue a reset. */
4750 val = REG_RD(bp, BNX2_MISC_ID);
4751
4752 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4753 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4754 REG_RD(bp, BNX2_MISC_COMMAND);
4755 udelay(5);
4756
4757 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4758 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4759
4760 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4761
4762 } else {
4763 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4764 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4765 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4766
4767 /* Chip reset. */
4768 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4769
4770 /* Reading back any register after chip reset will hang the
4771 * bus on 5706 A0 and A1. The msleep below provides plenty
4772 * of margin for write posting.
4773 */
4774 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4775 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4776 msleep(20);
4777
4778 /* Reset takes approximate 30 usec */
4779 for (i = 0; i < 10; i++) {
4780 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4781 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4782 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4783 break;
4784 udelay(10);
4785 }
4786
4787 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4788 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4789 pr_err("Chip reset did not complete\n");
4790 return -EBUSY;
4791 }
4792 }
4793
4794 /* Make sure byte swapping is properly configured. */
4795 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4796 if (val != 0x01020304) {
4797 pr_err("Chip not in correct endian mode\n");
4798 return -ENODEV;
4799 }
4800
4801 /* Wait for the firmware to finish its initialization. */
4802 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4803 if (rc)
4804 return rc;
4805
4806 spin_lock_bh(&bp->phy_lock);
4807 old_port = bp->phy_port;
4808 bnx2_init_fw_cap(bp);
4809 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4810 old_port != bp->phy_port)
4811 bnx2_set_default_remote_link(bp);
4812 spin_unlock_bh(&bp->phy_lock);
4813
4814 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4815 /* Adjust the voltage regular to two steps lower. The default
4816 * of this register is 0x0000000e. */
4817 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4818
4819 /* Remove bad rbuf memory from the free pool. */
4820 rc = bnx2_alloc_bad_rbuf(bp);
4821 }
4822
4823 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4824 bnx2_setup_msix_tbl(bp);
4825 /* Prevent MSIX table reads and write from timing out */
4826 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4827 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4828 }
4829
4830 return rc;
4831 }
4832
4833 static int
4834 bnx2_init_chip(struct bnx2 *bp)
4835 {
4836 u32 val, mtu;
4837 int rc, i;
4838
4839 /* Make sure the interrupt is not active. */
4840 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4841
4842 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4843 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4844 #ifdef __BIG_ENDIAN
4845 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4846 #endif
4847 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4848 DMA_READ_CHANS << 12 |
4849 DMA_WRITE_CHANS << 16;
4850
4851 val |= (0x2 << 20) | (1 << 11);
4852
4853 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4854 val |= (1 << 23);
4855
4856 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4857 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4858 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4859
4860 REG_WR(bp, BNX2_DMA_CONFIG, val);
4861
4862 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4863 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4864 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4865 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4866 }
4867
4868 if (bp->flags & BNX2_FLAG_PCIX) {
4869 u16 val16;
4870
4871 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4872 &val16);
4873 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4874 val16 & ~PCI_X_CMD_ERO);
4875 }
4876
4877 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4878 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4879 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4880 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4881
4882 /* Initialize context mapping and zero out the quick contexts. The
4883 * context block must have already been enabled. */
4884 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4885 rc = bnx2_init_5709_context(bp);
4886 if (rc)
4887 return rc;
4888 } else
4889 bnx2_init_context(bp);
4890
4891 if ((rc = bnx2_init_cpus(bp)) != 0)
4892 return rc;
4893
4894 bnx2_init_nvram(bp);
4895
4896 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4897
4898 val = REG_RD(bp, BNX2_MQ_CONFIG);
4899 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4900 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4901 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4902 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4903 if (CHIP_REV(bp) == CHIP_REV_Ax)
4904 val |= BNX2_MQ_CONFIG_HALT_DIS;
4905 }
4906
4907 REG_WR(bp, BNX2_MQ_CONFIG, val);
4908
4909 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4910 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4911 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4912
4913 val = (BCM_PAGE_BITS - 8) << 24;
4914 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4915
4916 /* Configure page size. */
4917 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4918 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4919 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4920 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4921
4922 val = bp->mac_addr[0] +
4923 (bp->mac_addr[1] << 8) +
4924 (bp->mac_addr[2] << 16) +
4925 bp->mac_addr[3] +
4926 (bp->mac_addr[4] << 8) +
4927 (bp->mac_addr[5] << 16);
4928 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4929
4930 /* Program the MTU. Also include 4 bytes for CRC32. */
4931 mtu = bp->dev->mtu;
4932 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4933 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4934 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4935 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4936
4937 if (mtu < 1500)
4938 mtu = 1500;
4939
4940 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4941 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4942 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4943
4944 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4945 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4946 bp->bnx2_napi[i].last_status_idx = 0;
4947
4948 bp->idle_chk_status_idx = 0xffff;
4949
4950 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4951
4952 /* Set up how to generate a link change interrupt. */
4953 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4954
4955 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4956 (u64) bp->status_blk_mapping & 0xffffffff);
4957 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4958
4959 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4960 (u64) bp->stats_blk_mapping & 0xffffffff);
4961 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4962 (u64) bp->stats_blk_mapping >> 32);
4963
4964 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4965 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4966
4967 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4968 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4969
4970 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4971 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4972
4973 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4974
4975 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4976
4977 REG_WR(bp, BNX2_HC_COM_TICKS,
4978 (bp->com_ticks_int << 16) | bp->com_ticks);
4979
4980 REG_WR(bp, BNX2_HC_CMD_TICKS,
4981 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4982
4983 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4984 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4985 else
4986 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4987 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4988
4989 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4990 val = BNX2_HC_CONFIG_COLLECT_STATS;
4991 else {
4992 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4993 BNX2_HC_CONFIG_COLLECT_STATS;
4994 }
4995
4996 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4997 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4998 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4999
5000 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
5001 }
5002
5003 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
5004 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5005
5006 REG_WR(bp, BNX2_HC_CONFIG, val);
5007
5008 if (bp->rx_ticks < 25)
5009 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5010 else
5011 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5012
5013 for (i = 1; i < bp->irq_nvecs; i++) {
5014 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5015 BNX2_HC_SB_CONFIG_1;
5016
5017 REG_WR(bp, base,
5018 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5019 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
5020 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5021
5022 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
5023 (bp->tx_quick_cons_trip_int << 16) |
5024 bp->tx_quick_cons_trip);
5025
5026 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
5027 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5028
5029 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5030 (bp->rx_quick_cons_trip_int << 16) |
5031 bp->rx_quick_cons_trip);
5032
5033 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5034 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5035 }
5036
5037 /* Clear internal stats counters. */
5038 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5039
5040 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
5041
5042 /* Initialize the receive filter. */
5043 bnx2_set_rx_mode(bp->dev);
5044
5045 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5046 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5047 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5048 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5049 }
5050 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
5051 1, 0);
5052
5053 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5054 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5055
5056 udelay(20);
5057
5058 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5059
5060 return rc;
5061 }
5062
5063 static void
5064 bnx2_clear_ring_states(struct bnx2 *bp)
5065 {
5066 struct bnx2_napi *bnapi;
5067 struct bnx2_tx_ring_info *txr;
5068 struct bnx2_rx_ring_info *rxr;
5069 int i;
5070
5071 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5072 bnapi = &bp->bnx2_napi[i];
5073 txr = &bnapi->tx_ring;
5074 rxr = &bnapi->rx_ring;
5075
5076 txr->tx_cons = 0;
5077 txr->hw_tx_cons = 0;
5078 rxr->rx_prod_bseq = 0;
5079 rxr->rx_prod = 0;
5080 rxr->rx_cons = 0;
5081 rxr->rx_pg_prod = 0;
5082 rxr->rx_pg_cons = 0;
5083 }
5084 }
5085
5086 static void
5087 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5088 {
5089 u32 val, offset0, offset1, offset2, offset3;
5090 u32 cid_addr = GET_CID_ADDR(cid);
5091
5092 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5093 offset0 = BNX2_L2CTX_TYPE_XI;
5094 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5095 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5096 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5097 } else {
5098 offset0 = BNX2_L2CTX_TYPE;
5099 offset1 = BNX2_L2CTX_CMD_TYPE;
5100 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5101 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5102 }
5103 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5104 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5105
5106 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5107 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5108
5109 val = (u64) txr->tx_desc_mapping >> 32;
5110 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5111
5112 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5113 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5114 }
5115
5116 static void
5117 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5118 {
5119 struct tx_bd *txbd;
5120 u32 cid = TX_CID;
5121 struct bnx2_napi *bnapi;
5122 struct bnx2_tx_ring_info *txr;
5123
5124 bnapi = &bp->bnx2_napi[ring_num];
5125 txr = &bnapi->tx_ring;
5126
5127 if (ring_num == 0)
5128 cid = TX_CID;
5129 else
5130 cid = TX_TSS_CID + ring_num - 1;
5131
5132 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5133
5134 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5135
5136 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5137 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5138
5139 txr->tx_prod = 0;
5140 txr->tx_prod_bseq = 0;
5141
5142 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5143 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5144
5145 bnx2_init_tx_context(bp, cid, txr);
5146 }
5147
5148 static void
5149 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5150 int num_rings)
5151 {
5152 int i;
5153 struct rx_bd *rxbd;
5154
5155 for (i = 0; i < num_rings; i++) {
5156 int j;
5157
5158 rxbd = &rx_ring[i][0];
5159 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5160 rxbd->rx_bd_len = buf_size;
5161 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5162 }
5163 if (i == (num_rings - 1))
5164 j = 0;
5165 else
5166 j = i + 1;
5167 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5168 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5169 }
5170 }
5171
5172 static void
5173 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5174 {
5175 int i;
5176 u16 prod, ring_prod;
5177 u32 cid, rx_cid_addr, val;
5178 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5179 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5180
5181 if (ring_num == 0)
5182 cid = RX_CID;
5183 else
5184 cid = RX_RSS_CID + ring_num - 1;
5185
5186 rx_cid_addr = GET_CID_ADDR(cid);
5187
5188 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5189 bp->rx_buf_use_size, bp->rx_max_ring);
5190
5191 bnx2_init_rx_context(bp, cid);
5192
5193 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5194 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5195 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5196 }
5197
5198 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5199 if (bp->rx_pg_ring_size) {
5200 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5201 rxr->rx_pg_desc_mapping,
5202 PAGE_SIZE, bp->rx_max_pg_ring);
5203 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5204 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5205 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5206 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5207
5208 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5209 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5210
5211 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5212 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5213
5214 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5215 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5216 }
5217
5218 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5219 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5220
5221 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5222 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5223
5224 ring_prod = prod = rxr->rx_pg_prod;
5225 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5226 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5227 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5228 ring_num, i, bp->rx_pg_ring_size);
5229 break;
5230 }
5231 prod = NEXT_RX_BD(prod);
5232 ring_prod = RX_PG_RING_IDX(prod);
5233 }
5234 rxr->rx_pg_prod = prod;
5235
5236 ring_prod = prod = rxr->rx_prod;
5237 for (i = 0; i < bp->rx_ring_size; i++) {
5238 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5239 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5240 ring_num, i, bp->rx_ring_size);
5241 break;
5242 }
5243 prod = NEXT_RX_BD(prod);
5244 ring_prod = RX_RING_IDX(prod);
5245 }
5246 rxr->rx_prod = prod;
5247
5248 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5249 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5250 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5251
5252 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5253 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5254
5255 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5256 }
5257
5258 static void
5259 bnx2_init_all_rings(struct bnx2 *bp)
5260 {
5261 int i;
5262 u32 val;
5263
5264 bnx2_clear_ring_states(bp);
5265
5266 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5267 for (i = 0; i < bp->num_tx_rings; i++)
5268 bnx2_init_tx_ring(bp, i);
5269
5270 if (bp->num_tx_rings > 1)
5271 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5272 (TX_TSS_CID << 7));
5273
5274 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5275 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5276
5277 for (i = 0; i < bp->num_rx_rings; i++)
5278 bnx2_init_rx_ring(bp, i);
5279
5280 if (bp->num_rx_rings > 1) {
5281 u32 tbl_32 = 0;
5282
5283 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5284 int shift = (i % 8) << 2;
5285
5286 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5287 if ((i % 8) == 7) {
5288 REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5289 REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5290 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5291 BNX2_RLUP_RSS_COMMAND_WRITE |
5292 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5293 tbl_32 = 0;
5294 }
5295 }
5296
5297 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5298 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5299
5300 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5301
5302 }
5303 }
5304
5305 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5306 {
5307 u32 max, num_rings = 1;
5308
5309 while (ring_size > MAX_RX_DESC_CNT) {
5310 ring_size -= MAX_RX_DESC_CNT;
5311 num_rings++;
5312 }
5313 /* round to next power of 2 */
5314 max = max_size;
5315 while ((max & num_rings) == 0)
5316 max >>= 1;
5317
5318 if (num_rings != max)
5319 max <<= 1;
5320
5321 return max;
5322 }
5323
5324 static void
5325 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5326 {
5327 u32 rx_size, rx_space, jumbo_size;
5328
5329 /* 8 for CRC and VLAN */
5330 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5331
5332 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5333 sizeof(struct skb_shared_info);
5334
5335 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5336 bp->rx_pg_ring_size = 0;
5337 bp->rx_max_pg_ring = 0;
5338 bp->rx_max_pg_ring_idx = 0;
5339 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5340 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5341
5342 jumbo_size = size * pages;
5343 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5344 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5345
5346 bp->rx_pg_ring_size = jumbo_size;
5347 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5348 MAX_RX_PG_RINGS);
5349 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5350 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5351 bp->rx_copy_thresh = 0;
5352 }
5353
5354 bp->rx_buf_use_size = rx_size;
5355 /* hw alignment */
5356 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5357 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5358 bp->rx_ring_size = size;
5359 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5360 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5361 }
5362
5363 static void
5364 bnx2_free_tx_skbs(struct bnx2 *bp)
5365 {
5366 int i;
5367
5368 for (i = 0; i < bp->num_tx_rings; i++) {
5369 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5370 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5371 int j;
5372
5373 if (txr->tx_buf_ring == NULL)
5374 continue;
5375
5376 for (j = 0; j < TX_DESC_CNT; ) {
5377 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5378 struct sk_buff *skb = tx_buf->skb;
5379 int k, last;
5380
5381 if (skb == NULL) {
5382 j++;
5383 continue;
5384 }
5385
5386 dma_unmap_single(&bp->pdev->dev,
5387 dma_unmap_addr(tx_buf, mapping),
5388 skb_headlen(skb),
5389 PCI_DMA_TODEVICE);
5390
5391 tx_buf->skb = NULL;
5392
5393 last = tx_buf->nr_frags;
5394 j++;
5395 for (k = 0; k < last; k++, j++) {
5396 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5397 dma_unmap_page(&bp->pdev->dev,
5398 dma_unmap_addr(tx_buf, mapping),
5399 skb_shinfo(skb)->frags[k].size,
5400 PCI_DMA_TODEVICE);
5401 }
5402 dev_kfree_skb(skb);
5403 }
5404 }
5405 }
5406
5407 static void
5408 bnx2_free_rx_skbs(struct bnx2 *bp)
5409 {
5410 int i;
5411
5412 for (i = 0; i < bp->num_rx_rings; i++) {
5413 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5414 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5415 int j;
5416
5417 if (rxr->rx_buf_ring == NULL)
5418 return;
5419
5420 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5421 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5422 struct sk_buff *skb = rx_buf->skb;
5423
5424 if (skb == NULL)
5425 continue;
5426
5427 dma_unmap_single(&bp->pdev->dev,
5428 dma_unmap_addr(rx_buf, mapping),
5429 bp->rx_buf_use_size,
5430 PCI_DMA_FROMDEVICE);
5431
5432 rx_buf->skb = NULL;
5433
5434 dev_kfree_skb(skb);
5435 }
5436 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5437 bnx2_free_rx_page(bp, rxr, j);
5438 }
5439 }
5440
5441 static void
5442 bnx2_free_skbs(struct bnx2 *bp)
5443 {
5444 bnx2_free_tx_skbs(bp);
5445 bnx2_free_rx_skbs(bp);
5446 }
5447
5448 static int
5449 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5450 {
5451 int rc;
5452
5453 rc = bnx2_reset_chip(bp, reset_code);
5454 bnx2_free_skbs(bp);
5455 if (rc)
5456 return rc;
5457
5458 if ((rc = bnx2_init_chip(bp)) != 0)
5459 return rc;
5460
5461 bnx2_init_all_rings(bp);
5462 return 0;
5463 }
5464
5465 static int
5466 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5467 {
5468 int rc;
5469
5470 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5471 return rc;
5472
5473 spin_lock_bh(&bp->phy_lock);
5474 bnx2_init_phy(bp, reset_phy);
5475 bnx2_set_link(bp);
5476 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5477 bnx2_remote_phy_event(bp);
5478 spin_unlock_bh(&bp->phy_lock);
5479 return 0;
5480 }
5481
5482 static int
5483 bnx2_shutdown_chip(struct bnx2 *bp)
5484 {
5485 u32 reset_code;
5486
5487 if (bp->flags & BNX2_FLAG_NO_WOL)
5488 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5489 else if (bp->wol)
5490 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5491 else
5492 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5493
5494 return bnx2_reset_chip(bp, reset_code);
5495 }
5496
5497 static int
5498 bnx2_test_registers(struct bnx2 *bp)
5499 {
5500 int ret;
5501 int i, is_5709;
5502 static const struct {
5503 u16 offset;
5504 u16 flags;
5505 #define BNX2_FL_NOT_5709 1
5506 u32 rw_mask;
5507 u32 ro_mask;
5508 } reg_tbl[] = {
5509 { 0x006c, 0, 0x00000000, 0x0000003f },
5510 { 0x0090, 0, 0xffffffff, 0x00000000 },
5511 { 0x0094, 0, 0x00000000, 0x00000000 },
5512
5513 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5514 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5515 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5516 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5517 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5518 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5519 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5520 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5521 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5522
5523 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5524 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5525 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5526 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5527 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5528 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5529
5530 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5531 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5532 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5533
5534 { 0x1000, 0, 0x00000000, 0x00000001 },
5535 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5536
5537 { 0x1408, 0, 0x01c00800, 0x00000000 },
5538 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5539 { 0x14a8, 0, 0x00000000, 0x000001ff },
5540 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5541 { 0x14b0, 0, 0x00000002, 0x00000001 },
5542 { 0x14b8, 0, 0x00000000, 0x00000000 },
5543 { 0x14c0, 0, 0x00000000, 0x00000009 },
5544 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5545 { 0x14cc, 0, 0x00000000, 0x00000001 },
5546 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5547
5548 { 0x1800, 0, 0x00000000, 0x00000001 },
5549 { 0x1804, 0, 0x00000000, 0x00000003 },
5550
5551 { 0x2800, 0, 0x00000000, 0x00000001 },
5552 { 0x2804, 0, 0x00000000, 0x00003f01 },
5553 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5554 { 0x2810, 0, 0xffff0000, 0x00000000 },
5555 { 0x2814, 0, 0xffff0000, 0x00000000 },
5556 { 0x2818, 0, 0xffff0000, 0x00000000 },
5557 { 0x281c, 0, 0xffff0000, 0x00000000 },
5558 { 0x2834, 0, 0xffffffff, 0x00000000 },
5559 { 0x2840, 0, 0x00000000, 0xffffffff },
5560 { 0x2844, 0, 0x00000000, 0xffffffff },
5561 { 0x2848, 0, 0xffffffff, 0x00000000 },
5562 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5563
5564 { 0x2c00, 0, 0x00000000, 0x00000011 },
5565 { 0x2c04, 0, 0x00000000, 0x00030007 },
5566
5567 { 0x3c00, 0, 0x00000000, 0x00000001 },
5568 { 0x3c04, 0, 0x00000000, 0x00070000 },
5569 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5570 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5571 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5572 { 0x3c14, 0, 0x00000000, 0xffffffff },
5573 { 0x3c18, 0, 0x00000000, 0xffffffff },
5574 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5575 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5576
5577 { 0x5004, 0, 0x00000000, 0x0000007f },
5578 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5579
5580 { 0x5c00, 0, 0x00000000, 0x00000001 },
5581 { 0x5c04, 0, 0x00000000, 0x0003000f },
5582 { 0x5c08, 0, 0x00000003, 0x00000000 },
5583 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5584 { 0x5c10, 0, 0x00000000, 0xffffffff },
5585 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5586 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5587 { 0x5c88, 0, 0x00000000, 0x00077373 },
5588 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5589
5590 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5591 { 0x680c, 0, 0xffffffff, 0x00000000 },
5592 { 0x6810, 0, 0xffffffff, 0x00000000 },
5593 { 0x6814, 0, 0xffffffff, 0x00000000 },
5594 { 0x6818, 0, 0xffffffff, 0x00000000 },
5595 { 0x681c, 0, 0xffffffff, 0x00000000 },
5596 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5597 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5598 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5599 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5600 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5601 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5602 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5603 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5604 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5605 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5606 { 0x684c, 0, 0xffffffff, 0x00000000 },
5607 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5608 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5609 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5610 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5611 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5612 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5613
5614 { 0xffff, 0, 0x00000000, 0x00000000 },
5615 };
5616
5617 ret = 0;
5618 is_5709 = 0;
5619 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5620 is_5709 = 1;
5621
5622 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5623 u32 offset, rw_mask, ro_mask, save_val, val;
5624 u16 flags = reg_tbl[i].flags;
5625
5626 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5627 continue;
5628
5629 offset = (u32) reg_tbl[i].offset;
5630 rw_mask = reg_tbl[i].rw_mask;
5631 ro_mask = reg_tbl[i].ro_mask;
5632
5633 save_val = readl(bp->regview + offset);
5634
5635 writel(0, bp->regview + offset);
5636
5637 val = readl(bp->regview + offset);
5638 if ((val & rw_mask) != 0) {
5639 goto reg_test_err;
5640 }
5641
5642 if ((val & ro_mask) != (save_val & ro_mask)) {
5643 goto reg_test_err;
5644 }
5645
5646 writel(0xffffffff, bp->regview + offset);
5647
5648 val = readl(bp->regview + offset);
5649 if ((val & rw_mask) != rw_mask) {
5650 goto reg_test_err;
5651 }
5652
5653 if ((val & ro_mask) != (save_val & ro_mask)) {
5654 goto reg_test_err;
5655 }
5656
5657 writel(save_val, bp->regview + offset);
5658 continue;
5659
5660 reg_test_err:
5661 writel(save_val, bp->regview + offset);
5662 ret = -ENODEV;
5663 break;
5664 }
5665 return ret;
5666 }
5667
5668 static int
5669 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5670 {
5671 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5672 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5673 int i;
5674
5675 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5676 u32 offset;
5677
5678 for (offset = 0; offset < size; offset += 4) {
5679
5680 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5681
5682 if (bnx2_reg_rd_ind(bp, start + offset) !=
5683 test_pattern[i]) {
5684 return -ENODEV;
5685 }
5686 }
5687 }
5688 return 0;
5689 }
5690
5691 static int
5692 bnx2_test_memory(struct bnx2 *bp)
5693 {
5694 int ret = 0;
5695 int i;
5696 static struct mem_entry {
5697 u32 offset;
5698 u32 len;
5699 } mem_tbl_5706[] = {
5700 { 0x60000, 0x4000 },
5701 { 0xa0000, 0x3000 },
5702 { 0xe0000, 0x4000 },
5703 { 0x120000, 0x4000 },
5704 { 0x1a0000, 0x4000 },
5705 { 0x160000, 0x4000 },
5706 { 0xffffffff, 0 },
5707 },
5708 mem_tbl_5709[] = {
5709 { 0x60000, 0x4000 },
5710 { 0xa0000, 0x3000 },
5711 { 0xe0000, 0x4000 },
5712 { 0x120000, 0x4000 },
5713 { 0x1a0000, 0x4000 },
5714 { 0xffffffff, 0 },
5715 };
5716 struct mem_entry *mem_tbl;
5717
5718 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5719 mem_tbl = mem_tbl_5709;
5720 else
5721 mem_tbl = mem_tbl_5706;
5722
5723 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5724 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5725 mem_tbl[i].len)) != 0) {
5726 return ret;
5727 }
5728 }
5729
5730 return ret;
5731 }
5732
5733 #define BNX2_MAC_LOOPBACK 0
5734 #define BNX2_PHY_LOOPBACK 1
5735
5736 static int
5737 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5738 {
5739 unsigned int pkt_size, num_pkts, i;
5740 struct sk_buff *skb, *rx_skb;
5741 unsigned char *packet;
5742 u16 rx_start_idx, rx_idx;
5743 dma_addr_t map;
5744 struct tx_bd *txbd;
5745 struct sw_bd *rx_buf;
5746 struct l2_fhdr *rx_hdr;
5747 int ret = -ENODEV;
5748 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5749 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5750 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5751
5752 tx_napi = bnapi;
5753
5754 txr = &tx_napi->tx_ring;
5755 rxr = &bnapi->rx_ring;
5756 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5757 bp->loopback = MAC_LOOPBACK;
5758 bnx2_set_mac_loopback(bp);
5759 }
5760 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5761 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5762 return 0;
5763
5764 bp->loopback = PHY_LOOPBACK;
5765 bnx2_set_phy_loopback(bp);
5766 }
5767 else
5768 return -EINVAL;
5769
5770 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5771 skb = netdev_alloc_skb(bp->dev, pkt_size);
5772 if (!skb)
5773 return -ENOMEM;
5774 packet = skb_put(skb, pkt_size);
5775 memcpy(packet, bp->dev->dev_addr, 6);
5776 memset(packet + 6, 0x0, 8);
5777 for (i = 14; i < pkt_size; i++)
5778 packet[i] = (unsigned char) (i & 0xff);
5779
5780 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5781 PCI_DMA_TODEVICE);
5782 if (dma_mapping_error(&bp->pdev->dev, map)) {
5783 dev_kfree_skb(skb);
5784 return -EIO;
5785 }
5786
5787 REG_WR(bp, BNX2_HC_COMMAND,
5788 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5789
5790 REG_RD(bp, BNX2_HC_COMMAND);
5791
5792 udelay(5);
5793 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5794
5795 num_pkts = 0;
5796
5797 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5798
5799 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5800 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5801 txbd->tx_bd_mss_nbytes = pkt_size;
5802 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5803
5804 num_pkts++;
5805 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5806 txr->tx_prod_bseq += pkt_size;
5807
5808 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5809 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5810
5811 udelay(100);
5812
5813 REG_WR(bp, BNX2_HC_COMMAND,
5814 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5815
5816 REG_RD(bp, BNX2_HC_COMMAND);
5817
5818 udelay(5);
5819
5820 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
5821 dev_kfree_skb(skb);
5822
5823 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5824 goto loopback_test_done;
5825
5826 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5827 if (rx_idx != rx_start_idx + num_pkts) {
5828 goto loopback_test_done;
5829 }
5830
5831 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5832 rx_skb = rx_buf->skb;
5833
5834 rx_hdr = rx_buf->desc;
5835 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5836
5837 dma_sync_single_for_cpu(&bp->pdev->dev,
5838 dma_unmap_addr(rx_buf, mapping),
5839 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5840
5841 if (rx_hdr->l2_fhdr_status &
5842 (L2_FHDR_ERRORS_BAD_CRC |
5843 L2_FHDR_ERRORS_PHY_DECODE |
5844 L2_FHDR_ERRORS_ALIGNMENT |
5845 L2_FHDR_ERRORS_TOO_SHORT |
5846 L2_FHDR_ERRORS_GIANT_FRAME)) {
5847
5848 goto loopback_test_done;
5849 }
5850
5851 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5852 goto loopback_test_done;
5853 }
5854
5855 for (i = 14; i < pkt_size; i++) {
5856 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5857 goto loopback_test_done;
5858 }
5859 }
5860
5861 ret = 0;
5862
5863 loopback_test_done:
5864 bp->loopback = 0;
5865 return ret;
5866 }
5867
5868 #define BNX2_MAC_LOOPBACK_FAILED 1
5869 #define BNX2_PHY_LOOPBACK_FAILED 2
5870 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5871 BNX2_PHY_LOOPBACK_FAILED)
5872
5873 static int
5874 bnx2_test_loopback(struct bnx2 *bp)
5875 {
5876 int rc = 0;
5877
5878 if (!netif_running(bp->dev))
5879 return BNX2_LOOPBACK_FAILED;
5880
5881 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5882 spin_lock_bh(&bp->phy_lock);
5883 bnx2_init_phy(bp, 1);
5884 spin_unlock_bh(&bp->phy_lock);
5885 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5886 rc |= BNX2_MAC_LOOPBACK_FAILED;
5887 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5888 rc |= BNX2_PHY_LOOPBACK_FAILED;
5889 return rc;
5890 }
5891
5892 #define NVRAM_SIZE 0x200
5893 #define CRC32_RESIDUAL 0xdebb20e3
5894
5895 static int
5896 bnx2_test_nvram(struct bnx2 *bp)
5897 {
5898 __be32 buf[NVRAM_SIZE / 4];
5899 u8 *data = (u8 *) buf;
5900 int rc = 0;
5901 u32 magic, csum;
5902
5903 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5904 goto test_nvram_done;
5905
5906 magic = be32_to_cpu(buf[0]);
5907 if (magic != 0x669955aa) {
5908 rc = -ENODEV;
5909 goto test_nvram_done;
5910 }
5911
5912 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5913 goto test_nvram_done;
5914
5915 csum = ether_crc_le(0x100, data);
5916 if (csum != CRC32_RESIDUAL) {
5917 rc = -ENODEV;
5918 goto test_nvram_done;
5919 }
5920
5921 csum = ether_crc_le(0x100, data + 0x100);
5922 if (csum != CRC32_RESIDUAL) {
5923 rc = -ENODEV;
5924 }
5925
5926 test_nvram_done:
5927 return rc;
5928 }
5929
5930 static int
5931 bnx2_test_link(struct bnx2 *bp)
5932 {
5933 u32 bmsr;
5934
5935 if (!netif_running(bp->dev))
5936 return -ENODEV;
5937
5938 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5939 if (bp->link_up)
5940 return 0;
5941 return -ENODEV;
5942 }
5943 spin_lock_bh(&bp->phy_lock);
5944 bnx2_enable_bmsr1(bp);
5945 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5946 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5947 bnx2_disable_bmsr1(bp);
5948 spin_unlock_bh(&bp->phy_lock);
5949
5950 if (bmsr & BMSR_LSTATUS) {
5951 return 0;
5952 }
5953 return -ENODEV;
5954 }
5955
5956 static int
5957 bnx2_test_intr(struct bnx2 *bp)
5958 {
5959 int i;
5960 u16 status_idx;
5961
5962 if (!netif_running(bp->dev))
5963 return -ENODEV;
5964
5965 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5966
5967 /* This register is not touched during run-time. */
5968 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5969 REG_RD(bp, BNX2_HC_COMMAND);
5970
5971 for (i = 0; i < 10; i++) {
5972 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5973 status_idx) {
5974
5975 break;
5976 }
5977
5978 msleep_interruptible(10);
5979 }
5980 if (i < 10)
5981 return 0;
5982
5983 return -ENODEV;
5984 }
5985
5986 /* Determining link for parallel detection. */
5987 static int
5988 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5989 {
5990 u32 mode_ctl, an_dbg, exp;
5991
5992 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5993 return 0;
5994
5995 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5996 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5997
5998 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5999 return 0;
6000
6001 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6002 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6003 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6004
6005 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
6006 return 0;
6007
6008 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6009 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6010 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6011
6012 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6013 return 0;
6014
6015 return 1;
6016 }
6017
6018 static void
6019 bnx2_5706_serdes_timer(struct bnx2 *bp)
6020 {
6021 int check_link = 1;
6022
6023 spin_lock(&bp->phy_lock);
6024 if (bp->serdes_an_pending) {
6025 bp->serdes_an_pending--;
6026 check_link = 0;
6027 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6028 u32 bmcr;
6029
6030 bp->current_interval = BNX2_TIMER_INTERVAL;
6031
6032 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6033
6034 if (bmcr & BMCR_ANENABLE) {
6035 if (bnx2_5706_serdes_has_link(bp)) {
6036 bmcr &= ~BMCR_ANENABLE;
6037 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6038 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6039 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
6040 }
6041 }
6042 }
6043 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
6044 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
6045 u32 phy2;
6046
6047 bnx2_write_phy(bp, 0x17, 0x0f01);
6048 bnx2_read_phy(bp, 0x15, &phy2);
6049 if (phy2 & 0x20) {
6050 u32 bmcr;
6051
6052 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6053 bmcr |= BMCR_ANENABLE;
6054 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6055
6056 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
6057 }
6058 } else
6059 bp->current_interval = BNX2_TIMER_INTERVAL;
6060
6061 if (check_link) {
6062 u32 val;
6063
6064 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6065 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6066 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6067
6068 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6069 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6070 bnx2_5706s_force_link_dn(bp, 1);
6071 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6072 } else
6073 bnx2_set_link(bp);
6074 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6075 bnx2_set_link(bp);
6076 }
6077 spin_unlock(&bp->phy_lock);
6078 }
6079
6080 static void
6081 bnx2_5708_serdes_timer(struct bnx2 *bp)
6082 {
6083 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6084 return;
6085
6086 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6087 bp->serdes_an_pending = 0;
6088 return;
6089 }
6090
6091 spin_lock(&bp->phy_lock);
6092 if (bp->serdes_an_pending)
6093 bp->serdes_an_pending--;
6094 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6095 u32 bmcr;
6096
6097 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6098 if (bmcr & BMCR_ANENABLE) {
6099 bnx2_enable_forced_2g5(bp);
6100 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6101 } else {
6102 bnx2_disable_forced_2g5(bp);
6103 bp->serdes_an_pending = 2;
6104 bp->current_interval = BNX2_TIMER_INTERVAL;
6105 }
6106
6107 } else
6108 bp->current_interval = BNX2_TIMER_INTERVAL;
6109
6110 spin_unlock(&bp->phy_lock);
6111 }
6112
6113 static void
6114 bnx2_timer(unsigned long data)
6115 {
6116 struct bnx2 *bp = (struct bnx2 *) data;
6117
6118 if (!netif_running(bp->dev))
6119 return;
6120
6121 if (atomic_read(&bp->intr_sem) != 0)
6122 goto bnx2_restart_timer;
6123
6124 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6125 BNX2_FLAG_USING_MSI)
6126 bnx2_chk_missed_msi(bp);
6127
6128 bnx2_send_heart_beat(bp);
6129
6130 bp->stats_blk->stat_FwRxDrop =
6131 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6132
6133 /* workaround occasional corrupted counters */
6134 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6135 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6136 BNX2_HC_COMMAND_STATS_NOW);
6137
6138 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6139 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6140 bnx2_5706_serdes_timer(bp);
6141 else
6142 bnx2_5708_serdes_timer(bp);
6143 }
6144
6145 bnx2_restart_timer:
6146 mod_timer(&bp->timer, jiffies + bp->current_interval);
6147 }
6148
6149 static int
6150 bnx2_request_irq(struct bnx2 *bp)
6151 {
6152 unsigned long flags;
6153 struct bnx2_irq *irq;
6154 int rc = 0, i;
6155
6156 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6157 flags = 0;
6158 else
6159 flags = IRQF_SHARED;
6160
6161 for (i = 0; i < bp->irq_nvecs; i++) {
6162 irq = &bp->irq_tbl[i];
6163 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6164 &bp->bnx2_napi[i]);
6165 if (rc)
6166 break;
6167 irq->requested = 1;
6168 }
6169 return rc;
6170 }
6171
6172 static void
6173 __bnx2_free_irq(struct bnx2 *bp)
6174 {
6175 struct bnx2_irq *irq;
6176 int i;
6177
6178 for (i = 0; i < bp->irq_nvecs; i++) {
6179 irq = &bp->irq_tbl[i];
6180 if (irq->requested)
6181 free_irq(irq->vector, &bp->bnx2_napi[i]);
6182 irq->requested = 0;
6183 }
6184 }
6185
6186 static void
6187 bnx2_free_irq(struct bnx2 *bp)
6188 {
6189
6190 __bnx2_free_irq(bp);
6191 if (bp->flags & BNX2_FLAG_USING_MSI)
6192 pci_disable_msi(bp->pdev);
6193 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6194 pci_disable_msix(bp->pdev);
6195
6196 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6197 }
6198
6199 static void
6200 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6201 {
6202 int i, total_vecs, rc;
6203 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6204 struct net_device *dev = bp->dev;
6205 const int len = sizeof(bp->irq_tbl[0].name);
6206
6207 bnx2_setup_msix_tbl(bp);
6208 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6209 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6210 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6211
6212 /* Need to flush the previous three writes to ensure MSI-X
6213 * is setup properly */
6214 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6215
6216 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6217 msix_ent[i].entry = i;
6218 msix_ent[i].vector = 0;
6219 }
6220
6221 total_vecs = msix_vecs;
6222 #ifdef BCM_CNIC
6223 total_vecs++;
6224 #endif
6225 rc = -ENOSPC;
6226 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6227 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6228 if (rc <= 0)
6229 break;
6230 if (rc > 0)
6231 total_vecs = rc;
6232 }
6233
6234 if (rc != 0)
6235 return;
6236
6237 msix_vecs = total_vecs;
6238 #ifdef BCM_CNIC
6239 msix_vecs--;
6240 #endif
6241 bp->irq_nvecs = msix_vecs;
6242 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6243 for (i = 0; i < total_vecs; i++) {
6244 bp->irq_tbl[i].vector = msix_ent[i].vector;
6245 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6246 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6247 }
6248 }
6249
6250 static int
6251 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6252 {
6253 int cpus = num_online_cpus();
6254 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6255
6256 bp->irq_tbl[0].handler = bnx2_interrupt;
6257 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6258 bp->irq_nvecs = 1;
6259 bp->irq_tbl[0].vector = bp->pdev->irq;
6260
6261 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
6262 bnx2_enable_msix(bp, msix_vecs);
6263
6264 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6265 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6266 if (pci_enable_msi(bp->pdev) == 0) {
6267 bp->flags |= BNX2_FLAG_USING_MSI;
6268 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6269 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6270 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6271 } else
6272 bp->irq_tbl[0].handler = bnx2_msi;
6273
6274 bp->irq_tbl[0].vector = bp->pdev->irq;
6275 }
6276 }
6277
6278 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6279 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
6280
6281 bp->num_rx_rings = bp->irq_nvecs;
6282 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
6283 }
6284
6285 /* Called with rtnl_lock */
6286 static int
6287 bnx2_open(struct net_device *dev)
6288 {
6289 struct bnx2 *bp = netdev_priv(dev);
6290 int rc;
6291
6292 rc = bnx2_request_firmware(bp);
6293 if (rc < 0)
6294 goto out;
6295
6296 netif_carrier_off(dev);
6297
6298 bnx2_set_power_state(bp, PCI_D0);
6299 bnx2_disable_int(bp);
6300
6301 rc = bnx2_setup_int_mode(bp, disable_msi);
6302 if (rc)
6303 goto open_err;
6304 bnx2_init_napi(bp);
6305 bnx2_napi_enable(bp);
6306 rc = bnx2_alloc_mem(bp);
6307 if (rc)
6308 goto open_err;
6309
6310 rc = bnx2_request_irq(bp);
6311 if (rc)
6312 goto open_err;
6313
6314 rc = bnx2_init_nic(bp, 1);
6315 if (rc)
6316 goto open_err;
6317
6318 mod_timer(&bp->timer, jiffies + bp->current_interval);
6319
6320 atomic_set(&bp->intr_sem, 0);
6321
6322 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6323
6324 bnx2_enable_int(bp);
6325
6326 if (bp->flags & BNX2_FLAG_USING_MSI) {
6327 /* Test MSI to make sure it is working
6328 * If MSI test fails, go back to INTx mode
6329 */
6330 if (bnx2_test_intr(bp) != 0) {
6331 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6332
6333 bnx2_disable_int(bp);
6334 bnx2_free_irq(bp);
6335
6336 bnx2_setup_int_mode(bp, 1);
6337
6338 rc = bnx2_init_nic(bp, 0);
6339
6340 if (!rc)
6341 rc = bnx2_request_irq(bp);
6342
6343 if (rc) {
6344 del_timer_sync(&bp->timer);
6345 goto open_err;
6346 }
6347 bnx2_enable_int(bp);
6348 }
6349 }
6350 if (bp->flags & BNX2_FLAG_USING_MSI)
6351 netdev_info(dev, "using MSI\n");
6352 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6353 netdev_info(dev, "using MSIX\n");
6354
6355 netif_tx_start_all_queues(dev);
6356 out:
6357 return rc;
6358
6359 open_err:
6360 bnx2_napi_disable(bp);
6361 bnx2_free_skbs(bp);
6362 bnx2_free_irq(bp);
6363 bnx2_free_mem(bp);
6364 bnx2_del_napi(bp);
6365 bnx2_release_firmware(bp);
6366 goto out;
6367 }
6368
6369 static void
6370 bnx2_reset_task(struct work_struct *work)
6371 {
6372 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6373 int rc;
6374
6375 rtnl_lock();
6376 if (!netif_running(bp->dev)) {
6377 rtnl_unlock();
6378 return;
6379 }
6380
6381 bnx2_netif_stop(bp, true);
6382
6383 rc = bnx2_init_nic(bp, 1);
6384 if (rc) {
6385 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6386 bnx2_napi_enable(bp);
6387 dev_close(bp->dev);
6388 rtnl_unlock();
6389 return;
6390 }
6391
6392 atomic_set(&bp->intr_sem, 1);
6393 bnx2_netif_start(bp, true);
6394 rtnl_unlock();
6395 }
6396
6397 static void
6398 bnx2_dump_state(struct bnx2 *bp)
6399 {
6400 struct net_device *dev = bp->dev;
6401 u32 val1, val2;
6402
6403 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6404 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6405 atomic_read(&bp->intr_sem), val1);
6406 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6407 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6408 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
6409 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6410 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6411 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6412 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6413 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6414 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6415 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6416 if (bp->flags & BNX2_FLAG_USING_MSIX)
6417 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6418 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6419 }
6420
6421 static void
6422 bnx2_tx_timeout(struct net_device *dev)
6423 {
6424 struct bnx2 *bp = netdev_priv(dev);
6425
6426 bnx2_dump_state(bp);
6427 bnx2_dump_mcp_state(bp);
6428
6429 /* This allows the netif to be shutdown gracefully before resetting */
6430 schedule_work(&bp->reset_task);
6431 }
6432
6433 /* Called with netif_tx_lock.
6434 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6435 * netif_wake_queue().
6436 */
6437 static netdev_tx_t
6438 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6439 {
6440 struct bnx2 *bp = netdev_priv(dev);
6441 dma_addr_t mapping;
6442 struct tx_bd *txbd;
6443 struct sw_tx_bd *tx_buf;
6444 u32 len, vlan_tag_flags, last_frag, mss;
6445 u16 prod, ring_prod;
6446 int i;
6447 struct bnx2_napi *bnapi;
6448 struct bnx2_tx_ring_info *txr;
6449 struct netdev_queue *txq;
6450
6451 /* Determine which tx ring we will be placed on */
6452 i = skb_get_queue_mapping(skb);
6453 bnapi = &bp->bnx2_napi[i];
6454 txr = &bnapi->tx_ring;
6455 txq = netdev_get_tx_queue(dev, i);
6456
6457 if (unlikely(bnx2_tx_avail(bp, txr) <
6458 (skb_shinfo(skb)->nr_frags + 1))) {
6459 netif_tx_stop_queue(txq);
6460 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6461
6462 return NETDEV_TX_BUSY;
6463 }
6464 len = skb_headlen(skb);
6465 prod = txr->tx_prod;
6466 ring_prod = TX_RING_IDX(prod);
6467
6468 vlan_tag_flags = 0;
6469 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6470 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6471 }
6472
6473 if (vlan_tx_tag_present(skb)) {
6474 vlan_tag_flags |=
6475 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6476 }
6477
6478 if ((mss = skb_shinfo(skb)->gso_size)) {
6479 u32 tcp_opt_len;
6480 struct iphdr *iph;
6481
6482 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6483
6484 tcp_opt_len = tcp_optlen(skb);
6485
6486 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6487 u32 tcp_off = skb_transport_offset(skb) -
6488 sizeof(struct ipv6hdr) - ETH_HLEN;
6489
6490 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6491 TX_BD_FLAGS_SW_FLAGS;
6492 if (likely(tcp_off == 0))
6493 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6494 else {
6495 tcp_off >>= 3;
6496 vlan_tag_flags |= ((tcp_off & 0x3) <<
6497 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6498 ((tcp_off & 0x10) <<
6499 TX_BD_FLAGS_TCP6_OFF4_SHL);
6500 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6501 }
6502 } else {
6503 iph = ip_hdr(skb);
6504 if (tcp_opt_len || (iph->ihl > 5)) {
6505 vlan_tag_flags |= ((iph->ihl - 5) +
6506 (tcp_opt_len >> 2)) << 8;
6507 }
6508 }
6509 } else
6510 mss = 0;
6511
6512 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6513 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
6514 dev_kfree_skb(skb);
6515 return NETDEV_TX_OK;
6516 }
6517
6518 tx_buf = &txr->tx_buf_ring[ring_prod];
6519 tx_buf->skb = skb;
6520 dma_unmap_addr_set(tx_buf, mapping, mapping);
6521
6522 txbd = &txr->tx_desc_ring[ring_prod];
6523
6524 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6525 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6526 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6527 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6528
6529 last_frag = skb_shinfo(skb)->nr_frags;
6530 tx_buf->nr_frags = last_frag;
6531 tx_buf->is_gso = skb_is_gso(skb);
6532
6533 for (i = 0; i < last_frag; i++) {
6534 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6535
6536 prod = NEXT_TX_BD(prod);
6537 ring_prod = TX_RING_IDX(prod);
6538 txbd = &txr->tx_desc_ring[ring_prod];
6539
6540 len = frag->size;
6541 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
6542 DMA_TO_DEVICE);
6543 if (dma_mapping_error(&bp->pdev->dev, mapping))
6544 goto dma_error;
6545 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6546 mapping);
6547
6548 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6549 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6550 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6551 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6552
6553 }
6554 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6555
6556 prod = NEXT_TX_BD(prod);
6557 txr->tx_prod_bseq += skb->len;
6558
6559 REG_WR16(bp, txr->tx_bidx_addr, prod);
6560 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6561
6562 mmiowb();
6563
6564 txr->tx_prod = prod;
6565
6566 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6567 netif_tx_stop_queue(txq);
6568
6569 /* netif_tx_stop_queue() must be done before checking
6570 * tx index in bnx2_tx_avail() below, because in
6571 * bnx2_tx_int(), we update tx index before checking for
6572 * netif_tx_queue_stopped().
6573 */
6574 smp_mb();
6575 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6576 netif_tx_wake_queue(txq);
6577 }
6578
6579 return NETDEV_TX_OK;
6580 dma_error:
6581 /* save value of frag that failed */
6582 last_frag = i;
6583
6584 /* start back at beginning and unmap skb */
6585 prod = txr->tx_prod;
6586 ring_prod = TX_RING_IDX(prod);
6587 tx_buf = &txr->tx_buf_ring[ring_prod];
6588 tx_buf->skb = NULL;
6589 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6590 skb_headlen(skb), PCI_DMA_TODEVICE);
6591
6592 /* unmap remaining mapped pages */
6593 for (i = 0; i < last_frag; i++) {
6594 prod = NEXT_TX_BD(prod);
6595 ring_prod = TX_RING_IDX(prod);
6596 tx_buf = &txr->tx_buf_ring[ring_prod];
6597 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6598 skb_shinfo(skb)->frags[i].size,
6599 PCI_DMA_TODEVICE);
6600 }
6601
6602 dev_kfree_skb(skb);
6603 return NETDEV_TX_OK;
6604 }
6605
6606 /* Called with rtnl_lock */
6607 static int
6608 bnx2_close(struct net_device *dev)
6609 {
6610 struct bnx2 *bp = netdev_priv(dev);
6611
6612 bnx2_disable_int_sync(bp);
6613 bnx2_napi_disable(bp);
6614 del_timer_sync(&bp->timer);
6615 bnx2_shutdown_chip(bp);
6616 bnx2_free_irq(bp);
6617 bnx2_free_skbs(bp);
6618 bnx2_free_mem(bp);
6619 bnx2_del_napi(bp);
6620 bp->link_up = 0;
6621 netif_carrier_off(bp->dev);
6622 bnx2_set_power_state(bp, PCI_D3hot);
6623 return 0;
6624 }
6625
6626 static void
6627 bnx2_save_stats(struct bnx2 *bp)
6628 {
6629 u32 *hw_stats = (u32 *) bp->stats_blk;
6630 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6631 int i;
6632
6633 /* The 1st 10 counters are 64-bit counters */
6634 for (i = 0; i < 20; i += 2) {
6635 u32 hi;
6636 u64 lo;
6637
6638 hi = temp_stats[i] + hw_stats[i];
6639 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6640 if (lo > 0xffffffff)
6641 hi++;
6642 temp_stats[i] = hi;
6643 temp_stats[i + 1] = lo & 0xffffffff;
6644 }
6645
6646 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6647 temp_stats[i] += hw_stats[i];
6648 }
6649
6650 #define GET_64BIT_NET_STATS64(ctr) \
6651 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
6652
6653 #define GET_64BIT_NET_STATS(ctr) \
6654 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6655 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6656
6657 #define GET_32BIT_NET_STATS(ctr) \
6658 (unsigned long) (bp->stats_blk->ctr + \
6659 bp->temp_stats_blk->ctr)
6660
6661 static struct rtnl_link_stats64 *
6662 bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
6663 {
6664 struct bnx2 *bp = netdev_priv(dev);
6665
6666 if (bp->stats_blk == NULL)
6667 return net_stats;
6668
6669 net_stats->rx_packets =
6670 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6671 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6672 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6673
6674 net_stats->tx_packets =
6675 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6676 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6677 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6678
6679 net_stats->rx_bytes =
6680 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6681
6682 net_stats->tx_bytes =
6683 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6684
6685 net_stats->multicast =
6686 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
6687
6688 net_stats->collisions =
6689 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6690
6691 net_stats->rx_length_errors =
6692 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6693 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6694
6695 net_stats->rx_over_errors =
6696 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6697 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6698
6699 net_stats->rx_frame_errors =
6700 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6701
6702 net_stats->rx_crc_errors =
6703 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6704
6705 net_stats->rx_errors = net_stats->rx_length_errors +
6706 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6707 net_stats->rx_crc_errors;
6708
6709 net_stats->tx_aborted_errors =
6710 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6711 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6712
6713 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6714 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6715 net_stats->tx_carrier_errors = 0;
6716 else {
6717 net_stats->tx_carrier_errors =
6718 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6719 }
6720
6721 net_stats->tx_errors =
6722 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6723 net_stats->tx_aborted_errors +
6724 net_stats->tx_carrier_errors;
6725
6726 net_stats->rx_missed_errors =
6727 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6728 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6729 GET_32BIT_NET_STATS(stat_FwRxDrop);
6730
6731 return net_stats;
6732 }
6733
6734 /* All ethtool functions called with rtnl_lock */
6735
6736 static int
6737 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6738 {
6739 struct bnx2 *bp = netdev_priv(dev);
6740 int support_serdes = 0, support_copper = 0;
6741
6742 cmd->supported = SUPPORTED_Autoneg;
6743 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6744 support_serdes = 1;
6745 support_copper = 1;
6746 } else if (bp->phy_port == PORT_FIBRE)
6747 support_serdes = 1;
6748 else
6749 support_copper = 1;
6750
6751 if (support_serdes) {
6752 cmd->supported |= SUPPORTED_1000baseT_Full |
6753 SUPPORTED_FIBRE;
6754 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6755 cmd->supported |= SUPPORTED_2500baseX_Full;
6756
6757 }
6758 if (support_copper) {
6759 cmd->supported |= SUPPORTED_10baseT_Half |
6760 SUPPORTED_10baseT_Full |
6761 SUPPORTED_100baseT_Half |
6762 SUPPORTED_100baseT_Full |
6763 SUPPORTED_1000baseT_Full |
6764 SUPPORTED_TP;
6765
6766 }
6767
6768 spin_lock_bh(&bp->phy_lock);
6769 cmd->port = bp->phy_port;
6770 cmd->advertising = bp->advertising;
6771
6772 if (bp->autoneg & AUTONEG_SPEED) {
6773 cmd->autoneg = AUTONEG_ENABLE;
6774 } else {
6775 cmd->autoneg = AUTONEG_DISABLE;
6776 }
6777
6778 if (netif_carrier_ok(dev)) {
6779 ethtool_cmd_speed_set(cmd, bp->line_speed);
6780 cmd->duplex = bp->duplex;
6781 }
6782 else {
6783 ethtool_cmd_speed_set(cmd, -1);
6784 cmd->duplex = -1;
6785 }
6786 spin_unlock_bh(&bp->phy_lock);
6787
6788 cmd->transceiver = XCVR_INTERNAL;
6789 cmd->phy_address = bp->phy_addr;
6790
6791 return 0;
6792 }
6793
6794 static int
6795 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6796 {
6797 struct bnx2 *bp = netdev_priv(dev);
6798 u8 autoneg = bp->autoneg;
6799 u8 req_duplex = bp->req_duplex;
6800 u16 req_line_speed = bp->req_line_speed;
6801 u32 advertising = bp->advertising;
6802 int err = -EINVAL;
6803
6804 spin_lock_bh(&bp->phy_lock);
6805
6806 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6807 goto err_out_unlock;
6808
6809 if (cmd->port != bp->phy_port &&
6810 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6811 goto err_out_unlock;
6812
6813 /* If device is down, we can store the settings only if the user
6814 * is setting the currently active port.
6815 */
6816 if (!netif_running(dev) && cmd->port != bp->phy_port)
6817 goto err_out_unlock;
6818
6819 if (cmd->autoneg == AUTONEG_ENABLE) {
6820 autoneg |= AUTONEG_SPEED;
6821
6822 advertising = cmd->advertising;
6823 if (cmd->port == PORT_TP) {
6824 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6825 if (!advertising)
6826 advertising = ETHTOOL_ALL_COPPER_SPEED;
6827 } else {
6828 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6829 if (!advertising)
6830 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6831 }
6832 advertising |= ADVERTISED_Autoneg;
6833 }
6834 else {
6835 u32 speed = ethtool_cmd_speed(cmd);
6836 if (cmd->port == PORT_FIBRE) {
6837 if ((speed != SPEED_1000 &&
6838 speed != SPEED_2500) ||
6839 (cmd->duplex != DUPLEX_FULL))
6840 goto err_out_unlock;
6841
6842 if (speed == SPEED_2500 &&
6843 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6844 goto err_out_unlock;
6845 } else if (speed == SPEED_1000 || speed == SPEED_2500)
6846 goto err_out_unlock;
6847
6848 autoneg &= ~AUTONEG_SPEED;
6849 req_line_speed = speed;
6850 req_duplex = cmd->duplex;
6851 advertising = 0;
6852 }
6853
6854 bp->autoneg = autoneg;
6855 bp->advertising = advertising;
6856 bp->req_line_speed = req_line_speed;
6857 bp->req_duplex = req_duplex;
6858
6859 err = 0;
6860 /* If device is down, the new settings will be picked up when it is
6861 * brought up.
6862 */
6863 if (netif_running(dev))
6864 err = bnx2_setup_phy(bp, cmd->port);
6865
6866 err_out_unlock:
6867 spin_unlock_bh(&bp->phy_lock);
6868
6869 return err;
6870 }
6871
6872 static void
6873 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6874 {
6875 struct bnx2 *bp = netdev_priv(dev);
6876
6877 strcpy(info->driver, DRV_MODULE_NAME);
6878 strcpy(info->version, DRV_MODULE_VERSION);
6879 strcpy(info->bus_info, pci_name(bp->pdev));
6880 strcpy(info->fw_version, bp->fw_version);
6881 }
6882
6883 #define BNX2_REGDUMP_LEN (32 * 1024)
6884
6885 static int
6886 bnx2_get_regs_len(struct net_device *dev)
6887 {
6888 return BNX2_REGDUMP_LEN;
6889 }
6890
6891 static void
6892 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6893 {
6894 u32 *p = _p, i, offset;
6895 u8 *orig_p = _p;
6896 struct bnx2 *bp = netdev_priv(dev);
6897 static const u32 reg_boundaries[] = {
6898 0x0000, 0x0098, 0x0400, 0x045c,
6899 0x0800, 0x0880, 0x0c00, 0x0c10,
6900 0x0c30, 0x0d08, 0x1000, 0x101c,
6901 0x1040, 0x1048, 0x1080, 0x10a4,
6902 0x1400, 0x1490, 0x1498, 0x14f0,
6903 0x1500, 0x155c, 0x1580, 0x15dc,
6904 0x1600, 0x1658, 0x1680, 0x16d8,
6905 0x1800, 0x1820, 0x1840, 0x1854,
6906 0x1880, 0x1894, 0x1900, 0x1984,
6907 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6908 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6909 0x2000, 0x2030, 0x23c0, 0x2400,
6910 0x2800, 0x2820, 0x2830, 0x2850,
6911 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6912 0x3c00, 0x3c94, 0x4000, 0x4010,
6913 0x4080, 0x4090, 0x43c0, 0x4458,
6914 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6915 0x4fc0, 0x5010, 0x53c0, 0x5444,
6916 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6917 0x5fc0, 0x6000, 0x6400, 0x6428,
6918 0x6800, 0x6848, 0x684c, 0x6860,
6919 0x6888, 0x6910, 0x8000
6920 };
6921
6922 regs->version = 0;
6923
6924 memset(p, 0, BNX2_REGDUMP_LEN);
6925
6926 if (!netif_running(bp->dev))
6927 return;
6928
6929 i = 0;
6930 offset = reg_boundaries[0];
6931 p += offset;
6932 while (offset < BNX2_REGDUMP_LEN) {
6933 *p++ = REG_RD(bp, offset);
6934 offset += 4;
6935 if (offset == reg_boundaries[i + 1]) {
6936 offset = reg_boundaries[i + 2];
6937 p = (u32 *) (orig_p + offset);
6938 i += 2;
6939 }
6940 }
6941 }
6942
6943 static void
6944 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6945 {
6946 struct bnx2 *bp = netdev_priv(dev);
6947
6948 if (bp->flags & BNX2_FLAG_NO_WOL) {
6949 wol->supported = 0;
6950 wol->wolopts = 0;
6951 }
6952 else {
6953 wol->supported = WAKE_MAGIC;
6954 if (bp->wol)
6955 wol->wolopts = WAKE_MAGIC;
6956 else
6957 wol->wolopts = 0;
6958 }
6959 memset(&wol->sopass, 0, sizeof(wol->sopass));
6960 }
6961
6962 static int
6963 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6964 {
6965 struct bnx2 *bp = netdev_priv(dev);
6966
6967 if (wol->wolopts & ~WAKE_MAGIC)
6968 return -EINVAL;
6969
6970 if (wol->wolopts & WAKE_MAGIC) {
6971 if (bp->flags & BNX2_FLAG_NO_WOL)
6972 return -EINVAL;
6973
6974 bp->wol = 1;
6975 }
6976 else {
6977 bp->wol = 0;
6978 }
6979 return 0;
6980 }
6981
6982 static int
6983 bnx2_nway_reset(struct net_device *dev)
6984 {
6985 struct bnx2 *bp = netdev_priv(dev);
6986 u32 bmcr;
6987
6988 if (!netif_running(dev))
6989 return -EAGAIN;
6990
6991 if (!(bp->autoneg & AUTONEG_SPEED)) {
6992 return -EINVAL;
6993 }
6994
6995 spin_lock_bh(&bp->phy_lock);
6996
6997 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6998 int rc;
6999
7000 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7001 spin_unlock_bh(&bp->phy_lock);
7002 return rc;
7003 }
7004
7005 /* Force a link down visible on the other side */
7006 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7007 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
7008 spin_unlock_bh(&bp->phy_lock);
7009
7010 msleep(20);
7011
7012 spin_lock_bh(&bp->phy_lock);
7013
7014 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
7015 bp->serdes_an_pending = 1;
7016 mod_timer(&bp->timer, jiffies + bp->current_interval);
7017 }
7018
7019 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
7020 bmcr &= ~BMCR_LOOPBACK;
7021 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
7022
7023 spin_unlock_bh(&bp->phy_lock);
7024
7025 return 0;
7026 }
7027
7028 static u32
7029 bnx2_get_link(struct net_device *dev)
7030 {
7031 struct bnx2 *bp = netdev_priv(dev);
7032
7033 return bp->link_up;
7034 }
7035
7036 static int
7037 bnx2_get_eeprom_len(struct net_device *dev)
7038 {
7039 struct bnx2 *bp = netdev_priv(dev);
7040
7041 if (bp->flash_info == NULL)
7042 return 0;
7043
7044 return (int) bp->flash_size;
7045 }
7046
7047 static int
7048 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7049 u8 *eebuf)
7050 {
7051 struct bnx2 *bp = netdev_priv(dev);
7052 int rc;
7053
7054 if (!netif_running(dev))
7055 return -EAGAIN;
7056
7057 /* parameters already validated in ethtool_get_eeprom */
7058
7059 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7060
7061 return rc;
7062 }
7063
7064 static int
7065 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7066 u8 *eebuf)
7067 {
7068 struct bnx2 *bp = netdev_priv(dev);
7069 int rc;
7070
7071 if (!netif_running(dev))
7072 return -EAGAIN;
7073
7074 /* parameters already validated in ethtool_set_eeprom */
7075
7076 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7077
7078 return rc;
7079 }
7080
7081 static int
7082 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7083 {
7084 struct bnx2 *bp = netdev_priv(dev);
7085
7086 memset(coal, 0, sizeof(struct ethtool_coalesce));
7087
7088 coal->rx_coalesce_usecs = bp->rx_ticks;
7089 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7090 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7091 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7092
7093 coal->tx_coalesce_usecs = bp->tx_ticks;
7094 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7095 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7096 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7097
7098 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7099
7100 return 0;
7101 }
7102
7103 static int
7104 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7105 {
7106 struct bnx2 *bp = netdev_priv(dev);
7107
7108 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7109 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7110
7111 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7112 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7113
7114 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7115 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7116
7117 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7118 if (bp->rx_quick_cons_trip_int > 0xff)
7119 bp->rx_quick_cons_trip_int = 0xff;
7120
7121 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7122 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7123
7124 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7125 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7126
7127 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7128 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7129
7130 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7131 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7132 0xff;
7133
7134 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7135 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7136 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7137 bp->stats_ticks = USEC_PER_SEC;
7138 }
7139 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7140 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7141 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7142
7143 if (netif_running(bp->dev)) {
7144 bnx2_netif_stop(bp, true);
7145 bnx2_init_nic(bp, 0);
7146 bnx2_netif_start(bp, true);
7147 }
7148
7149 return 0;
7150 }
7151
7152 static void
7153 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7154 {
7155 struct bnx2 *bp = netdev_priv(dev);
7156
7157 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7158 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7159
7160 ering->rx_pending = bp->rx_ring_size;
7161 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7162
7163 ering->tx_max_pending = MAX_TX_DESC_CNT;
7164 ering->tx_pending = bp->tx_ring_size;
7165 }
7166
7167 static int
7168 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7169 {
7170 if (netif_running(bp->dev)) {
7171 /* Reset will erase chipset stats; save them */
7172 bnx2_save_stats(bp);
7173
7174 bnx2_netif_stop(bp, true);
7175 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7176 __bnx2_free_irq(bp);
7177 bnx2_free_skbs(bp);
7178 bnx2_free_mem(bp);
7179 }
7180
7181 bnx2_set_rx_ring_size(bp, rx);
7182 bp->tx_ring_size = tx;
7183
7184 if (netif_running(bp->dev)) {
7185 int rc;
7186
7187 rc = bnx2_alloc_mem(bp);
7188 if (!rc)
7189 rc = bnx2_request_irq(bp);
7190
7191 if (!rc)
7192 rc = bnx2_init_nic(bp, 0);
7193
7194 if (rc) {
7195 bnx2_napi_enable(bp);
7196 dev_close(bp->dev);
7197 return rc;
7198 }
7199 #ifdef BCM_CNIC
7200 mutex_lock(&bp->cnic_lock);
7201 /* Let cnic know about the new status block. */
7202 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7203 bnx2_setup_cnic_irq_info(bp);
7204 mutex_unlock(&bp->cnic_lock);
7205 #endif
7206 bnx2_netif_start(bp, true);
7207 }
7208 return 0;
7209 }
7210
7211 static int
7212 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7213 {
7214 struct bnx2 *bp = netdev_priv(dev);
7215 int rc;
7216
7217 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7218 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7219 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7220
7221 return -EINVAL;
7222 }
7223 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7224 return rc;
7225 }
7226
7227 static void
7228 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7229 {
7230 struct bnx2 *bp = netdev_priv(dev);
7231
7232 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7233 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7234 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7235 }
7236
7237 static int
7238 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7239 {
7240 struct bnx2 *bp = netdev_priv(dev);
7241
7242 bp->req_flow_ctrl = 0;
7243 if (epause->rx_pause)
7244 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7245 if (epause->tx_pause)
7246 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7247
7248 if (epause->autoneg) {
7249 bp->autoneg |= AUTONEG_FLOW_CTRL;
7250 }
7251 else {
7252 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7253 }
7254
7255 if (netif_running(dev)) {
7256 spin_lock_bh(&bp->phy_lock);
7257 bnx2_setup_phy(bp, bp->phy_port);
7258 spin_unlock_bh(&bp->phy_lock);
7259 }
7260
7261 return 0;
7262 }
7263
7264 static struct {
7265 char string[ETH_GSTRING_LEN];
7266 } bnx2_stats_str_arr[] = {
7267 { "rx_bytes" },
7268 { "rx_error_bytes" },
7269 { "tx_bytes" },
7270 { "tx_error_bytes" },
7271 { "rx_ucast_packets" },
7272 { "rx_mcast_packets" },
7273 { "rx_bcast_packets" },
7274 { "tx_ucast_packets" },
7275 { "tx_mcast_packets" },
7276 { "tx_bcast_packets" },
7277 { "tx_mac_errors" },
7278 { "tx_carrier_errors" },
7279 { "rx_crc_errors" },
7280 { "rx_align_errors" },
7281 { "tx_single_collisions" },
7282 { "tx_multi_collisions" },
7283 { "tx_deferred" },
7284 { "tx_excess_collisions" },
7285 { "tx_late_collisions" },
7286 { "tx_total_collisions" },
7287 { "rx_fragments" },
7288 { "rx_jabbers" },
7289 { "rx_undersize_packets" },
7290 { "rx_oversize_packets" },
7291 { "rx_64_byte_packets" },
7292 { "rx_65_to_127_byte_packets" },
7293 { "rx_128_to_255_byte_packets" },
7294 { "rx_256_to_511_byte_packets" },
7295 { "rx_512_to_1023_byte_packets" },
7296 { "rx_1024_to_1522_byte_packets" },
7297 { "rx_1523_to_9022_byte_packets" },
7298 { "tx_64_byte_packets" },
7299 { "tx_65_to_127_byte_packets" },
7300 { "tx_128_to_255_byte_packets" },
7301 { "tx_256_to_511_byte_packets" },
7302 { "tx_512_to_1023_byte_packets" },
7303 { "tx_1024_to_1522_byte_packets" },
7304 { "tx_1523_to_9022_byte_packets" },
7305 { "rx_xon_frames" },
7306 { "rx_xoff_frames" },
7307 { "tx_xon_frames" },
7308 { "tx_xoff_frames" },
7309 { "rx_mac_ctrl_frames" },
7310 { "rx_filtered_packets" },
7311 { "rx_ftq_discards" },
7312 { "rx_discards" },
7313 { "rx_fw_discards" },
7314 };
7315
7316 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7317 sizeof(bnx2_stats_str_arr[0]))
7318
7319 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7320
7321 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7322 STATS_OFFSET32(stat_IfHCInOctets_hi),
7323 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7324 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7325 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7326 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7327 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7328 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7329 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7330 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7331 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7332 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7333 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7334 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7335 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7336 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7337 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7338 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7339 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7340 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7341 STATS_OFFSET32(stat_EtherStatsCollisions),
7342 STATS_OFFSET32(stat_EtherStatsFragments),
7343 STATS_OFFSET32(stat_EtherStatsJabbers),
7344 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7345 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7346 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7347 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7348 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7349 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7350 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7351 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7352 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7353 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7354 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7355 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7356 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7357 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7358 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7359 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7360 STATS_OFFSET32(stat_XonPauseFramesReceived),
7361 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7362 STATS_OFFSET32(stat_OutXonSent),
7363 STATS_OFFSET32(stat_OutXoffSent),
7364 STATS_OFFSET32(stat_MacControlFramesReceived),
7365 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7366 STATS_OFFSET32(stat_IfInFTQDiscards),
7367 STATS_OFFSET32(stat_IfInMBUFDiscards),
7368 STATS_OFFSET32(stat_FwRxDrop),
7369 };
7370
7371 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7372 * skipped because of errata.
7373 */
7374 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7375 8,0,8,8,8,8,8,8,8,8,
7376 4,0,4,4,4,4,4,4,4,4,
7377 4,4,4,4,4,4,4,4,4,4,
7378 4,4,4,4,4,4,4,4,4,4,
7379 4,4,4,4,4,4,4,
7380 };
7381
7382 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7383 8,0,8,8,8,8,8,8,8,8,
7384 4,4,4,4,4,4,4,4,4,4,
7385 4,4,4,4,4,4,4,4,4,4,
7386 4,4,4,4,4,4,4,4,4,4,
7387 4,4,4,4,4,4,4,
7388 };
7389
7390 #define BNX2_NUM_TESTS 6
7391
7392 static struct {
7393 char string[ETH_GSTRING_LEN];
7394 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7395 { "register_test (offline)" },
7396 { "memory_test (offline)" },
7397 { "loopback_test (offline)" },
7398 { "nvram_test (online)" },
7399 { "interrupt_test (online)" },
7400 { "link_test (online)" },
7401 };
7402
7403 static int
7404 bnx2_get_sset_count(struct net_device *dev, int sset)
7405 {
7406 switch (sset) {
7407 case ETH_SS_TEST:
7408 return BNX2_NUM_TESTS;
7409 case ETH_SS_STATS:
7410 return BNX2_NUM_STATS;
7411 default:
7412 return -EOPNOTSUPP;
7413 }
7414 }
7415
7416 static void
7417 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7418 {
7419 struct bnx2 *bp = netdev_priv(dev);
7420
7421 bnx2_set_power_state(bp, PCI_D0);
7422
7423 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7424 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7425 int i;
7426
7427 bnx2_netif_stop(bp, true);
7428 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7429 bnx2_free_skbs(bp);
7430
7431 if (bnx2_test_registers(bp) != 0) {
7432 buf[0] = 1;
7433 etest->flags |= ETH_TEST_FL_FAILED;
7434 }
7435 if (bnx2_test_memory(bp) != 0) {
7436 buf[1] = 1;
7437 etest->flags |= ETH_TEST_FL_FAILED;
7438 }
7439 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7440 etest->flags |= ETH_TEST_FL_FAILED;
7441
7442 if (!netif_running(bp->dev))
7443 bnx2_shutdown_chip(bp);
7444 else {
7445 bnx2_init_nic(bp, 1);
7446 bnx2_netif_start(bp, true);
7447 }
7448
7449 /* wait for link up */
7450 for (i = 0; i < 7; i++) {
7451 if (bp->link_up)
7452 break;
7453 msleep_interruptible(1000);
7454 }
7455 }
7456
7457 if (bnx2_test_nvram(bp) != 0) {
7458 buf[3] = 1;
7459 etest->flags |= ETH_TEST_FL_FAILED;
7460 }
7461 if (bnx2_test_intr(bp) != 0) {
7462 buf[4] = 1;
7463 etest->flags |= ETH_TEST_FL_FAILED;
7464 }
7465
7466 if (bnx2_test_link(bp) != 0) {
7467 buf[5] = 1;
7468 etest->flags |= ETH_TEST_FL_FAILED;
7469
7470 }
7471 if (!netif_running(bp->dev))
7472 bnx2_set_power_state(bp, PCI_D3hot);
7473 }
7474
7475 static void
7476 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7477 {
7478 switch (stringset) {
7479 case ETH_SS_STATS:
7480 memcpy(buf, bnx2_stats_str_arr,
7481 sizeof(bnx2_stats_str_arr));
7482 break;
7483 case ETH_SS_TEST:
7484 memcpy(buf, bnx2_tests_str_arr,
7485 sizeof(bnx2_tests_str_arr));
7486 break;
7487 }
7488 }
7489
7490 static void
7491 bnx2_get_ethtool_stats(struct net_device *dev,
7492 struct ethtool_stats *stats, u64 *buf)
7493 {
7494 struct bnx2 *bp = netdev_priv(dev);
7495 int i;
7496 u32 *hw_stats = (u32 *) bp->stats_blk;
7497 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7498 u8 *stats_len_arr = NULL;
7499
7500 if (hw_stats == NULL) {
7501 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7502 return;
7503 }
7504
7505 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7506 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7507 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7508 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7509 stats_len_arr = bnx2_5706_stats_len_arr;
7510 else
7511 stats_len_arr = bnx2_5708_stats_len_arr;
7512
7513 for (i = 0; i < BNX2_NUM_STATS; i++) {
7514 unsigned long offset;
7515
7516 if (stats_len_arr[i] == 0) {
7517 /* skip this counter */
7518 buf[i] = 0;
7519 continue;
7520 }
7521
7522 offset = bnx2_stats_offset_arr[i];
7523 if (stats_len_arr[i] == 4) {
7524 /* 4-byte counter */
7525 buf[i] = (u64) *(hw_stats + offset) +
7526 *(temp_stats + offset);
7527 continue;
7528 }
7529 /* 8-byte counter */
7530 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7531 *(hw_stats + offset + 1) +
7532 (((u64) *(temp_stats + offset)) << 32) +
7533 *(temp_stats + offset + 1);
7534 }
7535 }
7536
7537 static int
7538 bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
7539 {
7540 struct bnx2 *bp = netdev_priv(dev);
7541
7542 switch (state) {
7543 case ETHTOOL_ID_ACTIVE:
7544 bnx2_set_power_state(bp, PCI_D0);
7545
7546 bp->leds_save = REG_RD(bp, BNX2_MISC_CFG);
7547 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7548 return 1; /* cycle on/off once per second */
7549
7550 case ETHTOOL_ID_ON:
7551 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7552 BNX2_EMAC_LED_1000MB_OVERRIDE |
7553 BNX2_EMAC_LED_100MB_OVERRIDE |
7554 BNX2_EMAC_LED_10MB_OVERRIDE |
7555 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7556 BNX2_EMAC_LED_TRAFFIC);
7557 break;
7558
7559 case ETHTOOL_ID_OFF:
7560 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7561 break;
7562
7563 case ETHTOOL_ID_INACTIVE:
7564 REG_WR(bp, BNX2_EMAC_LED, 0);
7565 REG_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7566
7567 if (!netif_running(dev))
7568 bnx2_set_power_state(bp, PCI_D3hot);
7569 break;
7570 }
7571
7572 return 0;
7573 }
7574
7575 static u32
7576 bnx2_fix_features(struct net_device *dev, u32 features)
7577 {
7578 struct bnx2 *bp = netdev_priv(dev);
7579
7580 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
7581 features |= NETIF_F_HW_VLAN_RX;
7582
7583 return features;
7584 }
7585
7586 static int
7587 bnx2_set_features(struct net_device *dev, u32 features)
7588 {
7589 struct bnx2 *bp = netdev_priv(dev);
7590
7591 /* TSO with VLAN tag won't work with current firmware */
7592 if (features & NETIF_F_HW_VLAN_TX)
7593 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7594 else
7595 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7596
7597 if ((!!(features & NETIF_F_HW_VLAN_RX) !=
7598 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7599 netif_running(dev)) {
7600 bnx2_netif_stop(bp, false);
7601 dev->features = features;
7602 bnx2_set_rx_mode(dev);
7603 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7604 bnx2_netif_start(bp, false);
7605 return 1;
7606 }
7607
7608 return 0;
7609 }
7610
7611 static const struct ethtool_ops bnx2_ethtool_ops = {
7612 .get_settings = bnx2_get_settings,
7613 .set_settings = bnx2_set_settings,
7614 .get_drvinfo = bnx2_get_drvinfo,
7615 .get_regs_len = bnx2_get_regs_len,
7616 .get_regs = bnx2_get_regs,
7617 .get_wol = bnx2_get_wol,
7618 .set_wol = bnx2_set_wol,
7619 .nway_reset = bnx2_nway_reset,
7620 .get_link = bnx2_get_link,
7621 .get_eeprom_len = bnx2_get_eeprom_len,
7622 .get_eeprom = bnx2_get_eeprom,
7623 .set_eeprom = bnx2_set_eeprom,
7624 .get_coalesce = bnx2_get_coalesce,
7625 .set_coalesce = bnx2_set_coalesce,
7626 .get_ringparam = bnx2_get_ringparam,
7627 .set_ringparam = bnx2_set_ringparam,
7628 .get_pauseparam = bnx2_get_pauseparam,
7629 .set_pauseparam = bnx2_set_pauseparam,
7630 .self_test = bnx2_self_test,
7631 .get_strings = bnx2_get_strings,
7632 .set_phys_id = bnx2_set_phys_id,
7633 .get_ethtool_stats = bnx2_get_ethtool_stats,
7634 .get_sset_count = bnx2_get_sset_count,
7635 };
7636
7637 /* Called with rtnl_lock */
7638 static int
7639 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7640 {
7641 struct mii_ioctl_data *data = if_mii(ifr);
7642 struct bnx2 *bp = netdev_priv(dev);
7643 int err;
7644
7645 switch(cmd) {
7646 case SIOCGMIIPHY:
7647 data->phy_id = bp->phy_addr;
7648
7649 /* fallthru */
7650 case SIOCGMIIREG: {
7651 u32 mii_regval;
7652
7653 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7654 return -EOPNOTSUPP;
7655
7656 if (!netif_running(dev))
7657 return -EAGAIN;
7658
7659 spin_lock_bh(&bp->phy_lock);
7660 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7661 spin_unlock_bh(&bp->phy_lock);
7662
7663 data->val_out = mii_regval;
7664
7665 return err;
7666 }
7667
7668 case SIOCSMIIREG:
7669 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7670 return -EOPNOTSUPP;
7671
7672 if (!netif_running(dev))
7673 return -EAGAIN;
7674
7675 spin_lock_bh(&bp->phy_lock);
7676 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7677 spin_unlock_bh(&bp->phy_lock);
7678
7679 return err;
7680
7681 default:
7682 /* do nothing */
7683 break;
7684 }
7685 return -EOPNOTSUPP;
7686 }
7687
7688 /* Called with rtnl_lock */
7689 static int
7690 bnx2_change_mac_addr(struct net_device *dev, void *p)
7691 {
7692 struct sockaddr *addr = p;
7693 struct bnx2 *bp = netdev_priv(dev);
7694
7695 if (!is_valid_ether_addr(addr->sa_data))
7696 return -EINVAL;
7697
7698 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7699 if (netif_running(dev))
7700 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7701
7702 return 0;
7703 }
7704
7705 /* Called with rtnl_lock */
7706 static int
7707 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7708 {
7709 struct bnx2 *bp = netdev_priv(dev);
7710
7711 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7712 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7713 return -EINVAL;
7714
7715 dev->mtu = new_mtu;
7716 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size);
7717 }
7718
7719 #ifdef CONFIG_NET_POLL_CONTROLLER
7720 static void
7721 poll_bnx2(struct net_device *dev)
7722 {
7723 struct bnx2 *bp = netdev_priv(dev);
7724 int i;
7725
7726 for (i = 0; i < bp->irq_nvecs; i++) {
7727 struct bnx2_irq *irq = &bp->irq_tbl[i];
7728
7729 disable_irq(irq->vector);
7730 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7731 enable_irq(irq->vector);
7732 }
7733 }
7734 #endif
7735
7736 static void __devinit
7737 bnx2_get_5709_media(struct bnx2 *bp)
7738 {
7739 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7740 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7741 u32 strap;
7742
7743 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7744 return;
7745 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7746 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7747 return;
7748 }
7749
7750 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7751 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7752 else
7753 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7754
7755 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7756 switch (strap) {
7757 case 0x4:
7758 case 0x5:
7759 case 0x6:
7760 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7761 return;
7762 }
7763 } else {
7764 switch (strap) {
7765 case 0x1:
7766 case 0x2:
7767 case 0x4:
7768 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7769 return;
7770 }
7771 }
7772 }
7773
7774 static void __devinit
7775 bnx2_get_pci_speed(struct bnx2 *bp)
7776 {
7777 u32 reg;
7778
7779 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7780 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7781 u32 clkreg;
7782
7783 bp->flags |= BNX2_FLAG_PCIX;
7784
7785 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7786
7787 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7788 switch (clkreg) {
7789 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7790 bp->bus_speed_mhz = 133;
7791 break;
7792
7793 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7794 bp->bus_speed_mhz = 100;
7795 break;
7796
7797 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7798 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7799 bp->bus_speed_mhz = 66;
7800 break;
7801
7802 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7803 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7804 bp->bus_speed_mhz = 50;
7805 break;
7806
7807 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7808 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7809 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7810 bp->bus_speed_mhz = 33;
7811 break;
7812 }
7813 }
7814 else {
7815 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7816 bp->bus_speed_mhz = 66;
7817 else
7818 bp->bus_speed_mhz = 33;
7819 }
7820
7821 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7822 bp->flags |= BNX2_FLAG_PCI_32BIT;
7823
7824 }
7825
7826 static void __devinit
7827 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7828 {
7829 int rc, i, j;
7830 u8 *data;
7831 unsigned int block_end, rosize, len;
7832
7833 #define BNX2_VPD_NVRAM_OFFSET 0x300
7834 #define BNX2_VPD_LEN 128
7835 #define BNX2_MAX_VER_SLEN 30
7836
7837 data = kmalloc(256, GFP_KERNEL);
7838 if (!data)
7839 return;
7840
7841 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7842 BNX2_VPD_LEN);
7843 if (rc)
7844 goto vpd_done;
7845
7846 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7847 data[i] = data[i + BNX2_VPD_LEN + 3];
7848 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7849 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7850 data[i + 3] = data[i + BNX2_VPD_LEN];
7851 }
7852
7853 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7854 if (i < 0)
7855 goto vpd_done;
7856
7857 rosize = pci_vpd_lrdt_size(&data[i]);
7858 i += PCI_VPD_LRDT_TAG_SIZE;
7859 block_end = i + rosize;
7860
7861 if (block_end > BNX2_VPD_LEN)
7862 goto vpd_done;
7863
7864 j = pci_vpd_find_info_keyword(data, i, rosize,
7865 PCI_VPD_RO_KEYWORD_MFR_ID);
7866 if (j < 0)
7867 goto vpd_done;
7868
7869 len = pci_vpd_info_field_size(&data[j]);
7870
7871 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7872 if (j + len > block_end || len != 4 ||
7873 memcmp(&data[j], "1028", 4))
7874 goto vpd_done;
7875
7876 j = pci_vpd_find_info_keyword(data, i, rosize,
7877 PCI_VPD_RO_KEYWORD_VENDOR0);
7878 if (j < 0)
7879 goto vpd_done;
7880
7881 len = pci_vpd_info_field_size(&data[j]);
7882
7883 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7884 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7885 goto vpd_done;
7886
7887 memcpy(bp->fw_version, &data[j], len);
7888 bp->fw_version[len] = ' ';
7889
7890 vpd_done:
7891 kfree(data);
7892 }
7893
7894 static int __devinit
7895 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7896 {
7897 struct bnx2 *bp;
7898 unsigned long mem_len;
7899 int rc, i, j;
7900 u32 reg;
7901 u64 dma_mask, persist_dma_mask;
7902 int err;
7903
7904 SET_NETDEV_DEV(dev, &pdev->dev);
7905 bp = netdev_priv(dev);
7906
7907 bp->flags = 0;
7908 bp->phy_flags = 0;
7909
7910 bp->temp_stats_blk =
7911 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7912
7913 if (bp->temp_stats_blk == NULL) {
7914 rc = -ENOMEM;
7915 goto err_out;
7916 }
7917
7918 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7919 rc = pci_enable_device(pdev);
7920 if (rc) {
7921 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7922 goto err_out;
7923 }
7924
7925 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7926 dev_err(&pdev->dev,
7927 "Cannot find PCI device base address, aborting\n");
7928 rc = -ENODEV;
7929 goto err_out_disable;
7930 }
7931
7932 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7933 if (rc) {
7934 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7935 goto err_out_disable;
7936 }
7937
7938 pci_set_master(pdev);
7939
7940 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7941 if (bp->pm_cap == 0) {
7942 dev_err(&pdev->dev,
7943 "Cannot find power management capability, aborting\n");
7944 rc = -EIO;
7945 goto err_out_release;
7946 }
7947
7948 bp->dev = dev;
7949 bp->pdev = pdev;
7950
7951 spin_lock_init(&bp->phy_lock);
7952 spin_lock_init(&bp->indirect_lock);
7953 #ifdef BCM_CNIC
7954 mutex_init(&bp->cnic_lock);
7955 #endif
7956 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7957
7958 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7959 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7960 dev->mem_end = dev->mem_start + mem_len;
7961 dev->irq = pdev->irq;
7962
7963 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7964
7965 if (!bp->regview) {
7966 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7967 rc = -ENOMEM;
7968 goto err_out_release;
7969 }
7970
7971 bnx2_set_power_state(bp, PCI_D0);
7972
7973 /* Configure byte swap and enable write to the reg_window registers.
7974 * Rely on CPU to do target byte swapping on big endian systems
7975 * The chip's target access swapping will not swap all accesses
7976 */
7977 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
7978 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7979 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7980
7981 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7982
7983 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7984 if (!pci_is_pcie(pdev)) {
7985 dev_err(&pdev->dev, "Not PCIE, aborting\n");
7986 rc = -EIO;
7987 goto err_out_unmap;
7988 }
7989 bp->flags |= BNX2_FLAG_PCIE;
7990 if (CHIP_REV(bp) == CHIP_REV_Ax)
7991 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7992
7993 /* AER (Advanced Error Reporting) hooks */
7994 err = pci_enable_pcie_error_reporting(pdev);
7995 if (!err)
7996 bp->flags |= BNX2_FLAG_AER_ENABLED;
7997
7998 } else {
7999 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
8000 if (bp->pcix_cap == 0) {
8001 dev_err(&pdev->dev,
8002 "Cannot find PCIX capability, aborting\n");
8003 rc = -EIO;
8004 goto err_out_unmap;
8005 }
8006 bp->flags |= BNX2_FLAG_BROKEN_STATS;
8007 }
8008
8009 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
8010 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
8011 bp->flags |= BNX2_FLAG_MSIX_CAP;
8012 }
8013
8014 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
8015 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
8016 bp->flags |= BNX2_FLAG_MSI_CAP;
8017 }
8018
8019 /* 5708 cannot support DMA addresses > 40-bit. */
8020 if (CHIP_NUM(bp) == CHIP_NUM_5708)
8021 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
8022 else
8023 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
8024
8025 /* Configure DMA attributes. */
8026 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8027 dev->features |= NETIF_F_HIGHDMA;
8028 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8029 if (rc) {
8030 dev_err(&pdev->dev,
8031 "pci_set_consistent_dma_mask failed, aborting\n");
8032 goto err_out_unmap;
8033 }
8034 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
8035 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8036 goto err_out_unmap;
8037 }
8038
8039 if (!(bp->flags & BNX2_FLAG_PCIE))
8040 bnx2_get_pci_speed(bp);
8041
8042 /* 5706A0 may falsely detect SERR and PERR. */
8043 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8044 reg = REG_RD(bp, PCI_COMMAND);
8045 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8046 REG_WR(bp, PCI_COMMAND, reg);
8047 }
8048 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
8049 !(bp->flags & BNX2_FLAG_PCIX)) {
8050
8051 dev_err(&pdev->dev,
8052 "5706 A1 can only be used in a PCIX bus, aborting\n");
8053 goto err_out_unmap;
8054 }
8055
8056 bnx2_init_nvram(bp);
8057
8058 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
8059
8060 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
8061 BNX2_SHM_HDR_SIGNATURE_SIG) {
8062 u32 off = PCI_FUNC(pdev->devfn) << 2;
8063
8064 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8065 } else
8066 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8067
8068 /* Get the permanent MAC address. First we need to make sure the
8069 * firmware is actually running.
8070 */
8071 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8072
8073 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8074 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8075 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8076 rc = -ENODEV;
8077 goto err_out_unmap;
8078 }
8079
8080 bnx2_read_vpd_fw_ver(bp);
8081
8082 j = strlen(bp->fw_version);
8083 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8084 for (i = 0; i < 3 && j < 24; i++) {
8085 u8 num, k, skip0;
8086
8087 if (i == 0) {
8088 bp->fw_version[j++] = 'b';
8089 bp->fw_version[j++] = 'c';
8090 bp->fw_version[j++] = ' ';
8091 }
8092 num = (u8) (reg >> (24 - (i * 8)));
8093 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8094 if (num >= k || !skip0 || k == 1) {
8095 bp->fw_version[j++] = (num / k) + '0';
8096 skip0 = 0;
8097 }
8098 }
8099 if (i != 2)
8100 bp->fw_version[j++] = '.';
8101 }
8102 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8103 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8104 bp->wol = 1;
8105
8106 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8107 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8108
8109 for (i = 0; i < 30; i++) {
8110 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8111 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8112 break;
8113 msleep(10);
8114 }
8115 }
8116 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8117 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8118 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8119 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8120 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8121
8122 if (j < 32)
8123 bp->fw_version[j++] = ' ';
8124 for (i = 0; i < 3 && j < 28; i++) {
8125 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8126 reg = be32_to_cpu(reg);
8127 memcpy(&bp->fw_version[j], &reg, 4);
8128 j += 4;
8129 }
8130 }
8131
8132 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8133 bp->mac_addr[0] = (u8) (reg >> 8);
8134 bp->mac_addr[1] = (u8) reg;
8135
8136 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8137 bp->mac_addr[2] = (u8) (reg >> 24);
8138 bp->mac_addr[3] = (u8) (reg >> 16);
8139 bp->mac_addr[4] = (u8) (reg >> 8);
8140 bp->mac_addr[5] = (u8) reg;
8141
8142 bp->tx_ring_size = MAX_TX_DESC_CNT;
8143 bnx2_set_rx_ring_size(bp, 255);
8144
8145 bp->tx_quick_cons_trip_int = 2;
8146 bp->tx_quick_cons_trip = 20;
8147 bp->tx_ticks_int = 18;
8148 bp->tx_ticks = 80;
8149
8150 bp->rx_quick_cons_trip_int = 2;
8151 bp->rx_quick_cons_trip = 12;
8152 bp->rx_ticks_int = 18;
8153 bp->rx_ticks = 18;
8154
8155 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8156
8157 bp->current_interval = BNX2_TIMER_INTERVAL;
8158
8159 bp->phy_addr = 1;
8160
8161 /* Disable WOL support if we are running on a SERDES chip. */
8162 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8163 bnx2_get_5709_media(bp);
8164 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8165 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8166
8167 bp->phy_port = PORT_TP;
8168 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8169 bp->phy_port = PORT_FIBRE;
8170 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8171 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8172 bp->flags |= BNX2_FLAG_NO_WOL;
8173 bp->wol = 0;
8174 }
8175 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8176 /* Don't do parallel detect on this board because of
8177 * some board problems. The link will not go down
8178 * if we do parallel detect.
8179 */
8180 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8181 pdev->subsystem_device == 0x310c)
8182 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8183 } else {
8184 bp->phy_addr = 2;
8185 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8186 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8187 }
8188 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8189 CHIP_NUM(bp) == CHIP_NUM_5708)
8190 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8191 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8192 (CHIP_REV(bp) == CHIP_REV_Ax ||
8193 CHIP_REV(bp) == CHIP_REV_Bx))
8194 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8195
8196 bnx2_init_fw_cap(bp);
8197
8198 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8199 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8200 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8201 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8202 bp->flags |= BNX2_FLAG_NO_WOL;
8203 bp->wol = 0;
8204 }
8205
8206 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8207 bp->tx_quick_cons_trip_int =
8208 bp->tx_quick_cons_trip;
8209 bp->tx_ticks_int = bp->tx_ticks;
8210 bp->rx_quick_cons_trip_int =
8211 bp->rx_quick_cons_trip;
8212 bp->rx_ticks_int = bp->rx_ticks;
8213 bp->comp_prod_trip_int = bp->comp_prod_trip;
8214 bp->com_ticks_int = bp->com_ticks;
8215 bp->cmd_ticks_int = bp->cmd_ticks;
8216 }
8217
8218 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8219 *
8220 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8221 * with byte enables disabled on the unused 32-bit word. This is legal
8222 * but causes problems on the AMD 8132 which will eventually stop
8223 * responding after a while.
8224 *
8225 * AMD believes this incompatibility is unique to the 5706, and
8226 * prefers to locally disable MSI rather than globally disabling it.
8227 */
8228 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8229 struct pci_dev *amd_8132 = NULL;
8230
8231 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8232 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8233 amd_8132))) {
8234
8235 if (amd_8132->revision >= 0x10 &&
8236 amd_8132->revision <= 0x13) {
8237 disable_msi = 1;
8238 pci_dev_put(amd_8132);
8239 break;
8240 }
8241 }
8242 }
8243
8244 bnx2_set_default_link(bp);
8245 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8246
8247 init_timer(&bp->timer);
8248 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8249 bp->timer.data = (unsigned long) bp;
8250 bp->timer.function = bnx2_timer;
8251
8252 #ifdef BCM_CNIC
8253 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8254 bp->cnic_eth_dev.max_iscsi_conn =
8255 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8256 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
8257 #endif
8258 pci_save_state(pdev);
8259
8260 return 0;
8261
8262 err_out_unmap:
8263 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
8264 pci_disable_pcie_error_reporting(pdev);
8265 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8266 }
8267
8268 if (bp->regview) {
8269 iounmap(bp->regview);
8270 bp->regview = NULL;
8271 }
8272
8273 err_out_release:
8274 pci_release_regions(pdev);
8275
8276 err_out_disable:
8277 pci_disable_device(pdev);
8278 pci_set_drvdata(pdev, NULL);
8279
8280 err_out:
8281 return rc;
8282 }
8283
8284 static char * __devinit
8285 bnx2_bus_string(struct bnx2 *bp, char *str)
8286 {
8287 char *s = str;
8288
8289 if (bp->flags & BNX2_FLAG_PCIE) {
8290 s += sprintf(s, "PCI Express");
8291 } else {
8292 s += sprintf(s, "PCI");
8293 if (bp->flags & BNX2_FLAG_PCIX)
8294 s += sprintf(s, "-X");
8295 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8296 s += sprintf(s, " 32-bit");
8297 else
8298 s += sprintf(s, " 64-bit");
8299 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8300 }
8301 return str;
8302 }
8303
8304 static void
8305 bnx2_del_napi(struct bnx2 *bp)
8306 {
8307 int i;
8308
8309 for (i = 0; i < bp->irq_nvecs; i++)
8310 netif_napi_del(&bp->bnx2_napi[i].napi);
8311 }
8312
8313 static void
8314 bnx2_init_napi(struct bnx2 *bp)
8315 {
8316 int i;
8317
8318 for (i = 0; i < bp->irq_nvecs; i++) {
8319 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8320 int (*poll)(struct napi_struct *, int);
8321
8322 if (i == 0)
8323 poll = bnx2_poll;
8324 else
8325 poll = bnx2_poll_msix;
8326
8327 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8328 bnapi->bp = bp;
8329 }
8330 }
8331
8332 static const struct net_device_ops bnx2_netdev_ops = {
8333 .ndo_open = bnx2_open,
8334 .ndo_start_xmit = bnx2_start_xmit,
8335 .ndo_stop = bnx2_close,
8336 .ndo_get_stats64 = bnx2_get_stats64,
8337 .ndo_set_rx_mode = bnx2_set_rx_mode,
8338 .ndo_do_ioctl = bnx2_ioctl,
8339 .ndo_validate_addr = eth_validate_addr,
8340 .ndo_set_mac_address = bnx2_change_mac_addr,
8341 .ndo_change_mtu = bnx2_change_mtu,
8342 .ndo_fix_features = bnx2_fix_features,
8343 .ndo_set_features = bnx2_set_features,
8344 .ndo_tx_timeout = bnx2_tx_timeout,
8345 #ifdef CONFIG_NET_POLL_CONTROLLER
8346 .ndo_poll_controller = poll_bnx2,
8347 #endif
8348 };
8349
8350 static int __devinit
8351 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8352 {
8353 static int version_printed = 0;
8354 struct net_device *dev = NULL;
8355 struct bnx2 *bp;
8356 int rc;
8357 char str[40];
8358
8359 if (version_printed++ == 0)
8360 pr_info("%s", version);
8361
8362 /* dev zeroed in init_etherdev */
8363 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8364
8365 if (!dev)
8366 return -ENOMEM;
8367
8368 rc = bnx2_init_board(pdev, dev);
8369 if (rc < 0) {
8370 free_netdev(dev);
8371 return rc;
8372 }
8373
8374 dev->netdev_ops = &bnx2_netdev_ops;
8375 dev->watchdog_timeo = TX_TIMEOUT;
8376 dev->ethtool_ops = &bnx2_ethtool_ops;
8377
8378 bp = netdev_priv(dev);
8379
8380 pci_set_drvdata(pdev, dev);
8381
8382 memcpy(dev->dev_addr, bp->mac_addr, 6);
8383 memcpy(dev->perm_addr, bp->mac_addr, 6);
8384
8385 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8386 NETIF_F_TSO | NETIF_F_TSO_ECN |
8387 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8388
8389 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8390 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8391
8392 dev->vlan_features = dev->hw_features;
8393 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8394 dev->features |= dev->hw_features;
8395 dev->priv_flags |= IFF_UNICAST_FLT;
8396
8397 if ((rc = register_netdev(dev))) {
8398 dev_err(&pdev->dev, "Cannot register net device\n");
8399 goto error;
8400 }
8401
8402 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8403 board_info[ent->driver_data].name,
8404 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8405 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8406 bnx2_bus_string(bp, str),
8407 dev->base_addr,
8408 bp->pdev->irq, dev->dev_addr);
8409
8410 return 0;
8411
8412 error:
8413 if (bp->regview)
8414 iounmap(bp->regview);
8415 pci_release_regions(pdev);
8416 pci_disable_device(pdev);
8417 pci_set_drvdata(pdev, NULL);
8418 free_netdev(dev);
8419 return rc;
8420 }
8421
8422 static void __devexit
8423 bnx2_remove_one(struct pci_dev *pdev)
8424 {
8425 struct net_device *dev = pci_get_drvdata(pdev);
8426 struct bnx2 *bp = netdev_priv(dev);
8427
8428 unregister_netdev(dev);
8429
8430 del_timer_sync(&bp->timer);
8431 cancel_work_sync(&bp->reset_task);
8432
8433 if (bp->regview)
8434 iounmap(bp->regview);
8435
8436 kfree(bp->temp_stats_blk);
8437
8438 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
8439 pci_disable_pcie_error_reporting(pdev);
8440 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8441 }
8442
8443 bnx2_release_firmware(bp);
8444
8445 free_netdev(dev);
8446
8447 pci_release_regions(pdev);
8448 pci_disable_device(pdev);
8449 pci_set_drvdata(pdev, NULL);
8450 }
8451
8452 static int
8453 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8454 {
8455 struct net_device *dev = pci_get_drvdata(pdev);
8456 struct bnx2 *bp = netdev_priv(dev);
8457
8458 /* PCI register 4 needs to be saved whether netif_running() or not.
8459 * MSI address and data need to be saved if using MSI and
8460 * netif_running().
8461 */
8462 pci_save_state(pdev);
8463 if (!netif_running(dev))
8464 return 0;
8465
8466 cancel_work_sync(&bp->reset_task);
8467 bnx2_netif_stop(bp, true);
8468 netif_device_detach(dev);
8469 del_timer_sync(&bp->timer);
8470 bnx2_shutdown_chip(bp);
8471 bnx2_free_skbs(bp);
8472 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8473 return 0;
8474 }
8475
8476 static int
8477 bnx2_resume(struct pci_dev *pdev)
8478 {
8479 struct net_device *dev = pci_get_drvdata(pdev);
8480 struct bnx2 *bp = netdev_priv(dev);
8481
8482 pci_restore_state(pdev);
8483 if (!netif_running(dev))
8484 return 0;
8485
8486 bnx2_set_power_state(bp, PCI_D0);
8487 netif_device_attach(dev);
8488 bnx2_init_nic(bp, 1);
8489 bnx2_netif_start(bp, true);
8490 return 0;
8491 }
8492
8493 /**
8494 * bnx2_io_error_detected - called when PCI error is detected
8495 * @pdev: Pointer to PCI device
8496 * @state: The current pci connection state
8497 *
8498 * This function is called after a PCI bus error affecting
8499 * this device has been detected.
8500 */
8501 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8502 pci_channel_state_t state)
8503 {
8504 struct net_device *dev = pci_get_drvdata(pdev);
8505 struct bnx2 *bp = netdev_priv(dev);
8506
8507 rtnl_lock();
8508 netif_device_detach(dev);
8509
8510 if (state == pci_channel_io_perm_failure) {
8511 rtnl_unlock();
8512 return PCI_ERS_RESULT_DISCONNECT;
8513 }
8514
8515 if (netif_running(dev)) {
8516 bnx2_netif_stop(bp, true);
8517 del_timer_sync(&bp->timer);
8518 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8519 }
8520
8521 pci_disable_device(pdev);
8522 rtnl_unlock();
8523
8524 /* Request a slot slot reset. */
8525 return PCI_ERS_RESULT_NEED_RESET;
8526 }
8527
8528 /**
8529 * bnx2_io_slot_reset - called after the pci bus has been reset.
8530 * @pdev: Pointer to PCI device
8531 *
8532 * Restart the card from scratch, as if from a cold-boot.
8533 */
8534 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8535 {
8536 struct net_device *dev = pci_get_drvdata(pdev);
8537 struct bnx2 *bp = netdev_priv(dev);
8538 pci_ers_result_t result;
8539 int err;
8540
8541 rtnl_lock();
8542 if (pci_enable_device(pdev)) {
8543 dev_err(&pdev->dev,
8544 "Cannot re-enable PCI device after reset\n");
8545 result = PCI_ERS_RESULT_DISCONNECT;
8546 } else {
8547 pci_set_master(pdev);
8548 pci_restore_state(pdev);
8549 pci_save_state(pdev);
8550
8551 if (netif_running(dev)) {
8552 bnx2_set_power_state(bp, PCI_D0);
8553 bnx2_init_nic(bp, 1);
8554 }
8555 result = PCI_ERS_RESULT_RECOVERED;
8556 }
8557 rtnl_unlock();
8558
8559 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
8560 return result;
8561
8562 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8563 if (err) {
8564 dev_err(&pdev->dev,
8565 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8566 err); /* non-fatal, continue */
8567 }
8568
8569 return result;
8570 }
8571
8572 /**
8573 * bnx2_io_resume - called when traffic can start flowing again.
8574 * @pdev: Pointer to PCI device
8575 *
8576 * This callback is called when the error recovery driver tells us that
8577 * its OK to resume normal operation.
8578 */
8579 static void bnx2_io_resume(struct pci_dev *pdev)
8580 {
8581 struct net_device *dev = pci_get_drvdata(pdev);
8582 struct bnx2 *bp = netdev_priv(dev);
8583
8584 rtnl_lock();
8585 if (netif_running(dev))
8586 bnx2_netif_start(bp, true);
8587
8588 netif_device_attach(dev);
8589 rtnl_unlock();
8590 }
8591
8592 static struct pci_error_handlers bnx2_err_handler = {
8593 .error_detected = bnx2_io_error_detected,
8594 .slot_reset = bnx2_io_slot_reset,
8595 .resume = bnx2_io_resume,
8596 };
8597
8598 static struct pci_driver bnx2_pci_driver = {
8599 .name = DRV_MODULE_NAME,
8600 .id_table = bnx2_pci_tbl,
8601 .probe = bnx2_init_one,
8602 .remove = __devexit_p(bnx2_remove_one),
8603 .suspend = bnx2_suspend,
8604 .resume = bnx2_resume,
8605 .err_handler = &bnx2_err_handler,
8606 };
8607
8608 static int __init bnx2_init(void)
8609 {
8610 return pci_register_driver(&bnx2_pci_driver);
8611 }
8612
8613 static void __exit bnx2_cleanup(void)
8614 {
8615 pci_unregister_driver(&bnx2_pci_driver);
8616 }
8617
8618 module_init(bnx2_init);
8619 module_exit(bnx2_cleanup);
8620
8621
8622
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree