3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/sys.h>
24 #include <linux/threads.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/unistd.h>
33 #include <asm/ftrace.h>
34 #include <asm/ptrace.h>
37 #undef SHOW_SYSCALLS_TASK
40 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
42 #if MSR_KERNEL >= 0x10000
43 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
45 #define LOAD_MSR_KERNEL(r, x) li r,(x)
49 .globl mcheck_transfer_to_handler
50 mcheck_transfer_to_handler:
57 .globl debug_transfer_to_handler
58 debug_transfer_to_handler:
65 .globl crit_transfer_to_handler
66 crit_transfer_to_handler:
67 #ifdef CONFIG_PPC_BOOK3E_MMU
78 #ifdef CONFIG_PHYS_64BIT
81 #endif /* CONFIG_PHYS_64BIT */
82 #endif /* CONFIG_PPC_BOOK3E_MMU */
92 mfspr r8,SPRN_SPRG_THREAD
94 stw r0,SAVED_KSP_LIMIT(r11)
95 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
101 .globl crit_transfer_to_handler
102 crit_transfer_to_handler:
108 stw r0,crit_srr0@l(0)
110 stw r0,crit_srr1@l(0)
112 mfspr r8,SPRN_SPRG_THREAD
114 stw r0,saved_ksp_limit@l(0)
115 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
121 * This code finishes saving the registers to the exception frame
122 * and jumps to the appropriate handler for the exception, turning
123 * on address translation.
124 * Note that we rely on the caller having set cr0.eq iff the exception
125 * occurred in kernel mode (i.e. MSR:PR = 0).
127 .globl transfer_to_handler_full
128 transfer_to_handler_full:
132 .globl transfer_to_handler
142 mfspr r12,SPRN_SPRG_THREAD
144 tovirt(r2,r2) /* set r2 to current */
145 beq 2f /* if from user, fix up THREAD.regs */
146 addi r11,r1,STACK_FRAME_OVERHEAD
148 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
149 /* Check to see if the dbcr0 register is set up to debug. Use the
150 internal debug mode bit to do this. */
151 lwz r12,THREAD_DBCR0(r12)
152 andis. r12,r12,DBCR0_IDM@h
154 /* From user and task is ptraced - load up global dbcr0 */
155 li r12,-1 /* clear all pending debug events */
157 lis r11,global_dbcr0@ha
159 addi r11,r11,global_dbcr0@l
161 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
174 2: /* if from kernel, check interrupted DOZE/NAP mode and
175 * check for stack overflow
177 lwz r9,KSP_LIMIT(r12)
178 cmplw r1,r9 /* if r1 <= ksp_limit */
179 ble- stack_ovf /* then the kernel stack overflowed */
181 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
182 rlwinm r9,r1,0,0,31-THREAD_SHIFT
183 tophys(r9,r9) /* check local flags */
184 lwz r12,TI_LOCAL_FLAGS(r9)
186 bt- 31-TLF_NAPPING,4f
187 bt- 31-TLF_SLEEPING,7f
188 #endif /* CONFIG_6xx || CONFIG_E500 */
189 .globl transfer_to_handler_cont
190 transfer_to_handler_cont:
193 lwz r11,0(r9) /* virtual address of handler */
194 lwz r9,4(r9) /* where to go when done */
195 #ifdef CONFIG_TRACE_IRQFLAGS
196 lis r12,reenable_mmu@h
197 ori r12,r12,reenable_mmu@l
202 reenable_mmu: /* re-enable mmu so we can */
206 andi. r10,r10,MSR_EE /* Did EE change? */
209 /* Save handler and return address into the 2 unused words
210 * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything
211 * else can be recovered from the pt_regs except r3 which for
212 * normal interrupts has been set to pt_regs and for syscalls
213 * is an argument, so we temporarily use ORIG_GPR3 to save it
218 bl trace_hardirqs_off
230 bctr /* jump to handler */
231 #else /* CONFIG_TRACE_IRQFLAGS */
236 RFI /* jump to handler, enable MMU */
237 #endif /* CONFIG_TRACE_IRQFLAGS */
239 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
240 4: rlwinm r12,r12,0,~_TLF_NAPPING
241 stw r12,TI_LOCAL_FLAGS(r9)
242 b power_save_ppc32_restore
244 7: rlwinm r12,r12,0,~_TLF_SLEEPING
245 stw r12,TI_LOCAL_FLAGS(r9)
246 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
247 rlwinm r9,r9,0,~MSR_EE
248 lwz r12,_LINK(r11) /* and return to address in LR */
249 b fast_exception_return
253 * On kernel stack overflow, load up an initial stack pointer
254 * and call StackOverflow(regs), which should not return.
257 /* sometimes we use a statically-allocated stack, which is OK. */
261 ble 5b /* r1 <= &_end is OK */
263 addi r3,r1,STACK_FRAME_OVERHEAD
264 lis r1,init_thread_union@ha
265 addi r1,r1,init_thread_union@l
266 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
267 lis r9,StackOverflow@ha
268 addi r9,r9,StackOverflow@l
269 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
277 * Handle a system call.
279 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
280 .stabs "entry_32.S",N_SO,0,0,0f
287 lwz r11,_CCR(r1) /* Clear SO bit in CR */
292 #endif /* SHOW_SYSCALLS */
293 #ifdef CONFIG_TRACE_IRQFLAGS
294 /* Return from syscalls can (and generally will) hard enable
295 * interrupts. You aren't supposed to call a syscall with
296 * interrupts disabled in the first place. However, to ensure
297 * that we get it right vs. lockdep if it happens, we force
298 * that hard enable here with appropriate tracing if we see
299 * that we have been called with interrupts off
304 /* We came in with interrupts disabled, we enable them now */
317 #endif /* CONFIG_TRACE_IRQFLAGS */
318 rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
319 lwz r11,TI_FLAGS(r10)
320 andi. r11,r11,_TIF_SYSCALL_T_OR_A
322 syscall_dotrace_cont:
323 cmplwi 0,r0,NR_syscalls
324 lis r10,sys_call_table@h
325 ori r10,r10,sys_call_table@l
328 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
330 addi r9,r1,STACK_FRAME_OVERHEAD
332 blrl /* Call handler */
333 .globl ret_from_syscall
336 bl do_show_syscall_exit
339 rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
340 /* disable interrupts so current_thread_info()->flags can't change */
341 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
342 /* Note: We don't bother telling lockdep about it */
347 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
348 bne- syscall_exit_work
350 blt+ syscall_exit_cont
351 lwz r11,_CCR(r1) /* Load CR */
353 oris r11,r11,0x1000 /* Set SO bit in CR */
357 #ifdef CONFIG_TRACE_IRQFLAGS
358 /* If we are going to return from the syscall with interrupts
359 * off, we trace that here. It shouldn't happen though but we
360 * want to catch the bugger if it does right ?
365 bl trace_hardirqs_off
368 #endif /* CONFIG_TRACE_IRQFLAGS */
369 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
370 /* If the process has its own DBCR0 value, load it up. The internal
371 debug mode bit tells us that dbcr0 should be loaded. */
372 lwz r0,THREAD+THREAD_DBCR0(r2)
373 andis. r10,r0,DBCR0_IDM@h
377 BEGIN_MMU_FTR_SECTION
378 lis r4,icache_44x_need_flush@ha
379 lwz r5,icache_44x_need_flush@l(r4)
383 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
384 #endif /* CONFIG_44x */
387 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
388 stwcx. r0,0,r1 /* to clear the reservation */
404 stw r7,icache_44x_need_flush@l(r4)
406 #endif /* CONFIG_44x */
418 /* Traced system call support */
423 addi r3,r1,STACK_FRAME_OVERHEAD
424 bl do_syscall_trace_enter
426 * Restore argument registers possibly just changed.
427 * We use the return value of do_syscall_trace_enter
428 * for call number to look up in the table (r0).
438 b syscall_dotrace_cont
441 andi. r0,r9,_TIF_RESTOREALL
447 andi. r0,r9,_TIF_NOERROR
449 lwz r11,_CCR(r1) /* Load CR */
451 oris r11,r11,0x1000 /* Set SO bit in CR */
454 1: stw r6,RESULT(r1) /* Save result */
455 stw r3,GPR3(r1) /* Update return value */
456 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
459 /* Clear per-syscall TIF flags if any are set. */
461 li r11,_TIF_PERSYSCALL_MASK
462 addi r12,r12,TI_FLAGS
465 #ifdef CONFIG_IBM405_ERR77
470 subi r12,r12,TI_FLAGS
472 4: /* Anything which requires enabling interrupts? */
473 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
476 /* Re-enable interrupts. There is no need to trace that with
477 * lockdep as we are supposed to have IRQs on at this point
483 /* Save NVGPRS if they're not saved already */
491 addi r3,r1,STACK_FRAME_OVERHEAD
492 bl do_syscall_trace_leave
493 b ret_from_except_full
497 #ifdef SHOW_SYSCALLS_TASK
498 lis r11,show_syscalls_task@ha
499 lwz r11,show_syscalls_task@l(r11)
530 do_show_syscall_exit:
531 #ifdef SHOW_SYSCALLS_TASK
532 lis r11,show_syscalls_task@ha
533 lwz r11,show_syscalls_task@l(r11)
539 stw r3,RESULT(r1) /* Save result */
549 7: .string "syscall %d(%x, %x, %x, %x, %x, "
550 77: .string "%x), current=%p\n"
551 79: .string " -> %x\n"
554 #ifdef SHOW_SYSCALLS_TASK
556 .globl show_syscalls_task
561 #endif /* SHOW_SYSCALLS */
564 * The fork/clone functions need to copy the full register set into
565 * the child process. Therefore we need to save all the nonvolatile
566 * registers (r13 - r31) before calling the C code.
572 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
573 stw r0,_TRAP(r1) /* register set saved */
580 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
581 stw r0,_TRAP(r1) /* register set saved */
588 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
589 stw r0,_TRAP(r1) /* register set saved */
592 .globl ppc_swapcontext
596 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
597 stw r0,_TRAP(r1) /* register set saved */
601 * Top-level page fault handling.
602 * This is in assembler because if do_page_fault tells us that
603 * it is a bad kernel page fault, we want to save the non-volatile
604 * registers before calling bad_page_fault.
606 .globl handle_page_fault
609 addi r3,r1,STACK_FRAME_OVERHEAD
618 addi r3,r1,STACK_FRAME_OVERHEAD
621 b ret_from_except_full
624 * This routine switches between two different tasks. The process
625 * state of one is saved on its kernel stack. Then the state
626 * of the other is restored from its kernel stack. The memory
627 * management hardware is updated to the second process's state.
628 * Finally, we can return to the second process.
629 * On entry, r3 points to the THREAD for the current task, r4
630 * points to the THREAD for the new task.
632 * This routine is always called with interrupts disabled.
634 * Note: there are two ways to get to the "going out" portion
635 * of this code; either by coming in via the entry (_switch)
636 * or via "fork" which must set up an environment equivalent
637 * to the "_switch" path. If you change this , you'll have to
638 * change the fork code also.
640 * The code which creates the new task context is in 'copy_thread'
641 * in arch/ppc/kernel/process.c
644 stwu r1,-INT_FRAME_SIZE(r1)
646 stw r0,INT_FRAME_SIZE+4(r1)
647 /* r3-r12 are caller saved -- Cort */
649 stw r0,_NIP(r1) /* Return to switch caller */
651 li r0,MSR_FP /* Disable floating-point */
652 #ifdef CONFIG_ALTIVEC
654 oris r0,r0,MSR_VEC@h /* Disable altivec */
655 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
656 stw r12,THREAD+THREAD_VRSAVE(r2)
657 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
658 #endif /* CONFIG_ALTIVEC */
661 oris r0,r0,MSR_SPE@h /* Disable SPE */
662 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
663 stw r12,THREAD+THREAD_SPEFSCR(r2)
664 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
665 #endif /* CONFIG_SPE */
666 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
674 stw r1,KSP(r3) /* Set old stack pointer */
677 /* We need a sync somewhere here to make sure that if the
678 * previous task gets rescheduled on another CPU, it sees all
679 * stores it has performed on this one.
682 #endif /* CONFIG_SMP */
686 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
687 lwz r1,KSP(r4) /* Load new stack pointer */
689 /* save the old current 'last' for return value */
691 addi r2,r4,-THREAD /* Update current */
693 #ifdef CONFIG_ALTIVEC
695 lwz r0,THREAD+THREAD_VRSAVE(r2)
696 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
697 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
698 #endif /* CONFIG_ALTIVEC */
701 lwz r0,THREAD+THREAD_SPEFSCR(r2)
702 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
703 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
704 #endif /* CONFIG_SPE */
708 /* r3-r12 are destroyed -- Cort */
711 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
713 addi r1,r1,INT_FRAME_SIZE
716 .globl fast_exception_return
717 fast_exception_return:
718 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
719 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
720 beq 1f /* if not, we've got problems */
723 2: REST_4GPRS(3, r11)
738 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
739 /* check if the exception happened in a restartable section */
740 1: lis r3,exc_exit_restart_end@ha
741 addi r3,r3,exc_exit_restart_end@l
744 lis r4,exc_exit_restart@ha
745 addi r4,r4,exc_exit_restart@l
748 lis r3,fee_restarts@ha
750 lwz r5,fee_restarts@l(r3)
752 stw r5,fee_restarts@l(r3)
753 mr r12,r4 /* restart at exc_exit_restart */
762 /* aargh, a nonrecoverable interrupt, panic */
763 /* aargh, we don't know which trap this is */
764 /* but the 601 doesn't implement the RI bit, so assume it's OK */
768 END_FTR_SECTION_IFSET(CPU_FTR_601)
771 addi r3,r1,STACK_FRAME_OVERHEAD
773 ori r10,r10,MSR_KERNEL@l
774 bl transfer_to_handler_full
775 .long nonrecoverable_exception
776 .long ret_from_except
779 .globl ret_from_except_full
780 ret_from_except_full:
784 .globl ret_from_except
786 /* Hard-disable interrupts so that current_thread_info()->flags
787 * can't change between when we test it and when we return
788 * from the interrupt. */
789 /* Note: We don't bother telling lockdep about it */
790 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
791 SYNC /* Some chip revs have problems here... */
792 MTMSRD(r10) /* disable interrupts */
794 lwz r3,_MSR(r1) /* Returning to user mode? */
798 user_exc_return: /* r10 contains MSR_KERNEL here */
799 /* Check current_thread_info()->flags */
800 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
802 andi. r0,r9,_TIF_USER_WORK_MASK
806 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
807 /* Check whether this process has its own DBCR0 value. The internal
808 debug mode bit tells us that dbcr0 should be loaded. */
809 lwz r0,THREAD+THREAD_DBCR0(r2)
810 andis. r10,r0,DBCR0_IDM@h
814 #ifdef CONFIG_PREEMPT
817 /* N.B. the only way to get here is from the beq following ret_from_except. */
819 /* check current_thread_info->preempt_count */
820 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
821 lwz r0,TI_PREEMPT(r9)
822 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
825 andi. r0,r0,_TIF_NEED_RESCHED
827 andi. r0,r3,MSR_EE /* interrupts off? */
828 beq restore /* don't schedule if so */
829 #ifdef CONFIG_TRACE_IRQFLAGS
830 /* Lockdep thinks irqs are enabled, we need to call
831 * preempt_schedule_irq with IRQs off, so we inform lockdep
832 * now that we -did- turn them off already
834 bl trace_hardirqs_off
836 1: bl preempt_schedule_irq
837 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
839 andi. r0,r3,_TIF_NEED_RESCHED
841 #ifdef CONFIG_TRACE_IRQFLAGS
842 /* And now, to properly rebalance the above, we tell lockdep they
843 * are being turned back on, which will happen when we return
849 #endif /* CONFIG_PREEMPT */
851 /* interrupts are hard-disabled at this point */
854 BEGIN_MMU_FTR_SECTION
856 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
857 lis r4,icache_44x_need_flush@ha
858 lwz r5,icache_44x_need_flush@l(r4)
863 stw r6,icache_44x_need_flush@l(r4)
865 #endif /* CONFIG_44x */
868 #ifdef CONFIG_TRACE_IRQFLAGS
869 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
870 * off in this assembly code while peeking at TI_FLAGS() and such. However
871 * we need to inform it if the exception turned interrupts off, and we
872 * are about to trun them back on.
874 * The problem here sadly is that we don't know whether the exceptions was
875 * one that turned interrupts off or not. So we always tell lockdep about
876 * turning them on here when we go back to wherever we came from with EE
877 * on, even if that may meen some redudant calls being tracked. Maybe later
878 * we could encode what the exception did somewhere or test the exception
879 * type in the pt_regs but that sounds overkill
886 #endif /* CONFIG_TRACE_IRQFLAGS */
901 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
902 stwcx. r0,0,r1 /* to clear the reservation */
904 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
905 andi. r10,r9,MSR_RI /* check if this exception occurred */
906 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
914 * Once we put values in SRR0 and SRR1, we are in a state
915 * where exceptions are not recoverable, since taking an
916 * exception will trash SRR0 and SRR1. Therefore we clear the
917 * MSR:RI bit to indicate this. If we do take an exception,
918 * we can't return to the point of the exception but we
919 * can restart the exception exit path at the label
920 * exc_exit_restart below. -- paulus
922 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
924 MTMSRD(r10) /* clear the RI bit */
925 .globl exc_exit_restart
933 .globl exc_exit_restart_end
934 exc_exit_restart_end:
938 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
940 * This is a bit different on 4xx/Book-E because it doesn't have
941 * the RI bit in the MSR.
942 * The TLB miss handler checks if we have interrupted
943 * the exception exit path and restarts it if so
944 * (well maybe one day it will... :).
951 .globl exc_exit_restart
960 .globl exc_exit_restart_end
961 exc_exit_restart_end:
964 b . /* prevent prefetch past rfi */
967 * Returning from a critical interrupt in user mode doesn't need
968 * to be any different from a normal exception. For a critical
969 * interrupt in the kernel, we just return (without checking for
970 * preemption) since the interrupt may have happened at some crucial
971 * place (e.g. inside the TLB miss handler), and because we will be
972 * running with r1 pointing into critical_stack, not the current
973 * process's kernel stack (and therefore current_thread_info() will
974 * give the wrong answer).
975 * We have to restore various SPRs that may have been in use at the
976 * time of the critical interrupt.
980 #define PPC_40x_TURN_OFF_MSR_DR \
981 /* avoid any possible TLB misses here by turning off MSR.DR, we \
982 * assume the instructions here are mapped by a pinned TLB entry */ \
988 #define PPC_40x_TURN_OFF_MSR_DR
991 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
994 andi. r3,r3,MSR_PR; \
995 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
996 bne user_exc_return; \
1000 REST_2GPRS(7, r1); \
1003 mtspr SPRN_XER,r10; \
1005 PPC405_ERR77(0,r1); \
1006 stwcx. r0,0,r1; /* to clear the reservation */ \
1007 lwz r11,_LINK(r1); \
1011 PPC_40x_TURN_OFF_MSR_DR; \
1014 mtspr SPRN_DEAR,r9; \
1015 mtspr SPRN_ESR,r10; \
1018 mtspr exc_lvl_srr0,r11; \
1019 mtspr exc_lvl_srr1,r12; \
1021 lwz r12,GPR12(r1); \
1022 lwz r10,GPR10(r1); \
1023 lwz r11,GPR11(r1); \
1025 PPC405_ERR77_SYNC; \
1027 b .; /* prevent prefetch past exc_lvl_rfi */
1029 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1030 lwz r9,_##exc_lvl_srr0(r1); \
1031 lwz r10,_##exc_lvl_srr1(r1); \
1032 mtspr SPRN_##exc_lvl_srr0,r9; \
1033 mtspr SPRN_##exc_lvl_srr1,r10;
1035 #if defined(CONFIG_PPC_BOOK3E_MMU)
1036 #ifdef CONFIG_PHYS_64BIT
1037 #define RESTORE_MAS7 \
1039 mtspr SPRN_MAS7,r11;
1041 #define RESTORE_MAS7
1042 #endif /* CONFIG_PHYS_64BIT */
1043 #define RESTORE_MMU_REGS \
1047 mtspr SPRN_MAS0,r9; \
1049 mtspr SPRN_MAS1,r10; \
1051 mtspr SPRN_MAS2,r11; \
1052 mtspr SPRN_MAS3,r9; \
1053 mtspr SPRN_MAS6,r10; \
1055 #elif defined(CONFIG_44x)
1056 #define RESTORE_MMU_REGS \
1058 mtspr SPRN_MMUCR,r9;
1060 #define RESTORE_MMU_REGS
1064 .globl ret_from_crit_exc
1066 mfspr r9,SPRN_SPRG_THREAD
1067 lis r10,saved_ksp_limit@ha;
1068 lwz r10,saved_ksp_limit@l(r10);
1070 stw r10,KSP_LIMIT(r9)
1071 lis r9,crit_srr0@ha;
1072 lwz r9,crit_srr0@l(r9);
1073 lis r10,crit_srr1@ha;
1074 lwz r10,crit_srr1@l(r10);
1076 mtspr SPRN_SRR1,r10;
1077 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1078 #endif /* CONFIG_40x */
1081 .globl ret_from_crit_exc
1083 mfspr r9,SPRN_SPRG_THREAD
1084 lwz r10,SAVED_KSP_LIMIT(r1)
1085 stw r10,KSP_LIMIT(r9)
1086 RESTORE_xSRR(SRR0,SRR1);
1088 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1090 .globl ret_from_debug_exc
1092 mfspr r9,SPRN_SPRG_THREAD
1093 lwz r10,SAVED_KSP_LIMIT(r1)
1094 stw r10,KSP_LIMIT(r9)
1095 lwz r9,THREAD_INFO-THREAD(r9)
1096 rlwinm r10,r1,0,0,(31-THREAD_SHIFT)
1097 lwz r10,TI_PREEMPT(r10)
1098 stw r10,TI_PREEMPT(r9)
1099 RESTORE_xSRR(SRR0,SRR1);
1100 RESTORE_xSRR(CSRR0,CSRR1);
1102 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1104 .globl ret_from_mcheck_exc
1105 ret_from_mcheck_exc:
1106 mfspr r9,SPRN_SPRG_THREAD
1107 lwz r10,SAVED_KSP_LIMIT(r1)
1108 stw r10,KSP_LIMIT(r9)
1109 RESTORE_xSRR(SRR0,SRR1);
1110 RESTORE_xSRR(CSRR0,CSRR1);
1111 RESTORE_xSRR(DSRR0,DSRR1);
1113 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1114 #endif /* CONFIG_BOOKE */
1117 * Load the DBCR0 value for a task that is being ptraced,
1118 * having first saved away the global DBCR0. Note that r0
1119 * has the dbcr0 value to set upon entry to this.
1122 mfmsr r10 /* first disable debug exceptions */
1123 rlwinm r10,r10,0,~MSR_DE
1126 mfspr r10,SPRN_DBCR0
1127 lis r11,global_dbcr0@ha
1128 addi r11,r11,global_dbcr0@l
1130 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
1141 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1149 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1151 do_work: /* r10 contains MSR_KERNEL here */
1152 andi. r0,r9,_TIF_NEED_RESCHED
1155 do_resched: /* r10 contains MSR_KERNEL here */
1156 /* Note: We don't need to inform lockdep that we are enabling
1157 * interrupts here. As far as it knows, they are already enabled
1161 MTMSRD(r10) /* hard-enable interrupts */
1164 /* Note: And we don't tell it we are disabling them again
1165 * neither. Those disable/enable cycles used to peek at
1166 * TI_FLAGS aren't advertised.
1168 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1170 MTMSRD(r10) /* disable interrupts */
1171 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
1173 andi. r0,r9,_TIF_NEED_RESCHED
1175 andi. r0,r9,_TIF_USER_WORK_MASK
1177 do_user_signal: /* r10 contains MSR_KERNEL here */
1180 MTMSRD(r10) /* hard-enable interrupts */
1181 /* save r13-r31 in the exception frame, if not already done */
1188 2: addi r3,r1,STACK_FRAME_OVERHEAD
1195 * We come here when we are at the end of handling an exception
1196 * that occurred at a place where taking an exception will lose
1197 * state information, such as the contents of SRR0 and SRR1.
1200 lis r10,exc_exit_restart_end@ha
1201 addi r10,r10,exc_exit_restart_end@l
1204 lis r11,exc_exit_restart@ha
1205 addi r11,r11,exc_exit_restart@l
1208 lis r10,ee_restarts@ha
1209 lwz r12,ee_restarts@l(r10)
1211 stw r12,ee_restarts@l(r10)
1212 mr r12,r11 /* restart at exc_exit_restart */
1214 3: /* OK, we can't recover, kill this process */
1215 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1218 END_FTR_SECTION_IFSET(CPU_FTR_601)
1225 4: addi r3,r1,STACK_FRAME_OVERHEAD
1226 bl nonrecoverable_exception
1227 /* shouldn't return */
1237 * PROM code for specific machines follows. Put it
1238 * here so it's easy to add arch-specific sections later.
1241 #ifdef CONFIG_PPC_RTAS
1243 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1244 * called with the MMU off.
1247 stwu r1,-INT_FRAME_SIZE(r1)
1249 stw r0,INT_FRAME_SIZE+4(r1)
1250 LOAD_REG_ADDR(r4, rtas)
1251 lis r6,1f@ha /* physical return address for rtas */
1255 lwz r8,RTASENTRY(r4)
1259 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1260 SYNC /* disable interrupts so SRR0/1 */
1261 MTMSRD(r0) /* don't get trashed */
1262 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1264 mtspr SPRN_SPRG_RTAS,r7
1269 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1270 lwz r9,8(r9) /* original msr value */
1272 addi r1,r1,INT_FRAME_SIZE
1274 mtspr SPRN_SPRG_RTAS,r0
1277 RFI /* return to caller */
1279 .globl machine_check_in_rtas
1280 machine_check_in_rtas:
1282 /* XXX load up BATs and panic */
1284 #endif /* CONFIG_PPC_RTAS */
1286 #ifdef CONFIG_FUNCTION_TRACER
1287 #ifdef CONFIG_DYNAMIC_FTRACE
1291 * It is required that _mcount on PPC32 must preserve the
1292 * link register. But we have r0 to play with. We use r0
1293 * to push the return address back to the caller of mcount
1294 * into the ctr register, restore the link register and
1295 * then jump back using the ctr register.
1303 _GLOBAL(ftrace_caller)
1305 /* r3 ends up with link register */
1306 subi r3, r3, MCOUNT_INSN_SIZE
1311 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1312 .globl ftrace_graph_call
1315 _GLOBAL(ftrace_graph_stub)
1317 MCOUNT_RESTORE_FRAME
1318 /* old link register ends up in ctr reg */
1326 subi r3, r3, MCOUNT_INSN_SIZE
1327 LOAD_REG_ADDR(r5, ftrace_trace_function)
1334 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1335 b ftrace_graph_caller
1337 MCOUNT_RESTORE_FRAME
1341 _GLOBAL(ftrace_stub)
1344 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1345 _GLOBAL(ftrace_graph_caller)
1346 /* load r4 with local address */
1348 subi r4, r4, MCOUNT_INSN_SIZE
1350 /* get the parent address */
1353 bl prepare_ftrace_return
1356 MCOUNT_RESTORE_FRAME
1357 /* old link register ends up in ctr reg */
1360 _GLOBAL(return_to_handler)
1361 /* need to save return values */
1368 bl ftrace_return_to_handler
1371 /* return value has real return address */
1379 /* Jump back to real return address */
1381 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1383 #endif /* CONFIG_MCOUNT */