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drm/radeon/kms: cayman/evergreen cs checker updates
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / evergreen_cs.c
blob5e4f9f876d4f9ded44b59f95fd1dc8a75295d4dd
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "evergreend.h"
31 #include "evergreen_reg_safe.h"
32 #include "cayman_reg_safe.h"
33
34 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36
37 struct evergreen_cs_track {
38 u32 group_size;
39 u32 nbanks;
40 u32 npipes;
41 /* value we track */
42 u32 nsamples;
43 u32 cb_color_base_last[12];
44 struct radeon_bo *cb_color_bo[12];
45 u32 cb_color_bo_offset[12];
46 struct radeon_bo *cb_color_fmask_bo[8];
47 struct radeon_bo *cb_color_cmask_bo[8];
48 u32 cb_color_info[12];
49 u32 cb_color_view[12];
50 u32 cb_color_pitch_idx[12];
51 u32 cb_color_slice_idx[12];
52 u32 cb_color_dim_idx[12];
53 u32 cb_color_dim[12];
54 u32 cb_color_pitch[12];
55 u32 cb_color_slice[12];
56 u32 cb_color_cmask_slice[8];
57 u32 cb_color_fmask_slice[8];
58 u32 cb_target_mask;
59 u32 cb_shader_mask;
60 u32 vgt_strmout_config;
61 u32 vgt_strmout_buffer_config;
62 u32 db_depth_control;
63 u32 db_depth_view;
64 u32 db_depth_size;
65 u32 db_depth_size_idx;
66 u32 db_z_info;
67 u32 db_z_idx;
68 u32 db_z_read_offset;
69 u32 db_z_write_offset;
70 struct radeon_bo *db_z_read_bo;
71 struct radeon_bo *db_z_write_bo;
72 u32 db_s_info;
73 u32 db_s_idx;
74 u32 db_s_read_offset;
75 u32 db_s_write_offset;
76 struct radeon_bo *db_s_read_bo;
77 struct radeon_bo *db_s_write_bo;
78 };
79
80 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
81 {
82 int i;
83
84 for (i = 0; i < 8; i++) {
85 track->cb_color_fmask_bo[i] = NULL;
86 track->cb_color_cmask_bo[i] = NULL;
87 track->cb_color_cmask_slice[i] = 0;
88 track->cb_color_fmask_slice[i] = 0;
89 }
90
91 for (i = 0; i < 12; i++) {
92 track->cb_color_base_last[i] = 0;
93 track->cb_color_bo[i] = NULL;
94 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
95 track->cb_color_info[i] = 0;
96 track->cb_color_view[i] = 0;
97 track->cb_color_pitch_idx[i] = 0;
98 track->cb_color_slice_idx[i] = 0;
99 track->cb_color_dim[i] = 0;
100 track->cb_color_pitch[i] = 0;
101 track->cb_color_slice[i] = 0;
102 track->cb_color_dim[i] = 0;
103 }
104 track->cb_target_mask = 0xFFFFFFFF;
105 track->cb_shader_mask = 0xFFFFFFFF;
106
107 track->db_depth_view = 0xFFFFC000;
108 track->db_depth_size = 0xFFFFFFFF;
109 track->db_depth_size_idx = 0;
110 track->db_depth_control = 0xFFFFFFFF;
111 track->db_z_info = 0xFFFFFFFF;
112 track->db_z_idx = 0xFFFFFFFF;
113 track->db_z_read_offset = 0xFFFFFFFF;
114 track->db_z_write_offset = 0xFFFFFFFF;
115 track->db_z_read_bo = NULL;
116 track->db_z_write_bo = NULL;
117 track->db_s_info = 0xFFFFFFFF;
118 track->db_s_idx = 0xFFFFFFFF;
119 track->db_s_read_offset = 0xFFFFFFFF;
120 track->db_s_write_offset = 0xFFFFFFFF;
121 track->db_s_read_bo = NULL;
122 track->db_s_write_bo = NULL;
123 }
124
125 static inline int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
126 {
127 /* XXX fill in */
128 return 0;
129 }
130
131 static int evergreen_cs_track_check(struct radeon_cs_parser *p)
132 {
133 struct evergreen_cs_track *track = p->track;
134
135 /* we don't support stream out buffer yet */
136 if (track->vgt_strmout_config || track->vgt_strmout_buffer_config) {
137 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
138 return -EINVAL;
139 }
140
141 /* XXX fill in */
142 return 0;
143 }
144
145 /**
146 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
147 * @parser: parser structure holding parsing context.
148 * @pkt: where to store packet informations
149 *
150 * Assume that chunk_ib_index is properly set. Will return -EINVAL
151 * if packet is bigger than remaining ib size. or if packets is unknown.
152 **/
153 int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
154 struct radeon_cs_packet *pkt,
155 unsigned idx)
156 {
157 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
158 uint32_t header;
159
160 if (idx >= ib_chunk->length_dw) {
161 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
162 idx, ib_chunk->length_dw);
163 return -EINVAL;
164 }
165 header = radeon_get_ib_value(p, idx);
166 pkt->idx = idx;
167 pkt->type = CP_PACKET_GET_TYPE(header);
168 pkt->count = CP_PACKET_GET_COUNT(header);
169 pkt->one_reg_wr = 0;
170 switch (pkt->type) {
171 case PACKET_TYPE0:
172 pkt->reg = CP_PACKET0_GET_REG(header);
173 break;
174 case PACKET_TYPE3:
175 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
176 break;
177 case PACKET_TYPE2:
178 pkt->count = -1;
179 break;
180 default:
181 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
182 return -EINVAL;
183 }
184 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
185 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
186 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
187 return -EINVAL;
188 }
189 return 0;
190 }
191
192 /**
193 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
194 * @parser: parser structure holding parsing context.
195 * @data: pointer to relocation data
196 * @offset_start: starting offset
197 * @offset_mask: offset mask (to align start offset on)
198 * @reloc: reloc informations
199 *
200 * Check next packet is relocation packet3, do bo validation and compute
201 * GPU offset using the provided start.
202 **/
203 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
204 struct radeon_cs_reloc **cs_reloc)
205 {
206 struct radeon_cs_chunk *relocs_chunk;
207 struct radeon_cs_packet p3reloc;
208 unsigned idx;
209 int r;
210
211 if (p->chunk_relocs_idx == -1) {
212 DRM_ERROR("No relocation chunk !\n");
213 return -EINVAL;
214 }
215 *cs_reloc = NULL;
216 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
217 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
218 if (r) {
219 return r;
220 }
221 p->idx += p3reloc.count + 2;
222 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
223 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
224 p3reloc.idx);
225 return -EINVAL;
226 }
227 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
228 if (idx >= relocs_chunk->length_dw) {
229 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
230 idx, relocs_chunk->length_dw);
231 return -EINVAL;
232 }
233 /* FIXME: we assume reloc size is 4 dwords */
234 *cs_reloc = p->relocs_ptr[(idx / 4)];
235 return 0;
236 }
237
238 /**
239 * evergreen_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
240 * @parser: parser structure holding parsing context.
241 *
242 * Check next packet is relocation packet3, do bo validation and compute
243 * GPU offset using the provided start.
244 **/
245 static inline int evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
246 {
247 struct radeon_cs_packet p3reloc;
248 int r;
249
250 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
251 if (r) {
252 return 0;
253 }
254 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
255 return 0;
256 }
257 return 1;
258 }
259
260 /**
261 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
262 * @parser: parser structure holding parsing context.
263 *
264 * Userspace sends a special sequence for VLINE waits.
265 * PACKET0 - VLINE_START_END + value
266 * PACKET3 - WAIT_REG_MEM poll vline status reg
267 * RELOC (P3) - crtc_id in reloc.
268 *
269 * This function parses this and relocates the VLINE START END
270 * and WAIT_REG_MEM packets to the correct crtc.
271 * It also detects a switched off crtc and nulls out the
272 * wait in that case.
273 */
274 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
275 {
276 struct drm_mode_object *obj;
277 struct drm_crtc *crtc;
278 struct radeon_crtc *radeon_crtc;
279 struct radeon_cs_packet p3reloc, wait_reg_mem;
280 int crtc_id;
281 int r;
282 uint32_t header, h_idx, reg, wait_reg_mem_info;
283 volatile uint32_t *ib;
284
285 ib = p->ib->ptr;
286
287 /* parse the WAIT_REG_MEM */
288 r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
289 if (r)
290 return r;
291
292 /* check its a WAIT_REG_MEM */
293 if (wait_reg_mem.type != PACKET_TYPE3 ||
294 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
295 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
296 r = -EINVAL;
297 return r;
298 }
299
300 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
301 /* bit 4 is reg (0) or mem (1) */
302 if (wait_reg_mem_info & 0x10) {
303 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
304 r = -EINVAL;
305 return r;
306 }
307 /* waiting for value to be equal */
308 if ((wait_reg_mem_info & 0x7) != 0x3) {
309 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
310 r = -EINVAL;
311 return r;
312 }
313 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
314 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
315 r = -EINVAL;
316 return r;
317 }
318
319 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
320 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
321 r = -EINVAL;
322 return r;
323 }
324
325 /* jump over the NOP */
326 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
327 if (r)
328 return r;
329
330 h_idx = p->idx - 2;
331 p->idx += wait_reg_mem.count + 2;
332 p->idx += p3reloc.count + 2;
333
334 header = radeon_get_ib_value(p, h_idx);
335 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
336 reg = CP_PACKET0_GET_REG(header);
337 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
338 if (!obj) {
339 DRM_ERROR("cannot find crtc %d\n", crtc_id);
340 r = -EINVAL;
341 goto out;
342 }
343 crtc = obj_to_crtc(obj);
344 radeon_crtc = to_radeon_crtc(crtc);
345 crtc_id = radeon_crtc->crtc_id;
346
347 if (!crtc->enabled) {
348 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
349 ib[h_idx + 2] = PACKET2(0);
350 ib[h_idx + 3] = PACKET2(0);
351 ib[h_idx + 4] = PACKET2(0);
352 ib[h_idx + 5] = PACKET2(0);
353 ib[h_idx + 6] = PACKET2(0);
354 ib[h_idx + 7] = PACKET2(0);
355 ib[h_idx + 8] = PACKET2(0);
356 } else {
357 switch (reg) {
358 case EVERGREEN_VLINE_START_END:
359 header &= ~R600_CP_PACKET0_REG_MASK;
360 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
361 ib[h_idx] = header;
362 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
363 break;
364 default:
365 DRM_ERROR("unknown crtc reloc\n");
366 r = -EINVAL;
367 goto out;
368 }
369 }
370 out:
371 return r;
372 }
373
374 static int evergreen_packet0_check(struct radeon_cs_parser *p,
375 struct radeon_cs_packet *pkt,
376 unsigned idx, unsigned reg)
377 {
378 int r;
379
380 switch (reg) {
381 case EVERGREEN_VLINE_START_END:
382 r = evergreen_cs_packet_parse_vline(p);
383 if (r) {
384 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
385 idx, reg);
386 return r;
387 }
388 break;
389 default:
390 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
391 reg, idx);
392 return -EINVAL;
393 }
394 return 0;
395 }
396
397 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
398 struct radeon_cs_packet *pkt)
399 {
400 unsigned reg, i;
401 unsigned idx;
402 int r;
403
404 idx = pkt->idx + 1;
405 reg = pkt->reg;
406 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
407 r = evergreen_packet0_check(p, pkt, idx, reg);
408 if (r) {
409 return r;
410 }
411 }
412 return 0;
413 }
414
415 /**
416 * evergreen_cs_check_reg() - check if register is authorized or not
417 * @parser: parser structure holding parsing context
418 * @reg: register we are testing
419 * @idx: index into the cs buffer
420 *
421 * This function will test against evergreen_reg_safe_bm and return 0
422 * if register is safe. If register is not flag as safe this function
423 * will test it against a list of register needind special handling.
424 */
425 static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
426 {
427 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
428 struct radeon_cs_reloc *reloc;
429 u32 last_reg;
430 u32 m, i, tmp, *ib;
431 int r;
432
433 if (p->rdev->family >= CHIP_CAYMAN)
434 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
435 else
436 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
437
438 i = (reg >> 7);
439 if (i > last_reg) {
440 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
441 return -EINVAL;
442 }
443 m = 1 << ((reg >> 2) & 31);
444 if (p->rdev->family >= CHIP_CAYMAN) {
445 if (!(cayman_reg_safe_bm[i] & m))
446 return 0;
447 } else {
448 if (!(evergreen_reg_safe_bm[i] & m))
449 return 0;
450 }
451 ib = p->ib->ptr;
452 switch (reg) {
453 /* force following reg to 0 in an attemp to disable out buffer
454 * which will need us to better understand how it works to perform
455 * security check on it (Jerome)
456 */
457 case SQ_ESGS_RING_SIZE:
458 case SQ_GSVS_RING_SIZE:
459 case SQ_ESTMP_RING_SIZE:
460 case SQ_GSTMP_RING_SIZE:
461 case SQ_HSTMP_RING_SIZE:
462 case SQ_LSTMP_RING_SIZE:
463 case SQ_PSTMP_RING_SIZE:
464 case SQ_VSTMP_RING_SIZE:
465 case SQ_ESGS_RING_ITEMSIZE:
466 case SQ_ESTMP_RING_ITEMSIZE:
467 case SQ_GSTMP_RING_ITEMSIZE:
468 case SQ_GSVS_RING_ITEMSIZE:
469 case SQ_GS_VERT_ITEMSIZE:
470 case SQ_GS_VERT_ITEMSIZE_1:
471 case SQ_GS_VERT_ITEMSIZE_2:
472 case SQ_GS_VERT_ITEMSIZE_3:
473 case SQ_GSVS_RING_OFFSET_1:
474 case SQ_GSVS_RING_OFFSET_2:
475 case SQ_GSVS_RING_OFFSET_3:
476 case SQ_HSTMP_RING_ITEMSIZE:
477 case SQ_LSTMP_RING_ITEMSIZE:
478 case SQ_PSTMP_RING_ITEMSIZE:
479 case SQ_VSTMP_RING_ITEMSIZE:
480 case VGT_TF_RING_SIZE:
481 /* get value to populate the IB don't remove */
482 /*tmp =radeon_get_ib_value(p, idx);
483 ib[idx] = 0;*/
484 break;
485 case SQ_ESGS_RING_BASE:
486 case SQ_GSVS_RING_BASE:
487 case SQ_ESTMP_RING_BASE:
488 case SQ_GSTMP_RING_BASE:
489 case SQ_HSTMP_RING_BASE:
490 case SQ_LSTMP_RING_BASE:
491 case SQ_PSTMP_RING_BASE:
492 case SQ_VSTMP_RING_BASE:
493 r = evergreen_cs_packet_next_reloc(p, &reloc);
494 if (r) {
495 dev_warn(p->dev, "bad SET_CONTEXT_REG "
496 "0x%04X\n", reg);
497 return -EINVAL;
498 }
499 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
500 break;
501 case DB_DEPTH_CONTROL:
502 track->db_depth_control = radeon_get_ib_value(p, idx);
503 break;
504 case CAYMAN_DB_EQAA:
505 if (p->rdev->family < CHIP_CAYMAN) {
506 dev_warn(p->dev, "bad SET_CONTEXT_REG "
507 "0x%04X\n", reg);
508 return -EINVAL;
509 }
510 break;
511 case CAYMAN_DB_DEPTH_INFO:
512 if (p->rdev->family < CHIP_CAYMAN) {
513 dev_warn(p->dev, "bad SET_CONTEXT_REG "
514 "0x%04X\n", reg);
515 return -EINVAL;
516 }
517 break;
518 case DB_Z_INFO:
519 r = evergreen_cs_packet_next_reloc(p, &reloc);
520 if (r) {
521 dev_warn(p->dev, "bad SET_CONTEXT_REG "
522 "0x%04X\n", reg);
523 return -EINVAL;
524 }
525 track->db_z_info = radeon_get_ib_value(p, idx);
526 ib[idx] &= ~Z_ARRAY_MODE(0xf);
527 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
528 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
529 ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
530 track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
531 } else {
532 ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
533 track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
534 }
535 break;
536 case DB_STENCIL_INFO:
537 track->db_s_info = radeon_get_ib_value(p, idx);
538 break;
539 case DB_DEPTH_VIEW:
540 track->db_depth_view = radeon_get_ib_value(p, idx);
541 break;
542 case DB_DEPTH_SIZE:
543 track->db_depth_size = radeon_get_ib_value(p, idx);
544 track->db_depth_size_idx = idx;
545 break;
546 case DB_Z_READ_BASE:
547 r = evergreen_cs_packet_next_reloc(p, &reloc);
548 if (r) {
549 dev_warn(p->dev, "bad SET_CONTEXT_REG "
550 "0x%04X\n", reg);
551 return -EINVAL;
552 }
553 track->db_z_read_offset = radeon_get_ib_value(p, idx);
554 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
555 track->db_z_read_bo = reloc->robj;
556 break;
557 case DB_Z_WRITE_BASE:
558 r = evergreen_cs_packet_next_reloc(p, &reloc);
559 if (r) {
560 dev_warn(p->dev, "bad SET_CONTEXT_REG "
561 "0x%04X\n", reg);
562 return -EINVAL;
563 }
564 track->db_z_write_offset = radeon_get_ib_value(p, idx);
565 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
566 track->db_z_write_bo = reloc->robj;
567 break;
568 case DB_STENCIL_READ_BASE:
569 r = evergreen_cs_packet_next_reloc(p, &reloc);
570 if (r) {
571 dev_warn(p->dev, "bad SET_CONTEXT_REG "
572 "0x%04X\n", reg);
573 return -EINVAL;
574 }
575 track->db_s_read_offset = radeon_get_ib_value(p, idx);
576 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
577 track->db_s_read_bo = reloc->robj;
578 break;
579 case DB_STENCIL_WRITE_BASE:
580 r = evergreen_cs_packet_next_reloc(p, &reloc);
581 if (r) {
582 dev_warn(p->dev, "bad SET_CONTEXT_REG "
583 "0x%04X\n", reg);
584 return -EINVAL;
585 }
586 track->db_s_write_offset = radeon_get_ib_value(p, idx);
587 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
588 track->db_s_write_bo = reloc->robj;
589 break;
590 case VGT_STRMOUT_CONFIG:
591 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
592 break;
593 case VGT_STRMOUT_BUFFER_CONFIG:
594 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
595 break;
596 case CB_TARGET_MASK:
597 track->cb_target_mask = radeon_get_ib_value(p, idx);
598 break;
599 case CB_SHADER_MASK:
600 track->cb_shader_mask = radeon_get_ib_value(p, idx);
601 break;
602 case PA_SC_AA_CONFIG:
603 if (p->rdev->family >= CHIP_CAYMAN) {
604 dev_warn(p->dev, "bad SET_CONTEXT_REG "
605 "0x%04X\n", reg);
606 return -EINVAL;
607 }
608 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
609 track->nsamples = 1 << tmp;
610 break;
611 case CAYMAN_PA_SC_AA_CONFIG:
612 if (p->rdev->family < CHIP_CAYMAN) {
613 dev_warn(p->dev, "bad SET_CONTEXT_REG "
614 "0x%04X\n", reg);
615 return -EINVAL;
616 }
617 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
618 track->nsamples = 1 << tmp;
619 break;
620 case CB_COLOR0_VIEW:
621 case CB_COLOR1_VIEW:
622 case CB_COLOR2_VIEW:
623 case CB_COLOR3_VIEW:
624 case CB_COLOR4_VIEW:
625 case CB_COLOR5_VIEW:
626 case CB_COLOR6_VIEW:
627 case CB_COLOR7_VIEW:
628 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
629 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
630 break;
631 case CB_COLOR8_VIEW:
632 case CB_COLOR9_VIEW:
633 case CB_COLOR10_VIEW:
634 case CB_COLOR11_VIEW:
635 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
636 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
637 break;
638 case CB_COLOR0_INFO:
639 case CB_COLOR1_INFO:
640 case CB_COLOR2_INFO:
641 case CB_COLOR3_INFO:
642 case CB_COLOR4_INFO:
643 case CB_COLOR5_INFO:
644 case CB_COLOR6_INFO:
645 case CB_COLOR7_INFO:
646 r = evergreen_cs_packet_next_reloc(p, &reloc);
647 if (r) {
648 dev_warn(p->dev, "bad SET_CONTEXT_REG "
649 "0x%04X\n", reg);
650 return -EINVAL;
651 }
652 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
653 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
654 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
655 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
656 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
657 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
658 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
659 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
660 }
661 break;
662 case CB_COLOR8_INFO:
663 case CB_COLOR9_INFO:
664 case CB_COLOR10_INFO:
665 case CB_COLOR11_INFO:
666 r = evergreen_cs_packet_next_reloc(p, &reloc);
667 if (r) {
668 dev_warn(p->dev, "bad SET_CONTEXT_REG "
669 "0x%04X\n", reg);
670 return -EINVAL;
671 }
672 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
673 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
674 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
675 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
676 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
677 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
678 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
679 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
680 }
681 break;
682 case CB_COLOR0_PITCH:
683 case CB_COLOR1_PITCH:
684 case CB_COLOR2_PITCH:
685 case CB_COLOR3_PITCH:
686 case CB_COLOR4_PITCH:
687 case CB_COLOR5_PITCH:
688 case CB_COLOR6_PITCH:
689 case CB_COLOR7_PITCH:
690 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
691 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
692 track->cb_color_pitch_idx[tmp] = idx;
693 break;
694 case CB_COLOR8_PITCH:
695 case CB_COLOR9_PITCH:
696 case CB_COLOR10_PITCH:
697 case CB_COLOR11_PITCH:
698 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
699 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
700 track->cb_color_pitch_idx[tmp] = idx;
701 break;
702 case CB_COLOR0_SLICE:
703 case CB_COLOR1_SLICE:
704 case CB_COLOR2_SLICE:
705 case CB_COLOR3_SLICE:
706 case CB_COLOR4_SLICE:
707 case CB_COLOR5_SLICE:
708 case CB_COLOR6_SLICE:
709 case CB_COLOR7_SLICE:
710 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
711 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
712 track->cb_color_slice_idx[tmp] = idx;
713 break;
714 case CB_COLOR8_SLICE:
715 case CB_COLOR9_SLICE:
716 case CB_COLOR10_SLICE:
717 case CB_COLOR11_SLICE:
718 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
719 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
720 track->cb_color_slice_idx[tmp] = idx;
721 break;
722 case CB_COLOR0_ATTRIB:
723 case CB_COLOR1_ATTRIB:
724 case CB_COLOR2_ATTRIB:
725 case CB_COLOR3_ATTRIB:
726 case CB_COLOR4_ATTRIB:
727 case CB_COLOR5_ATTRIB:
728 case CB_COLOR6_ATTRIB:
729 case CB_COLOR7_ATTRIB:
730 case CB_COLOR8_ATTRIB:
731 case CB_COLOR9_ATTRIB:
732 case CB_COLOR10_ATTRIB:
733 case CB_COLOR11_ATTRIB:
734 break;
735 case CB_COLOR0_DIM:
736 case CB_COLOR1_DIM:
737 case CB_COLOR2_DIM:
738 case CB_COLOR3_DIM:
739 case CB_COLOR4_DIM:
740 case CB_COLOR5_DIM:
741 case CB_COLOR6_DIM:
742 case CB_COLOR7_DIM:
743 tmp = (reg - CB_COLOR0_DIM) / 0x3c;
744 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
745 track->cb_color_dim_idx[tmp] = idx;
746 break;
747 case CB_COLOR8_DIM:
748 case CB_COLOR9_DIM:
749 case CB_COLOR10_DIM:
750 case CB_COLOR11_DIM:
751 tmp = ((reg - CB_COLOR8_DIM) / 0x1c) + 8;
752 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
753 track->cb_color_dim_idx[tmp] = idx;
754 break;
755 case CB_COLOR0_FMASK:
756 case CB_COLOR1_FMASK:
757 case CB_COLOR2_FMASK:
758 case CB_COLOR3_FMASK:
759 case CB_COLOR4_FMASK:
760 case CB_COLOR5_FMASK:
761 case CB_COLOR6_FMASK:
762 case CB_COLOR7_FMASK:
763 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
764 r = evergreen_cs_packet_next_reloc(p, &reloc);
765 if (r) {
766 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
767 return -EINVAL;
768 }
769 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
770 track->cb_color_fmask_bo[tmp] = reloc->robj;
771 break;
772 case CB_COLOR0_CMASK:
773 case CB_COLOR1_CMASK:
774 case CB_COLOR2_CMASK:
775 case CB_COLOR3_CMASK:
776 case CB_COLOR4_CMASK:
777 case CB_COLOR5_CMASK:
778 case CB_COLOR6_CMASK:
779 case CB_COLOR7_CMASK:
780 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
781 r = evergreen_cs_packet_next_reloc(p, &reloc);
782 if (r) {
783 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
784 return -EINVAL;
785 }
786 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
787 track->cb_color_cmask_bo[tmp] = reloc->robj;
788 break;
789 case CB_COLOR0_FMASK_SLICE:
790 case CB_COLOR1_FMASK_SLICE:
791 case CB_COLOR2_FMASK_SLICE:
792 case CB_COLOR3_FMASK_SLICE:
793 case CB_COLOR4_FMASK_SLICE:
794 case CB_COLOR5_FMASK_SLICE:
795 case CB_COLOR6_FMASK_SLICE:
796 case CB_COLOR7_FMASK_SLICE:
797 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
798 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
799 break;
800 case CB_COLOR0_CMASK_SLICE:
801 case CB_COLOR1_CMASK_SLICE:
802 case CB_COLOR2_CMASK_SLICE:
803 case CB_COLOR3_CMASK_SLICE:
804 case CB_COLOR4_CMASK_SLICE:
805 case CB_COLOR5_CMASK_SLICE:
806 case CB_COLOR6_CMASK_SLICE:
807 case CB_COLOR7_CMASK_SLICE:
808 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
809 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
810 break;
811 case CB_COLOR0_BASE:
812 case CB_COLOR1_BASE:
813 case CB_COLOR2_BASE:
814 case CB_COLOR3_BASE:
815 case CB_COLOR4_BASE:
816 case CB_COLOR5_BASE:
817 case CB_COLOR6_BASE:
818 case CB_COLOR7_BASE:
819 r = evergreen_cs_packet_next_reloc(p, &reloc);
820 if (r) {
821 dev_warn(p->dev, "bad SET_CONTEXT_REG "
822 "0x%04X\n", reg);
823 return -EINVAL;
824 }
825 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
826 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
827 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
828 track->cb_color_base_last[tmp] = ib[idx];
829 track->cb_color_bo[tmp] = reloc->robj;
830 break;
831 case CB_COLOR8_BASE:
832 case CB_COLOR9_BASE:
833 case CB_COLOR10_BASE:
834 case CB_COLOR11_BASE:
835 r = evergreen_cs_packet_next_reloc(p, &reloc);
836 if (r) {
837 dev_warn(p->dev, "bad SET_CONTEXT_REG "
838 "0x%04X\n", reg);
839 return -EINVAL;
840 }
841 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
842 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
843 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
844 track->cb_color_base_last[tmp] = ib[idx];
845 track->cb_color_bo[tmp] = reloc->robj;
846 break;
847 case CB_IMMED0_BASE:
848 case CB_IMMED1_BASE:
849 case CB_IMMED2_BASE:
850 case CB_IMMED3_BASE:
851 case CB_IMMED4_BASE:
852 case CB_IMMED5_BASE:
853 case CB_IMMED6_BASE:
854 case CB_IMMED7_BASE:
855 case CB_IMMED8_BASE:
856 case CB_IMMED9_BASE:
857 case CB_IMMED10_BASE:
858 case CB_IMMED11_BASE:
859 case DB_HTILE_DATA_BASE:
860 case SQ_PGM_START_FS:
861 case SQ_PGM_START_ES:
862 case SQ_PGM_START_VS:
863 case SQ_PGM_START_GS:
864 case SQ_PGM_START_PS:
865 case SQ_PGM_START_HS:
866 case SQ_PGM_START_LS:
867 case GDS_ADDR_BASE:
868 case SQ_CONST_MEM_BASE:
869 case SQ_ALU_CONST_CACHE_GS_0:
870 case SQ_ALU_CONST_CACHE_GS_1:
871 case SQ_ALU_CONST_CACHE_GS_2:
872 case SQ_ALU_CONST_CACHE_GS_3:
873 case SQ_ALU_CONST_CACHE_GS_4:
874 case SQ_ALU_CONST_CACHE_GS_5:
875 case SQ_ALU_CONST_CACHE_GS_6:
876 case SQ_ALU_CONST_CACHE_GS_7:
877 case SQ_ALU_CONST_CACHE_GS_8:
878 case SQ_ALU_CONST_CACHE_GS_9:
879 case SQ_ALU_CONST_CACHE_GS_10:
880 case SQ_ALU_CONST_CACHE_GS_11:
881 case SQ_ALU_CONST_CACHE_GS_12:
882 case SQ_ALU_CONST_CACHE_GS_13:
883 case SQ_ALU_CONST_CACHE_GS_14:
884 case SQ_ALU_CONST_CACHE_GS_15:
885 case SQ_ALU_CONST_CACHE_PS_0:
886 case SQ_ALU_CONST_CACHE_PS_1:
887 case SQ_ALU_CONST_CACHE_PS_2:
888 case SQ_ALU_CONST_CACHE_PS_3:
889 case SQ_ALU_CONST_CACHE_PS_4:
890 case SQ_ALU_CONST_CACHE_PS_5:
891 case SQ_ALU_CONST_CACHE_PS_6:
892 case SQ_ALU_CONST_CACHE_PS_7:
893 case SQ_ALU_CONST_CACHE_PS_8:
894 case SQ_ALU_CONST_CACHE_PS_9:
895 case SQ_ALU_CONST_CACHE_PS_10:
896 case SQ_ALU_CONST_CACHE_PS_11:
897 case SQ_ALU_CONST_CACHE_PS_12:
898 case SQ_ALU_CONST_CACHE_PS_13:
899 case SQ_ALU_CONST_CACHE_PS_14:
900 case SQ_ALU_CONST_CACHE_PS_15:
901 case SQ_ALU_CONST_CACHE_VS_0:
902 case SQ_ALU_CONST_CACHE_VS_1:
903 case SQ_ALU_CONST_CACHE_VS_2:
904 case SQ_ALU_CONST_CACHE_VS_3:
905 case SQ_ALU_CONST_CACHE_VS_4:
906 case SQ_ALU_CONST_CACHE_VS_5:
907 case SQ_ALU_CONST_CACHE_VS_6:
908 case SQ_ALU_CONST_CACHE_VS_7:
909 case SQ_ALU_CONST_CACHE_VS_8:
910 case SQ_ALU_CONST_CACHE_VS_9:
911 case SQ_ALU_CONST_CACHE_VS_10:
912 case SQ_ALU_CONST_CACHE_VS_11:
913 case SQ_ALU_CONST_CACHE_VS_12:
914 case SQ_ALU_CONST_CACHE_VS_13:
915 case SQ_ALU_CONST_CACHE_VS_14:
916 case SQ_ALU_CONST_CACHE_VS_15:
917 case SQ_ALU_CONST_CACHE_HS_0:
918 case SQ_ALU_CONST_CACHE_HS_1:
919 case SQ_ALU_CONST_CACHE_HS_2:
920 case SQ_ALU_CONST_CACHE_HS_3:
921 case SQ_ALU_CONST_CACHE_HS_4:
922 case SQ_ALU_CONST_CACHE_HS_5:
923 case SQ_ALU_CONST_CACHE_HS_6:
924 case SQ_ALU_CONST_CACHE_HS_7:
925 case SQ_ALU_CONST_CACHE_HS_8:
926 case SQ_ALU_CONST_CACHE_HS_9:
927 case SQ_ALU_CONST_CACHE_HS_10:
928 case SQ_ALU_CONST_CACHE_HS_11:
929 case SQ_ALU_CONST_CACHE_HS_12:
930 case SQ_ALU_CONST_CACHE_HS_13:
931 case SQ_ALU_CONST_CACHE_HS_14:
932 case SQ_ALU_CONST_CACHE_HS_15:
933 case SQ_ALU_CONST_CACHE_LS_0:
934 case SQ_ALU_CONST_CACHE_LS_1:
935 case SQ_ALU_CONST_CACHE_LS_2:
936 case SQ_ALU_CONST_CACHE_LS_3:
937 case SQ_ALU_CONST_CACHE_LS_4:
938 case SQ_ALU_CONST_CACHE_LS_5:
939 case SQ_ALU_CONST_CACHE_LS_6:
940 case SQ_ALU_CONST_CACHE_LS_7:
941 case SQ_ALU_CONST_CACHE_LS_8:
942 case SQ_ALU_CONST_CACHE_LS_9:
943 case SQ_ALU_CONST_CACHE_LS_10:
944 case SQ_ALU_CONST_CACHE_LS_11:
945 case SQ_ALU_CONST_CACHE_LS_12:
946 case SQ_ALU_CONST_CACHE_LS_13:
947 case SQ_ALU_CONST_CACHE_LS_14:
948 case SQ_ALU_CONST_CACHE_LS_15:
949 r = evergreen_cs_packet_next_reloc(p, &reloc);
950 if (r) {
951 dev_warn(p->dev, "bad SET_CONTEXT_REG "
952 "0x%04X\n", reg);
953 return -EINVAL;
954 }
955 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
956 break;
957 default:
958 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
959 return -EINVAL;
960 }
961 return 0;
962 }
963
964 /**
965 * evergreen_check_texture_resource() - check if register is authorized or not
966 * @p: parser structure holding parsing context
967 * @idx: index into the cs buffer
968 * @texture: texture's bo structure
969 * @mipmap: mipmap's bo structure
970 *
971 * This function will check that the resource has valid field and that
972 * the texture and mipmap bo object are big enough to cover this resource.
973 */
974 static inline int evergreen_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
975 struct radeon_bo *texture,
976 struct radeon_bo *mipmap)
977 {
978 /* XXX fill in */
979 return 0;
980 }
981
982 static int evergreen_packet3_check(struct radeon_cs_parser *p,
983 struct radeon_cs_packet *pkt)
984 {
985 struct radeon_cs_reloc *reloc;
986 struct evergreen_cs_track *track;
987 volatile u32 *ib;
988 unsigned idx;
989 unsigned i;
990 unsigned start_reg, end_reg, reg;
991 int r;
992 u32 idx_value;
993
994 track = (struct evergreen_cs_track *)p->track;
995 ib = p->ib->ptr;
996 idx = pkt->idx + 1;
997 idx_value = radeon_get_ib_value(p, idx);
998
999 switch (pkt->opcode) {
1000 case PACKET3_SET_PREDICATION:
1001 {
1002 int pred_op;
1003 int tmp;
1004 if (pkt->count != 1) {
1005 DRM_ERROR("bad SET PREDICATION\n");
1006 return -EINVAL;
1007 }
1008
1009 tmp = radeon_get_ib_value(p, idx + 1);
1010 pred_op = (tmp >> 16) & 0x7;
1011
1012 /* for the clear predicate operation */
1013 if (pred_op == 0)
1014 return 0;
1015
1016 if (pred_op > 2) {
1017 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1018 return -EINVAL;
1019 }
1020
1021 r = evergreen_cs_packet_next_reloc(p, &reloc);
1022 if (r) {
1023 DRM_ERROR("bad SET PREDICATION\n");
1024 return -EINVAL;
1025 }
1026
1027 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1028 ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
1029 }
1030 break;
1031 case PACKET3_CONTEXT_CONTROL:
1032 if (pkt->count != 1) {
1033 DRM_ERROR("bad CONTEXT_CONTROL\n");
1034 return -EINVAL;
1035 }
1036 break;
1037 case PACKET3_INDEX_TYPE:
1038 case PACKET3_NUM_INSTANCES:
1039 case PACKET3_CLEAR_STATE:
1040 if (pkt->count) {
1041 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1042 return -EINVAL;
1043 }
1044 break;
1045 case CAYMAN_PACKET3_DEALLOC_STATE:
1046 if (p->rdev->family < CHIP_CAYMAN) {
1047 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
1048 return -EINVAL;
1049 }
1050 if (pkt->count) {
1051 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1052 return -EINVAL;
1053 }
1054 break;
1055 case PACKET3_INDEX_BASE:
1056 if (pkt->count != 1) {
1057 DRM_ERROR("bad INDEX_BASE\n");
1058 return -EINVAL;
1059 }
1060 r = evergreen_cs_packet_next_reloc(p, &reloc);
1061 if (r) {
1062 DRM_ERROR("bad INDEX_BASE\n");
1063 return -EINVAL;
1064 }
1065 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1066 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1067 r = evergreen_cs_track_check(p);
1068 if (r) {
1069 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1070 return r;
1071 }
1072 break;
1073 case PACKET3_DRAW_INDEX:
1074 if (pkt->count != 3) {
1075 DRM_ERROR("bad DRAW_INDEX\n");
1076 return -EINVAL;
1077 }
1078 r = evergreen_cs_packet_next_reloc(p, &reloc);
1079 if (r) {
1080 DRM_ERROR("bad DRAW_INDEX\n");
1081 return -EINVAL;
1082 }
1083 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1084 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1085 r = evergreen_cs_track_check(p);
1086 if (r) {
1087 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1088 return r;
1089 }
1090 break;
1091 case PACKET3_DRAW_INDEX_2:
1092 if (pkt->count != 4) {
1093 DRM_ERROR("bad DRAW_INDEX_2\n");
1094 return -EINVAL;
1095 }
1096 r = evergreen_cs_packet_next_reloc(p, &reloc);
1097 if (r) {
1098 DRM_ERROR("bad DRAW_INDEX_2\n");
1099 return -EINVAL;
1100 }
1101 ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1102 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1103 r = evergreen_cs_track_check(p);
1104 if (r) {
1105 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1106 return r;
1107 }
1108 break;
1109 case PACKET3_DRAW_INDEX_AUTO:
1110 if (pkt->count != 1) {
1111 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1112 return -EINVAL;
1113 }
1114 r = evergreen_cs_track_check(p);
1115 if (r) {
1116 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1117 return r;
1118 }
1119 break;
1120 case PACKET3_DRAW_INDEX_MULTI_AUTO:
1121 if (pkt->count != 2) {
1122 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
1123 return -EINVAL;
1124 }
1125 r = evergreen_cs_track_check(p);
1126 if (r) {
1127 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1128 return r;
1129 }
1130 break;
1131 case PACKET3_DRAW_INDEX_IMMD:
1132 if (pkt->count < 2) {
1133 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1134 return -EINVAL;
1135 }
1136 r = evergreen_cs_track_check(p);
1137 if (r) {
1138 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1139 return r;
1140 }
1141 break;
1142 case PACKET3_DRAW_INDEX_OFFSET:
1143 if (pkt->count != 2) {
1144 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
1145 return -EINVAL;
1146 }
1147 r = evergreen_cs_track_check(p);
1148 if (r) {
1149 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1150 return r;
1151 }
1152 break;
1153 case PACKET3_DRAW_INDEX_OFFSET_2:
1154 if (pkt->count != 3) {
1155 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
1156 return -EINVAL;
1157 }
1158 r = evergreen_cs_track_check(p);
1159 if (r) {
1160 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1161 return r;
1162 }
1163 break;
1164 case PACKET3_WAIT_REG_MEM:
1165 if (pkt->count != 5) {
1166 DRM_ERROR("bad WAIT_REG_MEM\n");
1167 return -EINVAL;
1168 }
1169 /* bit 4 is reg (0) or mem (1) */
1170 if (idx_value & 0x10) {
1171 r = evergreen_cs_packet_next_reloc(p, &reloc);
1172 if (r) {
1173 DRM_ERROR("bad WAIT_REG_MEM\n");
1174 return -EINVAL;
1175 }
1176 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1177 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1178 }
1179 break;
1180 case PACKET3_SURFACE_SYNC:
1181 if (pkt->count != 3) {
1182 DRM_ERROR("bad SURFACE_SYNC\n");
1183 return -EINVAL;
1184 }
1185 /* 0xffffffff/0x0 is flush all cache flag */
1186 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1187 radeon_get_ib_value(p, idx + 2) != 0) {
1188 r = evergreen_cs_packet_next_reloc(p, &reloc);
1189 if (r) {
1190 DRM_ERROR("bad SURFACE_SYNC\n");
1191 return -EINVAL;
1192 }
1193 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1194 }
1195 break;
1196 case PACKET3_EVENT_WRITE:
1197 if (pkt->count != 2 && pkt->count != 0) {
1198 DRM_ERROR("bad EVENT_WRITE\n");
1199 return -EINVAL;
1200 }
1201 if (pkt->count) {
1202 r = evergreen_cs_packet_next_reloc(p, &reloc);
1203 if (r) {
1204 DRM_ERROR("bad EVENT_WRITE\n");
1205 return -EINVAL;
1206 }
1207 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1208 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1209 }
1210 break;
1211 case PACKET3_EVENT_WRITE_EOP:
1212 if (pkt->count != 4) {
1213 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1214 return -EINVAL;
1215 }
1216 r = evergreen_cs_packet_next_reloc(p, &reloc);
1217 if (r) {
1218 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1219 return -EINVAL;
1220 }
1221 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1222 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1223 break;
1224 case PACKET3_EVENT_WRITE_EOS:
1225 if (pkt->count != 3) {
1226 DRM_ERROR("bad EVENT_WRITE_EOS\n");
1227 return -EINVAL;
1228 }
1229 r = evergreen_cs_packet_next_reloc(p, &reloc);
1230 if (r) {
1231 DRM_ERROR("bad EVENT_WRITE_EOS\n");
1232 return -EINVAL;
1233 }
1234 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1235 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1236 break;
1237 case PACKET3_SET_CONFIG_REG:
1238 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
1239 end_reg = 4 * pkt->count + start_reg - 4;
1240 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
1241 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1242 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1243 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1244 return -EINVAL;
1245 }
1246 for (i = 0; i < pkt->count; i++) {
1247 reg = start_reg + (4 * i);
1248 r = evergreen_cs_check_reg(p, reg, idx+1+i);
1249 if (r)
1250 return r;
1251 }
1252 break;
1253 case PACKET3_SET_CONTEXT_REG:
1254 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
1255 end_reg = 4 * pkt->count + start_reg - 4;
1256 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
1257 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1258 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1259 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1260 return -EINVAL;
1261 }
1262 for (i = 0; i < pkt->count; i++) {
1263 reg = start_reg + (4 * i);
1264 r = evergreen_cs_check_reg(p, reg, idx+1+i);
1265 if (r)
1266 return r;
1267 }
1268 break;
1269 case PACKET3_SET_RESOURCE:
1270 if (pkt->count % 8) {
1271 DRM_ERROR("bad SET_RESOURCE\n");
1272 return -EINVAL;
1273 }
1274 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
1275 end_reg = 4 * pkt->count + start_reg - 4;
1276 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
1277 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1278 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1279 DRM_ERROR("bad SET_RESOURCE\n");
1280 return -EINVAL;
1281 }
1282 for (i = 0; i < (pkt->count / 8); i++) {
1283 struct radeon_bo *texture, *mipmap;
1284 u32 size, offset;
1285
1286 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
1287 case SQ_TEX_VTX_VALID_TEXTURE:
1288 /* tex base */
1289 r = evergreen_cs_packet_next_reloc(p, &reloc);
1290 if (r) {
1291 DRM_ERROR("bad SET_RESOURCE (tex)\n");
1292 return -EINVAL;
1293 }
1294 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1295 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1296 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
1297 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1298 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
1299 texture = reloc->robj;
1300 /* tex mip base */
1301 r = evergreen_cs_packet_next_reloc(p, &reloc);
1302 if (r) {
1303 DRM_ERROR("bad SET_RESOURCE (tex)\n");
1304 return -EINVAL;
1305 }
1306 ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1307 mipmap = reloc->robj;
1308 r = evergreen_check_texture_resource(p, idx+1+(i*8),
1309 texture, mipmap);
1310 if (r)
1311 return r;
1312 break;
1313 case SQ_TEX_VTX_VALID_BUFFER:
1314 /* vtx base */
1315 r = evergreen_cs_packet_next_reloc(p, &reloc);
1316 if (r) {
1317 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
1318 return -EINVAL;
1319 }
1320 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
1321 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
1322 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1323 /* force size to size of the buffer */
1324 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1325 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj);
1326 }
1327 ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1328 ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1329 break;
1330 case SQ_TEX_VTX_INVALID_TEXTURE:
1331 case SQ_TEX_VTX_INVALID_BUFFER:
1332 default:
1333 DRM_ERROR("bad SET_RESOURCE\n");
1334 return -EINVAL;
1335 }
1336 }
1337 break;
1338 case PACKET3_SET_ALU_CONST:
1339 /* XXX fix me ALU const buffers only */
1340 break;
1341 case PACKET3_SET_BOOL_CONST:
1342 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
1343 end_reg = 4 * pkt->count + start_reg - 4;
1344 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
1345 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1346 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1347 DRM_ERROR("bad SET_BOOL_CONST\n");
1348 return -EINVAL;
1349 }
1350 break;
1351 case PACKET3_SET_LOOP_CONST:
1352 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
1353 end_reg = 4 * pkt->count + start_reg - 4;
1354 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
1355 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1356 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1357 DRM_ERROR("bad SET_LOOP_CONST\n");
1358 return -EINVAL;
1359 }
1360 break;
1361 case PACKET3_SET_CTL_CONST:
1362 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
1363 end_reg = 4 * pkt->count + start_reg - 4;
1364 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
1365 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1366 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1367 DRM_ERROR("bad SET_CTL_CONST\n");
1368 return -EINVAL;
1369 }
1370 break;
1371 case PACKET3_SET_SAMPLER:
1372 if (pkt->count % 3) {
1373 DRM_ERROR("bad SET_SAMPLER\n");
1374 return -EINVAL;
1375 }
1376 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
1377 end_reg = 4 * pkt->count + start_reg - 4;
1378 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
1379 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1380 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1381 DRM_ERROR("bad SET_SAMPLER\n");
1382 return -EINVAL;
1383 }
1384 break;
1385 case PACKET3_NOP:
1386 break;
1387 default:
1388 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1389 return -EINVAL;
1390 }
1391 return 0;
1392 }
1393
1394 int evergreen_cs_parse(struct radeon_cs_parser *p)
1395 {
1396 struct radeon_cs_packet pkt;
1397 struct evergreen_cs_track *track;
1398 int r;
1399
1400 if (p->track == NULL) {
1401 /* initialize tracker, we are in kms */
1402 track = kzalloc(sizeof(*track), GFP_KERNEL);
1403 if (track == NULL)
1404 return -ENOMEM;
1405 evergreen_cs_track_init(track);
1406 track->npipes = p->rdev->config.evergreen.tiling_npipes;
1407 track->nbanks = p->rdev->config.evergreen.tiling_nbanks;
1408 track->group_size = p->rdev->config.evergreen.tiling_group_size;
1409 p->track = track;
1410 }
1411 do {
1412 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
1413 if (r) {
1414 kfree(p->track);
1415 p->track = NULL;
1416 return r;
1417 }
1418 p->idx += pkt.count + 2;
1419 switch (pkt.type) {
1420 case PACKET_TYPE0:
1421 r = evergreen_cs_parse_packet0(p, &pkt);
1422 break;
1423 case PACKET_TYPE2:
1424 break;
1425 case PACKET_TYPE3:
1426 r = evergreen_packet3_check(p, &pkt);
1427 break;
1428 default:
1429 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1430 kfree(p->track);
1431 p->track = NULL;
1432 return -EINVAL;
1433 }
1434 if (r) {
1435 kfree(p->track);
1436 p->track = NULL;
1437 return r;
1438 }
1439 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1440 #if 0
1441 for (r = 0; r < p->ib->length_dw; r++) {
1442 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1443 mdelay(1);
1444 }
1445 #endif
1446 kfree(p->track);
1447 p->track = NULL;
1448 return 0;
1449 }
1450
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree