2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
225 const u8 command
, const u8 token
,
226 const u8 arg0
, const u8 arg1
)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev
))
236 mutex_lock(&rt2x00dev
->csr_mutex
);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
243 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
244 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
245 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
246 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
247 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
250 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
251 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
254 mutex_unlock(&rt2x00dev
->csr_mutex
);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
258 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
263 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
264 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
265 if (reg
&& reg
!= ~0)
270 ERROR(rt2x00dev
, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
285 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
286 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
287 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
293 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
298 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
308 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
317 crc
= crc_ccitt(~0, data
, len
- 2);
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
327 return fw_crc
== crc
;
330 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
331 const u8
*data
, const size_t len
)
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
345 if (rt2x00_is_usb(rt2x00dev
)) {
354 * Validate the firmware length
356 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
357 return FW_BAD_LENGTH
;
360 * Check if the chipset requires one of the upper parts
363 if (rt2x00_is_usb(rt2x00dev
) &&
364 !rt2x00_rt(rt2x00dev
, RT2860
) &&
365 !rt2x00_rt(rt2x00dev
, RT2872
) &&
366 !rt2x00_rt(rt2x00dev
, RT3070
) &&
367 ((len
/ fw_len
) == 1))
368 return FW_BAD_VERSION
;
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
374 while (offset
< len
) {
375 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
385 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
386 const u8
*data
, const size_t len
)
392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
395 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
398 * Wait for stable hardware.
400 if (rt2800_wait_csr_ready(rt2x00dev
))
403 if (rt2x00_is_pci(rt2x00dev
)) {
404 if (rt2x00_rt(rt2x00dev
, RT3572
) ||
405 rt2x00_rt(rt2x00dev
, RT5390
)) {
406 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
407 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
408 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
409 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
411 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
415 * Disable DMA, will be reenabled later when enabling
418 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
419 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
420 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
421 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
422 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
423 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
424 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
427 * Write firmware to the device.
429 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
432 * Wait for device to stabilize.
434 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
435 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
436 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
441 if (i
== REGISTER_BUSY_COUNT
) {
442 ERROR(rt2x00dev
, "PBF system register not ready.\n");
447 * Initialize firmware.
449 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
450 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
455 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
457 void rt2800_write_tx_data(struct queue_entry
*entry
,
458 struct txentry_desc
*txdesc
)
460 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
464 * Initialize TX Info descriptor
466 rt2x00_desc_read(txwi
, 0, &word
);
467 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
468 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
469 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
470 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
471 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
472 rt2x00_set_field32(&word
, TXWI_W0_TS
,
473 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
474 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
475 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
476 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
477 txdesc
->u
.ht
.mpdu_density
);
478 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
479 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
480 rt2x00_set_field32(&word
, TXWI_W0_BW
,
481 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
482 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
483 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
484 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
485 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
486 rt2x00_desc_write(txwi
, 0, word
);
488 rt2x00_desc_read(txwi
, 1, &word
);
489 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
490 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
491 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
492 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
493 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
494 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
495 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
496 txdesc
->key_idx
: txdesc
->u
.ht
.wcid
);
497 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
499 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
500 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
501 rt2x00_desc_write(txwi
, 1, word
);
504 * Always write 0 to IV/EIV fields, hardware will insert the IV
505 * from the IVEIV register when TXD_W3_WIV is set to 0.
506 * When TXD_W3_WIV is set to 1 it will use the IV data
507 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
508 * crypto entry in the registers should be used to encrypt the frame.
510 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
511 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
515 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
517 int rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
518 int rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
519 int rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
525 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
526 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
527 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
528 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
529 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
530 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
532 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
533 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
534 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
535 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
536 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
540 * Convert the value from the descriptor into the RSSI value
541 * If the value in the descriptor is 0, it is considered invalid
542 * and the default (extremely low) rssi value is assumed
544 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
545 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
546 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
549 * mac80211 only accepts a single RSSI value. Calculating the
550 * average doesn't deliver a fair answer either since -60:-60 would
551 * be considered equally good as -50:-70 while the second is the one
552 * which gives less energy...
554 rssi0
= max(rssi0
, rssi1
);
555 return max(rssi0
, rssi2
);
558 void rt2800_process_rxwi(struct queue_entry
*entry
,
559 struct rxdone_entry_desc
*rxdesc
)
561 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
564 rt2x00_desc_read(rxwi
, 0, &word
);
566 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
567 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
569 rt2x00_desc_read(rxwi
, 1, &word
);
571 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
572 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
574 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
575 rxdesc
->flags
|= RX_FLAG_40MHZ
;
578 * Detect RX rate, always use MCS as signal type.
580 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
581 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
582 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
585 * Mask of 0x8 bit to remove the short preamble flag.
587 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
588 rxdesc
->signal
&= ~0x8;
590 rt2x00_desc_read(rxwi
, 2, &word
);
593 * Convert descriptor AGC value to RSSI value.
595 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
598 * Remove RXWI descriptor from start of buffer.
600 skb_pull(entry
->skb
, RXWI_DESC_SIZE
);
602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
604 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
606 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
607 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
608 struct txdone_entry_desc txdesc
;
614 * Obtain the status about this packet.
617 rt2x00_desc_read(txwi
, 0, &word
);
619 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
620 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
622 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
623 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
626 * If a frame was meant to be sent as a single non-aggregated MPDU
627 * but ended up in an aggregate the used tx rate doesn't correlate
628 * with the one specified in the TXWI as the whole aggregate is sent
629 * with the same rate.
631 * For example: two frames are sent to rt2x00, the first one sets
632 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
633 * and requests MCS15. If the hw aggregates both frames into one
634 * AMDPU the tx status for both frames will contain MCS7 although
635 * the frame was sent successfully.
637 * Hence, replace the requested rate with the real tx rate to not
638 * confuse the rate control algortihm by providing clearly wrong
641 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
642 skbdesc
->tx_rate_idx
= real_mcs
;
646 if (aggr
== 1 || ampdu
== 1)
647 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
650 * Ralink has a retry mechanism using a global fallback
651 * table. We setup this fallback table to try the immediate
652 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
653 * always contains the MCS used for the last transmission, be
654 * it successful or not.
656 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
658 * Transmission succeeded. The number of retries is
661 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
662 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
665 * Transmission failed. The number of retries is
666 * always 7 in this case (for a total number of 8
669 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
670 txdesc
.retry
= rt2x00dev
->long_retry
;
674 * the frame was retried at least once
675 * -> hw used fallback rates
678 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
680 rt2x00lib_txdone(entry
, &txdesc
);
682 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
684 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
686 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
687 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
688 unsigned int beacon_base
;
689 unsigned int padding_len
;
693 * Disable beaconing while we are reloading the beacon data,
694 * otherwise we might be sending out invalid data.
696 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
698 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
699 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
702 * Add space for the TXWI in front of the skb.
704 memset(skb_push(entry
->skb
, TXWI_DESC_SIZE
), 0, TXWI_DESC_SIZE
);
707 * Register descriptor details in skb frame descriptor.
709 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
710 skbdesc
->desc
= entry
->skb
->data
;
711 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
714 * Add the TXWI for the beacon to the skb.
716 rt2800_write_tx_data(entry
, txdesc
);
719 * Dump beacon to userspace through debugfs.
721 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
724 * Write entire beacon with TXWI and padding to register.
726 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
727 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
728 ERROR(rt2x00dev
, "Failure padding beacon, aborting\n");
729 /* skb freed by skb_pad() on failure */
731 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
735 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
736 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
737 entry
->skb
->len
+ padding_len
);
740 * Enable beaconing again.
742 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
743 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
746 * Clean up beacon skb.
748 dev_kfree_skb_any(entry
->skb
);
751 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
753 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
754 unsigned int beacon_base
)
759 * For the Beacon base registers we only need to clear
760 * the whole TXWI which (when set to 0) will invalidate
763 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
764 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
767 void rt2800_clear_beacon(struct queue_entry
*entry
)
769 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
773 * Disable beaconing while we are reloading the beacon data,
774 * otherwise we might be sending out invalid data.
776 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
777 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
778 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
783 rt2800_clear_beacon_register(rt2x00dev
,
784 HW_BEACON_OFFSET(entry
->entry_idx
));
787 * Enabled beaconing again.
789 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
790 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
792 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
794 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
795 const struct rt2x00debug rt2800_rt2x00debug
= {
796 .owner
= THIS_MODULE
,
798 .read
= rt2800_register_read
,
799 .write
= rt2800_register_write
,
800 .flags
= RT2X00DEBUGFS_OFFSET
,
801 .word_base
= CSR_REG_BASE
,
802 .word_size
= sizeof(u32
),
803 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
806 .read
= rt2x00_eeprom_read
,
807 .write
= rt2x00_eeprom_write
,
808 .word_base
= EEPROM_BASE
,
809 .word_size
= sizeof(u16
),
810 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
813 .read
= rt2800_bbp_read
,
814 .write
= rt2800_bbp_write
,
815 .word_base
= BBP_BASE
,
816 .word_size
= sizeof(u8
),
817 .word_count
= BBP_SIZE
/ sizeof(u8
),
820 .read
= rt2x00_rf_read
,
821 .write
= rt2800_rf_write
,
822 .word_base
= RF_BASE
,
823 .word_size
= sizeof(u32
),
824 .word_count
= RF_SIZE
/ sizeof(u32
),
827 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
828 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
830 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
834 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
835 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
837 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
839 #ifdef CONFIG_RT2X00_LIB_LEDS
840 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
841 enum led_brightness brightness
)
843 struct rt2x00_led
*led
=
844 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
845 unsigned int enabled
= brightness
!= LED_OFF
;
846 unsigned int bg_mode
=
847 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
848 unsigned int polarity
=
849 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
850 EEPROM_FREQ_LED_POLARITY
);
851 unsigned int ledmode
=
852 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
853 EEPROM_FREQ_LED_MODE
);
856 /* Check for SoC (SOC devices don't support MCU requests) */
857 if (rt2x00_is_soc(led
->rt2x00dev
)) {
858 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
860 /* Set LED Polarity */
861 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
864 if (led
->type
== LED_TYPE_RADIO
) {
865 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
867 } else if (led
->type
== LED_TYPE_ASSOC
) {
868 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
870 } else if (led
->type
== LED_TYPE_QUALITY
) {
871 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
875 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
878 if (led
->type
== LED_TYPE_RADIO
) {
879 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
881 } else if (led
->type
== LED_TYPE_ASSOC
) {
882 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
883 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
884 } else if (led
->type
== LED_TYPE_QUALITY
) {
886 * The brightness is divided into 6 levels (0 - 5),
887 * The specs tell us the following levels:
889 * to determine the level in a simple way we can simply
890 * work with bitshifting:
893 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
894 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
900 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
901 struct rt2x00_led
*led
, enum led_type type
)
903 led
->rt2x00dev
= rt2x00dev
;
905 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
906 led
->flags
= LED_INITIALIZED
;
908 #endif /* CONFIG_RT2X00_LIB_LEDS */
911 * Configuration handlers.
913 static void rt2800_config_wcid(struct rt2x00_dev
*rt2x00dev
,
917 struct mac_wcid_entry wcid_entry
;
920 offset
= MAC_WCID_ENTRY(wcid
);
922 memset(&wcid_entry
, 0xff, sizeof(wcid_entry
));
924 memcpy(wcid_entry
.mac
, address
, ETH_ALEN
);
926 rt2800_register_multiwrite(rt2x00dev
, offset
,
927 &wcid_entry
, sizeof(wcid_entry
));
930 static void rt2800_delete_wcid_attr(struct rt2x00_dev
*rt2x00dev
, int wcid
)
933 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
934 rt2800_register_write(rt2x00dev
, offset
, 0);
937 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev
*rt2x00dev
,
938 int wcid
, u32 bssidx
)
940 u32 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
944 * The BSS Idx numbers is split in a main value of 3 bits,
945 * and a extended field for adding one additional bit to the value.
947 rt2800_register_read(rt2x00dev
, offset
, ®
);
948 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
, (bssidx
& 0x7));
949 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
950 (bssidx
& 0x8) >> 3);
951 rt2800_register_write(rt2x00dev
, offset
, reg
);
954 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev
*rt2x00dev
,
955 struct rt2x00lib_crypto
*crypto
,
956 struct ieee80211_key_conf
*key
)
958 struct mac_iveiv_entry iveiv_entry
;
962 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
964 if (crypto
->cmd
== SET_KEY
) {
965 rt2800_register_read(rt2x00dev
, offset
, ®
);
966 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
967 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
969 * Both the cipher as the BSS Idx numbers are split in a main
970 * value of 3 bits, and a extended field for adding one additional
973 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
974 (crypto
->cipher
& 0x7));
975 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
976 (crypto
->cipher
& 0x8) >> 3);
977 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
978 rt2800_register_write(rt2x00dev
, offset
, reg
);
980 /* Delete the cipher without touching the bssidx */
981 rt2800_register_read(rt2x00dev
, offset
, ®
);
982 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
, 0);
983 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
, 0);
984 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
, 0);
985 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, 0);
986 rt2800_register_write(rt2x00dev
, offset
, reg
);
989 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
991 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
992 if ((crypto
->cipher
== CIPHER_TKIP
) ||
993 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
994 (crypto
->cipher
== CIPHER_AES
))
995 iveiv_entry
.iv
[3] |= 0x20;
996 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
997 rt2800_register_multiwrite(rt2x00dev
, offset
,
998 &iveiv_entry
, sizeof(iveiv_entry
));
1001 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1002 struct rt2x00lib_crypto
*crypto
,
1003 struct ieee80211_key_conf
*key
)
1005 struct hw_key_entry key_entry
;
1006 struct rt2x00_field32 field
;
1010 if (crypto
->cmd
== SET_KEY
) {
1011 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1013 memcpy(key_entry
.key
, crypto
->key
,
1014 sizeof(key_entry
.key
));
1015 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1016 sizeof(key_entry
.tx_mic
));
1017 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1018 sizeof(key_entry
.rx_mic
));
1020 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1021 rt2800_register_multiwrite(rt2x00dev
, offset
,
1022 &key_entry
, sizeof(key_entry
));
1026 * The cipher types are stored over multiple registers
1027 * starting with SHARED_KEY_MODE_BASE each word will have
1028 * 32 bits and contains the cipher types for 2 bssidx each.
1029 * Using the correct defines correctly will cause overhead,
1030 * so just calculate the correct offset.
1032 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1033 field
.bit_mask
= 0x7 << field
.bit_offset
;
1035 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1037 rt2800_register_read(rt2x00dev
, offset
, ®
);
1038 rt2x00_set_field32(®
, field
,
1039 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1040 rt2800_register_write(rt2x00dev
, offset
, reg
);
1043 * Update WCID information
1045 rt2800_config_wcid(rt2x00dev
, crypto
->address
, key
->hw_key_idx
);
1046 rt2800_config_wcid_attr_bssidx(rt2x00dev
, key
->hw_key_idx
,
1048 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1052 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1054 static inline int rt2800_find_wcid(struct rt2x00_dev
*rt2x00dev
)
1056 struct mac_wcid_entry wcid_entry
;
1061 * Search for the first free WCID entry and return the corresponding
1064 * Make sure the WCID starts _after_ the last possible shared key
1067 * Since parts of the pairwise key table might be shared with
1068 * the beacon frame buffers 6 & 7 we should only write into the
1069 * first 222 entries.
1071 for (idx
= 33; idx
<= 222; idx
++) {
1072 offset
= MAC_WCID_ENTRY(idx
);
1073 rt2800_register_multiread(rt2x00dev
, offset
, &wcid_entry
,
1074 sizeof(wcid_entry
));
1075 if (is_broadcast_ether_addr(wcid_entry
.mac
))
1080 * Use -1 to indicate that we don't have any more space in the WCID
1086 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1087 struct rt2x00lib_crypto
*crypto
,
1088 struct ieee80211_key_conf
*key
)
1090 struct hw_key_entry key_entry
;
1093 if (crypto
->cmd
== SET_KEY
) {
1095 * Allow key configuration only for STAs that are
1098 if (crypto
->wcid
< 0)
1100 key
->hw_key_idx
= crypto
->wcid
;
1102 memcpy(key_entry
.key
, crypto
->key
,
1103 sizeof(key_entry
.key
));
1104 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1105 sizeof(key_entry
.tx_mic
));
1106 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1107 sizeof(key_entry
.rx_mic
));
1109 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1110 rt2800_register_multiwrite(rt2x00dev
, offset
,
1111 &key_entry
, sizeof(key_entry
));
1115 * Update WCID information
1117 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1121 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1123 int rt2800_sta_add(struct rt2x00_dev
*rt2x00dev
, struct ieee80211_vif
*vif
,
1124 struct ieee80211_sta
*sta
)
1127 struct rt2x00_sta
*sta_priv
= sta_to_rt2x00_sta(sta
);
1130 * Find next free WCID.
1132 wcid
= rt2800_find_wcid(rt2x00dev
);
1135 * Store selected wcid even if it is invalid so that we can
1136 * later decide if the STA is uploaded into the hw.
1138 sta_priv
->wcid
= wcid
;
1141 * No space left in the device, however, we can still communicate
1142 * with the STA -> No error.
1148 * Clean up WCID attributes and write STA address to the device.
1150 rt2800_delete_wcid_attr(rt2x00dev
, wcid
);
1151 rt2800_config_wcid(rt2x00dev
, sta
->addr
, wcid
);
1152 rt2800_config_wcid_attr_bssidx(rt2x00dev
, wcid
,
1153 rt2x00lib_get_bssidx(rt2x00dev
, vif
));
1156 EXPORT_SYMBOL_GPL(rt2800_sta_add
);
1158 int rt2800_sta_remove(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1161 * Remove WCID entry, no need to clean the attributes as they will
1162 * get renewed when the WCID is reused.
1164 rt2800_config_wcid(rt2x00dev
, NULL
, wcid
);
1168 EXPORT_SYMBOL_GPL(rt2800_sta_remove
);
1170 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1171 const unsigned int filter_flags
)
1176 * Start configuration steps.
1177 * Note that the version error will always be dropped
1178 * and broadcast frames will always be accepted since
1179 * there is no filter for it at this time.
1181 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1182 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1183 !(filter_flags
& FIF_FCSFAIL
));
1184 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1185 !(filter_flags
& FIF_PLCPFAIL
));
1186 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1187 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1188 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1189 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1190 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1191 !(filter_flags
& FIF_ALLMULTI
));
1192 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1193 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1194 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1195 !(filter_flags
& FIF_CONTROL
));
1196 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1197 !(filter_flags
& FIF_CONTROL
));
1198 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1199 !(filter_flags
& FIF_CONTROL
));
1200 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1201 !(filter_flags
& FIF_CONTROL
));
1202 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1203 !(filter_flags
& FIF_CONTROL
));
1204 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1205 !(filter_flags
& FIF_PSPOLL
));
1206 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
1207 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
1208 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1209 !(filter_flags
& FIF_CONTROL
));
1210 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1212 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1214 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1215 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1218 bool update_bssid
= false;
1220 if (flags
& CONFIG_UPDATE_TYPE
) {
1222 * Enable synchronisation.
1224 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1225 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1226 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1228 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1230 * Tune beacon queue transmit parameters for AP mode
1232 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1233 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1234 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1235 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1236 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1237 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1239 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1240 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1241 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1242 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1243 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1244 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1248 if (flags
& CONFIG_UPDATE_MAC
) {
1249 if (flags
& CONFIG_UPDATE_TYPE
&&
1250 conf
->sync
== TSF_SYNC_AP_NONE
) {
1252 * The BSSID register has to be set to our own mac
1253 * address in AP mode.
1255 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1256 update_bssid
= true;
1259 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1260 reg
= le32_to_cpu(conf
->mac
[1]);
1261 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1262 conf
->mac
[1] = cpu_to_le32(reg
);
1265 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1266 conf
->mac
, sizeof(conf
->mac
));
1269 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1270 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1271 reg
= le32_to_cpu(conf
->bssid
[1]);
1272 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1273 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1274 conf
->bssid
[1] = cpu_to_le32(reg
);
1277 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1278 conf
->bssid
, sizeof(conf
->bssid
));
1281 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1283 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1284 struct rt2x00lib_erp
*erp
)
1286 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1287 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1288 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1289 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1290 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1293 /* default protection rate for HT20: OFDM 24M */
1294 mm20_rate
= gf20_rate
= 0x4004;
1296 /* default protection rate for HT40: duplicate OFDM 24M */
1297 mm40_rate
= gf40_rate
= 0x4084;
1299 switch (protection
) {
1300 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1302 * All STAs in this BSS are HT20/40 but there might be
1303 * STAs not supporting greenfield mode.
1304 * => Disable protection for HT transmissions.
1306 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1309 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1311 * All STAs in this BSS are HT20 or HT20/40 but there
1312 * might be STAs not supporting greenfield mode.
1313 * => Protect all HT40 transmissions.
1315 mm20_mode
= gf20_mode
= 0;
1316 mm40_mode
= gf40_mode
= 2;
1319 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1321 * Nonmember protection:
1322 * According to 802.11n we _should_ protect all
1323 * HT transmissions (but we don't have to).
1325 * But if cts_protection is enabled we _shall_ protect
1326 * all HT transmissions using a CCK rate.
1328 * And if any station is non GF we _shall_ protect
1331 * We decide to protect everything
1332 * -> fall through to mixed mode.
1334 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1336 * Legacy STAs are present
1337 * => Protect all HT transmissions.
1339 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1342 * If erp protection is needed we have to protect HT
1343 * transmissions with CCK 11M long preamble.
1345 if (erp
->cts_protection
) {
1346 /* don't duplicate RTS/CTS in CCK mode */
1347 mm20_rate
= mm40_rate
= 0x0003;
1348 gf20_rate
= gf40_rate
= 0x0003;
1353 /* check for STAs not supporting greenfield mode */
1355 gf20_mode
= gf40_mode
= 2;
1357 /* Update HT protection config */
1358 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1359 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1360 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1361 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1363 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1364 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1365 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1366 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1368 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1369 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1370 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1371 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1373 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1374 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1375 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1376 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1379 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1384 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1385 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1386 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1387 !!erp
->short_preamble
);
1388 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1389 !!erp
->short_preamble
);
1390 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1393 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1394 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1395 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1396 erp
->cts_protection
? 2 : 0);
1397 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1400 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1401 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1403 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1406 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1407 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1408 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1410 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1412 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1413 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1414 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1417 if (changed
& BSS_CHANGED_BEACON_INT
) {
1418 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1419 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1420 erp
->beacon_int
* 16);
1421 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1424 if (changed
& BSS_CHANGED_HT
)
1425 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1427 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1429 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1433 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1435 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1436 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1437 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1438 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1440 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1441 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1443 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1445 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1446 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1447 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1448 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1449 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1450 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1451 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1452 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1453 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1454 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1455 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1457 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1458 (led_g_mode
<< 2) | led_r_mode
, 1);
1463 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1467 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1468 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1470 if (rt2x00_is_pci(rt2x00dev
)) {
1471 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1472 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1473 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1474 } else if (rt2x00_is_usb(rt2x00dev
))
1475 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1478 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1479 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
1480 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, gpio_bit3
);
1481 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1484 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1490 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1491 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1493 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1494 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1495 rt2800_config_3572bt_ant(rt2x00dev
);
1498 * Configure the TX antenna.
1500 switch (ant
->tx_chain_num
) {
1502 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1505 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1506 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1507 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1509 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1512 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1517 * Configure the RX antenna.
1519 switch (ant
->rx_chain_num
) {
1521 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1522 rt2x00_rt(rt2x00dev
, RT3090
) ||
1523 rt2x00_rt(rt2x00dev
, RT3390
)) {
1524 rt2x00_eeprom_read(rt2x00dev
,
1525 EEPROM_NIC_CONF1
, &eeprom
);
1526 if (rt2x00_get_field16(eeprom
,
1527 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1528 rt2800_set_ant_diversity(rt2x00dev
,
1529 rt2x00dev
->default_ant
.rx
);
1531 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1534 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1535 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1536 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1537 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1538 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1539 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1541 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1545 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1549 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1550 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1552 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1554 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1555 struct rt2x00lib_conf
*libconf
)
1560 if (libconf
->rf
.channel
<= 14) {
1561 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1562 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1563 } else if (libconf
->rf
.channel
<= 64) {
1564 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1565 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1566 } else if (libconf
->rf
.channel
<= 128) {
1567 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1568 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1570 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1571 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1574 rt2x00dev
->lna_gain
= lna_gain
;
1577 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1578 struct ieee80211_conf
*conf
,
1579 struct rf_channel
*rf
,
1580 struct channel_info
*info
)
1582 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1584 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1585 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1587 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1588 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1589 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1590 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1591 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1593 if (rf
->channel
> 14) {
1595 * When TX power is below 0, we should increase it by 7 to
1596 * make it a positive value (Minimum value is -7).
1597 * However this means that values between 0 and 7 have
1598 * double meaning, and we should set a 7DBm boost flag.
1600 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1601 (info
->default_power1
>= 0));
1603 if (info
->default_power1
< 0)
1604 info
->default_power1
+= 7;
1606 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1608 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1609 (info
->default_power2
>= 0));
1611 if (info
->default_power2
< 0)
1612 info
->default_power2
+= 7;
1614 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1616 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1617 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1620 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1622 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1623 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1624 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1625 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1629 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1630 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1631 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1632 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1636 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1637 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1638 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1639 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1642 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1643 struct ieee80211_conf
*conf
,
1644 struct rf_channel
*rf
,
1645 struct channel_info
*info
)
1649 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1650 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1652 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1653 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1654 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1656 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1657 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1658 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1660 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1661 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1662 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1664 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1665 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1666 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1668 rt2800_rfcsr_write(rt2x00dev
, 24,
1669 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1671 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1672 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1673 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1676 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
1677 struct ieee80211_conf
*conf
,
1678 struct rf_channel
*rf
,
1679 struct channel_info
*info
)
1684 if (rf
->channel
<= 14) {
1685 rt2800_bbp_write(rt2x00dev
, 25, 0x15);
1686 rt2800_bbp_write(rt2x00dev
, 26, 0x85);
1688 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
1689 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
1692 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1693 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1695 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1696 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1697 if (rf
->channel
<= 14)
1698 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
1700 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
1701 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1703 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
1704 if (rf
->channel
<= 14)
1705 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
1707 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
1708 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
1710 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1711 if (rf
->channel
<= 14) {
1712 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
1713 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1714 (info
->default_power1
& 0x3) |
1715 ((info
->default_power1
& 0xC) << 1));
1717 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
1718 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1719 (info
->default_power1
& 0x3) |
1720 ((info
->default_power1
& 0xC) << 1));
1722 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1724 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1725 if (rf
->channel
<= 14) {
1726 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
1727 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1728 (info
->default_power2
& 0x3) |
1729 ((info
->default_power2
& 0xC) << 1));
1731 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
1732 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1733 (info
->default_power2
& 0x3) |
1734 ((info
->default_power2
& 0xC) << 1));
1736 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1738 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1739 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1740 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1741 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1742 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
1743 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
1744 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1745 if (rf
->channel
<= 14) {
1746 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1747 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1749 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1750 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1752 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
1754 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1756 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1760 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
1762 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1764 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1768 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1770 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1771 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1772 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1774 rt2800_rfcsr_write(rt2x00dev
, 24,
1775 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1776 rt2800_rfcsr_write(rt2x00dev
, 31,
1777 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1779 if (rf
->channel
<= 14) {
1780 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
1781 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
1782 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1783 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
1784 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1785 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
1786 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1787 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
1788 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
1789 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
1790 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1791 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1792 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
1794 rt2800_rfcsr_write(rt2x00dev
, 7, 0x14);
1795 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1796 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1797 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
1798 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
1799 rt2800_rfcsr_write(rt2x00dev
, 16, 0x7a);
1800 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1801 if (rf
->channel
<= 64) {
1802 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
1803 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
1804 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1805 } else if (rf
->channel
<= 128) {
1806 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
1807 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
1808 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1810 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
1811 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
1812 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1814 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
1815 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
1816 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
1819 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1820 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT7
, 0);
1821 if (rf
->channel
<= 14)
1822 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 1);
1824 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 0);
1825 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1827 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1828 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1829 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1832 #define RT5390_POWER_BOUND 0x27
1833 #define RT5390_FREQ_OFFSET_BOUND 0x5f
1835 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
1836 struct ieee80211_conf
*conf
,
1837 struct rf_channel
*rf
,
1838 struct channel_info
*info
)
1842 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
1843 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
1844 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
1845 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
1846 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
1848 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
1849 if (info
->default_power1
> RT5390_POWER_BOUND
)
1850 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, RT5390_POWER_BOUND
);
1852 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
1853 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
1855 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1856 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1857 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
1858 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1859 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1860 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1862 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1863 if (rt2x00dev
->freq_offset
> RT5390_FREQ_OFFSET_BOUND
)
1864 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
,
1865 RT5390_FREQ_OFFSET_BOUND
);
1867 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
1868 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1870 if (rf
->channel
<= 14) {
1871 int idx
= rf
->channel
-1;
1873 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1874 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
1875 /* r55/r59 value array of channel 1~14 */
1876 static const char r55_bt_rev
[] = {0x83, 0x83,
1877 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1878 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1879 static const char r59_bt_rev
[] = {0x0e, 0x0e,
1880 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1881 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1883 rt2800_rfcsr_write(rt2x00dev
, 55,
1885 rt2800_rfcsr_write(rt2x00dev
, 59,
1888 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
1889 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1890 0x88, 0x88, 0x86, 0x85, 0x84};
1892 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
1895 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
1896 static const char r55_nonbt_rev
[] = {0x23, 0x23,
1897 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1898 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1899 static const char r59_nonbt_rev
[] = {0x07, 0x07,
1900 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1901 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1903 rt2800_rfcsr_write(rt2x00dev
, 55,
1904 r55_nonbt_rev
[idx
]);
1905 rt2800_rfcsr_write(rt2x00dev
, 59,
1906 r59_nonbt_rev
[idx
]);
1907 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
1908 static const char r59_non_bt
[] = {0x8f, 0x8f,
1909 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1910 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1912 rt2800_rfcsr_write(rt2x00dev
, 59,
1918 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1919 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
1920 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
1921 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1923 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1924 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1925 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1928 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
1929 struct ieee80211_conf
*conf
,
1930 struct rf_channel
*rf
,
1931 struct channel_info
*info
)
1934 unsigned int tx_pin
;
1937 if (rf
->channel
<= 14) {
1938 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
1939 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
1941 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
1942 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
1945 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
1946 rt2x00_rf(rt2x00dev
, RF3020
) ||
1947 rt2x00_rf(rt2x00dev
, RF3021
) ||
1948 rt2x00_rf(rt2x00dev
, RF3022
) ||
1949 rt2x00_rf(rt2x00dev
, RF3320
))
1950 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
1951 else if (rt2x00_rf(rt2x00dev
, RF3052
))
1952 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
1953 else if (rt2x00_rf(rt2x00dev
, RF5370
) ||
1954 rt2x00_rf(rt2x00dev
, RF5390
))
1955 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
1957 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
1960 * Change BBP settings
1962 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
1963 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
1964 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
1965 rt2800_bbp_write(rt2x00dev
, 86, 0);
1967 if (rf
->channel
<= 14) {
1968 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
1969 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
1970 &rt2x00dev
->cap_flags
)) {
1971 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1972 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1974 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
1975 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1979 if (rt2x00_rt(rt2x00dev
, RT3572
))
1980 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
1982 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
1984 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
1985 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1987 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1990 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
1991 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
1992 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
1993 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
1994 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
1996 if (rt2x00_rt(rt2x00dev
, RT3572
))
1997 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
2001 /* Turn on unused PA or LNA when not using 1T or 1R */
2002 if (rt2x00dev
->default_ant
.tx_chain_num
== 2) {
2003 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
2005 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
2009 /* Turn on unused PA or LNA when not using 1T or 1R */
2010 if (rt2x00dev
->default_ant
.rx_chain_num
== 2) {
2011 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
2012 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
2015 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
2016 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
2017 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
2018 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
2019 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
2020 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
2022 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
2024 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
2026 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2028 if (rt2x00_rt(rt2x00dev
, RT3572
))
2029 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
2031 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2032 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
2033 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2035 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
2036 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
2037 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
2039 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2040 if (conf_is_ht40(conf
)) {
2041 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
2042 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2043 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
2045 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2046 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
2047 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
2054 * Clear channel statistic counters
2056 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
2057 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
2058 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
2061 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
2070 * Read TSSI boundaries for temperature compensation from
2073 * Array idx 0 1 2 3 4 5 6 7 8
2074 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2075 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2077 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2078 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
2079 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2080 EEPROM_TSSI_BOUND_BG1_MINUS4
);
2081 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2082 EEPROM_TSSI_BOUND_BG1_MINUS3
);
2084 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
2085 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2086 EEPROM_TSSI_BOUND_BG2_MINUS2
);
2087 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2088 EEPROM_TSSI_BOUND_BG2_MINUS1
);
2090 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
2091 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2092 EEPROM_TSSI_BOUND_BG3_REF
);
2093 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2094 EEPROM_TSSI_BOUND_BG3_PLUS1
);
2096 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
2097 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2098 EEPROM_TSSI_BOUND_BG4_PLUS2
);
2099 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2100 EEPROM_TSSI_BOUND_BG4_PLUS3
);
2102 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
2103 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2104 EEPROM_TSSI_BOUND_BG5_PLUS4
);
2106 step
= rt2x00_get_field16(eeprom
,
2107 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
2109 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
2110 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2111 EEPROM_TSSI_BOUND_A1_MINUS4
);
2112 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2113 EEPROM_TSSI_BOUND_A1_MINUS3
);
2115 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
2116 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2117 EEPROM_TSSI_BOUND_A2_MINUS2
);
2118 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2119 EEPROM_TSSI_BOUND_A2_MINUS1
);
2121 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
2122 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2123 EEPROM_TSSI_BOUND_A3_REF
);
2124 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2125 EEPROM_TSSI_BOUND_A3_PLUS1
);
2127 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
2128 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2129 EEPROM_TSSI_BOUND_A4_PLUS2
);
2130 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2131 EEPROM_TSSI_BOUND_A4_PLUS3
);
2133 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
2134 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2135 EEPROM_TSSI_BOUND_A5_PLUS4
);
2137 step
= rt2x00_get_field16(eeprom
,
2138 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
2142 * Check if temperature compensation is supported.
2144 if (tssi_bounds
[4] == 0xff)
2148 * Read current TSSI (BBP 49).
2150 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
2153 * Compare TSSI value (BBP49) with the compensation boundaries
2154 * from the EEPROM and increase or decrease tx power.
2156 for (i
= 0; i
<= 3; i
++) {
2157 if (current_tssi
> tssi_bounds
[i
])
2162 for (i
= 8; i
>= 5; i
--) {
2163 if (current_tssi
< tssi_bounds
[i
])
2168 return (i
- 4) * step
;
2171 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
2172 enum ieee80211_band band
)
2179 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
2182 * HT40 compensation not required.
2184 if (eeprom
== 0xffff ||
2185 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2188 if (band
== IEEE80211_BAND_2GHZ
) {
2189 comp_en
= rt2x00_get_field16(eeprom
,
2190 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
2192 comp_type
= rt2x00_get_field16(eeprom
,
2193 EEPROM_TXPOWER_DELTA_TYPE_2G
);
2194 comp_value
= rt2x00_get_field16(eeprom
,
2195 EEPROM_TXPOWER_DELTA_VALUE_2G
);
2197 comp_value
= -comp_value
;
2200 comp_en
= rt2x00_get_field16(eeprom
,
2201 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
2203 comp_type
= rt2x00_get_field16(eeprom
,
2204 EEPROM_TXPOWER_DELTA_TYPE_5G
);
2205 comp_value
= rt2x00_get_field16(eeprom
,
2206 EEPROM_TXPOWER_DELTA_VALUE_5G
);
2208 comp_value
= -comp_value
;
2215 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
2216 enum ieee80211_band band
, int power_level
,
2217 u8 txpower
, int delta
)
2223 u8 eirp_txpower_criterion
;
2226 if (!((band
== IEEE80211_BAND_5GHZ
) && is_rate_b
))
2229 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
2231 * Check if eirp txpower exceed txpower_limit.
2232 * We use OFDM 6M as criterion and its eirp txpower
2233 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2234 * .11b data rate need add additional 4dbm
2235 * when calculating eirp txpower.
2237 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
2238 criterion
= rt2x00_get_field32(reg
, TX_PWR_CFG_0_6MBS
);
2240 rt2x00_eeprom_read(rt2x00dev
,
2241 EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
2243 if (band
== IEEE80211_BAND_2GHZ
)
2244 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2245 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
2247 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2248 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
2250 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
2251 (is_rate_b
? 4 : 0) + delta
;
2253 reg_limit
= (eirp_txpower
> power_level
) ?
2254 (eirp_txpower
- power_level
) : 0;
2258 return txpower
+ delta
- reg_limit
;
2261 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
2262 enum ieee80211_band band
,
2274 * Calculate HT40 compensation delta
2276 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
2279 * calculate temperature compensation delta
2281 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
2284 * set to normal bbp tx power control mode: +/- 0dBm
2286 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
2287 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, 0);
2288 rt2800_bbp_write(rt2x00dev
, 1, r1
);
2289 offset
= TX_PWR_CFG_0
;
2291 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
2292 /* just to be safe */
2293 if (offset
> TX_PWR_CFG_4
)
2296 rt2800_register_read(rt2x00dev
, offset
, ®
);
2298 /* read the next four txpower values */
2299 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
2302 is_rate_b
= i
? 0 : 1;
2304 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2305 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2306 * TX_PWR_CFG_4: unknown
2308 txpower
= rt2x00_get_field16(eeprom
,
2309 EEPROM_TXPOWER_BYRATE_RATE0
);
2310 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2311 power_level
, txpower
, delta
);
2312 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
2315 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2316 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2317 * TX_PWR_CFG_4: unknown
2319 txpower
= rt2x00_get_field16(eeprom
,
2320 EEPROM_TXPOWER_BYRATE_RATE1
);
2321 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2322 power_level
, txpower
, delta
);
2323 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
2326 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2327 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2328 * TX_PWR_CFG_4: unknown
2330 txpower
= rt2x00_get_field16(eeprom
,
2331 EEPROM_TXPOWER_BYRATE_RATE2
);
2332 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2333 power_level
, txpower
, delta
);
2334 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
2337 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2338 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2339 * TX_PWR_CFG_4: unknown
2341 txpower
= rt2x00_get_field16(eeprom
,
2342 EEPROM_TXPOWER_BYRATE_RATE3
);
2343 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2344 power_level
, txpower
, delta
);
2345 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
2347 /* read the next four txpower values */
2348 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
2353 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2354 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2355 * TX_PWR_CFG_4: unknown
2357 txpower
= rt2x00_get_field16(eeprom
,
2358 EEPROM_TXPOWER_BYRATE_RATE0
);
2359 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2360 power_level
, txpower
, delta
);
2361 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
2364 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2365 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2366 * TX_PWR_CFG_4: unknown
2368 txpower
= rt2x00_get_field16(eeprom
,
2369 EEPROM_TXPOWER_BYRATE_RATE1
);
2370 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2371 power_level
, txpower
, delta
);
2372 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
2375 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2376 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2377 * TX_PWR_CFG_4: unknown
2379 txpower
= rt2x00_get_field16(eeprom
,
2380 EEPROM_TXPOWER_BYRATE_RATE2
);
2381 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2382 power_level
, txpower
, delta
);
2383 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
2386 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2387 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2388 * TX_PWR_CFG_4: unknown
2390 txpower
= rt2x00_get_field16(eeprom
,
2391 EEPROM_TXPOWER_BYRATE_RATE3
);
2392 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2393 power_level
, txpower
, delta
);
2394 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
2396 rt2800_register_write(rt2x00dev
, offset
, reg
);
2398 /* next TX_PWR_CFG register */
2403 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
2405 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->curr_band
,
2406 rt2x00dev
->tx_power
);
2408 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
2410 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
2411 struct rt2x00lib_conf
*libconf
)
2415 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2416 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
2417 libconf
->conf
->short_frame_max_tx_count
);
2418 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
2419 libconf
->conf
->long_frame_max_tx_count
);
2420 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2423 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
2424 struct rt2x00lib_conf
*libconf
)
2426 enum dev_state state
=
2427 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
2428 STATE_SLEEP
: STATE_AWAKE
;
2431 if (state
== STATE_SLEEP
) {
2432 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
2434 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2435 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
2436 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
2437 libconf
->conf
->listen_interval
- 1);
2438 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
2439 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2441 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2443 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2444 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
2445 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
2446 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
2447 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2449 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2453 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
2454 struct rt2x00lib_conf
*libconf
,
2455 const unsigned int flags
)
2457 /* Always recalculate LNA gain before changing configuration */
2458 rt2800_config_lna_gain(rt2x00dev
, libconf
);
2460 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2461 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
2462 &libconf
->rf
, &libconf
->channel
);
2463 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2464 libconf
->conf
->power_level
);
2466 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
2467 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2468 libconf
->conf
->power_level
);
2469 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
2470 rt2800_config_retry_limit(rt2x00dev
, libconf
);
2471 if (flags
& IEEE80211_CONF_CHANGE_PS
)
2472 rt2800_config_ps(rt2x00dev
, libconf
);
2474 EXPORT_SYMBOL_GPL(rt2800_config
);
2479 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2484 * Update FCS error count from register.
2486 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2487 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
2489 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
2491 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
2493 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2494 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2495 rt2x00_rt(rt2x00dev
, RT3071
) ||
2496 rt2x00_rt(rt2x00dev
, RT3090
) ||
2497 rt2x00_rt(rt2x00dev
, RT3390
) ||
2498 rt2x00_rt(rt2x00dev
, RT5390
))
2499 return 0x1c + (2 * rt2x00dev
->lna_gain
);
2501 return 0x2e + rt2x00dev
->lna_gain
;
2504 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2505 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
2507 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
2510 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
2511 struct link_qual
*qual
, u8 vgc_level
)
2513 if (qual
->vgc_level
!= vgc_level
) {
2514 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
2515 qual
->vgc_level
= vgc_level
;
2516 qual
->vgc_level_reg
= vgc_level
;
2520 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2522 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
2524 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
2526 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
2529 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
2533 * When RSSI is better then -80 increase VGC level with 0x10
2535 rt2800_set_vgc(rt2x00dev
, qual
,
2536 rt2800_get_default_vgc(rt2x00dev
) +
2537 ((qual
->rssi
> -80) * 0x10));
2539 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
2542 * Initialization functions.
2544 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
2551 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2552 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2553 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2554 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2555 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2556 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
2557 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2559 ret
= rt2800_drv_init_registers(rt2x00dev
);
2563 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
2564 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
2565 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
2566 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
2567 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
2568 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
2570 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
2571 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
2572 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
2573 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
2574 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
2575 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
2577 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
2578 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
2580 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
2582 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
2583 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
2584 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
2585 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
2586 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
2587 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
2588 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
2589 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
2591 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
2593 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
2594 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
2595 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
2596 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
2598 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2599 rt2x00_rt(rt2x00dev
, RT3090
) ||
2600 rt2x00_rt(rt2x00dev
, RT3390
)) {
2601 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2602 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2603 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2604 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2605 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2606 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
2607 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
2608 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2611 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2614 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2616 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
2617 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2619 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
2620 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2621 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
2623 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2624 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2626 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2627 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2628 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2629 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
2630 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
2631 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2632 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2633 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
2634 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
2635 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2636 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2638 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
2639 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2642 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
2643 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
2644 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
2645 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
2646 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
2647 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
2648 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
2649 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
2650 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
2651 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
2653 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
2654 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
2655 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
2656 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
2657 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
2659 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
2660 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
2661 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
2662 rt2x00_rt(rt2x00dev
, RT2883
) ||
2663 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
2664 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
2666 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
2667 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
2668 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
2669 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
2671 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
2672 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
2673 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
2674 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
2675 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
2676 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
2677 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
2678 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
2679 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
2681 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
2683 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2684 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
2685 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
2686 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
2687 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
2688 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
2689 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
2690 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2692 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
2693 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
2694 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
2695 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
2696 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
2697 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
2698 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
2699 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
2700 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
2702 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2703 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
2704 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
2705 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2706 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2707 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2708 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2709 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2710 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2711 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2712 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
2713 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2715 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2716 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
2717 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
2718 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2719 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2720 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2721 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2722 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2723 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2724 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2725 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
2726 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2728 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2729 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
2730 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
2731 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2732 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2733 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2734 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2735 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2736 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2737 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2738 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
2739 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2741 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2742 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
2743 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
2744 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2745 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2746 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2747 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2748 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2749 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2750 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2751 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
2752 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2754 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2755 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
2756 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
2757 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2758 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2759 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2760 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2761 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2762 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2763 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2764 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
2765 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2767 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2768 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
2769 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
2770 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2771 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2772 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2773 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2774 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2775 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2776 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2777 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
2778 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2780 if (rt2x00_is_usb(rt2x00dev
)) {
2781 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
2783 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2784 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2785 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2786 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2787 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2788 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
2789 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
2790 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
2791 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
2792 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
2793 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2797 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2798 * although it is reserved.
2800 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
2801 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
2802 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
2803 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
2804 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
2805 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
2806 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
2807 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
2808 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
2809 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
2810 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
2811 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
2813 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
2815 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2816 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
2817 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
2818 IEEE80211_MAX_RTS_THRESHOLD
);
2819 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
2820 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2822 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
2825 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2826 * time should be set to 16. However, the original Ralink driver uses
2827 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2828 * connection problems with 11g + CTS protection. Hence, use the same
2829 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2831 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
2832 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
2833 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
2834 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
2835 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
2836 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
2837 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
2839 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
2842 * ASIC will keep garbage value after boot, clear encryption keys.
2844 for (i
= 0; i
< 4; i
++)
2845 rt2800_register_write(rt2x00dev
,
2846 SHARED_KEY_MODE_ENTRY(i
), 0);
2848 for (i
= 0; i
< 256; i
++) {
2849 rt2800_config_wcid(rt2x00dev
, NULL
, i
);
2850 rt2800_delete_wcid_attr(rt2x00dev
, i
);
2851 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
2857 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE0
);
2858 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE1
);
2859 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE2
);
2860 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE3
);
2861 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE4
);
2862 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE5
);
2863 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE6
);
2864 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE7
);
2866 if (rt2x00_is_usb(rt2x00dev
)) {
2867 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2868 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
2869 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2870 } else if (rt2x00_is_pcie(rt2x00dev
)) {
2871 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2872 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
2873 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2876 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
2877 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
2878 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
2879 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
2880 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
2881 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
2882 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
2883 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
2884 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
2885 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
2887 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
2888 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
2889 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
2890 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
2891 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
2892 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
2893 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
2894 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
2895 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
2896 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
2898 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
2899 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
2900 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
2901 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
2902 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
2903 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
2904 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
2905 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
2906 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
2907 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
2909 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
2910 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
2911 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
2912 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
2913 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
2914 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
2917 * Do not force the BA window size, we use the TXWI to set it
2919 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
2920 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
2921 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
2922 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
2925 * We must clear the error counters.
2926 * These registers are cleared on read,
2927 * so we may pass a useless variable to store the value.
2929 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2930 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
2931 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
2932 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
2933 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
2934 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
2937 * Setup leadtime for pre tbtt interrupt to 6ms
2939 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
2940 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
2941 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
2944 * Set up channel statistics timer
2946 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
2947 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
2948 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
2949 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
2950 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
2951 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
2952 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
2957 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
2962 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2963 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
2964 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
2967 udelay(REGISTER_BUSY_DELAY
);
2970 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
2974 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
2980 * BBP was enabled after firmware was loaded,
2981 * but we need to reactivate it now.
2983 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
2984 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
2987 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2988 rt2800_bbp_read(rt2x00dev
, 0, &value
);
2989 if ((value
!= 0xff) && (value
!= 0x00))
2991 udelay(REGISTER_BUSY_DELAY
);
2994 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
2998 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
3005 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
3006 rt2800_wait_bbp_ready(rt2x00dev
)))
3009 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3010 rt2800_bbp_read(rt2x00dev
, 4, &value
);
3011 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
3012 rt2800_bbp_write(rt2x00dev
, 4, value
);
3015 if (rt2800_is_305x_soc(rt2x00dev
) ||
3016 rt2x00_rt(rt2x00dev
, RT3572
) ||
3017 rt2x00_rt(rt2x00dev
, RT5390
))
3018 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
3020 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
3021 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
3023 if (rt2x00_rt(rt2x00dev
, RT5390
))
3024 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
3026 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
3027 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
3028 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
3029 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3030 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
3031 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
3032 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
3033 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
3034 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
3036 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
3037 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
3040 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
3042 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3043 rt2x00_rt(rt2x00dev
, RT3071
) ||
3044 rt2x00_rt(rt2x00dev
, RT3090
) ||
3045 rt2x00_rt(rt2x00dev
, RT3390
) ||
3046 rt2x00_rt(rt2x00dev
, RT3572
) ||
3047 rt2x00_rt(rt2x00dev
, RT5390
)) {
3048 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
3049 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
3050 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
3051 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3052 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
3053 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
3055 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
3058 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
3059 if (rt2x00_rt(rt2x00dev
, RT5390
))
3060 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
3062 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
3064 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
3065 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
3066 else if (rt2x00_rt(rt2x00dev
, RT5390
))
3067 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
3069 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
3071 if (rt2x00_rt(rt2x00dev
, RT5390
))
3072 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
3074 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
3076 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
3078 if (rt2x00_rt(rt2x00dev
, RT5390
))
3079 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
3081 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
3083 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3084 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3085 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3086 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
3087 rt2x00_rt(rt2x00dev
, RT3572
) ||
3088 rt2x00_rt(rt2x00dev
, RT5390
) ||
3089 rt2800_is_305x_soc(rt2x00dev
))
3090 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
3092 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
3094 if (rt2x00_rt(rt2x00dev
, RT5390
))
3095 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
3097 if (rt2800_is_305x_soc(rt2x00dev
))
3098 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
3099 else if (rt2x00_rt(rt2x00dev
, RT5390
))
3100 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
3102 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
3104 if (rt2x00_rt(rt2x00dev
, RT5390
))
3105 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
3107 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
3109 if (rt2x00_rt(rt2x00dev
, RT5390
))
3110 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
3112 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3113 rt2x00_rt(rt2x00dev
, RT3090
) ||
3114 rt2x00_rt(rt2x00dev
, RT3390
) ||
3115 rt2x00_rt(rt2x00dev
, RT3572
) ||
3116 rt2x00_rt(rt2x00dev
, RT5390
)) {
3117 rt2800_bbp_read(rt2x00dev
, 138, &value
);
3119 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3120 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3122 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3125 rt2800_bbp_write(rt2x00dev
, 138, value
);
3128 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3131 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3132 div_mode
= rt2x00_get_field16(eeprom
,
3133 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3134 ant
= (div_mode
== 3) ? 1 : 0;
3136 /* check if this is a Bluetooth combo card */
3137 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
3140 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
3141 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
3142 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT6
, 0);
3143 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 0);
3144 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 0);
3146 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 1);
3148 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 1);
3149 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
3152 rt2800_bbp_read(rt2x00dev
, 152, &value
);
3154 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
3156 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
3157 rt2800_bbp_write(rt2x00dev
, 152, value
);
3159 /* Init frequency calibration */
3160 rt2800_bbp_write(rt2x00dev
, 142, 1);
3161 rt2800_bbp_write(rt2x00dev
, 143, 57);
3164 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
3165 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
3167 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
3168 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
3169 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
3170 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
3177 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
3178 bool bw40
, u8 rfcsr24
, u8 filter_target
)
3187 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3189 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3190 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
3191 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3193 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
3194 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
3195 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
3197 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3198 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
3199 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3202 * Set power & frequency of passband test tone
3204 rt2800_bbp_write(rt2x00dev
, 24, 0);
3206 for (i
= 0; i
< 100; i
++) {
3207 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3210 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
3216 * Set power & frequency of stopband test tone
3218 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
3220 for (i
= 0; i
< 100; i
++) {
3221 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3224 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
3226 if ((passband
- stopband
) <= filter_target
) {
3228 overtuned
+= ((passband
- stopband
) == filter_target
);
3232 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3235 rfcsr24
-= !!overtuned
;
3237 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3241 static int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
3248 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
3249 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3250 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3251 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3252 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3253 !rt2x00_rt(rt2x00dev
, RT5390
) &&
3254 !rt2800_is_305x_soc(rt2x00dev
))
3258 * Init RF calibration.
3260 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3261 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
3262 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
3263 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3265 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 0);
3266 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3268 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3269 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
3270 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3272 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
3273 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3276 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3277 rt2x00_rt(rt2x00dev
, RT3071
) ||
3278 rt2x00_rt(rt2x00dev
, RT3090
)) {
3279 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3280 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3281 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3282 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
3283 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3284 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
3285 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3286 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
3287 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3288 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3289 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3290 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3291 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3292 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3293 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3294 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3295 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3296 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3297 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
3298 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3299 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
3300 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
3301 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3302 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
3303 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3304 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
3305 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
3306 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
3307 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
3308 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
3309 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
3310 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3311 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
3312 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
3313 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3314 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3315 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
3316 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
3317 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
3318 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
3319 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
3320 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
3321 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3322 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
3323 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3324 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
3325 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3326 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3327 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
3328 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
3329 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
3330 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
3331 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3332 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
3333 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
3334 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3335 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
3336 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
3337 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
3338 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
3339 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
3340 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
3341 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
3342 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
3343 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
3344 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
3345 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
3346 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3347 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
3348 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
3349 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
3350 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
3351 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
3352 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
3353 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3354 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
3355 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3356 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
3357 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3358 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3359 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3360 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
3361 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
3362 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
3363 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3364 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
3365 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
3366 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
3367 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
3368 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3369 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3370 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3371 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
3372 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
3373 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3374 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
3375 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3376 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
3377 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
3378 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3379 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3380 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3381 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3382 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3383 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3384 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3385 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3386 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3387 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
3388 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3389 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3390 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
3391 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
3392 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
3393 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
3394 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3395 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
3397 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3398 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
3399 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
3400 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
3401 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
3402 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3403 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
3405 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
3406 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
3407 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
3408 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
3409 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
3410 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
3411 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
3412 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
3413 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
3414 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
3415 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
3417 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
3418 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
3419 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
3420 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
3421 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
3422 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3423 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
3425 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
3426 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
3427 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
3428 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3429 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
3431 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3432 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
3433 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
3434 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
3435 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
3436 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
3437 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
3438 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
3439 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
3440 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
3442 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3443 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
3445 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
3446 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
3447 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
3448 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
3449 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
3450 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
3451 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3452 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
3454 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
3455 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
3456 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
3457 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
3459 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
3460 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3461 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
3463 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
3464 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
3465 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
3466 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
3467 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
3468 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
3469 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
3471 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
3472 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3473 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
3475 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
3476 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
3477 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
3480 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
3481 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3482 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3483 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3484 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3485 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3486 rt2x00_rt(rt2x00dev
, RT3090
)) {
3487 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
3489 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3490 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3491 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3493 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3494 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3495 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3496 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
3497 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3498 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
3499 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3501 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
3503 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3505 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3506 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3507 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3508 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3509 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3510 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3511 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3512 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3513 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3514 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3515 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3517 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3518 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3519 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3520 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3522 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3523 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3524 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3528 * Set RX Filter calibration for 20MHz and 40MHz
3530 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3531 rt2x00dev
->calibration
[0] =
3532 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
3533 rt2x00dev
->calibration
[1] =
3534 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
3535 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3536 rt2x00_rt(rt2x00dev
, RT3090
) ||
3537 rt2x00_rt(rt2x00dev
, RT3390
) ||
3538 rt2x00_rt(rt2x00dev
, RT3572
)) {
3539 rt2x00dev
->calibration
[0] =
3540 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
3541 rt2x00dev
->calibration
[1] =
3542 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
3545 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
3547 * Set back to initial state
3549 rt2800_bbp_write(rt2x00dev
, 24, 0);
3551 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3552 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
3553 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3556 * Set BBP back to BW20
3558 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3559 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
3560 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3563 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3564 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3565 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3566 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
3567 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
3569 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
3570 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
3571 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
3573 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
3574 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
3575 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
3576 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3577 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3578 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3579 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
3580 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
3581 &rt2x00dev
->cap_flags
))
3582 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
3584 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
3585 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
3586 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
3587 rt2x00_get_field16(eeprom
,
3588 EEPROM_TXMIXER_GAIN_BG_VAL
));
3589 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
3592 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
3593 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
3595 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
3596 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3597 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3598 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
3599 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3600 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
3602 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
3605 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3606 rt2x00_rt(rt2x00dev
, RT3090
) ||
3607 rt2x00_rt(rt2x00dev
, RT3390
)) {
3608 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
3609 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
3610 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
3611 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
3612 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
3613 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
3614 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
3616 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
3617 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
3618 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
3620 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
3621 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
3622 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
3624 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
3625 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
3626 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
3629 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3630 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
3631 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
3632 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
3634 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
3635 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
3636 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
3637 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
3638 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
3641 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3642 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
3643 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
3644 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
3646 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
3647 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
3648 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
3650 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3651 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
3652 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3658 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
3664 * Initialize all registers.
3666 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
3667 rt2800_init_registers(rt2x00dev
) ||
3668 rt2800_init_bbp(rt2x00dev
) ||
3669 rt2800_init_rfcsr(rt2x00dev
)))
3673 * Send signal to firmware during boot time.
3675 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
3677 if (rt2x00_is_usb(rt2x00dev
) &&
3678 (rt2x00_rt(rt2x00dev
, RT3070
) ||
3679 rt2x00_rt(rt2x00dev
, RT3071
) ||
3680 rt2x00_rt(rt2x00dev
, RT3572
))) {
3682 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
3689 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3690 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3691 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
3692 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3696 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3697 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
3698 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
3699 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
3700 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
3701 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3703 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3704 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3705 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
3706 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3709 * Initialize LED control
3711 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
3712 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
3713 word
& 0xff, (word
>> 8) & 0xff);
3715 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
3716 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
3717 word
& 0xff, (word
>> 8) & 0xff);
3719 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
3720 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
3721 word
& 0xff, (word
>> 8) & 0xff);
3725 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
3727 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
3731 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3732 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
3733 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
3734 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3736 /* Wait for DMA, ignore error */
3737 rt2800_wait_wpdma_ready(rt2x00dev
);
3739 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3740 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
3741 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
3742 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3744 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
3746 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
3750 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
3752 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
3754 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
3756 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
3760 mutex_lock(&rt2x00dev
->csr_mutex
);
3762 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
3763 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
3764 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
3765 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
3766 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
3768 /* Wait until the EEPROM has been loaded */
3769 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
3771 /* Apparently the data is read from end to start */
3772 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
, ®
);
3773 /* The returned value is in CPU order, but eeprom is le */
3774 rt2x00dev
->eeprom
[i
] = cpu_to_le32(reg
);
3775 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
, ®
);
3776 *(u32
*)&rt2x00dev
->eeprom
[i
+ 2] = cpu_to_le32(reg
);
3777 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
, ®
);
3778 *(u32
*)&rt2x00dev
->eeprom
[i
+ 4] = cpu_to_le32(reg
);
3779 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
, ®
);
3780 *(u32
*)&rt2x00dev
->eeprom
[i
+ 6] = cpu_to_le32(reg
);
3782 mutex_unlock(&rt2x00dev
->csr_mutex
);
3785 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
3789 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
3790 rt2800_efuse_read(rt2x00dev
, i
);
3792 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
3794 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
3798 u8 default_lna_gain
;
3801 * Start validation of the data that has been read.
3803 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
3804 if (!is_valid_ether_addr(mac
)) {
3805 random_ether_addr(mac
);
3806 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
3809 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
3810 if (word
== 0xffff) {
3811 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
3812 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
3813 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
3814 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
3815 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
3816 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
3817 rt2x00_rt(rt2x00dev
, RT2872
)) {
3819 * There is a max of 2 RX streams for RT28x0 series
3821 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
3822 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
3823 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
3826 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
3827 if (word
== 0xffff) {
3828 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
3829 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
3830 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
3831 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
3832 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
3833 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
3834 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
3835 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
3836 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
3837 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
3838 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
3839 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
3840 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
3841 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
3842 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
3843 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
3844 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
3847 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
3848 if ((word
& 0x00ff) == 0x00ff) {
3849 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
3850 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
3851 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
3853 if ((word
& 0xff00) == 0xff00) {
3854 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
3855 LED_MODE_TXRX_ACTIVITY
);
3856 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
3857 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
3858 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
3859 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
3860 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
3861 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
3865 * During the LNA validation we are going to use
3866 * lna0 as correct value. Note that EEPROM_LNA
3867 * is never validated.
3869 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
3870 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
3872 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
3873 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
3874 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
3875 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
3876 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
3877 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
3879 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
3880 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
3881 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
3882 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
3883 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
3884 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
3886 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
3888 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
3889 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
3890 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
3891 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
3892 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
3893 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
3895 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
3896 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
3897 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
3898 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
3899 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
3900 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
3902 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
3906 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
3908 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
3915 * Read EEPROM word for configuration.
3917 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3920 * Identify RF chipset by EEPROM value
3921 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3922 * RT53xx: defined in "EEPROM_CHIP_ID" field
3924 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
3925 if (rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT5390
)
3926 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &value
);
3928 value
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
3930 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
3931 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
3933 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
3934 !rt2x00_rt(rt2x00dev
, RT2872
) &&
3935 !rt2x00_rt(rt2x00dev
, RT2883
) &&
3936 !rt2x00_rt(rt2x00dev
, RT3070
) &&
3937 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3938 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3939 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3940 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3941 !rt2x00_rt(rt2x00dev
, RT5390
)) {
3942 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
3946 switch (rt2x00dev
->chip
.rf
) {
3961 ERROR(rt2x00dev
, "Invalid RF chipset 0x%x detected.\n",
3962 rt2x00dev
->chip
.rf
);
3967 * Identify default antenna configuration.
3969 rt2x00dev
->default_ant
.tx_chain_num
=
3970 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
3971 rt2x00dev
->default_ant
.rx_chain_num
=
3972 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
3974 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3976 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3977 rt2x00_rt(rt2x00dev
, RT3090
) ||
3978 rt2x00_rt(rt2x00dev
, RT3390
)) {
3979 value
= rt2x00_get_field16(eeprom
,
3980 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3985 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3986 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
3989 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3990 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
3994 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3995 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
3999 * Determine external LNA informations.
4001 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
4002 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
4003 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
4004 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
4007 * Detect if this device has an hardware controlled radio.
4009 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
4010 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
4013 * Detect if this device has Bluetooth co-existence.
4015 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
4016 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
4019 * Read frequency offset and RF programming sequence.
4021 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
4022 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
4025 * Store led settings, for correct led behaviour.
4027 #ifdef CONFIG_RT2X00_LIB_LEDS
4028 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
4029 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
4030 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
4032 rt2x00dev
->led_mcu_reg
= eeprom
;
4033 #endif /* CONFIG_RT2X00_LIB_LEDS */
4036 * Check if support EIRP tx power limit feature.
4038 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
4040 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
4041 EIRP_MAX_TX_POWER_LIMIT
)
4042 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
4046 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
4049 * RF value list for rt28xx
4050 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4052 static const struct rf_channel rf_vals
[] = {
4053 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4054 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4055 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4056 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4057 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4058 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4059 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4060 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4061 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4062 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4063 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4064 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4065 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4066 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4068 /* 802.11 UNI / HyperLan 2 */
4069 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4070 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4071 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4072 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4073 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4074 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4075 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4076 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4077 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4078 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4079 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4080 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4082 /* 802.11 HyperLan 2 */
4083 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4084 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4085 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4086 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4087 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4088 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4089 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4090 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4091 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4092 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4093 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4094 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4095 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4096 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4097 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4098 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4101 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4102 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4103 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4104 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4105 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4106 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4107 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4108 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4109 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4110 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4111 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4114 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4115 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4116 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4117 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4118 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4119 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4120 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4124 * RF value list for rt3xxx
4125 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4127 static const struct rf_channel rf_vals_3x
[] = {
4143 /* 802.11 UNI / HyperLan 2 */
4157 /* 802.11 HyperLan 2 */
4189 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
4191 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
4192 struct channel_info
*info
;
4193 char *default_power1
;
4194 char *default_power2
;
4199 * Disable powersaving as default on PCI devices.
4201 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
4202 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
4205 * Initialize all hw fields.
4207 rt2x00dev
->hw
->flags
=
4208 IEEE80211_HW_SIGNAL_DBM
|
4209 IEEE80211_HW_SUPPORTS_PS
|
4210 IEEE80211_HW_PS_NULLFUNC_STACK
|
4211 IEEE80211_HW_AMPDU_AGGREGATION
;
4213 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4214 * unless we are capable of sending the buffered frames out after the
4215 * DTIM transmission using rt2x00lib_beacondone. This will send out
4216 * multicast and broadcast traffic immediately instead of buffering it
4217 * infinitly and thus dropping it after some time.
4219 if (!rt2x00_is_usb(rt2x00dev
))
4220 rt2x00dev
->hw
->flags
|=
4221 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
4223 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
4224 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
4225 rt2x00_eeprom_addr(rt2x00dev
,
4226 EEPROM_MAC_ADDR_0
));
4229 * As rt2800 has a global fallback table we cannot specify
4230 * more then one tx rate per frame but since the hw will
4231 * try several rates (based on the fallback table) we should
4232 * initialize max_report_rates to the maximum number of rates
4233 * we are going to try. Otherwise mac80211 will truncate our
4234 * reported tx rates and the rc algortihm will end up with
4237 rt2x00dev
->hw
->max_rates
= 1;
4238 rt2x00dev
->hw
->max_report_rates
= 7;
4239 rt2x00dev
->hw
->max_rate_tries
= 1;
4241 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4244 * Initialize hw_mode information.
4246 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
4247 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
4249 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
4250 rt2x00_rf(rt2x00dev
, RF2720
)) {
4251 spec
->num_channels
= 14;
4252 spec
->channels
= rf_vals
;
4253 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
4254 rt2x00_rf(rt2x00dev
, RF2750
)) {
4255 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4256 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
4257 spec
->channels
= rf_vals
;
4258 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
4259 rt2x00_rf(rt2x00dev
, RF2020
) ||
4260 rt2x00_rf(rt2x00dev
, RF3021
) ||
4261 rt2x00_rf(rt2x00dev
, RF3022
) ||
4262 rt2x00_rf(rt2x00dev
, RF3320
) ||
4263 rt2x00_rf(rt2x00dev
, RF5370
) ||
4264 rt2x00_rf(rt2x00dev
, RF5390
)) {
4265 spec
->num_channels
= 14;
4266 spec
->channels
= rf_vals_3x
;
4267 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
4268 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4269 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
4270 spec
->channels
= rf_vals_3x
;
4274 * Initialize HT information.
4276 if (!rt2x00_rf(rt2x00dev
, RF2020
))
4277 spec
->ht
.ht_supported
= true;
4279 spec
->ht
.ht_supported
= false;
4282 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
4283 IEEE80211_HT_CAP_GRN_FLD
|
4284 IEEE80211_HT_CAP_SGI_20
|
4285 IEEE80211_HT_CAP_SGI_40
;
4287 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
4288 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
4291 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
4292 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
4294 spec
->ht
.ampdu_factor
= 3;
4295 spec
->ht
.ampdu_density
= 4;
4296 spec
->ht
.mcs
.tx_params
=
4297 IEEE80211_HT_MCS_TX_DEFINED
|
4298 IEEE80211_HT_MCS_TX_RX_DIFF
|
4299 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
4300 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
4302 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
4304 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
4306 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
4308 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
4309 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
4314 * Create channel information array
4316 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
4320 spec
->channels_info
= info
;
4322 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
4323 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
4325 for (i
= 0; i
< 14; i
++) {
4326 info
[i
].default_power1
= default_power1
[i
];
4327 info
[i
].default_power2
= default_power2
[i
];
4330 if (spec
->num_channels
> 14) {
4331 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
4332 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
4334 for (i
= 14; i
< spec
->num_channels
; i
++) {
4335 info
[i
].default_power1
= default_power1
[i
];
4336 info
[i
].default_power2
= default_power2
[i
];
4342 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
4345 * IEEE80211 stack callback functions.
4347 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
4350 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4351 struct mac_iveiv_entry iveiv_entry
;
4354 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
4355 rt2800_register_multiread(rt2x00dev
, offset
,
4356 &iveiv_entry
, sizeof(iveiv_entry
));
4358 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
4359 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
4361 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
4363 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
4365 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4367 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
4369 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
4370 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
4371 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
4373 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
4374 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
4375 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
4377 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
4378 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
4379 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
4381 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
4382 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
4383 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
4385 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
4386 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
4387 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
4389 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
4390 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
4391 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
4393 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
4394 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
4395 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
4399 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
4401 int rt2800_conf_tx(struct ieee80211_hw
*hw
,
4402 struct ieee80211_vif
*vif
, u16 queue_idx
,
4403 const struct ieee80211_tx_queue_params
*params
)
4405 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4406 struct data_queue
*queue
;
4407 struct rt2x00_field32 field
;
4413 * First pass the configuration through rt2x00lib, that will
4414 * update the queue settings and validate the input. After that
4415 * we are free to update the registers based on the value
4416 * in the queue parameter.
4418 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
4423 * We only need to perform additional register initialization
4429 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
4431 /* Update WMM TXOP register */
4432 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
4433 field
.bit_offset
= (queue_idx
& 1) * 16;
4434 field
.bit_mask
= 0xffff << field
.bit_offset
;
4436 rt2800_register_read(rt2x00dev
, offset
, ®
);
4437 rt2x00_set_field32(®
, field
, queue
->txop
);
4438 rt2800_register_write(rt2x00dev
, offset
, reg
);
4440 /* Update WMM registers */
4441 field
.bit_offset
= queue_idx
* 4;
4442 field
.bit_mask
= 0xf << field
.bit_offset
;
4444 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
4445 rt2x00_set_field32(®
, field
, queue
->aifs
);
4446 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
4448 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
4449 rt2x00_set_field32(®
, field
, queue
->cw_min
);
4450 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
4452 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
4453 rt2x00_set_field32(®
, field
, queue
->cw_max
);
4454 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
4456 /* Update EDCA registers */
4457 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
4459 rt2800_register_read(rt2x00dev
, offset
, ®
);
4460 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
4461 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
4462 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
4463 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
4464 rt2800_register_write(rt2x00dev
, offset
, reg
);
4468 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
4470 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
4472 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4476 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
4477 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
4478 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
4479 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
4483 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
4485 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
4486 enum ieee80211_ampdu_mlme_action action
,
4487 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
4490 struct rt2x00_sta
*sta_priv
= (struct rt2x00_sta
*)sta
->drv_priv
;
4494 * Don't allow aggregation for stations the hardware isn't aware
4495 * of because tx status reports for frames to an unknown station
4496 * always contain wcid=255 and thus we can't distinguish between
4497 * multiple stations which leads to unwanted situations when the
4498 * hw reorders frames due to aggregation.
4500 if (sta_priv
->wcid
< 0)
4504 case IEEE80211_AMPDU_RX_START
:
4505 case IEEE80211_AMPDU_RX_STOP
:
4507 * The hw itself takes care of setting up BlockAck mechanisms.
4508 * So, we only have to allow mac80211 to nagotiate a BlockAck
4509 * agreement. Once that is done, the hw will BlockAck incoming
4510 * AMPDUs without further setup.
4513 case IEEE80211_AMPDU_TX_START
:
4514 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4516 case IEEE80211_AMPDU_TX_STOP
:
4517 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4519 case IEEE80211_AMPDU_TX_OPERATIONAL
:
4522 WARNING((struct rt2x00_dev
*)hw
->priv
, "Unknown AMPDU action\n");
4527 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
4529 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
4530 struct survey_info
*survey
)
4532 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4533 struct ieee80211_conf
*conf
= &hw
->conf
;
4534 u32 idle
, busy
, busy_ext
;
4539 survey
->channel
= conf
->channel
;
4541 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
4542 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
4543 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
4546 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
4547 SURVEY_INFO_CHANNEL_TIME_BUSY
|
4548 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
4550 survey
->channel_time
= (idle
+ busy
) / 1000;
4551 survey
->channel_time_busy
= busy
/ 1000;
4552 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
4558 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
4560 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
4561 MODULE_VERSION(DRV_VERSION
);
4562 MODULE_DESCRIPTION("Ralink RT2800 library");
4563 MODULE_LICENSE("GPL");