arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37
  38 #ifndef CONFIG_X86_64
  39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  40 #else
  41 #define mod_64(x, y) ((x) % (y))
  42 #endif
  43
  44 #define PRId64 "d"
  45 #define PRIx64 "llx"
  46 #define PRIu64 "u"
  47 #define PRIo64 "o"
  48
  49 #define APIC_BUS_CYCLE_NS 1
  50
  51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  52 #define apic_debug(fmt, arg...)
  53
  54 #define APIC_LVT_NUM                    6
  55 /* 14 is the version for Xeon and Pentium 8.4.8*/
  56 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  57 #define LAPIC_MMIO_LENGTH               (1 << 12)
  58 /* followed define is not in apicdef.h */
  59 #define APIC_SHORT_MASK                 0xc0000
  60 #define APIC_DEST_NOSHORT               0x0
  61 #define APIC_DEST_MASK                  0x800
  62 #define MAX_APIC_VECTOR                 256
  63
  64 #define VEC_POS(v) ((v) & (32 - 1))
  65 #define REG_POS(v) (((v) >> 5) << 4)
  66
  67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  68 {
  69         return *((u32 *) (apic->regs + reg_off));
  70 }
  71
  72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  73 {
  74         *((u32 *) (apic->regs + reg_off)) = val;
  75 }
  76
  77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  78 {
  79         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  80 }
  81
  82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  83 {
  84         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 static inline void apic_set_vector(int vec, void *bitmap)
  88 {
  89         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  90 }
  91
  92 static inline void apic_clear_vector(int vec, void *bitmap)
  93 {
  94         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  95 }
  96
  97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  98 {
  99         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 100 }
 101
 102 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 103 {
 104         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 105 }
 106
 107 static inline int apic_enabled(struct kvm_lapic *apic)
 108 {
 109         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 110 }
 111
 112 #define LVT_MASK        \
 113         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 114
 115 #define LINT_MASK       \
 116         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 117          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 118
 119 static inline int kvm_apic_id(struct kvm_lapic *apic)
 120 {
 121         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 122 }
 123
 124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 125 {
 126         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 127 }
 128
 129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 130 {
 131         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 132 }
 133
 134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 135 {
 136         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 137 }
 138
 139 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 140         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 141         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 142         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 143         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 144         LVT_MASK                /* LVTERR */
 145 };
 146
 147 static int find_highest_vector(void *bitmap)
 148 {
 149         u32 *word = bitmap;
 150         int word_offset = MAX_APIC_VECTOR >> 5;
 151
 152         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 153                 continue;
 154
 155         if (likely(!word_offset && !word[0]))
 156                 return -1;
 157         else
 158                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 159 }
 160
 161 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 162 {
 163         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 164 }
 165
 166 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 167 {
 168         apic_clear_vector(vec, apic->regs + APIC_IRR);
 169 }
 170
 171 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 172 {
 173         int result;
 174
 175         result = find_highest_vector(apic->regs + APIC_IRR);
 176         ASSERT(result == -1 || result >= 16);
 177
 178         return result;
 179 }
 180
 181 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 182 {
 183         struct kvm_lapic *apic = vcpu->arch.apic;
 184         int highest_irr;
 185
 186         if (!apic)
 187                 return 0;
 188         highest_irr = apic_find_highest_irr(apic);
 189
 190         return highest_irr;
 191 }
 192 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 193
 194 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
 195 {
 196         struct kvm_lapic *apic = vcpu->arch.apic;
 197
 198         if (!apic_test_and_set_irr(vec, apic)) {
 199                 /* a new pending irq is set in IRR */
 200                 if (trig)
 201                         apic_set_vector(vec, apic->regs + APIC_TMR);
 202                 else
 203                         apic_clear_vector(vec, apic->regs + APIC_TMR);
 204                 kvm_vcpu_kick(apic->vcpu);
 205                 return 1;
 206         }
 207         return 0;
 208 }
 209
 210 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 211 {
 212         int result;
 213
 214         result = find_highest_vector(apic->regs + APIC_ISR);
 215         ASSERT(result == -1 || result >= 16);
 216
 217         return result;
 218 }
 219
 220 static void apic_update_ppr(struct kvm_lapic *apic)
 221 {
 222         u32 tpr, isrv, ppr;
 223         int isr;
 224
 225         tpr = apic_get_reg(apic, APIC_TASKPRI);
 226         isr = apic_find_highest_isr(apic);
 227         isrv = (isr != -1) ? isr : 0;
 228
 229         if ((tpr & 0xf0) >= (isrv & 0xf0))
 230                 ppr = tpr & 0xff;
 231         else
 232                 ppr = isrv & 0xf0;
 233
 234         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 235                    apic, ppr, isr, isrv);
 236
 237         apic_set_reg(apic, APIC_PROCPRI, ppr);
 238 }
 239
 240 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 241 {
 242         apic_set_reg(apic, APIC_TASKPRI, tpr);
 243         apic_update_ppr(apic);
 244 }
 245
 246 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 247 {
 248         return kvm_apic_id(apic) == dest;
 249 }
 250
 251 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 252 {
 253         int result = 0;
 254         u8 logical_id;
 255
 256         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 257
 258         switch (apic_get_reg(apic, APIC_DFR)) {
 259         case APIC_DFR_FLAT:
 260                 if (logical_id & mda)
 261                         result = 1;
 262                 break;
 263         case APIC_DFR_CLUSTER:
 264                 if (((logical_id >> 4) == (mda >> 0x4))
 265                     && (logical_id & mda & 0xf))
 266                         result = 1;
 267                 break;
 268         default:
 269                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 270                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 271                 break;
 272         }
 273
 274         return result;
 275 }
 276
 277 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 278                            int short_hand, int dest, int dest_mode)
 279 {
 280         int result = 0;
 281         struct kvm_lapic *target = vcpu->arch.apic;
 282
 283         apic_debug("target %p, source %p, dest 0x%x, "
 284                    "dest_mode 0x%x, short_hand 0x%x",
 285                    target, source, dest, dest_mode, short_hand);
 286
 287         ASSERT(!target);
 288         switch (short_hand) {
 289         case APIC_DEST_NOSHORT:
 290                 if (dest_mode == 0) {
 291                         /* Physical mode. */
 292                         if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
 293                                 result = 1;
 294                 } else
 295                         /* Logical mode. */
 296                         result = kvm_apic_match_logical_addr(target, dest);
 297                 break;
 298         case APIC_DEST_SELF:
 299                 if (target == source)
 300                         result = 1;
 301                 break;
 302         case APIC_DEST_ALLINC:
 303                 result = 1;
 304                 break;
 305         case APIC_DEST_ALLBUT:
 306                 if (target != source)
 307                         result = 1;
 308                 break;
 309         default:
 310                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 311                        short_hand);
 312                 break;
 313         }
 314
 315         return result;
 316 }
 317
 318 /*
 319  * Add a pending IRQ into lapic.
 320  * Return 1 if successfully added and 0 if discarded.
 321  */
 322 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 323                              int vector, int level, int trig_mode)
 324 {
 325         int orig_irr, result = 0;
 326         struct kvm_vcpu *vcpu = apic->vcpu;
 327
 328         switch (delivery_mode) {
 329         case APIC_DM_FIXED:
 330         case APIC_DM_LOWEST:
 331                 /* FIXME add logic for vcpu on reset */
 332                 if (unlikely(!apic_enabled(apic)))
 333                         break;
 334
 335                 orig_irr = apic_test_and_set_irr(vector, apic);
 336                 if (orig_irr && trig_mode) {
 337                         apic_debug("level trig mode repeatedly for vector %d",
 338                                    vector);
 339                         break;
 340                 }
 341
 342                 if (trig_mode) {
 343                         apic_debug("level trig mode for vector %d", vector);
 344                         apic_set_vector(vector, apic->regs + APIC_TMR);
 345                 } else
 346                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 347
 348                 kvm_vcpu_kick(vcpu);
 349
 350                 result = (orig_irr == 0);
 351                 break;
 352
 353         case APIC_DM_REMRD:
 354                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 355                 break;
 356
 357         case APIC_DM_SMI:
 358                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 359                 break;
 360
 361         case APIC_DM_NMI:
 362                 kvm_inject_nmi(vcpu);
 363                 break;
 364
 365         case APIC_DM_INIT:
 366                 if (level) {
 367                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 368                                 printk(KERN_DEBUG
 369                                        "INIT on a runnable vcpu %d\n",
 370                                        vcpu->vcpu_id);
 371                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 372                         kvm_vcpu_kick(vcpu);
 373                 } else {
 374                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 375                                    vcpu->vcpu_id);
 376                 }
 377                 break;
 378
 379         case APIC_DM_STARTUP:
 380                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 381                            vcpu->vcpu_id, vector);
 382                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 383                         vcpu->arch.sipi_vector = vector;
 384                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 385                         kvm_vcpu_kick(vcpu);
 386                 }
 387                 break;
 388
 389         default:
 390                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 391                        delivery_mode);
 392                 break;
 393         }
 394         return result;
 395 }
 396
 397 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
 398                                        unsigned long bitmap)
 399 {
 400         int last;
 401         int next;
 402         struct kvm_lapic *apic = NULL;
 403
 404         last = kvm->arch.round_robin_prev_vcpu;
 405         next = last;
 406
 407         do {
 408                 if (++next == KVM_MAX_VCPUS)
 409                         next = 0;
 410                 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
 411                         continue;
 412                 apic = kvm->vcpus[next]->arch.apic;
 413                 if (apic && apic_enabled(apic))
 414                         break;
 415                 apic = NULL;
 416         } while (next != last);
 417         kvm->arch.round_robin_prev_vcpu = next;
 418
 419         if (!apic)
 420                 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
 421
 422         return apic;
 423 }
 424
 425 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
 426                 unsigned long bitmap)
 427 {
 428         struct kvm_lapic *apic;
 429
 430         apic = kvm_apic_round_robin(kvm, vector, bitmap);
 431         if (apic)
 432                 return apic->vcpu;
 433         return NULL;
 434 }
 435
 436 static void apic_set_eoi(struct kvm_lapic *apic)
 437 {
 438         int vector = apic_find_highest_isr(apic);
 439         int trigger_mode;
 440         /*
 441          * Not every write EOI will has corresponding ISR,
 442          * one example is when Kernel check timer on setup_IO_APIC
 443          */
 444         if (vector == -1)
 445                 return;
 446
 447         apic_clear_vector(vector, apic->regs + APIC_ISR);
 448         apic_update_ppr(apic);
 449
 450         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 451                 trigger_mode = IOAPIC_LEVEL_TRIG;
 452         else
 453                 trigger_mode = IOAPIC_EDGE_TRIG;
 454         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 455 }
 456
 457 static void apic_send_ipi(struct kvm_lapic *apic)
 458 {
 459         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 460         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 461
 462         unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
 463         unsigned int short_hand = icr_low & APIC_SHORT_MASK;
 464         unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
 465         unsigned int level = icr_low & APIC_INT_ASSERT;
 466         unsigned int dest_mode = icr_low & APIC_DEST_MASK;
 467         unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
 468         unsigned int vector = icr_low & APIC_VECTOR_MASK;
 469
 470         struct kvm_vcpu *target;
 471         struct kvm_vcpu *vcpu;
 472         unsigned long lpr_map = 0;
 473         int i;
 474
 475         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 476                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 477                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 478                    icr_high, icr_low, short_hand, dest,
 479                    trig_mode, level, dest_mode, delivery_mode, vector);
 480
 481         for (i = 0; i < KVM_MAX_VCPUS; i++) {
 482                 vcpu = apic->vcpu->kvm->vcpus[i];
 483                 if (!vcpu)
 484                         continue;
 485
 486                 if (vcpu->arch.apic &&
 487                     apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
 488                         if (delivery_mode == APIC_DM_LOWEST)
 489                                 set_bit(vcpu->vcpu_id, &lpr_map);
 490                         else
 491                                 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
 492                                                   vector, level, trig_mode);
 493                 }
 494         }
 495
 496         if (delivery_mode == APIC_DM_LOWEST) {
 497                 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
 498                 if (target != NULL)
 499                         __apic_accept_irq(target->arch.apic, delivery_mode,
 500                                           vector, level, trig_mode);
 501         }
 502 }
 503
 504 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 505 {
 506         ktime_t remaining;
 507         s64 ns;
 508         u32 tmcct;
 509
 510         ASSERT(apic != NULL);
 511
 512         /* if initial count is 0, current count should also be 0 */
 513         if (apic_get_reg(apic, APIC_TMICT) == 0)
 514                 return 0;
 515
 516         remaining = hrtimer_expires_remaining(&apic->timer.dev);
 517         if (ktime_to_ns(remaining) < 0)
 518                 remaining = ktime_set(0, 0);
 519
 520         ns = mod_64(ktime_to_ns(remaining), apic->timer.period);
 521         tmcct = div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
 522
 523         return tmcct;
 524 }
 525
 526 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 527 {
 528         struct kvm_vcpu *vcpu = apic->vcpu;
 529         struct kvm_run *run = vcpu->run;
 530
 531         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 532         run->tpr_access.rip = kvm_rip_read(vcpu);
 533         run->tpr_access.is_write = write;
 534 }
 535
 536 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 537 {
 538         if (apic->vcpu->arch.tpr_access_reporting)
 539                 __report_tpr_access(apic, write);
 540 }
 541
 542 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 543 {
 544         u32 val = 0;
 545
 546         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 547
 548         if (offset >= LAPIC_MMIO_LENGTH)
 549                 return 0;
 550
 551         switch (offset) {
 552         case APIC_ARBPRI:
 553                 printk(KERN_WARNING "Access APIC ARBPRI register "
 554                        "which is for P6\n");
 555                 break;
 556
 557         case APIC_TMCCT:        /* Timer CCR */
 558                 val = apic_get_tmcct(apic);
 559                 break;
 560
 561         case APIC_TASKPRI:
 562                 report_tpr_access(apic, false);
 563                 /* fall thru */
 564         default:
 565                 apic_update_ppr(apic);
 566                 val = apic_get_reg(apic, offset);
 567                 break;
 568         }
 569
 570         return val;
 571 }
 572
 573 static void apic_mmio_read(struct kvm_io_device *this,
 574                            gpa_t address, int len, void *data)
 575 {
 576         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 577         unsigned int offset = address - apic->base_address;
 578         unsigned char alignment = offset & 0xf;
 579         u32 result;
 580
 581         if ((alignment + len) > 4) {
 582                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 583                        (unsigned long)address, len);
 584                 return;
 585         }
 586         result = __apic_read(apic, offset & ~0xf);
 587
 588         switch (len) {
 589         case 1:
 590         case 2:
 591         case 4:
 592                 memcpy(data, (char *)&result + alignment, len);
 593                 break;
 594         default:
 595                 printk(KERN_ERR "Local APIC read with len = %x, "
 596                        "should be 1,2, or 4 instead\n", len);
 597                 break;
 598         }
 599 }
 600
 601 static void update_divide_count(struct kvm_lapic *apic)
 602 {
 603         u32 tmp1, tmp2, tdcr;
 604
 605         tdcr = apic_get_reg(apic, APIC_TDCR);
 606         tmp1 = tdcr & 0xf;
 607         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 608         apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
 609
 610         apic_debug("timer divide count is 0x%x\n",
 611                                    apic->timer.divide_count);
 612 }
 613
 614 static void start_apic_timer(struct kvm_lapic *apic)
 615 {
 616         ktime_t now = apic->timer.dev.base->get_time();
 617
 618         apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
 619                     APIC_BUS_CYCLE_NS * apic->timer.divide_count;
 620         atomic_set(&apic->timer.pending, 0);
 621
 622         if (!apic->timer.period)
 623                 return;
 624
 625         hrtimer_start(&apic->timer.dev,
 626                       ktime_add_ns(now, apic->timer.period),
 627                       HRTIMER_MODE_ABS);
 628
 629         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 630                            PRIx64 ", "
 631                            "timer initial count 0x%x, period %lldns, "
 632                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 633                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 634                            apic_get_reg(apic, APIC_TMICT),
 635                            apic->timer.period,
 636                            ktime_to_ns(ktime_add_ns(now,
 637                                         apic->timer.period)));
 638 }
 639
 640 static void apic_mmio_write(struct kvm_io_device *this,
 641                             gpa_t address, int len, const void *data)
 642 {
 643         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 644         unsigned int offset = address - apic->base_address;
 645         unsigned char alignment = offset & 0xf;
 646         u32 val;
 647
 648         /*
 649          * APIC register must be aligned on 128-bits boundary.
 650          * 32/64/128 bits registers must be accessed thru 32 bits.
 651          * Refer SDM 8.4.1
 652          */
 653         if (len != 4 || alignment) {
 654                 /* Don't shout loud, $infamous_os would cause only noise. */
 655                 apic_debug("apic write: bad size=%d %lx\n",
 656                            len, (long)address);
 657                 return;
 658         }
 659
 660         val = *(u32 *) data;
 661
 662         /* too common printing */
 663         if (offset != APIC_EOI)
 664                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 665                            "0x%x\n", __func__, offset, len, val);
 666
 667         offset &= 0xff0;
 668
 669         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 670
 671         switch (offset) {
 672         case APIC_ID:           /* Local APIC ID */
 673                 apic_set_reg(apic, APIC_ID, val);
 674                 break;
 675
 676         case APIC_TASKPRI:
 677                 report_tpr_access(apic, true);
 678                 apic_set_tpr(apic, val & 0xff);
 679                 break;
 680
 681         case APIC_EOI:
 682                 apic_set_eoi(apic);
 683                 break;
 684
 685         case APIC_LDR:
 686                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 687                 break;
 688
 689         case APIC_DFR:
 690                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 691                 break;
 692
 693         case APIC_SPIV:
 694                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 695                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 696                         int i;
 697                         u32 lvt_val;
 698
 699                         for (i = 0; i < APIC_LVT_NUM; i++) {
 700                                 lvt_val = apic_get_reg(apic,
 701                                                        APIC_LVTT + 0x10 * i);
 702                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 703                                              lvt_val | APIC_LVT_MASKED);
 704                         }
 705                         atomic_set(&apic->timer.pending, 0);
 706
 707                 }
 708                 break;
 709
 710         case APIC_ICR:
 711                 /* No delay here, so we always clear the pending bit */
 712                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 713                 apic_send_ipi(apic);
 714                 break;
 715
 716         case APIC_ICR2:
 717                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 718                 break;
 719
 720         case APIC_LVTT:
 721         case APIC_LVTTHMR:
 722         case APIC_LVTPC:
 723         case APIC_LVT0:
 724         case APIC_LVT1:
 725         case APIC_LVTERR:
 726                 /* TODO: Check vector */
 727                 if (!apic_sw_enabled(apic))
 728                         val |= APIC_LVT_MASKED;
 729
 730                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 731                 apic_set_reg(apic, offset, val);
 732
 733                 break;
 734
 735         case APIC_TMICT:
 736                 hrtimer_cancel(&apic->timer.dev);
 737                 apic_set_reg(apic, APIC_TMICT, val);
 738                 start_apic_timer(apic);
 739                 return;
 740
 741         case APIC_TDCR:
 742                 if (val & 4)
 743                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 744                 apic_set_reg(apic, APIC_TDCR, val);
 745                 update_divide_count(apic);
 746                 break;
 747
 748         default:
 749                 apic_debug("Local APIC Write to read-only register %x\n",
 750                            offset);
 751                 break;
 752         }
 753
 754 }
 755
 756 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
 757                            int len, int size)
 758 {
 759         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 760         int ret = 0;
 761
 762
 763         if (apic_hw_enabled(apic) &&
 764             (addr >= apic->base_address) &&
 765             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 766                 ret = 1;
 767
 768         return ret;
 769 }
 770
 771 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 772 {
 773         if (!vcpu->arch.apic)
 774                 return;
 775
 776         hrtimer_cancel(&vcpu->arch.apic->timer.dev);
 777
 778         if (vcpu->arch.apic->regs_page)
 779                 __free_page(vcpu->arch.apic->regs_page);
 780
 781         kfree(vcpu->arch.apic);
 782 }
 783
 784 /*
 785  *----------------------------------------------------------------------
 786  * LAPIC interface
 787  *----------------------------------------------------------------------
 788  */
 789
 790 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 791 {
 792         struct kvm_lapic *apic = vcpu->arch.apic;
 793
 794         if (!apic)
 795                 return;
 796         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 797                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 798 }
 799 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
 800
 801 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 802 {
 803         struct kvm_lapic *apic = vcpu->arch.apic;
 804         u64 tpr;
 805
 806         if (!apic)
 807                 return 0;
 808         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 809
 810         return (tpr & 0xf0) >> 4;
 811 }
 812 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 813
 814 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 815 {
 816         struct kvm_lapic *apic = vcpu->arch.apic;
 817
 818         if (!apic) {
 819                 value |= MSR_IA32_APICBASE_BSP;
 820                 vcpu->arch.apic_base = value;
 821                 return;
 822         }
 823         if (apic->vcpu->vcpu_id)
 824                 value &= ~MSR_IA32_APICBASE_BSP;
 825
 826         vcpu->arch.apic_base = value;
 827         apic->base_address = apic->vcpu->arch.apic_base &
 828                              MSR_IA32_APICBASE_BASE;
 829
 830         /* with FSB delivery interrupt, we can restart APIC functionality */
 831         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 832                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 833
 834 }
 835
 836 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
 837 {
 838         return vcpu->arch.apic_base;
 839 }
 840 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
 841
 842 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 843 {
 844         struct kvm_lapic *apic;
 845         int i;
 846
 847         apic_debug("%s\n", __func__);
 848
 849         ASSERT(vcpu);
 850         apic = vcpu->arch.apic;
 851         ASSERT(apic != NULL);
 852
 853         /* Stop the timer in case it's a reset to an active apic */
 854         hrtimer_cancel(&apic->timer.dev);
 855
 856         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 857         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 858
 859         for (i = 0; i < APIC_LVT_NUM; i++)
 860                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 861         apic_set_reg(apic, APIC_LVT0,
 862                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 863
 864         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 865         apic_set_reg(apic, APIC_SPIV, 0xff);
 866         apic_set_reg(apic, APIC_TASKPRI, 0);
 867         apic_set_reg(apic, APIC_LDR, 0);
 868         apic_set_reg(apic, APIC_ESR, 0);
 869         apic_set_reg(apic, APIC_ICR, 0);
 870         apic_set_reg(apic, APIC_ICR2, 0);
 871         apic_set_reg(apic, APIC_TDCR, 0);
 872         apic_set_reg(apic, APIC_TMICT, 0);
 873         for (i = 0; i < 8; i++) {
 874                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 875                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 876                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 877         }
 878         update_divide_count(apic);
 879         atomic_set(&apic->timer.pending, 0);
 880         if (vcpu->vcpu_id == 0)
 881                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 882         apic_update_ppr(apic);
 883
 884         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 885                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 886                    vcpu, kvm_apic_id(apic),
 887                    vcpu->arch.apic_base, apic->base_address);
 888 }
 889 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 890
 891 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 892 {
 893         struct kvm_lapic *apic = vcpu->arch.apic;
 894         int ret = 0;
 895
 896         if (!apic)
 897                 return 0;
 898         ret = apic_enabled(apic);
 899
 900         return ret;
 901 }
 902 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 903
 904 /*
 905  *----------------------------------------------------------------------
 906  * timer interface
 907  *----------------------------------------------------------------------
 908  */
 909
 910 /* TODO: make sure __apic_timer_fn runs in current pCPU */
 911 static int __apic_timer_fn(struct kvm_lapic *apic)
 912 {
 913         int result = 0;
 914         wait_queue_head_t *q = &apic->vcpu->wq;
 915
 916         if(!atomic_inc_and_test(&apic->timer.pending))
 917                 set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests);
 918         if (waitqueue_active(q))
 919                 wake_up_interruptible(q);
 920
 921         if (apic_lvtt_period(apic)) {
 922                 result = 1;
 923                 hrtimer_add_expires_ns(&apic->timer.dev, apic->timer.period);
 924         }
 925         return result;
 926 }
 927
 928 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 929 {
 930         struct kvm_lapic *lapic = vcpu->arch.apic;
 931
 932         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 933                 return atomic_read(&lapic->timer.pending);
 934
 935         return 0;
 936 }
 937
 938 static int __inject_apic_timer_irq(struct kvm_lapic *apic)
 939 {
 940         int vector;
 941
 942         vector = apic_lvt_vector(apic, APIC_LVTT);
 943         return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
 944 }
 945
 946 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
 947 {
 948         struct kvm_lapic *apic;
 949         int restart_timer = 0;
 950
 951         apic = container_of(data, struct kvm_lapic, timer.dev);
 952
 953         restart_timer = __apic_timer_fn(apic);
 954
 955         if (restart_timer)
 956                 return HRTIMER_RESTART;
 957         else
 958                 return HRTIMER_NORESTART;
 959 }
 960
 961 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 962 {
 963         struct kvm_lapic *apic;
 964
 965         ASSERT(vcpu != NULL);
 966         apic_debug("apic_init %d\n", vcpu->vcpu_id);
 967
 968         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
 969         if (!apic)
 970                 goto nomem;
 971
 972         vcpu->arch.apic = apic;
 973
 974         apic->regs_page = alloc_page(GFP_KERNEL);
 975         if (apic->regs_page == NULL) {
 976                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
 977                        vcpu->vcpu_id);
 978                 goto nomem_free_apic;
 979         }
 980         apic->regs = page_address(apic->regs_page);
 981         memset(apic->regs, 0, PAGE_SIZE);
 982         apic->vcpu = vcpu;
 983
 984         hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
 985         apic->timer.dev.function = apic_timer_fn;
 986         apic->base_address = APIC_DEFAULT_PHYS_BASE;
 987         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
 988
 989         kvm_lapic_reset(vcpu);
 990         apic->dev.read = apic_mmio_read;
 991         apic->dev.write = apic_mmio_write;
 992         apic->dev.in_range = apic_mmio_range;
 993         apic->dev.private = apic;
 994
 995         return 0;
 996 nomem_free_apic:
 997         kfree(apic);
 998 nomem:
 999         return -ENOMEM;
1000 }
1001 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1002
1003 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1004 {
1005         struct kvm_lapic *apic = vcpu->arch.apic;
1006         int highest_irr;
1007
1008         if (!apic || !apic_enabled(apic))
1009                 return -1;
1010
1011         apic_update_ppr(apic);
1012         highest_irr = apic_find_highest_irr(apic);
1013         if ((highest_irr == -1) ||
1014             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1015                 return -1;
1016         return highest_irr;
1017 }
1018
1019 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1020 {
1021         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1022         int r = 0;
1023
1024         if (vcpu->vcpu_id == 0) {
1025                 if (!apic_hw_enabled(vcpu->arch.apic))
1026                         r = 1;
1027                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1028                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1029                         r = 1;
1030         }
1031         return r;
1032 }
1033
1034 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1035 {
1036         struct kvm_lapic *apic = vcpu->arch.apic;
1037
1038         if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1039                 atomic_read(&apic->timer.pending) > 0) {
1040                 if (__inject_apic_timer_irq(apic))
1041                         atomic_dec(&apic->timer.pending);
1042         }
1043 }
1044
1045 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1046 {
1047         int vector = kvm_apic_has_interrupt(vcpu);
1048         struct kvm_lapic *apic = vcpu->arch.apic;
1049
1050         if (vector == -1)
1051                 return -1;
1052
1053         apic_set_vector(vector, apic->regs + APIC_ISR);
1054         apic_update_ppr(apic);
1055         apic_clear_irr(vector, apic);
1056         return vector;
1057 }
1058
1059 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1060 {
1061         struct kvm_lapic *apic = vcpu->arch.apic;
1062
1063         apic->base_address = vcpu->arch.apic_base &
1064                              MSR_IA32_APICBASE_BASE;
1065         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1066         apic_update_ppr(apic);
1067         hrtimer_cancel(&apic->timer.dev);
1068         update_divide_count(apic);
1069         start_apic_timer(apic);
1070 }
1071
1072 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1073 {
1074         struct kvm_lapic *apic = vcpu->arch.apic;
1075         struct hrtimer *timer;
1076
1077         if (!apic)
1078                 return;
1079
1080         timer = &apic->timer.dev;
1081         if (hrtimer_cancel(timer))
1082                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1083 }
1084
1085 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1086 {
1087         u32 data;
1088         void *vapic;
1089
1090         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1091                 return;
1092
1093         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1094         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1095         kunmap_atomic(vapic, KM_USER0);
1096
1097         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1098 }
1099
1100 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1101 {
1102         u32 data, tpr;
1103         int max_irr, max_isr;
1104         struct kvm_lapic *apic;
1105         void *vapic;
1106
1107         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1108                 return;
1109
1110         apic = vcpu->arch.apic;
1111         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1112         max_irr = apic_find_highest_irr(apic);
1113         if (max_irr < 0)
1114                 max_irr = 0;
1115         max_isr = apic_find_highest_isr(apic);
1116         if (max_isr < 0)
1117                 max_isr = 0;
1118         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1119
1120         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1121         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1122         kunmap_atomic(vapic, KM_USER0);
1123 }
1124
1125 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1126 {
1127         if (!irqchip_in_kernel(vcpu->kvm))
1128                 return;
1129
1130         vcpu->arch.apic->vapic_addr = vapic_addr;
1131 }