include/asm-mips/txx9/tx4938.h

   1 /*
   2  * Definitions for TX4937/TX4938
   3  * Copyright (C) 2000-2001 Toshiba Corporation
   4  *
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  *
  10  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11  */
  12 #ifndef __ASM_TXX9_TX4938_H
  13 #define __ASM_TXX9_TX4938_H
  14
  15 /* some controllers are compatible with 4927 */
  16 #include <asm/txx9/tx4927.h>
  17
  18 #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
  19 #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
  20
  21 #define TX4938_NR_IRQ_LOCAL     TX4938_IRQ_PIC_BEG
  22
  23 #define TX4938_IRQ_IRC_PCIC     (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
  24 #define TX4938_IRQ_IRC_PCIERR   (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
  25
  26 #define TX4938_PCIIO_0 0x10000000
  27 #define TX4938_PCIIO_1 0x01010000
  28 #define TX4938_PCIMEM_0 0x08000000
  29 #define TX4938_PCIMEM_1 0x11000000
  30
  31 #define TX4938_PCIIO_SIZE_0 0x01000000
  32 #define TX4938_PCIIO_SIZE_1 0x00010000
  33 #define TX4938_PCIMEM_SIZE_0 0x08000000
  34 #define TX4938_PCIMEM_SIZE_1 0x00010000
  35
  36 #define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
  37 #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
  38
  39 /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
  40 #define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
  41 #define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
  42 #define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
  43 #define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
  44 #define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
  45 #define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
  46 #define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
  47 #define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
  48 #define TX4938_NR_TMR   3
  49 #define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
  50 #define TX4938_NR_SIO   2
  51 #define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
  52 #define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
  53 #define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
  54 #define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
  55 #define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
  56
  57 #define _CONST64(c)     c##ull
  58
  59 #include <asm/byteorder.h>
  60
  61 #ifdef __BIG_ENDIAN
  62 #define endian_def_l2(e1, e2)   \
  63         volatile unsigned long e1, e2
  64 #define endian_def_s2(e1, e2)   \
  65         volatile unsigned short e1, e2
  66 #define endian_def_sb2(e1, e2, e3)      \
  67         volatile unsigned short e1;volatile unsigned char e2, e3
  68 #define endian_def_b2s(e1, e2, e3)      \
  69         volatile unsigned char e1, e2;volatile unsigned short e3
  70 #define endian_def_b4(e1, e2, e3, e4)   \
  71         volatile unsigned char e1, e2, e3, e4
  72 #else
  73 #define endian_def_l2(e1, e2)   \
  74         volatile unsigned long e2, e1
  75 #define endian_def_s2(e1, e2)   \
  76         volatile unsigned short e2, e1
  77 #define endian_def_sb2(e1, e2, e3)      \
  78         volatile unsigned char e3, e2;volatile unsigned short e1
  79 #define endian_def_b2s(e1, e2, e3)      \
  80         volatile unsigned short e3;volatile unsigned char e2, e1
  81 #define endian_def_b4(e1, e2, e3, e4)   \
  82         volatile unsigned char e4, e3, e2, e1
  83 #endif
  84
  85
  86 struct tx4938_sdramc_reg {
  87         volatile unsigned long long cr[4];
  88         volatile unsigned long long unused0[4];
  89         volatile unsigned long long tr;
  90         volatile unsigned long long unused1[2];
  91         volatile unsigned long long cmd;
  92         volatile unsigned long long sfcmd;
  93 };
  94
  95 struct tx4938_ebusc_reg {
  96         volatile unsigned long long cr[8];
  97 };
  98
  99 struct tx4938_dma_reg {
 100         struct tx4938_dma_ch_reg {
 101                 volatile unsigned long long cha;
 102                 volatile unsigned long long sar;
 103                 volatile unsigned long long dar;
 104                 endian_def_l2(unused0, cntr);
 105                 endian_def_l2(unused1, sair);
 106                 endian_def_l2(unused2, dair);
 107                 endian_def_l2(unused3, ccr);
 108                 endian_def_l2(unused4, csr);
 109         } ch[4];
 110         volatile unsigned long long dbr[8];
 111         volatile unsigned long long tdhr;
 112         volatile unsigned long long midr;
 113         endian_def_l2(unused0, mcr);
 114 };
 115
 116 struct tx4938_aclc_reg {
 117         volatile unsigned long acctlen;
 118         volatile unsigned long acctldis;
 119         volatile unsigned long acregacc;
 120         volatile unsigned long unused0;
 121         volatile unsigned long acintsts;
 122         volatile unsigned long acintmsts;
 123         volatile unsigned long acinten;
 124         volatile unsigned long acintdis;
 125         volatile unsigned long acsemaph;
 126         volatile unsigned long unused1[7];
 127         volatile unsigned long acgpidat;
 128         volatile unsigned long acgpodat;
 129         volatile unsigned long acslten;
 130         volatile unsigned long acsltdis;
 131         volatile unsigned long acfifosts;
 132         volatile unsigned long unused2[11];
 133         volatile unsigned long acdmasts;
 134         volatile unsigned long acdmasel;
 135         volatile unsigned long unused3[6];
 136         volatile unsigned long acaudodat;
 137         volatile unsigned long acsurrdat;
 138         volatile unsigned long accentdat;
 139         volatile unsigned long aclfedat;
 140         volatile unsigned long acaudiat;
 141         volatile unsigned long unused4;
 142         volatile unsigned long acmodoat;
 143         volatile unsigned long acmodidat;
 144         volatile unsigned long unused5[15];
 145         volatile unsigned long acrevid;
 146 };
 147
 148
 149 struct tx4938_tmr_reg {
 150         volatile unsigned long tcr;
 151         volatile unsigned long tisr;
 152         volatile unsigned long cpra;
 153         volatile unsigned long cprb;
 154         volatile unsigned long itmr;
 155         volatile unsigned long unused0[3];
 156         volatile unsigned long ccdr;
 157         volatile unsigned long unused1[3];
 158         volatile unsigned long pgmr;
 159         volatile unsigned long unused2[3];
 160         volatile unsigned long wtmr;
 161         volatile unsigned long unused3[43];
 162         volatile unsigned long trr;
 163 };
 164
 165 struct tx4938_sio_reg {
 166         volatile unsigned long lcr;
 167         volatile unsigned long dicr;
 168         volatile unsigned long disr;
 169         volatile unsigned long cisr;
 170         volatile unsigned long fcr;
 171         volatile unsigned long flcr;
 172         volatile unsigned long bgr;
 173         volatile unsigned long tfifo;
 174         volatile unsigned long rfifo;
 175 };
 176
 177 struct tx4938_ndfmc_reg {
 178         endian_def_l2(unused0, dtr);
 179         endian_def_l2(unused1, mcr);
 180         endian_def_l2(unused2, sr);
 181         endian_def_l2(unused3, isr);
 182         endian_def_l2(unused4, imr);
 183         endian_def_l2(unused5, spr);
 184         endian_def_l2(unused6, rstr);
 185 };
 186
 187 struct tx4938_spi_reg {
 188         volatile unsigned long mcr;
 189         volatile unsigned long cr0;
 190         volatile unsigned long cr1;
 191         volatile unsigned long fs;
 192         volatile unsigned long unused1;
 193         volatile unsigned long sr;
 194         volatile unsigned long dr;
 195         volatile unsigned long unused2;
 196 };
 197
 198 struct tx4938_sramc_reg {
 199         volatile unsigned long long cr;
 200 };
 201
 202 struct tx4938_ccfg_reg {
 203         u64 ccfg;
 204         u64 crir;
 205         u64 pcfg;
 206         u64 toea;
 207         u64 clkctr;
 208         u64 unused0;
 209         u64 garbc;
 210         u64 unused1;
 211         u64 unused2;
 212         u64 ramp;
 213         u64 unused3;
 214         u64 jmpadr;
 215 };
 216
 217 #undef endian_def_l2
 218 #undef endian_def_s2
 219 #undef endian_def_sb2
 220 #undef endian_def_b2s
 221 #undef endian_def_b4
 222
 223 /*
 224  * NDFMC
 225  */
 226
 227 /* NDFMCR : NDFMC Mode Control */
 228 #define TX4938_NDFMCR_WE        0x80
 229 #define TX4938_NDFMCR_ECC_ALL   0x60
 230 #define TX4938_NDFMCR_ECC_RESET 0x60
 231 #define TX4938_NDFMCR_ECC_READ  0x40
 232 #define TX4938_NDFMCR_ECC_ON    0x20
 233 #define TX4938_NDFMCR_ECC_OFF   0x00
 234 #define TX4938_NDFMCR_CE        0x10
 235 #define TX4938_NDFMCR_BSPRT     0x04
 236 #define TX4938_NDFMCR_ALE       0x02
 237 #define TX4938_NDFMCR_CLE       0x01
 238
 239 /* NDFMCR : NDFMC Status */
 240 #define TX4938_NDFSR_BUSY       0x80
 241
 242 /* NDFMCR : NDFMC Reset */
 243 #define TX4938_NDFRSTR_RST      0x01
 244
 245 /*
 246  * IRC
 247  */
 248
 249 #define TX4938_IR_ECCERR        0
 250 #define TX4938_IR_WTOERR        1
 251 #define TX4938_NUM_IR_INT       6
 252 #define TX4938_IR_INT(n)        (2 + (n))
 253 #define TX4938_NUM_IR_SIO       2
 254 #define TX4938_IR_SIO(n)        (8 + (n))
 255 #define TX4938_NUM_IR_DMA       4
 256 #define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
 257 #define TX4938_IR_PIO   14
 258 #define TX4938_IR_PDMAC 15
 259 #define TX4938_IR_PCIC  16
 260 #define TX4938_NUM_IR_TMR       3
 261 #define TX4938_IR_TMR(n)        (17 + (n))
 262 #define TX4938_IR_NDFMC 21
 263 #define TX4938_IR_PCIERR        22
 264 #define TX4938_IR_PCIPME        23
 265 #define TX4938_IR_ACLC  24
 266 #define TX4938_IR_ACLCPME       25
 267 #define TX4938_IR_PCIC1 26
 268 #define TX4938_IR_SPI   31
 269 #define TX4938_NUM_IR   32
 270 /* multiplex */
 271 #define TX4938_IR_ETH0  TX4938_IR_INT(4)
 272 #define TX4938_IR_ETH1  TX4938_IR_INT(3)
 273
 274 /*
 275  * CCFG
 276  */
 277 /* CCFG : Chip Configuration */
 278 #define TX4938_CCFG_WDRST       _CONST64(0x0000020000000000)
 279 #define TX4938_CCFG_WDREXEN     _CONST64(0x0000010000000000)
 280 #define TX4938_CCFG_BCFG_MASK   _CONST64(0x000000ff00000000)
 281 #define TX4938_CCFG_TINTDIS     0x01000000
 282 #define TX4938_CCFG_PCI66       0x00800000
 283 #define TX4938_CCFG_PCIMODE     0x00400000
 284 #define TX4938_CCFG_PCI1_66     0x00200000
 285 #define TX4938_CCFG_DIVMODE_MASK        0x001e0000
 286 #define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
 287 #define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
 288 #define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
 289 #define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
 290 #define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
 291 #define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
 292 #define TX4938_CCFG_DIVMODE_10  (0xb << 17)
 293 #define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
 294 #define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
 295 #define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
 296 #define TX4938_CCFG_BEOW        0x00010000
 297 #define TX4938_CCFG_WR  0x00008000
 298 #define TX4938_CCFG_TOE 0x00004000
 299 #define TX4938_CCFG_PCIARB      0x00002000
 300 #define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
 301 #define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
 302 #define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
 303 #define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
 304 #define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
 305 #define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
 306 #define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
 307 #define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
 308 #define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
 309 #define TX4938_CCFG_PCI1DMD     0x00000100
 310 #define TX4938_CCFG_SYSSP_MASK  0x000000c0
 311 #define TX4938_CCFG_ENDIAN      0x00000004
 312 #define TX4938_CCFG_HALT        0x00000002
 313 #define TX4938_CCFG_ACEHOLD     0x00000001
 314
 315 /* PCFG : Pin Configuration */
 316 #define TX4938_PCFG_ETH0_SEL    _CONST64(0x8000000000000000)
 317 #define TX4938_PCFG_ETH1_SEL    _CONST64(0x4000000000000000)
 318 #define TX4938_PCFG_ATA_SEL     _CONST64(0x2000000000000000)
 319 #define TX4938_PCFG_ISA_SEL     _CONST64(0x1000000000000000)
 320 #define TX4938_PCFG_SPI_SEL     _CONST64(0x0800000000000000)
 321 #define TX4938_PCFG_NDF_SEL     _CONST64(0x0400000000000000)
 322 #define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
 323 #define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
 324 #define TX4938_PCFG_SYSCLKEN    0x08000000
 325 #define TX4938_PCFG_SDCLKEN_ALL 0x07800000
 326 #define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
 327 #define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
 328 #define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
 329 #define TX4938_PCFG_SEL2        0x00000200
 330 #define TX4938_PCFG_SEL1        0x00000100
 331 #define TX4938_PCFG_DMASEL_ALL  0x0000000f
 332 #define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
 333 #define TX4938_PCFG_DMASEL0_SIO1        0x00000001
 334 #define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
 335 #define TX4938_PCFG_DMASEL1_SIO1        0x00000002
 336 #define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
 337 #define TX4938_PCFG_DMASEL2_SIO0        0x00000004
 338 #define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
 339 #define TX4938_PCFG_DMASEL3_SIO0        0x00000008
 340
 341 /* CLKCTR : Clock Control */
 342 #define TX4938_CLKCTR_NDFCKD    _CONST64(0x0001000000000000)
 343 #define TX4938_CLKCTR_NDFRST    _CONST64(0x0000000100000000)
 344 #define TX4938_CLKCTR_ETH1CKD   0x80000000
 345 #define TX4938_CLKCTR_ETH0CKD   0x40000000
 346 #define TX4938_CLKCTR_SPICKD    0x20000000
 347 #define TX4938_CLKCTR_SRAMCKD   0x10000000
 348 #define TX4938_CLKCTR_PCIC1CKD  0x08000000
 349 #define TX4938_CLKCTR_DMA1CKD   0x04000000
 350 #define TX4938_CLKCTR_ACLCKD    0x02000000
 351 #define TX4938_CLKCTR_PIOCKD    0x01000000
 352 #define TX4938_CLKCTR_DMACKD    0x00800000
 353 #define TX4938_CLKCTR_PCICKD    0x00400000
 354 #define TX4938_CLKCTR_TM0CKD    0x00100000
 355 #define TX4938_CLKCTR_TM1CKD    0x00080000
 356 #define TX4938_CLKCTR_TM2CKD    0x00040000
 357 #define TX4938_CLKCTR_SIO0CKD   0x00020000
 358 #define TX4938_CLKCTR_SIO1CKD   0x00010000
 359 #define TX4938_CLKCTR_ETH1RST   0x00008000
 360 #define TX4938_CLKCTR_ETH0RST   0x00004000
 361 #define TX4938_CLKCTR_SPIRST    0x00002000
 362 #define TX4938_CLKCTR_SRAMRST   0x00001000
 363 #define TX4938_CLKCTR_PCIC1RST  0x00000800
 364 #define TX4938_CLKCTR_DMA1RST   0x00000400
 365 #define TX4938_CLKCTR_ACLRST    0x00000200
 366 #define TX4938_CLKCTR_PIORST    0x00000100
 367 #define TX4938_CLKCTR_DMARST    0x00000080
 368 #define TX4938_CLKCTR_PCIRST    0x00000040
 369 #define TX4938_CLKCTR_TM0RST    0x00000010
 370 #define TX4938_CLKCTR_TM1RST    0x00000008
 371 #define TX4938_CLKCTR_TM2RST    0x00000004
 372 #define TX4938_CLKCTR_SIO0RST   0x00000002
 373 #define TX4938_CLKCTR_SIO1RST   0x00000001
 374
 375 /*
 376  * DMA
 377  */
 378 /* bits for MCR */
 379 #define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
 380 #define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
 381 #define TX4938_DMA_MCR_RSFIF    0x00000080
 382 #define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
 383 #define TX4938_DMA_MCR_RPRT     0x00000002
 384 #define TX4938_DMA_MCR_MSTEN    0x00000001
 385
 386 /* bits for CCRn */
 387 #define TX4938_DMA_CCR_IMMCHN   0x20000000
 388 #define TX4938_DMA_CCR_USEXFSZ  0x10000000
 389 #define TX4938_DMA_CCR_LE       0x08000000
 390 #define TX4938_DMA_CCR_DBINH    0x04000000
 391 #define TX4938_DMA_CCR_SBINH    0x02000000
 392 #define TX4938_DMA_CCR_CHRST    0x01000000
 393 #define TX4938_DMA_CCR_RVBYTE   0x00800000
 394 #define TX4938_DMA_CCR_ACKPOL   0x00400000
 395 #define TX4938_DMA_CCR_REQPL    0x00200000
 396 #define TX4938_DMA_CCR_EGREQ    0x00100000
 397 #define TX4938_DMA_CCR_CHDN     0x00080000
 398 #define TX4938_DMA_CCR_DNCTL    0x00060000
 399 #define TX4938_DMA_CCR_EXTRQ    0x00010000
 400 #define TX4938_DMA_CCR_INTRQD   0x0000e000
 401 #define TX4938_DMA_CCR_INTENE   0x00001000
 402 #define TX4938_DMA_CCR_INTENC   0x00000800
 403 #define TX4938_DMA_CCR_INTENT   0x00000400
 404 #define TX4938_DMA_CCR_CHNEN    0x00000200
 405 #define TX4938_DMA_CCR_XFACT    0x00000100
 406 #define TX4938_DMA_CCR_SMPCHN   0x00000020
 407 #define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
 408 #define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
 409 #define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
 410 #define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
 411 #define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
 412 #define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
 413 #define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
 414 #define TX4938_DMA_CCR_MEMIO    0x00000002
 415 #define TX4938_DMA_CCR_SNGAD    0x00000001
 416
 417 /* bits for CSRn */
 418 #define TX4938_DMA_CSR_CHNEN    0x00000400
 419 #define TX4938_DMA_CSR_STLXFER  0x00000200
 420 #define TX4938_DMA_CSR_CHNACT   0x00000100
 421 #define TX4938_DMA_CSR_ABCHC    0x00000080
 422 #define TX4938_DMA_CSR_NCHNC    0x00000040
 423 #define TX4938_DMA_CSR_NTRNFC   0x00000020
 424 #define TX4938_DMA_CSR_EXTDN    0x00000010
 425 #define TX4938_DMA_CSR_CFERR    0x00000008
 426 #define TX4938_DMA_CSR_CHERR    0x00000004
 427 #define TX4938_DMA_CSR_DESERR   0x00000002
 428 #define TX4938_DMA_CSR_SORERR   0x00000001
 429
 430 #define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
 431 #define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
 432 #define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
 433 #define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
 434 #define tx4938_pcicptr          tx4927_pcicptr
 435 #define tx4938_pcic1ptr \
 436                 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
 437 #define tx4938_ccfgptr \
 438                 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
 439 #define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
 440 #define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
 441 #define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
 442 #define tx4938_spiptr           ((struct tx4938_spi_reg *)TX4938_SPI_REG)
 443 #define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
 444
 445
 446 #define TX4938_REV_PCODE()      \
 447         ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
 448
 449 #define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
 450 #define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
 451 #define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
 452
 453 #define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
 454 #define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
 455
 456 #define TX4938_EBUSC_CR(ch)     __raw_readq(&tx4938_ebuscptr->cr[(ch)])
 457 #define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
 458 #define TX4938_EBUSC_SIZE(ch)   \
 459         (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
 460
 461 int tx4938_report_pciclk(void);
 462 void tx4938_report_pci1clk(void);
 463 int tx4938_pciclk66_setup(void);
 464 struct pci_dev;
 465 int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
 466
 467 #endif