2 * linux/arch/mips/txx9/pci.c
4 * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
5 * linux/arch/mips/txx9/rbtx4938/setup.c,
6 * and RBTX49xx patch from CELF patch archive.
8 * Copyright 2001-2005 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
16 #include <linux/delay.h>
17 #include <linux/jiffies.h>
19 #include <asm/txx9/pci.h>
20 #ifdef CONFIG_TOSHIBA_FPCIB0
21 #include <linux/interrupt.h>
22 #include <asm/i8259.h>
23 #include <asm/txx9/smsc_fdc37m81x.h>
27 early_read_config_word(struct pci_controller
*hose
,
28 int top_bus
, int bus
, int devfn
, int offset
, u16
*value
)
30 struct pci_dev fake_dev
;
31 struct pci_bus fake_bus
;
33 fake_dev
.bus
= &fake_bus
;
34 fake_dev
.sysdata
= hose
;
35 fake_dev
.devfn
= devfn
;
36 fake_bus
.number
= bus
;
37 fake_bus
.sysdata
= hose
;
38 fake_bus
.ops
= hose
->pci_ops
;
41 /* Fake a parent bus structure. */
42 fake_bus
.parent
= &fake_bus
;
44 fake_bus
.parent
= NULL
;
46 return pci_read_config_word(&fake_dev
, offset
, value
);
49 int __init
txx9_pci66_check(struct pci_controller
*hose
, int top_bus
,
57 /* It seems SLC90E66 needs some time after PCI reset... */
60 printk(KERN_INFO
"PCI: Checking 66MHz capabilities...\n");
62 for (pci_devfn
= 0; pci_devfn
< 0xff; pci_devfn
++) {
63 if (PCI_FUNC(pci_devfn
))
65 if (early_read_config_word(hose
, top_bus
, current_bus
,
66 pci_devfn
, PCI_VENDOR_ID
, &vid
) !=
72 /* check 66MHz capability */
76 early_read_config_word(hose
, top_bus
, current_bus
,
77 pci_devfn
, PCI_STATUS
, &stat
);
78 if (!(stat
& PCI_STATUS_66MHZ
)) {
80 "PCI: %02x:%02x not 66MHz capable.\n",
81 current_bus
, pci_devfn
);
90 static struct resource primary_pci_mem_res
[2] = {
91 { .name
= "PCI MEM" },
92 { .name
= "PCI MMIO" },
94 static struct resource primary_pci_io_res
= { .name
= "PCI IO" };
95 struct pci_controller txx9_primary_pcic
= {
96 .mem_resource
= &primary_pci_mem_res
[0],
97 .io_resource
= &primary_pci_io_res
,
101 int txx9_pci_mem_high __initdata
= 1;
103 int txx9_pci_mem_high __initdata
;
107 * allocate pci_controller and resources.
108 * mem_base, io_base: physical addresss. 0 for auto assignment.
109 * mem_size and io_size means max size on auto assignment.
110 * pcic must be &txx9_primary_pcic or NULL.
112 struct pci_controller
*__init
113 txx9_alloc_pci_controller(struct pci_controller
*pcic
,
114 unsigned long mem_base
, unsigned long mem_size
,
115 unsigned long io_base
, unsigned long io_size
)
118 struct pci_controller c
;
119 struct resource r_mem
[2];
120 struct resource r_io
;
122 int min_size
= 0x10000;
125 new = kzalloc(sizeof(*new), GFP_KERNEL
);
128 new->r_mem
[0].name
= "PCI mem";
129 new->r_mem
[1].name
= "PCI mmio";
130 new->r_io
.name
= "PCI io";
131 new->c
.mem_resource
= new->r_mem
;
132 new->c
.io_resource
= &new->r_io
;
135 BUG_ON(pcic
!= &txx9_primary_pcic
);
136 pcic
->io_resource
->flags
= IORESOURCE_IO
;
139 * for auto assignment, first search a (big) region for PCI
140 * MEM, then search a region for PCI IO.
143 pcic
->mem_resource
[0].start
= mem_base
;
144 pcic
->mem_resource
[0].end
= mem_base
+ mem_size
- 1;
145 if (request_resource(&iomem_resource
, &pcic
->mem_resource
[0]))
148 unsigned long min
= 0, max
= 0x20000000; /* low 512MB */
150 /* default size for auto assignment */
151 if (txx9_pci_mem_high
)
152 mem_size
= 0x20000000; /* mem:512M(max) */
154 mem_size
= 0x08000000; /* mem:128M(max) */
156 if (txx9_pci_mem_high
) {
160 /* search free region for PCI MEM */
161 for (; mem_size
>= min_size
; mem_size
/= 2) {
162 if (allocate_resource(&iomem_resource
,
163 &pcic
->mem_resource
[0],
165 mem_size
, NULL
, NULL
) == 0)
168 if (mem_size
< min_size
)
172 pcic
->mem_resource
[1].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
174 pcic
->mem_resource
[1].start
= io_base
;
175 pcic
->mem_resource
[1].end
= io_base
+ io_size
- 1;
176 if (request_resource(&iomem_resource
, &pcic
->mem_resource
[1]))
177 goto release_and_exit
;
180 /* default size for auto assignment */
181 io_size
= 0x01000000; /* io:16M(max) */
182 /* search free region for PCI IO in low 512MB */
183 for (; io_size
>= min_size
; io_size
/= 2) {
184 if (allocate_resource(&iomem_resource
,
185 &pcic
->mem_resource
[1],
186 io_size
, 0, 0x20000000,
187 io_size
, NULL
, NULL
) == 0)
190 if (io_size
< min_size
)
191 goto release_and_exit
;
192 io_base
= pcic
->mem_resource
[1].start
;
195 pcic
->mem_resource
[0].flags
= IORESOURCE_MEM
;
196 if (pcic
== &txx9_primary_pcic
&&
197 mips_io_port_base
== (unsigned long)-1) {
198 /* map ioport 0 to PCI I/O space address 0 */
199 set_io_port_base(IO_BASE
+ pcic
->mem_resource
[1].start
);
200 pcic
->io_resource
->start
= 0;
201 pcic
->io_offset
= 0; /* busaddr == ioaddr */
202 pcic
->io_map_base
= IO_BASE
+ pcic
->mem_resource
[1].start
;
204 /* physaddr to ioaddr */
205 pcic
->io_resource
->start
=
206 io_base
- (mips_io_port_base
- IO_BASE
);
207 pcic
->io_offset
= io_base
- (mips_io_port_base
- IO_BASE
);
208 pcic
->io_map_base
= mips_io_port_base
;
210 pcic
->io_resource
->end
= pcic
->io_resource
->start
+ io_size
- 1;
212 pcic
->mem_offset
= 0; /* busaddr == physaddr */
214 printk(KERN_INFO
"PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n",
215 (unsigned long long)pcic
->mem_resource
[1].start
,
216 (unsigned long long)pcic
->mem_resource
[1].end
,
217 (unsigned long long)pcic
->mem_resource
[0].start
,
218 (unsigned long long)pcic
->mem_resource
[0].end
);
220 /* register_pci_controller() will request MEM resource */
221 release_resource(&pcic
->mem_resource
[0]);
224 release_resource(&pcic
->mem_resource
[0]);
227 printk(KERN_ERR
"PCI: Failed to allocate resources.\n");
232 txx9_arch_pci_init(void)
234 PCIBIOS_MIN_IO
= 0x8000; /* reseve legacy I/O space */
237 arch_initcall(txx9_arch_pci_init
);
239 /* IRQ/IDSEL mapping */
240 int txx9_pci_option
=
241 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
244 TXX9_PCI_OPT_CLK_AUTO
;
246 enum txx9_pci_err_action txx9_pci_err_action
= TXX9_PCI_ERR_REPORT
;
248 #ifdef CONFIG_TOSHIBA_FPCIB0
249 static irqreturn_t
i8259_interrupt(int irq
, void *dev_id
)
253 isairq
= i8259_irq();
254 if (unlikely(isairq
<= I8259A_IRQ_BASE
))
256 generic_handle_irq(isairq
);
261 txx9_i8259_irq_setup(int irq
)
266 err
= request_irq(irq
, &i8259_interrupt
, IRQF_DISABLED
|IRQF_SHARED
,
267 "cascade(i8259)", (void *)(long)irq
);
269 printk(KERN_INFO
"PCI-ISA bridge PIC (irq %d)\n", irq
);
273 static void __init
quirk_slc90e66_bridge(struct pci_dev
*dev
)
275 int irq
; /* PCI/ISA Bridge interrupt */
279 irq
= pcibios_map_irq(dev
, PCI_SLOT(dev
->devfn
), 1); /* INTA */
282 txx9_i8259_irq_setup(irq
);
283 pci_read_config_byte(dev
, 0x64, ®_64
);
284 pci_read_config_dword(dev
, 0xb0, ®_b0
);
285 pci_read_config_byte(dev
, 0xe1, ®_e1
);
286 /* serial irq control */
289 reg_b0
|= 0x00010000;
290 /* ide irq on isa14 */
293 pci_write_config_byte(dev
, 0x64, reg_64
);
294 pci_write_config_dword(dev
, 0xb0, reg_b0
);
295 pci_write_config_byte(dev
, 0xe1, reg_e1
);
297 smsc_fdc37m81x_init(0x3f0);
298 smsc_fdc37m81x_config_beg();
299 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM
,
301 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT
, 1);
302 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2
, 12);
303 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE
,
305 smsc_fdc37m81x_config_end();
308 static void quirk_slc90e66_ide(struct pci_dev
*dev
)
311 int regs
[2] = {0x41, 0x43};
314 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
315 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, 14);
316 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &dat
);
317 printk(KERN_INFO
"PCI: %s: IRQ %02x", pci_name(dev
), dat
);
318 /* enable SMSC SLC90E66 IDE */
319 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
320 pci_read_config_byte(dev
, regs
[i
], &dat
);
321 pci_write_config_byte(dev
, regs
[i
], dat
| 0x80);
322 pci_read_config_byte(dev
, regs
[i
], &dat
);
323 printk(KERN_CONT
" IDETIM%d %02x", i
, dat
);
325 pci_read_config_byte(dev
, 0x5c, &dat
);
327 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
329 * This line of code is intended to provide the user with a work
330 * around solution to the anomalies cited in SMSC's anomaly sheet
331 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
333 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
336 pci_write_config_byte(dev
, regs
[i
], dat
);
337 pci_read_config_byte(dev
, 0x5c, &dat
);
338 printk(KERN_CONT
" REG5C %02x", dat
);
339 printk(KERN_CONT
"\n");
341 #endif /* CONFIG_TOSHIBA_FPCIB0 */
343 static void final_fixup(struct pci_dev
*dev
)
347 /* Do build-in self test */
348 if (pci_read_config_byte(dev
, PCI_BIST
, &bist
) == PCIBIOS_SUCCESSFUL
&&
349 (bist
& PCI_BIST_CAPABLE
)) {
350 unsigned long timeout
;
351 pci_set_power_state(dev
, PCI_D0
);
352 printk(KERN_INFO
"PCI: %s BIST...", pci_name(dev
));
353 pci_write_config_byte(dev
, PCI_BIST
, PCI_BIST_START
);
354 timeout
= jiffies
+ HZ
* 2; /* timeout after 2 sec */
356 pci_read_config_byte(dev
, PCI_BIST
, &bist
);
357 if (time_after(jiffies
, timeout
))
359 } while (bist
& PCI_BIST_START
);
360 if (bist
& (PCI_BIST_CODE_MASK
| PCI_BIST_START
))
361 printk(KERN_CONT
"failed. (0x%x)\n", bist
);
363 printk(KERN_CONT
"OK.\n");
367 #ifdef CONFIG_TOSHIBA_FPCIB0
368 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_0
,
370 quirk_slc90e66_bridge
);
371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_1
,
373 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_1
,
376 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, final_fixup
);
377 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID
, PCI_ANY_ID
, final_fixup
);