2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic
;
63 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
64 static int disable_apic_timer __cpuinitdata
;
65 /* Local APIC timer works in C2 */
66 int local_apic_timer_c2_ok
;
67 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
69 int first_system_vector
= 0xfe;
71 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
74 * Debug level, exported for io_apic.c
76 unsigned int apic_verbosity
;
80 /* Have we found an MP table */
83 static struct resource lapic_resource
= {
85 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
88 static unsigned int calibration_result
;
90 static int lapic_next_event(unsigned long delta
,
91 struct clock_event_device
*evt
);
92 static void lapic_timer_setup(enum clock_event_mode mode
,
93 struct clock_event_device
*evt
);
94 static void lapic_timer_broadcast(cpumask_t mask
);
95 static void apic_pm_activate(void);
98 * The local apic timer can be used for any function which is CPU local.
100 static struct clock_event_device lapic_clockevent
= {
102 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
103 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
105 .set_mode
= lapic_timer_setup
,
106 .set_next_event
= lapic_next_event
,
107 .broadcast
= lapic_timer_broadcast
,
111 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase
;
116 static unsigned long apic_phys
;
119 * Get the LAPIC version
121 static inline int lapic_get_version(void)
123 return GET_APIC_VERSION(apic_read(APIC_LVR
));
127 * Check, if the APIC is integrated or a separate chip
129 static inline int lapic_is_integrated(void)
134 return APIC_INTEGRATED(lapic_get_version());
139 * Check, whether this is a modern or a first generation APIC
141 static int modern_apic(void)
143 /* AMD systems use old APIC versions, so check the CPU */
144 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
145 boot_cpu_data
.x86
>= 0xf)
147 return lapic_get_version() >= 0x14;
151 * Paravirt kernels also might be using these below ops. So we still
152 * use generic apic_read()/apic_write(), which might be pointing to different
153 * ops in PARAVIRT case.
155 void xapic_wait_icr_idle(void)
157 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
161 u32
safe_xapic_wait_icr_idle(void)
168 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
172 } while (timeout
++ < 1000);
177 void xapic_icr_write(u32 low
, u32 id
)
179 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
180 apic_write(APIC_ICR
, low
);
183 u64
xapic_icr_read(void)
187 icr2
= apic_read(APIC_ICR2
);
188 icr1
= apic_read(APIC_ICR
);
190 return icr1
| ((u64
)icr2
<< 32);
193 static struct apic_ops xapic_ops
= {
194 .read
= native_apic_mem_read
,
195 .write
= native_apic_mem_write
,
196 .icr_read
= xapic_icr_read
,
197 .icr_write
= xapic_icr_write
,
198 .wait_icr_idle
= xapic_wait_icr_idle
,
199 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
202 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
203 EXPORT_SYMBOL_GPL(apic_ops
);
206 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
208 void __cpuinit
enable_NMI_through_LVT0(void)
212 /* unmask and set to NMI */
215 /* Level triggered for 82489DX (32bit mode) */
216 if (!lapic_is_integrated())
217 v
|= APIC_LVT_LEVEL_TRIGGER
;
219 apic_write(APIC_LVT0
, v
);
223 * get_physical_broadcast - Get number of physical broadcast IDs
225 int get_physical_broadcast(void)
227 return modern_apic() ? 0xff : 0xf;
231 * lapic_get_maxlvt - get the maximum number of local vector table entries
233 int lapic_get_maxlvt(void)
237 v
= apic_read(APIC_LVR
);
239 * - we always have APIC integrated on 64bit mode
240 * - 82489DXs do not report # of LVT entries
242 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
251 #define APIC_DIVISOR 1
253 #define APIC_DIVISOR 16
257 * This function sets up the local APIC timer, with a timeout of
258 * 'clocks' APIC bus clock. During calibration we actually call
259 * this function twice on the boot CPU, once with a bogus timeout
260 * value, second time for real. The other (noncalibrating) CPUs
261 * call this function only once, with the real, calibrated value.
263 * We do reads before writes even if unnecessary, to get around the
264 * P5 APIC double write bug.
266 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
268 unsigned int lvtt_value
, tmp_value
;
270 lvtt_value
= LOCAL_TIMER_VECTOR
;
272 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
273 if (!lapic_is_integrated())
274 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
277 lvtt_value
|= APIC_LVT_MASKED
;
279 apic_write(APIC_LVTT
, lvtt_value
);
284 tmp_value
= apic_read(APIC_TDCR
);
285 apic_write(APIC_TDCR
,
286 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
290 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
294 * Setup extended LVT, AMD specific (K8, family 10h)
296 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
297 * MCE interrupts are supported. Thus MCE offset must be set to 0.
299 * If mask=1, the LVT entry does not generate interrupts while mask=0
300 * enables the vector. See also the BKDGs.
303 #define APIC_EILVT_LVTOFF_MCE 0
304 #define APIC_EILVT_LVTOFF_IBS 1
306 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
308 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
309 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
314 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
316 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
317 return APIC_EILVT_LVTOFF_MCE
;
320 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
322 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
323 return APIC_EILVT_LVTOFF_IBS
;
325 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
328 * Program the next event, relative to now
330 static int lapic_next_event(unsigned long delta
,
331 struct clock_event_device
*evt
)
333 apic_write(APIC_TMICT
, delta
);
338 * Setup the lapic timer in periodic or oneshot mode
340 static void lapic_timer_setup(enum clock_event_mode mode
,
341 struct clock_event_device
*evt
)
346 /* Lapic used as dummy for broadcast ? */
347 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
350 local_irq_save(flags
);
353 case CLOCK_EVT_MODE_PERIODIC
:
354 case CLOCK_EVT_MODE_ONESHOT
:
355 __setup_APIC_LVTT(calibration_result
,
356 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
358 case CLOCK_EVT_MODE_UNUSED
:
359 case CLOCK_EVT_MODE_SHUTDOWN
:
360 v
= apic_read(APIC_LVTT
);
361 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
362 apic_write(APIC_LVTT
, v
);
364 case CLOCK_EVT_MODE_RESUME
:
365 /* Nothing to do here */
369 local_irq_restore(flags
);
373 * Local APIC timer broadcast function
375 static void lapic_timer_broadcast(cpumask_t mask
)
378 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
383 * Setup the local APIC timer for this CPU. Copy the initilized values
384 * of the boot CPU and register the clock event in the framework.
386 static void __devinit
setup_APIC_timer(void)
388 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
390 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
391 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
393 clockevents_register_device(levt
);
397 * In this functions we calibrate APIC bus clocks to the external timer.
399 * We want to do the calibration only once since we want to have local timer
400 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
403 * This was previously done by reading the PIT/HPET and waiting for a wrap
404 * around to find out, that a tick has elapsed. I have a box, where the PIT
405 * readout is broken, so it never gets out of the wait loop again. This was
406 * also reported by others.
408 * Monitoring the jiffies value is inaccurate and the clockevents
409 * infrastructure allows us to do a simple substitution of the interrupt
412 * The calibration routine also uses the pm_timer when possible, as the PIT
413 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
414 * back to normal later in the boot process).
417 #define LAPIC_CAL_LOOPS (HZ/10)
419 static __initdata
int lapic_cal_loops
= -1;
420 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
421 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
422 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
423 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
426 * Temporary interrupt handler.
428 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
430 unsigned long long tsc
= 0;
431 long tapic
= apic_read(APIC_TMCCT
);
432 unsigned long pm
= acpi_pm_read_early();
437 switch (lapic_cal_loops
++) {
439 lapic_cal_t1
= tapic
;
440 lapic_cal_tsc1
= tsc
;
442 lapic_cal_j1
= jiffies
;
445 case LAPIC_CAL_LOOPS
:
446 lapic_cal_t2
= tapic
;
447 lapic_cal_tsc2
= tsc
;
448 if (pm
< lapic_cal_pm1
)
449 pm
+= ACPI_PM_OVRRUN
;
451 lapic_cal_j2
= jiffies
;
456 static int __init
calibrate_APIC_clock(void)
458 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
459 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
460 const long pm_thresh
= pm_100ms
/100;
461 void (*real_handler
)(struct clock_event_device
*dev
);
462 unsigned long deltaj
;
464 int pm_referenced
= 0;
468 /* Replace the global interrupt handler */
469 real_handler
= global_clock_event
->event_handler
;
470 global_clock_event
->event_handler
= lapic_cal_handler
;
473 * Setup the APIC counter to 1e9. There is no way the lapic
474 * can underflow in the 100ms detection time frame
476 __setup_APIC_LVTT(1000000000, 0, 0);
478 /* Let the interrupts run */
481 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
486 /* Restore the real event handler */
487 global_clock_event
->event_handler
= real_handler
;
489 /* Build delta t1-t2 as apic timer counts down */
490 delta
= lapic_cal_t1
- lapic_cal_t2
;
491 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
493 /* Check, if the PM timer is available */
494 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
495 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
501 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
503 if (deltapm
> (pm_100ms
- pm_thresh
) &&
504 deltapm
< (pm_100ms
+ pm_thresh
)) {
505 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
507 res
= (((u64
) deltapm
) * mult
) >> 22;
508 do_div(res
, 1000000);
509 printk(KERN_WARNING
"APIC calibration not consistent "
510 "with PM Timer: %ldms instead of 100ms\n",
512 /* Correct the lapic counter value */
513 res
= (((u64
) delta
) * pm_100ms
);
514 do_div(res
, deltapm
);
515 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
516 "%lu (%ld)\n", (unsigned long) res
, delta
);
522 /* Calculate the scaled math multiplication factor */
523 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
524 lapic_clockevent
.shift
);
525 lapic_clockevent
.max_delta_ns
=
526 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
527 lapic_clockevent
.min_delta_ns
=
528 clockevent_delta2ns(0xF, &lapic_clockevent
);
530 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
532 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
533 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
534 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
538 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
539 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
541 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
542 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
545 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
547 calibration_result
/ (1000000 / HZ
),
548 calibration_result
% (1000000 / HZ
));
551 * Do a sanity check on the APIC calibration result
553 if (calibration_result
< (1000000 / HZ
)) {
556 "APIC frequency too slow, disabling apic timer\n");
560 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
562 /* We trust the pm timer based calibration */
563 if (!pm_referenced
) {
564 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
567 * Setup the apic timer manually
569 levt
->event_handler
= lapic_cal_handler
;
570 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
571 lapic_cal_loops
= -1;
573 /* Let the interrupts run */
576 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
581 /* Stop the lapic timer */
582 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
587 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
588 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
590 /* Check, if the jiffies result is consistent */
591 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
592 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
594 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
598 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
600 "APIC timer disabled due to verification failure.\n");
608 * Setup the boot APIC
610 * Calibrate and verify the result.
612 void __init
setup_boot_APIC_clock(void)
615 * The local apic timer can be disabled via the kernel
616 * commandline or from the CPU detection code. Register the lapic
617 * timer as a dummy clock event source on SMP systems, so the
618 * broadcast mechanism is used. On UP systems simply ignore it.
620 if (disable_apic_timer
) {
621 printk(KERN_INFO
"Disabling APIC timer\n");
622 /* No broadcast on UP ! */
623 if (num_possible_cpus() > 1) {
624 lapic_clockevent
.mult
= 1;
630 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
631 "calibrating APIC timer ...\n");
633 if (calibrate_APIC_clock()) {
634 /* No broadcast on UP ! */
635 if (num_possible_cpus() > 1)
641 * If nmi_watchdog is set to IO_APIC, we need the
642 * PIT/HPET going. Otherwise register lapic as a dummy
645 if (nmi_watchdog
!= NMI_IO_APIC
)
646 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
648 printk(KERN_WARNING
"APIC timer registered as dummy,"
649 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
651 /* Setup the lapic or request the broadcast */
655 void __devinit
setup_secondary_APIC_clock(void)
661 * The guts of the apic timer interrupt
663 static void local_apic_timer_interrupt(void)
665 int cpu
= smp_processor_id();
666 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
669 * Normally we should not be here till LAPIC has been initialized but
670 * in some cases like kdump, its possible that there is a pending LAPIC
671 * timer interrupt from previous kernel's context and is delivered in
672 * new kernel the moment interrupts are enabled.
674 * Interrupts are enabled early and LAPIC is setup much later, hence
675 * its possible that when we get here evt->event_handler is NULL.
676 * Check for event_handler being NULL and discard the interrupt as
679 if (!evt
->event_handler
) {
681 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
683 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
688 * the NMI deadlock-detector uses this.
691 add_pda(apic_timer_irqs
, 1);
693 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
696 evt
->event_handler(evt
);
700 * Local APIC timer interrupt. This is the most natural way for doing
701 * local interrupts, but local timer interrupts can be emulated by
702 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
704 * [ if a single-CPU system runs an SMP kernel then we call the local
705 * interrupt as well. Thus we cannot inline the local irq ... ]
707 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
709 struct pt_regs
*old_regs
= set_irq_regs(regs
);
712 * NOTE! We'd better ACK the irq immediately,
713 * because timer handling can be slow.
717 * update_process_times() expects us to have done irq_enter().
718 * Besides, if we don't timer interrupts ignore the global
719 * interrupt lock, which is the WrongThing (tm) to do.
722 local_apic_timer_interrupt();
725 set_irq_regs(old_regs
);
728 int setup_profiling_timer(unsigned int multiplier
)
734 * Local APIC start and shutdown
738 * clear_local_APIC - shutdown the local APIC
740 * This is called, when a CPU is disabled and before rebooting, so the state of
741 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
742 * leftovers during boot.
744 void clear_local_APIC(void)
749 /* APIC hasn't been mapped yet */
753 maxlvt
= lapic_get_maxlvt();
755 * Masking an LVT entry can trigger a local APIC error
756 * if the vector is zero. Mask LVTERR first to prevent this.
759 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
760 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
763 * Careful: we have to set masks only first to deassert
764 * any level-triggered sources.
766 v
= apic_read(APIC_LVTT
);
767 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
768 v
= apic_read(APIC_LVT0
);
769 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
770 v
= apic_read(APIC_LVT1
);
771 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
773 v
= apic_read(APIC_LVTPC
);
774 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
777 /* lets not touch this if we didn't frob it */
778 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
780 v
= apic_read(APIC_LVTTHMR
);
781 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
785 * Clean APIC state for other OSs:
787 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
788 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
789 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
791 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
793 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
795 /* Integrated APIC (!82489DX) ? */
796 if (lapic_is_integrated()) {
798 /* Clear ESR due to Pentium errata 3AP and 11AP */
799 apic_write(APIC_ESR
, 0);
805 * disable_local_APIC - clear and disable the local APIC
807 void disable_local_APIC(void)
814 * Disable APIC (implies clearing of registers
817 value
= apic_read(APIC_SPIV
);
818 value
&= ~APIC_SPIV_APIC_ENABLED
;
819 apic_write(APIC_SPIV
, value
);
823 * When LAPIC was disabled by the BIOS and enabled by the kernel,
824 * restore the disabled state.
826 if (enabled_via_apicbase
) {
829 rdmsr(MSR_IA32_APICBASE
, l
, h
);
830 l
&= ~MSR_IA32_APICBASE_ENABLE
;
831 wrmsr(MSR_IA32_APICBASE
, l
, h
);
837 * If Linux enabled the LAPIC against the BIOS default disable it down before
838 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
839 * not power-off. Additionally clear all LVT entries before disable_local_APIC
840 * for the case where Linux didn't enable the LAPIC.
842 void lapic_shutdown(void)
849 local_irq_save(flags
);
852 if (!enabled_via_apicbase
)
856 disable_local_APIC();
859 local_irq_restore(flags
);
863 * This is to verify that we're looking at a real local APIC.
864 * Check these against your board if the CPUs aren't getting
865 * started for no apparent reason.
867 int __init
verify_local_APIC(void)
869 unsigned int reg0
, reg1
;
872 * The version register is read-only in a real APIC.
874 reg0
= apic_read(APIC_LVR
);
875 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
876 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
877 reg1
= apic_read(APIC_LVR
);
878 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
881 * The two version reads above should print the same
882 * numbers. If the second one is different, then we
883 * poke at a non-APIC.
889 * Check if the version looks reasonably.
891 reg1
= GET_APIC_VERSION(reg0
);
892 if (reg1
== 0x00 || reg1
== 0xff)
894 reg1
= lapic_get_maxlvt();
895 if (reg1
< 0x02 || reg1
== 0xff)
899 * The ID register is read/write in a real APIC.
901 reg0
= apic_read(APIC_ID
);
902 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
903 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
904 reg1
= apic_read(APIC_ID
);
905 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
906 apic_write(APIC_ID
, reg0
);
907 if (reg1
!= (reg0
^ APIC_ID_MASK
))
911 * The next two are just to see if we have sane values.
912 * They're only really relevant if we're in Virtual Wire
913 * compatibility mode, but most boxes are anymore.
915 reg0
= apic_read(APIC_LVT0
);
916 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
917 reg1
= apic_read(APIC_LVT1
);
918 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
924 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
926 void __init
sync_Arb_IDs(void)
929 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
932 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
938 apic_wait_icr_idle();
940 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
941 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
942 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
946 * An initial setup of the virtual wire mode.
948 void __init
init_bsp_APIC(void)
953 * Don't do the setup now if we have a SMP BIOS as the
954 * through-I/O-APIC virtual wire mode might be active.
956 if (smp_found_config
|| !cpu_has_apic
)
960 * Do not trust the local APIC being empty at bootup.
967 value
= apic_read(APIC_SPIV
);
968 value
&= ~APIC_VECTOR_MASK
;
969 value
|= APIC_SPIV_APIC_ENABLED
;
972 /* This bit is reserved on P4/Xeon and should be cleared */
973 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
974 (boot_cpu_data
.x86
== 15))
975 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
978 value
|= APIC_SPIV_FOCUS_DISABLED
;
979 value
|= SPURIOUS_APIC_VECTOR
;
980 apic_write(APIC_SPIV
, value
);
983 * Set up the virtual wire mode.
985 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
987 if (!lapic_is_integrated()) /* 82489DX */
988 value
|= APIC_LVT_LEVEL_TRIGGER
;
989 apic_write(APIC_LVT1
, value
);
992 static void __cpuinit
lapic_setup_esr(void)
994 unsigned long oldvalue
, value
, maxlvt
;
995 if (lapic_is_integrated() && !esr_disable
) {
998 * Something untraceable is creating bad interrupts on
999 * secondary quads ... for the moment, just leave the
1000 * ESR disabled - we can't do anything useful with the
1001 * errors anyway - mbligh
1003 printk(KERN_INFO
"Leaving ESR disabled.\n");
1007 maxlvt
= lapic_get_maxlvt();
1008 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1009 apic_write(APIC_ESR
, 0);
1010 oldvalue
= apic_read(APIC_ESR
);
1012 /* enables sending errors */
1013 value
= ERROR_APIC_VECTOR
;
1014 apic_write(APIC_LVTERR
, value
);
1016 * spec says clear errors after enabling vector.
1019 apic_write(APIC_ESR
, 0);
1020 value
= apic_read(APIC_ESR
);
1021 if (value
!= oldvalue
)
1022 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1023 "vector: 0x%08lx after: 0x%08lx\n",
1026 printk(KERN_INFO
"No ESR for 82489DX.\n");
1032 * setup_local_APIC - setup the local APIC
1034 void __cpuinit
setup_local_APIC(void)
1039 #ifdef CONFIG_X86_32
1040 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1042 apic_write(APIC_ESR
, 0);
1043 apic_write(APIC_ESR
, 0);
1044 apic_write(APIC_ESR
, 0);
1045 apic_write(APIC_ESR
, 0);
1052 * Double-check whether this APIC is really registered.
1053 * This is meaningless in clustered apic mode, so we skip it.
1055 if (!apic_id_registered())
1059 * Intel recommends to set DFR, LDR and TPR before enabling
1060 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1061 * document number 292116). So here it goes...
1066 * Set Task Priority to 'accept all'. We never change this
1069 value
= apic_read(APIC_TASKPRI
);
1070 value
&= ~APIC_TPRI_MASK
;
1071 apic_write(APIC_TASKPRI
, value
);
1074 * After a crash, we no longer service the interrupts and a pending
1075 * interrupt from previous kernel might still have ISR bit set.
1077 * Most probably by now CPU has serviced that pending interrupt and
1078 * it might not have done the ack_APIC_irq() because it thought,
1079 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1080 * does not clear the ISR bit and cpu thinks it has already serivced
1081 * the interrupt. Hence a vector might get locked. It was noticed
1082 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1084 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1085 value
= apic_read(APIC_ISR
+ i
*0x10);
1086 for (j
= 31; j
>= 0; j
--) {
1093 * Now that we are all set up, enable the APIC
1095 value
= apic_read(APIC_SPIV
);
1096 value
&= ~APIC_VECTOR_MASK
;
1100 value
|= APIC_SPIV_APIC_ENABLED
;
1102 #ifdef CONFIG_X86_32
1104 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1105 * certain networking cards. If high frequency interrupts are
1106 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1107 * entry is masked/unmasked at a high rate as well then sooner or
1108 * later IOAPIC line gets 'stuck', no more interrupts are received
1109 * from the device. If focus CPU is disabled then the hang goes
1112 * [ This bug can be reproduced easily with a level-triggered
1113 * PCI Ne2000 networking cards and PII/PIII processors, dual
1117 * Actually disabling the focus CPU check just makes the hang less
1118 * frequent as it makes the interrupt distributon model be more
1119 * like LRU than MRU (the short-term load is more even across CPUs).
1120 * See also the comment in end_level_ioapic_irq(). --macro
1124 * - enable focus processor (bit==0)
1125 * - 64bit mode always use processor focus
1126 * so no need to set it
1128 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1132 * Set spurious IRQ vector
1134 value
|= SPURIOUS_APIC_VECTOR
;
1135 apic_write(APIC_SPIV
, value
);
1138 * Set up LVT0, LVT1:
1140 * set up through-local-APIC on the BP's LINT0. This is not
1141 * strictly necessary in pure symmetric-IO mode, but sometimes
1142 * we delegate interrupts to the 8259A.
1145 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1147 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1148 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1149 value
= APIC_DM_EXTINT
;
1150 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1151 smp_processor_id());
1153 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1154 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1155 smp_processor_id());
1157 apic_write(APIC_LVT0
, value
);
1160 * only the BP should see the LINT1 NMI signal, obviously.
1162 if (!smp_processor_id())
1163 value
= APIC_DM_NMI
;
1165 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1166 if (!lapic_is_integrated()) /* 82489DX */
1167 value
|= APIC_LVT_LEVEL_TRIGGER
;
1168 apic_write(APIC_LVT1
, value
);
1173 void __cpuinit
end_local_APIC_setup(void)
1177 #ifdef CONFIG_X86_32
1180 /* Disable the local apic timer */
1181 value
= apic_read(APIC_LVTT
);
1182 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1183 apic_write(APIC_LVTT
, value
);
1187 setup_apic_nmi_watchdog(NULL
);
1192 * Detect and initialize APIC
1194 static int __init
detect_init_APIC(void)
1198 /* Disabled by kernel option? */
1202 switch (boot_cpu_data
.x86_vendor
) {
1203 case X86_VENDOR_AMD
:
1204 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1205 (boot_cpu_data
.x86
== 15))
1208 case X86_VENDOR_INTEL
:
1209 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1210 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1217 if (!cpu_has_apic
) {
1219 * Over-ride BIOS and try to enable the local APIC only if
1220 * "lapic" specified.
1222 if (!force_enable_local_apic
) {
1223 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1224 "you can enable it with \"lapic\"\n");
1228 * Some BIOSes disable the local APIC in the APIC_BASE
1229 * MSR. This can only be done in software for Intel P6 or later
1230 * and AMD K7 (Model > 1) or later.
1232 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1233 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1235 "Local APIC disabled by BIOS -- reenabling.\n");
1236 l
&= ~MSR_IA32_APICBASE_BASE
;
1237 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1238 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1239 enabled_via_apicbase
= 1;
1243 * The APIC feature bit should now be enabled
1246 features
= cpuid_edx(1);
1247 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1248 printk(KERN_WARNING
"Could not enable APIC!\n");
1251 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1252 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1254 /* The BIOS may have set up the APIC at some other address */
1255 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1256 if (l
& MSR_IA32_APICBASE_ENABLE
)
1257 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1259 printk(KERN_INFO
"Found and enabled local APIC!\n");
1266 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1271 * init_apic_mappings - initialize APIC mappings
1273 void __init
init_apic_mappings(void)
1276 * If no local APIC can be found then set up a fake all
1277 * zeroes page to simulate the local APIC and another
1278 * one for the IO-APIC.
1280 if (!smp_found_config
&& detect_init_APIC()) {
1281 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1282 apic_phys
= __pa(apic_phys
);
1284 apic_phys
= mp_lapic_addr
;
1286 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1287 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1291 * Fetch the APIC ID of the BSP in case we have a
1292 * default configuration (or the MP table is broken).
1294 if (boot_cpu_physical_apicid
== -1U)
1295 boot_cpu_physical_apicid
= read_apic_id();
1300 * This initializes the IO-APIC and APIC hardware if this is
1304 int apic_version
[MAX_APICS
];
1306 int __init
APIC_init_uniprocessor(void)
1308 if (!smp_found_config
&& !cpu_has_apic
)
1312 * Complain if the BIOS pretends there is one.
1314 if (!cpu_has_apic
&&
1315 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1316 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1317 boot_cpu_physical_apicid
);
1318 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1322 verify_local_APIC();
1327 * Hack: In case of kdump, after a crash, kernel might be booting
1328 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1329 * might be zero if read from MP tables. Get it from LAPIC.
1331 #ifdef CONFIG_CRASH_DUMP
1332 boot_cpu_physical_apicid
= read_apic_id();
1334 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1338 #ifdef CONFIG_X86_IO_APIC
1339 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1341 localise_nmi_watchdog();
1342 end_local_APIC_setup();
1343 #ifdef CONFIG_X86_IO_APIC
1344 if (smp_found_config
)
1345 if (!skip_ioapic_setup
&& nr_ioapics
)
1354 * Local APIC interrupts
1358 * This interrupt should _never_ happen with our APIC/SMP architecture
1360 void smp_spurious_interrupt(struct pt_regs
*regs
)
1366 * Check if this really is a spurious interrupt and ACK it
1367 * if it is a vectored one. Just in case...
1368 * Spurious interrupts should not be ACKed.
1370 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1371 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1374 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1375 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1376 "should never happen.\n", smp_processor_id());
1377 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1382 * This interrupt should never happen with our APIC/SMP architecture
1384 void smp_error_interrupt(struct pt_regs
*regs
)
1386 unsigned long v
, v1
;
1389 /* First tickle the hardware, only then report what went on. -- REW */
1390 v
= apic_read(APIC_ESR
);
1391 apic_write(APIC_ESR
, 0);
1392 v1
= apic_read(APIC_ESR
);
1394 atomic_inc(&irq_err_count
);
1396 /* Here is what the APIC error bits mean:
1399 2: Send accept error
1400 3: Receive accept error
1402 5: Send illegal vector
1403 6: Received illegal vector
1404 7: Illegal register address
1406 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1407 smp_processor_id(), v
, v1
);
1412 * connect_bsp_APIC - attach the APIC to the interrupt system
1414 void __init
connect_bsp_APIC(void)
1416 #ifdef CONFIG_X86_32
1419 * Do not trust the local APIC being empty at bootup.
1423 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1424 * local APIC to INT and NMI lines.
1426 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1427 "enabling APIC mode.\n");
1436 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1437 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1439 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1442 void disconnect_bsp_APIC(int virt_wire_setup
)
1446 #ifdef CONFIG_X86_32
1449 * Put the board back into PIC mode (has an effect only on
1450 * certain older boards). Note that APIC interrupts, including
1451 * IPIs, won't work beyond this point! The only exception are
1454 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1455 "entering PIC mode.\n");
1462 /* Go back to Virtual Wire compatibility mode */
1464 /* For the spurious interrupt use vector F, and enable it */
1465 value
= apic_read(APIC_SPIV
);
1466 value
&= ~APIC_VECTOR_MASK
;
1467 value
|= APIC_SPIV_APIC_ENABLED
;
1469 apic_write(APIC_SPIV
, value
);
1471 if (!virt_wire_setup
) {
1473 * For LVT0 make it edge triggered, active high,
1474 * external and enabled
1476 value
= apic_read(APIC_LVT0
);
1477 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1478 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1479 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1480 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1481 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1482 apic_write(APIC_LVT0
, value
);
1485 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1489 * For LVT1 make it edge triggered, active high,
1492 value
= apic_read(APIC_LVT1
);
1493 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1494 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1495 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1496 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1497 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1498 apic_write(APIC_LVT1
, value
);
1501 void __cpuinit
generic_processor_info(int apicid
, int version
)
1509 if (version
== 0x0) {
1510 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1511 "fixing up to 0x10. (tell your hw vendor)\n",
1515 apic_version
[apicid
] = version
;
1517 if (num_processors
>= NR_CPUS
) {
1518 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1519 " Processor ignored.\n", NR_CPUS
);
1524 cpus_complement(tmp_map
, cpu_present_map
);
1525 cpu
= first_cpu(tmp_map
);
1527 physid_set(apicid
, phys_cpu_present_map
);
1528 if (apicid
== boot_cpu_physical_apicid
) {
1530 * x86_bios_cpu_apicid is required to have processors listed
1531 * in same order as logical cpu numbers. Hence the first
1532 * entry is BSP, and so on.
1536 if (apicid
> max_physical_apicid
)
1537 max_physical_apicid
= apicid
;
1539 #ifdef CONFIG_X86_32
1541 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1542 * but we need to work other dependencies like SMP_SUSPEND etc
1543 * before this can be done without some confusion.
1544 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1545 * - Ashok Raj <ashok.raj@intel.com>
1547 if (max_physical_apicid
>= 8) {
1548 switch (boot_cpu_data
.x86_vendor
) {
1549 case X86_VENDOR_INTEL
:
1550 if (!APIC_XAPIC(version
)) {
1554 /* If P4 and above fall through */
1555 case X86_VENDOR_AMD
:
1561 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1562 /* are we being called early in kernel startup? */
1563 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1564 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1565 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1567 cpu_to_apicid
[cpu
] = apicid
;
1568 bios_cpu_apicid
[cpu
] = apicid
;
1570 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1571 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1575 cpu_set(cpu
, cpu_possible_map
);
1576 cpu_set(cpu
, cpu_present_map
);
1586 * 'active' is true if the local APIC was enabled by us and
1587 * not the BIOS; this signifies that we are also responsible
1588 * for disabling it before entering apm/acpi suspend
1591 /* r/w apic fields */
1592 unsigned int apic_id
;
1593 unsigned int apic_taskpri
;
1594 unsigned int apic_ldr
;
1595 unsigned int apic_dfr
;
1596 unsigned int apic_spiv
;
1597 unsigned int apic_lvtt
;
1598 unsigned int apic_lvtpc
;
1599 unsigned int apic_lvt0
;
1600 unsigned int apic_lvt1
;
1601 unsigned int apic_lvterr
;
1602 unsigned int apic_tmict
;
1603 unsigned int apic_tdcr
;
1604 unsigned int apic_thmr
;
1607 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1609 unsigned long flags
;
1612 if (!apic_pm_state
.active
)
1615 maxlvt
= lapic_get_maxlvt();
1617 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1618 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1619 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1620 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1621 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1622 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1624 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1625 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1626 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1627 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1628 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1629 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1630 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1632 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1635 local_irq_save(flags
);
1636 disable_local_APIC();
1637 local_irq_restore(flags
);
1641 static int lapic_resume(struct sys_device
*dev
)
1644 unsigned long flags
;
1647 if (!apic_pm_state
.active
)
1650 maxlvt
= lapic_get_maxlvt();
1652 local_irq_save(flags
);
1654 #ifdef CONFIG_X86_64
1661 * Make sure the APICBASE points to the right address
1663 * FIXME! This will be wrong if we ever support suspend on
1664 * SMP! We'll need to do this as part of the CPU restore!
1666 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1667 l
&= ~MSR_IA32_APICBASE_BASE
;
1668 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1669 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1672 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1673 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1674 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1675 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1676 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1677 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1678 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1679 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1680 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1682 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1685 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1686 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1687 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1688 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1689 apic_write(APIC_ESR
, 0);
1690 apic_read(APIC_ESR
);
1691 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1692 apic_write(APIC_ESR
, 0);
1693 apic_read(APIC_ESR
);
1695 local_irq_restore(flags
);
1701 * This device has no shutdown method - fully functioning local APICs
1702 * are needed on every CPU up until machine_halt/restart/poweroff.
1705 static struct sysdev_class lapic_sysclass
= {
1707 .resume
= lapic_resume
,
1708 .suspend
= lapic_suspend
,
1711 static struct sys_device device_lapic
= {
1713 .cls
= &lapic_sysclass
,
1716 static void __devinit
apic_pm_activate(void)
1718 apic_pm_state
.active
= 1;
1721 static int __init
init_lapic_sysfs(void)
1727 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1729 error
= sysdev_class_register(&lapic_sysclass
);
1731 error
= sysdev_register(&device_lapic
);
1734 device_initcall(init_lapic_sysfs
);
1736 #else /* CONFIG_PM */
1738 static void apic_pm_activate(void) { }
1740 #endif /* CONFIG_PM */
1743 * APIC command line parameters
1745 static int __init
parse_lapic(char *arg
)
1747 force_enable_local_apic
= 1;
1750 early_param("lapic", parse_lapic
);
1752 static int __init
setup_disableapic(char *arg
)
1755 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1758 early_param("disableapic", setup_disableapic
);
1760 /* same as disableapic, for compatibility */
1761 static int __init
setup_nolapic(char *arg
)
1763 return setup_disableapic(arg
);
1765 early_param("nolapic", setup_nolapic
);
1767 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1769 local_apic_timer_c2_ok
= 1;
1772 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1774 static int __init
parse_disable_apic_timer(char *arg
)
1776 disable_apic_timer
= 1;
1779 early_param("noapictimer", parse_disable_apic_timer
);
1781 static int __init
parse_nolapic_timer(char *arg
)
1783 disable_apic_timer
= 1;
1786 early_param("nolapic_timer", parse_nolapic_timer
);
1788 #ifdef CONFIG_X86_64
1789 static __init
int setup_apicpmtimer(char *s
)
1791 apic_calibrate_pmtmr
= 1;
1795 __setup("apicpmtimer", setup_apicpmtimer
);
1798 static int __init
apic_set_verbosity(char *arg
)
1801 #ifdef CONFIG_X86_64
1802 skip_ioapic_setup
= 0;
1809 if (strcmp("debug", arg
) == 0)
1810 apic_verbosity
= APIC_DEBUG
;
1811 else if (strcmp("verbose", arg
) == 0)
1812 apic_verbosity
= APIC_VERBOSE
;
1814 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1815 " use apic=verbose or apic=debug\n", arg
);
1821 early_param("apic", apic_set_verbosity
);
1823 static int __init
lapic_insert_resource(void)
1828 /* Put local APIC into the resource map. */
1829 lapic_resource
.start
= apic_phys
;
1830 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1831 insert_resource(&iomem_resource
, &lapic_resource
);
1837 * need call insert after e820_reserve_resources()
1838 * that is using request_resource
1840 late_initcall(lapic_insert_resource
);