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usb: musb: core: set has_tt flag
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / musb / musb_core.c
blob826485bed55a0c36840fddbb504d77ced71f56a4
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
116
117
118 unsigned musb_debug;
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124
125 #define MUSB_VERSION "6.0"
126
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136
137
138 /*-------------------------------------------------------------------------*/
139
140 static inline struct musb *dev_to_musb(struct device *dev)
141 {
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
145 #else
146 return dev_get_drvdata(dev);
147 #endif
148 }
149
150 /*-------------------------------------------------------------------------*/
151
152 #ifndef CONFIG_BLACKFIN
153 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
154 {
155 void __iomem *addr = otg->io_priv;
156 int i = 0;
157 u8 r;
158 u8 power;
159
160 /* Make sure the transceiver is not in low power mode */
161 power = musb_readb(addr, MUSB_POWER);
162 power &= ~MUSB_POWER_SUSPENDM;
163 musb_writeb(addr, MUSB_POWER, power);
164
165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
167 */
168
169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
172
173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
174 & MUSB_ULPI_REG_CMPLT)) {
175 i++;
176 if (i == 10000) {
177 DBG(3, "ULPI read timed out\n");
178 return -ETIMEDOUT;
179 }
180
181 }
182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
183 r &= ~MUSB_ULPI_REG_CMPLT;
184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
185
186 return musb_readb(addr, MUSB_ULPI_REG_DATA);
187 }
188
189 static int musb_ulpi_write(struct otg_transceiver *otg,
190 u32 offset, u32 data)
191 {
192 void __iomem *addr = otg->io_priv;
193 int i = 0;
194 u8 r = 0;
195 u8 power;
196
197 /* Make sure the transceiver is not in low power mode */
198 power = musb_readb(addr, MUSB_POWER);
199 power &= ~MUSB_POWER_SUSPENDM;
200 musb_writeb(addr, MUSB_POWER, power);
201
202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
205
206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
207 & MUSB_ULPI_REG_CMPLT)) {
208 i++;
209 if (i == 10000) {
210 DBG(3, "ULPI write timed out\n");
211 return -ETIMEDOUT;
212 }
213 }
214
215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
216 r &= ~MUSB_ULPI_REG_CMPLT;
217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
218
219 return 0;
220 }
221 #else
222 #define musb_ulpi_read NULL
223 #define musb_ulpi_write NULL
224 #endif
225
226 static struct otg_io_access_ops musb_ulpi_access = {
227 .read = musb_ulpi_read,
228 .write = musb_ulpi_write,
229 };
230
231 /*-------------------------------------------------------------------------*/
232
233 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
234
235 /*
236 * Load an endpoint's FIFO
237 */
238 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
239 {
240 void __iomem *fifo = hw_ep->fifo;
241
242 prefetch((u8 *)src);
243
244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
246
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
254 writesl(fifo, src + index, len >> 2);
255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
263 writesw(fifo, src + index, len >> 1);
264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270 /* byte aligned */
271 writesb(fifo, src, len);
272 }
273 }
274
275 #if !defined(CONFIG_USB_MUSB_AM35X)
276 /*
277 * Unload an endpoint's FIFO
278 */
279 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
280 {
281 void __iomem *fifo = hw_ep->fifo;
282
283 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
284 'R', hw_ep->epnum, fifo, len, dst);
285
286 /* we can't assume unaligned writes work */
287 if (likely((0x01 & (unsigned long) dst) == 0)) {
288 u16 index = 0;
289
290 /* best case is 32bit-aligned destination address */
291 if ((0x02 & (unsigned long) dst) == 0) {
292 if (len >= 4) {
293 readsl(fifo, dst, len >> 2);
294 index = len & ~0x03;
295 }
296 if (len & 0x02) {
297 *(u16 *)&dst[index] = musb_readw(fifo, 0);
298 index += 2;
299 }
300 } else {
301 if (len >= 2) {
302 readsw(fifo, dst, len >> 1);
303 index = len & ~0x01;
304 }
305 }
306 if (len & 0x01)
307 dst[index] = musb_readb(fifo, 0);
308 } else {
309 /* byte aligned */
310 readsb(fifo, dst, len);
311 }
312 }
313 #endif
314
315 #endif /* normal PIO */
316
317
318 /*-------------------------------------------------------------------------*/
319
320 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
321 static const u8 musb_test_packet[53] = {
322 /* implicit SYNC then DATA0 to start */
323
324 /* JKJKJKJK x9 */
325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
326 /* JJKKJJKK x8 */
327 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
328 /* JJJJKKKK x8 */
329 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
330 /* JJJJJJJKKKKKKK x8 */
331 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
332 /* JJJJJJJK x8 */
333 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
334 /* JKKKKKKK x10, JK */
335 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
336
337 /* implicit CRC16 then EOP to end */
338 };
339
340 void musb_load_testpacket(struct musb *musb)
341 {
342 void __iomem *regs = musb->endpoints[0].regs;
343
344 musb_ep_select(musb->mregs, 0);
345 musb_write_fifo(musb->control_ep,
346 sizeof(musb_test_packet), musb_test_packet);
347 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
348 }
349
350 /*-------------------------------------------------------------------------*/
351
352 const char *otg_state_string(struct musb *musb)
353 {
354 switch (musb->xceiv->state) {
355 case OTG_STATE_A_IDLE: return "a_idle";
356 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
357 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
358 case OTG_STATE_A_HOST: return "a_host";
359 case OTG_STATE_A_SUSPEND: return "a_suspend";
360 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
361 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
362 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
363 case OTG_STATE_B_IDLE: return "b_idle";
364 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
365 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
366 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
367 case OTG_STATE_B_HOST: return "b_host";
368 default: return "UNDEFINED";
369 }
370 }
371
372 #ifdef CONFIG_USB_MUSB_OTG
373
374 /*
375 * Handles OTG hnp timeouts, such as b_ase0_brst
376 */
377 void musb_otg_timer_func(unsigned long data)
378 {
379 struct musb *musb = (struct musb *)data;
380 unsigned long flags;
381
382 spin_lock_irqsave(&musb->lock, flags);
383 switch (musb->xceiv->state) {
384 case OTG_STATE_B_WAIT_ACON:
385 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
386 musb_g_disconnect(musb);
387 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
388 musb->is_active = 0;
389 break;
390 case OTG_STATE_A_SUSPEND:
391 case OTG_STATE_A_WAIT_BCON:
392 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
393 musb_set_vbus(musb, 0);
394 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
395 break;
396 default:
397 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
398 }
399 musb->ignore_disconnect = 0;
400 spin_unlock_irqrestore(&musb->lock, flags);
401 }
402
403 /*
404 * Stops the HNP transition. Caller must take care of locking.
405 */
406 void musb_hnp_stop(struct musb *musb)
407 {
408 struct usb_hcd *hcd = musb_to_hcd(musb);
409 void __iomem *mbase = musb->mregs;
410 u8 reg;
411
412 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
413
414 switch (musb->xceiv->state) {
415 case OTG_STATE_A_PERIPHERAL:
416 musb_g_disconnect(musb);
417 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
418 break;
419 case OTG_STATE_B_HOST:
420 DBG(1, "HNP: Disabling HR\n");
421 hcd->self.is_b_host = 0;
422 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
423 MUSB_DEV_MODE(musb);
424 reg = musb_readb(mbase, MUSB_POWER);
425 reg |= MUSB_POWER_SUSPENDM;
426 musb_writeb(mbase, MUSB_POWER, reg);
427 /* REVISIT: Start SESSION_REQUEST here? */
428 break;
429 default:
430 DBG(1, "HNP: Stopping in unknown state %s\n",
431 otg_state_string(musb));
432 }
433
434 /*
435 * When returning to A state after HNP, avoid hub_port_rebounce(),
436 * which cause occasional OPT A "Did not receive reset after connect"
437 * errors.
438 */
439 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
440 }
441
442 #endif
443
444 /*
445 * Interrupt Service Routine to record USB "global" interrupts.
446 * Since these do not happen often and signify things of
447 * paramount importance, it seems OK to check them individually;
448 * the order of the tests is specified in the manual
449 *
450 * @param musb instance pointer
451 * @param int_usb register contents
452 * @param devctl
453 * @param power
454 */
455
456 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
457 u8 devctl, u8 power)
458 {
459 irqreturn_t handled = IRQ_NONE;
460
461 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
462 int_usb);
463
464 /* in host mode, the peripheral may issue remote wakeup.
465 * in peripheral mode, the host may resume the link.
466 * spurious RESUME irqs happen too, paired with SUSPEND.
467 */
468 if (int_usb & MUSB_INTR_RESUME) {
469 handled = IRQ_HANDLED;
470 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
471
472 if (devctl & MUSB_DEVCTL_HM) {
473 #ifdef CONFIG_USB_MUSB_HDRC_HCD
474 void __iomem *mbase = musb->mregs;
475
476 switch (musb->xceiv->state) {
477 case OTG_STATE_A_SUSPEND:
478 /* remote wakeup? later, GetPortStatus
479 * will stop RESUME signaling
480 */
481
482 if (power & MUSB_POWER_SUSPENDM) {
483 /* spurious */
484 musb->int_usb &= ~MUSB_INTR_SUSPEND;
485 DBG(2, "Spurious SUSPENDM\n");
486 break;
487 }
488
489 power &= ~MUSB_POWER_SUSPENDM;
490 musb_writeb(mbase, MUSB_POWER,
491 power | MUSB_POWER_RESUME);
492
493 musb->port1_status |=
494 (USB_PORT_STAT_C_SUSPEND << 16)
495 | MUSB_PORT_STAT_RESUME;
496 musb->rh_timer = jiffies
497 + msecs_to_jiffies(20);
498
499 musb->xceiv->state = OTG_STATE_A_HOST;
500 musb->is_active = 1;
501 usb_hcd_resume_root_hub(musb_to_hcd(musb));
502 break;
503 case OTG_STATE_B_WAIT_ACON:
504 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
505 musb->is_active = 1;
506 MUSB_DEV_MODE(musb);
507 break;
508 default:
509 WARNING("bogus %s RESUME (%s)\n",
510 "host",
511 otg_state_string(musb));
512 }
513 #endif
514 } else {
515 switch (musb->xceiv->state) {
516 #ifdef CONFIG_USB_MUSB_HDRC_HCD
517 case OTG_STATE_A_SUSPEND:
518 /* possibly DISCONNECT is upcoming */
519 musb->xceiv->state = OTG_STATE_A_HOST;
520 usb_hcd_resume_root_hub(musb_to_hcd(musb));
521 break;
522 #endif
523 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
524 case OTG_STATE_B_WAIT_ACON:
525 case OTG_STATE_B_PERIPHERAL:
526 /* disconnect while suspended? we may
527 * not get a disconnect irq...
528 */
529 if ((devctl & MUSB_DEVCTL_VBUS)
530 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
531 ) {
532 musb->int_usb |= MUSB_INTR_DISCONNECT;
533 musb->int_usb &= ~MUSB_INTR_SUSPEND;
534 break;
535 }
536 musb_g_resume(musb);
537 break;
538 case OTG_STATE_B_IDLE:
539 musb->int_usb &= ~MUSB_INTR_SUSPEND;
540 break;
541 #endif
542 default:
543 WARNING("bogus %s RESUME (%s)\n",
544 "peripheral",
545 otg_state_string(musb));
546 }
547 }
548 }
549
550 #ifdef CONFIG_USB_MUSB_HDRC_HCD
551 /* see manual for the order of the tests */
552 if (int_usb & MUSB_INTR_SESSREQ) {
553 void __iomem *mbase = musb->mregs;
554
555 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
556 && (devctl & MUSB_DEVCTL_BDEVICE)) {
557 DBG(3, "SessReq while on B state\n");
558 return IRQ_HANDLED;
559 }
560
561 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
562
563 /* IRQ arrives from ID pin sense or (later, if VBUS power
564 * is removed) SRP. responses are time critical:
565 * - turn on VBUS (with silicon-specific mechanism)
566 * - go through A_WAIT_VRISE
567 * - ... to A_WAIT_BCON.
568 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
569 */
570 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
571 musb->ep0_stage = MUSB_EP0_START;
572 musb->xceiv->state = OTG_STATE_A_IDLE;
573 MUSB_HST_MODE(musb);
574 musb_set_vbus(musb, 1);
575
576 handled = IRQ_HANDLED;
577 }
578
579 if (int_usb & MUSB_INTR_VBUSERROR) {
580 int ignore = 0;
581
582 /* During connection as an A-Device, we may see a short
583 * current spikes causing voltage drop, because of cable
584 * and peripheral capacitance combined with vbus draw.
585 * (So: less common with truly self-powered devices, where
586 * vbus doesn't act like a power supply.)
587 *
588 * Such spikes are short; usually less than ~500 usec, max
589 * of ~2 msec. That is, they're not sustained overcurrent
590 * errors, though they're reported using VBUSERROR irqs.
591 *
592 * Workarounds: (a) hardware: use self powered devices.
593 * (b) software: ignore non-repeated VBUS errors.
594 *
595 * REVISIT: do delays from lots of DEBUG_KERNEL checks
596 * make trouble here, keeping VBUS < 4.4V ?
597 */
598 switch (musb->xceiv->state) {
599 case OTG_STATE_A_HOST:
600 /* recovery is dicey once we've gotten past the
601 * initial stages of enumeration, but if VBUS
602 * stayed ok at the other end of the link, and
603 * another reset is due (at least for high speed,
604 * to redo the chirp etc), it might work OK...
605 */
606 case OTG_STATE_A_WAIT_BCON:
607 case OTG_STATE_A_WAIT_VRISE:
608 if (musb->vbuserr_retry) {
609 void __iomem *mbase = musb->mregs;
610
611 musb->vbuserr_retry--;
612 ignore = 1;
613 devctl |= MUSB_DEVCTL_SESSION;
614 musb_writeb(mbase, MUSB_DEVCTL, devctl);
615 } else {
616 musb->port1_status |=
617 USB_PORT_STAT_OVERCURRENT
618 | (USB_PORT_STAT_C_OVERCURRENT << 16);
619 }
620 break;
621 default:
622 break;
623 }
624
625 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
626 otg_state_string(musb),
627 devctl,
628 ({ char *s;
629 switch (devctl & MUSB_DEVCTL_VBUS) {
630 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
631 s = "<SessEnd"; break;
632 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
633 s = "<AValid"; break;
634 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
635 s = "<VBusValid"; break;
636 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
637 default:
638 s = "VALID"; break;
639 }; s; }),
640 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
641 musb->port1_status);
642
643 /* go through A_WAIT_VFALL then start a new session */
644 if (!ignore)
645 musb_set_vbus(musb, 0);
646 handled = IRQ_HANDLED;
647 }
648
649 #endif
650 if (int_usb & MUSB_INTR_SUSPEND) {
651 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
652 otg_state_string(musb), devctl, power);
653 handled = IRQ_HANDLED;
654
655 switch (musb->xceiv->state) {
656 #ifdef CONFIG_USB_MUSB_OTG
657 case OTG_STATE_A_PERIPHERAL:
658 /* We also come here if the cable is removed, since
659 * this silicon doesn't report ID-no-longer-grounded.
660 *
661 * We depend on T(a_wait_bcon) to shut us down, and
662 * hope users don't do anything dicey during this
663 * undesired detour through A_WAIT_BCON.
664 */
665 musb_hnp_stop(musb);
666 usb_hcd_resume_root_hub(musb_to_hcd(musb));
667 musb_root_disconnect(musb);
668 musb_platform_try_idle(musb, jiffies
669 + msecs_to_jiffies(musb->a_wait_bcon
670 ? : OTG_TIME_A_WAIT_BCON));
671
672 break;
673 #endif
674 case OTG_STATE_B_IDLE:
675 if (!musb->is_active)
676 break;
677 case OTG_STATE_B_PERIPHERAL:
678 musb_g_suspend(musb);
679 musb->is_active = is_otg_enabled(musb)
680 && musb->xceiv->gadget->b_hnp_enable;
681 if (musb->is_active) {
682 #ifdef CONFIG_USB_MUSB_OTG
683 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
684 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
685 mod_timer(&musb->otg_timer, jiffies
686 + msecs_to_jiffies(
687 OTG_TIME_B_ASE0_BRST));
688 #endif
689 }
690 break;
691 case OTG_STATE_A_WAIT_BCON:
692 if (musb->a_wait_bcon != 0)
693 musb_platform_try_idle(musb, jiffies
694 + msecs_to_jiffies(musb->a_wait_bcon));
695 break;
696 case OTG_STATE_A_HOST:
697 musb->xceiv->state = OTG_STATE_A_SUSPEND;
698 musb->is_active = is_otg_enabled(musb)
699 && musb->xceiv->host->b_hnp_enable;
700 break;
701 case OTG_STATE_B_HOST:
702 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
703 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
704 break;
705 default:
706 /* "should not happen" */
707 musb->is_active = 0;
708 break;
709 }
710 }
711
712 #ifdef CONFIG_USB_MUSB_HDRC_HCD
713 if (int_usb & MUSB_INTR_CONNECT) {
714 struct usb_hcd *hcd = musb_to_hcd(musb);
715
716 handled = IRQ_HANDLED;
717 musb->is_active = 1;
718 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
719
720 musb->ep0_stage = MUSB_EP0_START;
721
722 #ifdef CONFIG_USB_MUSB_OTG
723 /* flush endpoints when transitioning from Device Mode */
724 if (is_peripheral_active(musb)) {
725 /* REVISIT HNP; just force disconnect */
726 }
727 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
728 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
729 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
730 #endif
731 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
732 |USB_PORT_STAT_HIGH_SPEED
733 |USB_PORT_STAT_ENABLE
734 );
735 musb->port1_status |= USB_PORT_STAT_CONNECTION
736 |(USB_PORT_STAT_C_CONNECTION << 16);
737
738 /* high vs full speed is just a guess until after reset */
739 if (devctl & MUSB_DEVCTL_LSDEV)
740 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
741
742 /* indicate new connection to OTG machine */
743 switch (musb->xceiv->state) {
744 case OTG_STATE_B_PERIPHERAL:
745 if (int_usb & MUSB_INTR_SUSPEND) {
746 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
747 int_usb &= ~MUSB_INTR_SUSPEND;
748 goto b_host;
749 } else
750 DBG(1, "CONNECT as b_peripheral???\n");
751 break;
752 case OTG_STATE_B_WAIT_ACON:
753 DBG(1, "HNP: CONNECT, now b_host\n");
754 b_host:
755 musb->xceiv->state = OTG_STATE_B_HOST;
756 hcd->self.is_b_host = 1;
757 musb->ignore_disconnect = 0;
758 del_timer(&musb->otg_timer);
759 break;
760 default:
761 if ((devctl & MUSB_DEVCTL_VBUS)
762 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
763 musb->xceiv->state = OTG_STATE_A_HOST;
764 hcd->self.is_b_host = 0;
765 }
766 break;
767 }
768
769 /* poke the root hub */
770 MUSB_HST_MODE(musb);
771 if (hcd->status_urb)
772 usb_hcd_poll_rh_status(hcd);
773 else
774 usb_hcd_resume_root_hub(hcd);
775
776 DBG(1, "CONNECT (%s) devctl %02x\n",
777 otg_state_string(musb), devctl);
778 }
779 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
780
781 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
782 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
783 otg_state_string(musb),
784 MUSB_MODE(musb), devctl);
785 handled = IRQ_HANDLED;
786
787 switch (musb->xceiv->state) {
788 #ifdef CONFIG_USB_MUSB_HDRC_HCD
789 case OTG_STATE_A_HOST:
790 case OTG_STATE_A_SUSPEND:
791 usb_hcd_resume_root_hub(musb_to_hcd(musb));
792 musb_root_disconnect(musb);
793 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
794 musb_platform_try_idle(musb, jiffies
795 + msecs_to_jiffies(musb->a_wait_bcon));
796 break;
797 #endif /* HOST */
798 #ifdef CONFIG_USB_MUSB_OTG
799 case OTG_STATE_B_HOST:
800 /* REVISIT this behaves for "real disconnect"
801 * cases; make sure the other transitions from
802 * from B_HOST act right too. The B_HOST code
803 * in hnp_stop() is currently not used...
804 */
805 musb_root_disconnect(musb);
806 musb_to_hcd(musb)->self.is_b_host = 0;
807 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
808 MUSB_DEV_MODE(musb);
809 musb_g_disconnect(musb);
810 break;
811 case OTG_STATE_A_PERIPHERAL:
812 musb_hnp_stop(musb);
813 musb_root_disconnect(musb);
814 /* FALLTHROUGH */
815 case OTG_STATE_B_WAIT_ACON:
816 /* FALLTHROUGH */
817 #endif /* OTG */
818 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
819 case OTG_STATE_B_PERIPHERAL:
820 case OTG_STATE_B_IDLE:
821 musb_g_disconnect(musb);
822 break;
823 #endif /* GADGET */
824 default:
825 WARNING("unhandled DISCONNECT transition (%s)\n",
826 otg_state_string(musb));
827 break;
828 }
829 }
830
831 /* mentor saves a bit: bus reset and babble share the same irq.
832 * only host sees babble; only peripheral sees bus reset.
833 */
834 if (int_usb & MUSB_INTR_RESET) {
835 handled = IRQ_HANDLED;
836 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
837 /*
838 * Looks like non-HS BABBLE can be ignored, but
839 * HS BABBLE is an error condition. For HS the solution
840 * is to avoid babble in the first place and fix what
841 * caused BABBLE. When HS BABBLE happens we can only
842 * stop the session.
843 */
844 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
845 DBG(1, "BABBLE devctl: %02x\n", devctl);
846 else {
847 ERR("Stopping host session -- babble\n");
848 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
849 }
850 } else if (is_peripheral_capable()) {
851 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
852 switch (musb->xceiv->state) {
853 #ifdef CONFIG_USB_OTG
854 case OTG_STATE_A_SUSPEND:
855 /* We need to ignore disconnect on suspend
856 * otherwise tusb 2.0 won't reconnect after a
857 * power cycle, which breaks otg compliance.
858 */
859 musb->ignore_disconnect = 1;
860 musb_g_reset(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
863 /* never use invalid T(a_wait_bcon) */
864 DBG(1, "HNP: in %s, %d msec timeout\n",
865 otg_state_string(musb),
866 TA_WAIT_BCON(musb));
867 mod_timer(&musb->otg_timer, jiffies
868 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
869 break;
870 case OTG_STATE_A_PERIPHERAL:
871 musb->ignore_disconnect = 0;
872 del_timer(&musb->otg_timer);
873 musb_g_reset(musb);
874 break;
875 case OTG_STATE_B_WAIT_ACON:
876 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
877 otg_state_string(musb));
878 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
879 musb_g_reset(musb);
880 break;
881 #endif
882 case OTG_STATE_B_IDLE:
883 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
884 /* FALLTHROUGH */
885 case OTG_STATE_B_PERIPHERAL:
886 musb_g_reset(musb);
887 break;
888 default:
889 DBG(1, "Unhandled BUS RESET as %s\n",
890 otg_state_string(musb));
891 }
892 }
893 }
894
895 #if 0
896 /* REVISIT ... this would be for multiplexing periodic endpoints, or
897 * supporting transfer phasing to prevent exceeding ISO bandwidth
898 * limits of a given frame or microframe.
899 *
900 * It's not needed for peripheral side, which dedicates endpoints;
901 * though it _might_ use SOF irqs for other purposes.
902 *
903 * And it's not currently needed for host side, which also dedicates
904 * endpoints, relies on TX/RX interval registers, and isn't claimed
905 * to support ISO transfers yet.
906 */
907 if (int_usb & MUSB_INTR_SOF) {
908 void __iomem *mbase = musb->mregs;
909 struct musb_hw_ep *ep;
910 u8 epnum;
911 u16 frame;
912
913 DBG(6, "START_OF_FRAME\n");
914 handled = IRQ_HANDLED;
915
916 /* start any periodic Tx transfers waiting for current frame */
917 frame = musb_readw(mbase, MUSB_FRAME);
918 ep = musb->endpoints;
919 for (epnum = 1; (epnum < musb->nr_endpoints)
920 && (musb->epmask >= (1 << epnum));
921 epnum++, ep++) {
922 /*
923 * FIXME handle framecounter wraps (12 bits)
924 * eliminate duplicated StartUrb logic
925 */
926 if (ep->dwWaitFrame >= frame) {
927 ep->dwWaitFrame = 0;
928 pr_debug("SOF --> periodic TX%s on %d\n",
929 ep->tx_channel ? " DMA" : "",
930 epnum);
931 if (!ep->tx_channel)
932 musb_h_tx_start(musb, epnum);
933 else
934 cppi_hostdma_start(musb, epnum);
935 }
936 } /* end of for loop */
937 }
938 #endif
939
940 schedule_work(&musb->irq_work);
941
942 return handled;
943 }
944
945 /*-------------------------------------------------------------------------*/
946
947 /*
948 * Program the HDRC to start (enable interrupts, dma, etc.).
949 */
950 void musb_start(struct musb *musb)
951 {
952 void __iomem *regs = musb->mregs;
953 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
954
955 DBG(2, "<== devctl %02x\n", devctl);
956
957 /* Set INT enable registers, enable interrupts */
958 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
959 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
960 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
961
962 musb_writeb(regs, MUSB_TESTMODE, 0);
963
964 /* put into basic highspeed mode and start session */
965 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
966 | MUSB_POWER_SOFTCONN
967 | MUSB_POWER_HSENAB
968 /* ENSUSPEND wedges tusb */
969 /* | MUSB_POWER_ENSUSPEND */
970 );
971
972 musb->is_active = 0;
973 devctl = musb_readb(regs, MUSB_DEVCTL);
974 devctl &= ~MUSB_DEVCTL_SESSION;
975
976 if (is_otg_enabled(musb)) {
977 /* session started after:
978 * (a) ID-grounded irq, host mode;
979 * (b) vbus present/connect IRQ, peripheral mode;
980 * (c) peripheral initiates, using SRP
981 */
982 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
983 musb->is_active = 1;
984 else
985 devctl |= MUSB_DEVCTL_SESSION;
986
987 } else if (is_host_enabled(musb)) {
988 /* assume ID pin is hard-wired to ground */
989 devctl |= MUSB_DEVCTL_SESSION;
990
991 } else /* peripheral is enabled */ {
992 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
993 musb->is_active = 1;
994 }
995 musb_platform_enable(musb);
996 musb_writeb(regs, MUSB_DEVCTL, devctl);
997 }
998
999
1000 static void musb_generic_disable(struct musb *musb)
1001 {
1002 void __iomem *mbase = musb->mregs;
1003 u16 temp;
1004
1005 /* disable interrupts */
1006 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1007 musb_writew(mbase, MUSB_INTRTXE, 0);
1008 musb_writew(mbase, MUSB_INTRRXE, 0);
1009
1010 /* off */
1011 musb_writeb(mbase, MUSB_DEVCTL, 0);
1012
1013 /* flush pending interrupts */
1014 temp = musb_readb(mbase, MUSB_INTRUSB);
1015 temp = musb_readw(mbase, MUSB_INTRTX);
1016 temp = musb_readw(mbase, MUSB_INTRRX);
1017
1018 }
1019
1020 /*
1021 * Make the HDRC stop (disable interrupts, etc.);
1022 * reversible by musb_start
1023 * called on gadget driver unregister
1024 * with controller locked, irqs blocked
1025 * acts as a NOP unless some role activated the hardware
1026 */
1027 void musb_stop(struct musb *musb)
1028 {
1029 /* stop IRQs, timers, ... */
1030 musb_platform_disable(musb);
1031 musb_generic_disable(musb);
1032 DBG(3, "HDRC disabled\n");
1033
1034 /* FIXME
1035 * - mark host and/or peripheral drivers unusable/inactive
1036 * - disable DMA (and enable it in HdrcStart)
1037 * - make sure we can musb_start() after musb_stop(); with
1038 * OTG mode, gadget driver module rmmod/modprobe cycles that
1039 * - ...
1040 */
1041 musb_platform_try_idle(musb, 0);
1042 }
1043
1044 static void musb_shutdown(struct platform_device *pdev)
1045 {
1046 struct musb *musb = dev_to_musb(&pdev->dev);
1047 unsigned long flags;
1048
1049 spin_lock_irqsave(&musb->lock, flags);
1050 musb_platform_disable(musb);
1051 musb_generic_disable(musb);
1052 if (musb->clock)
1053 clk_put(musb->clock);
1054 spin_unlock_irqrestore(&musb->lock, flags);
1055
1056 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1057 usb_remove_hcd(musb_to_hcd(musb));
1058 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1059 musb_platform_exit(musb);
1060
1061 /* FIXME power down */
1062 }
1063
1064
1065 /*-------------------------------------------------------------------------*/
1066
1067 /*
1068 * The silicon either has hard-wired endpoint configurations, or else
1069 * "dynamic fifo" sizing. The driver has support for both, though at this
1070 * writing only the dynamic sizing is very well tested. Since we switched
1071 * away from compile-time hardware parameters, we can no longer rely on
1072 * dead code elimination to leave only the relevant one in the object file.
1073 *
1074 * We don't currently use dynamic fifo setup capability to do anything
1075 * more than selecting one of a bunch of predefined configurations.
1076 */
1077 #if defined(CONFIG_USB_TUSB6010) || \
1078 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1079 || defined(CONFIG_ARCH_OMAP4)
1080 static ushort __initdata fifo_mode = 4;
1081 #else
1082 static ushort __initdata fifo_mode = 2;
1083 #endif
1084
1085 /* "modprobe ... fifo_mode=1" etc */
1086 module_param(fifo_mode, ushort, 0);
1087 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1088
1089 /*
1090 * tables defining fifo_mode values. define more if you like.
1091 * for host side, make sure both halves of ep1 are set up.
1092 */
1093
1094 /* mode 0 - fits in 2KB */
1095 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1096 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1097 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1098 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1099 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1100 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1101 };
1102
1103 /* mode 1 - fits in 4KB */
1104 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1105 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1106 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1107 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1108 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1109 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1110 };
1111
1112 /* mode 2 - fits in 4KB */
1113 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1114 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1117 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1118 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1119 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1120 };
1121
1122 /* mode 3 - fits in 4KB */
1123 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1124 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1125 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1126 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1127 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1128 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1129 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1130 };
1131
1132 /* mode 4 - fits in 16KB */
1133 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1134 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1141 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1142 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1143 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1144 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1145 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1146 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1147 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1148 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1149 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1150 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1151 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1152 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1153 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1154 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1155 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1156 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1157 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1158 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1159 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1160 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1161 };
1162
1163 /* mode 5 - fits in 8KB */
1164 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1165 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1166 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1167 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1168 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1169 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1170 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1171 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1172 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1173 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1174 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1175 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1176 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1177 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1178 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1179 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1180 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1181 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1182 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1183 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1184 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1185 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1186 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1187 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1188 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1189 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1190 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1191 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1192 };
1193
1194 /*
1195 * configure a fifo; for non-shared endpoints, this may be called
1196 * once for a tx fifo and once for an rx fifo.
1197 *
1198 * returns negative errno or offset for next fifo.
1199 */
1200 static int __init
1201 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1202 const struct musb_fifo_cfg *cfg, u16 offset)
1203 {
1204 void __iomem *mbase = musb->mregs;
1205 int size = 0;
1206 u16 maxpacket = cfg->maxpacket;
1207 u16 c_off = offset >> 3;
1208 u8 c_size;
1209
1210 /* expect hw_ep has already been zero-initialized */
1211
1212 size = ffs(max(maxpacket, (u16) 8)) - 1;
1213 maxpacket = 1 << size;
1214
1215 c_size = size - 3;
1216 if (cfg->mode == BUF_DOUBLE) {
1217 if ((offset + (maxpacket << 1)) >
1218 (1 << (musb->config->ram_bits + 2)))
1219 return -EMSGSIZE;
1220 c_size |= MUSB_FIFOSZ_DPB;
1221 } else {
1222 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1223 return -EMSGSIZE;
1224 }
1225
1226 /* configure the FIFO */
1227 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1228
1229 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1230 /* EP0 reserved endpoint for control, bidirectional;
1231 * EP1 reserved for bulk, two unidirection halves.
1232 */
1233 if (hw_ep->epnum == 1)
1234 musb->bulk_ep = hw_ep;
1235 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1236 #endif
1237 switch (cfg->style) {
1238 case FIFO_TX:
1239 musb_write_txfifosz(mbase, c_size);
1240 musb_write_txfifoadd(mbase, c_off);
1241 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1242 hw_ep->max_packet_sz_tx = maxpacket;
1243 break;
1244 case FIFO_RX:
1245 musb_write_rxfifosz(mbase, c_size);
1246 musb_write_rxfifoadd(mbase, c_off);
1247 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1248 hw_ep->max_packet_sz_rx = maxpacket;
1249 break;
1250 case FIFO_RXTX:
1251 musb_write_txfifosz(mbase, c_size);
1252 musb_write_txfifoadd(mbase, c_off);
1253 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1254 hw_ep->max_packet_sz_rx = maxpacket;
1255
1256 musb_write_rxfifosz(mbase, c_size);
1257 musb_write_rxfifoadd(mbase, c_off);
1258 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1259 hw_ep->max_packet_sz_tx = maxpacket;
1260
1261 hw_ep->is_shared_fifo = true;
1262 break;
1263 }
1264
1265 /* NOTE rx and tx endpoint irqs aren't managed separately,
1266 * which happens to be ok
1267 */
1268 musb->epmask |= (1 << hw_ep->epnum);
1269
1270 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1271 }
1272
1273 static struct musb_fifo_cfg __initdata ep0_cfg = {
1274 .style = FIFO_RXTX, .maxpacket = 64,
1275 };
1276
1277 static int __init ep_config_from_table(struct musb *musb)
1278 {
1279 const struct musb_fifo_cfg *cfg;
1280 unsigned i, n;
1281 int offset;
1282 struct musb_hw_ep *hw_ep = musb->endpoints;
1283
1284 if (musb->config->fifo_cfg) {
1285 cfg = musb->config->fifo_cfg;
1286 n = musb->config->fifo_cfg_size;
1287 goto done;
1288 }
1289
1290 switch (fifo_mode) {
1291 default:
1292 fifo_mode = 0;
1293 /* FALLTHROUGH */
1294 case 0:
1295 cfg = mode_0_cfg;
1296 n = ARRAY_SIZE(mode_0_cfg);
1297 break;
1298 case 1:
1299 cfg = mode_1_cfg;
1300 n = ARRAY_SIZE(mode_1_cfg);
1301 break;
1302 case 2:
1303 cfg = mode_2_cfg;
1304 n = ARRAY_SIZE(mode_2_cfg);
1305 break;
1306 case 3:
1307 cfg = mode_3_cfg;
1308 n = ARRAY_SIZE(mode_3_cfg);
1309 break;
1310 case 4:
1311 cfg = mode_4_cfg;
1312 n = ARRAY_SIZE(mode_4_cfg);
1313 break;
1314 case 5:
1315 cfg = mode_5_cfg;
1316 n = ARRAY_SIZE(mode_5_cfg);
1317 break;
1318 }
1319
1320 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1321 musb_driver_name, fifo_mode);
1322
1323
1324 done:
1325 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1326 /* assert(offset > 0) */
1327
1328 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1329 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1330 */
1331
1332 for (i = 0; i < n; i++) {
1333 u8 epn = cfg->hw_ep_num;
1334
1335 if (epn >= musb->config->num_eps) {
1336 pr_debug("%s: invalid ep %d\n",
1337 musb_driver_name, epn);
1338 return -EINVAL;
1339 }
1340 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1341 if (offset < 0) {
1342 pr_debug("%s: mem overrun, ep %d\n",
1343 musb_driver_name, epn);
1344 return -EINVAL;
1345 }
1346 epn++;
1347 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1348 }
1349
1350 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1351 musb_driver_name,
1352 n + 1, musb->config->num_eps * 2 - 1,
1353 offset, (1 << (musb->config->ram_bits + 2)));
1354
1355 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1356 if (!musb->bulk_ep) {
1357 pr_debug("%s: missing bulk\n", musb_driver_name);
1358 return -EINVAL;
1359 }
1360 #endif
1361
1362 return 0;
1363 }
1364
1365
1366 /*
1367 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1368 * @param musb the controller
1369 */
1370 static int __init ep_config_from_hw(struct musb *musb)
1371 {
1372 u8 epnum = 0;
1373 struct musb_hw_ep *hw_ep;
1374 void *mbase = musb->mregs;
1375 int ret = 0;
1376
1377 DBG(2, "<== static silicon ep config\n");
1378
1379 /* FIXME pick up ep0 maxpacket size */
1380
1381 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1382 musb_ep_select(mbase, epnum);
1383 hw_ep = musb->endpoints + epnum;
1384
1385 ret = musb_read_fifosize(musb, hw_ep, epnum);
1386 if (ret < 0)
1387 break;
1388
1389 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1390
1391 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1392 /* pick an RX/TX endpoint for bulk */
1393 if (hw_ep->max_packet_sz_tx < 512
1394 || hw_ep->max_packet_sz_rx < 512)
1395 continue;
1396
1397 /* REVISIT: this algorithm is lazy, we should at least
1398 * try to pick a double buffered endpoint.
1399 */
1400 if (musb->bulk_ep)
1401 continue;
1402 musb->bulk_ep = hw_ep;
1403 #endif
1404 }
1405
1406 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1407 if (!musb->bulk_ep) {
1408 pr_debug("%s: missing bulk\n", musb_driver_name);
1409 return -EINVAL;
1410 }
1411 #endif
1412
1413 return 0;
1414 }
1415
1416 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1417
1418 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1419 * configure endpoints, or take their config from silicon
1420 */
1421 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1422 {
1423 u8 reg;
1424 char *type;
1425 char aInfo[90], aRevision[32], aDate[12];
1426 void __iomem *mbase = musb->mregs;
1427 int status = 0;
1428 int i;
1429
1430 /* log core options (read using indexed model) */
1431 reg = musb_read_configdata(mbase);
1432
1433 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1434 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1435 strcat(aInfo, ", dyn FIFOs");
1436 musb->dyn_fifo = true;
1437 }
1438 if (reg & MUSB_CONFIGDATA_MPRXE) {
1439 strcat(aInfo, ", bulk combine");
1440 musb->bulk_combine = true;
1441 }
1442 if (reg & MUSB_CONFIGDATA_MPTXE) {
1443 strcat(aInfo, ", bulk split");
1444 musb->bulk_split = true;
1445 }
1446 if (reg & MUSB_CONFIGDATA_HBRXE) {
1447 strcat(aInfo, ", HB-ISO Rx");
1448 musb->hb_iso_rx = true;
1449 }
1450 if (reg & MUSB_CONFIGDATA_HBTXE) {
1451 strcat(aInfo, ", HB-ISO Tx");
1452 musb->hb_iso_tx = true;
1453 }
1454 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1455 strcat(aInfo, ", SoftConn");
1456
1457 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1458 musb_driver_name, reg, aInfo);
1459
1460 aDate[0] = 0;
1461 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1462 musb->is_multipoint = 1;
1463 type = "M";
1464 } else {
1465 musb->is_multipoint = 0;
1466 type = "";
1467 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1468 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1469 printk(KERN_ERR
1470 "%s: kernel must blacklist external hubs\n",
1471 musb_driver_name);
1472 #endif
1473 #endif
1474 }
1475
1476 /* log release info */
1477 musb->hwvers = musb_read_hwvers(mbase);
1478 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1479 MUSB_HWVERS_MINOR(musb->hwvers),
1480 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1481 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1482 musb_driver_name, type, aRevision, aDate);
1483
1484 /* configure ep0 */
1485 musb_configure_ep0(musb);
1486
1487 /* discover endpoint configuration */
1488 musb->nr_endpoints = 1;
1489 musb->epmask = 1;
1490
1491 if (musb->dyn_fifo)
1492 status = ep_config_from_table(musb);
1493 else
1494 status = ep_config_from_hw(musb);
1495
1496 if (status < 0)
1497 return status;
1498
1499 /* finish init, and print endpoint config */
1500 for (i = 0; i < musb->nr_endpoints; i++) {
1501 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1502
1503 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1504 #ifdef CONFIG_USB_TUSB6010
1505 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1506 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1507 hw_ep->fifo_sync_va =
1508 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1509
1510 if (i == 0)
1511 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1512 else
1513 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1514 #endif
1515
1516 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1517 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1518 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1519 hw_ep->rx_reinit = 1;
1520 hw_ep->tx_reinit = 1;
1521 #endif
1522
1523 if (hw_ep->max_packet_sz_tx) {
1524 DBG(1,
1525 "%s: hw_ep %d%s, %smax %d\n",
1526 musb_driver_name, i,
1527 hw_ep->is_shared_fifo ? "shared" : "tx",
1528 hw_ep->tx_double_buffered
1529 ? "doublebuffer, " : "",
1530 hw_ep->max_packet_sz_tx);
1531 }
1532 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1533 DBG(1,
1534 "%s: hw_ep %d%s, %smax %d\n",
1535 musb_driver_name, i,
1536 "rx",
1537 hw_ep->rx_double_buffered
1538 ? "doublebuffer, " : "",
1539 hw_ep->max_packet_sz_rx);
1540 }
1541 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1542 DBG(1, "hw_ep %d not configured\n", i);
1543 }
1544
1545 return 0;
1546 }
1547
1548 /*-------------------------------------------------------------------------*/
1549
1550 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1551 defined(CONFIG_ARCH_OMAP4)
1552
1553 static irqreturn_t generic_interrupt(int irq, void *__hci)
1554 {
1555 unsigned long flags;
1556 irqreturn_t retval = IRQ_NONE;
1557 struct musb *musb = __hci;
1558
1559 spin_lock_irqsave(&musb->lock, flags);
1560
1561 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1562 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1563 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1564
1565 if (musb->int_usb || musb->int_tx || musb->int_rx)
1566 retval = musb_interrupt(musb);
1567
1568 spin_unlock_irqrestore(&musb->lock, flags);
1569
1570 return retval;
1571 }
1572
1573 #else
1574 #define generic_interrupt NULL
1575 #endif
1576
1577 /*
1578 * handle all the irqs defined by the HDRC core. for now we expect: other
1579 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1580 * will be assigned, and the irq will already have been acked.
1581 *
1582 * called in irq context with spinlock held, irqs blocked
1583 */
1584 irqreturn_t musb_interrupt(struct musb *musb)
1585 {
1586 irqreturn_t retval = IRQ_NONE;
1587 u8 devctl, power;
1588 int ep_num;
1589 u32 reg;
1590
1591 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1592 power = musb_readb(musb->mregs, MUSB_POWER);
1593
1594 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1595 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1596 musb->int_usb, musb->int_tx, musb->int_rx);
1597
1598 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1599 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1600 if (!musb->gadget_driver) {
1601 DBG(5, "No gadget driver loaded\n");
1602 return IRQ_HANDLED;
1603 }
1604 #endif
1605
1606 /* the core can interrupt us for multiple reasons; docs have
1607 * a generic interrupt flowchart to follow
1608 */
1609 if (musb->int_usb)
1610 retval |= musb_stage0_irq(musb, musb->int_usb,
1611 devctl, power);
1612
1613 /* "stage 1" is handling endpoint irqs */
1614
1615 /* handle endpoint 0 first */
1616 if (musb->int_tx & 1) {
1617 if (devctl & MUSB_DEVCTL_HM)
1618 retval |= musb_h_ep0_irq(musb);
1619 else
1620 retval |= musb_g_ep0_irq(musb);
1621 }
1622
1623 /* RX on endpoints 1-15 */
1624 reg = musb->int_rx >> 1;
1625 ep_num = 1;
1626 while (reg) {
1627 if (reg & 1) {
1628 /* musb_ep_select(musb->mregs, ep_num); */
1629 /* REVISIT just retval = ep->rx_irq(...) */
1630 retval = IRQ_HANDLED;
1631 if (devctl & MUSB_DEVCTL_HM) {
1632 if (is_host_capable())
1633 musb_host_rx(musb, ep_num);
1634 } else {
1635 if (is_peripheral_capable())
1636 musb_g_rx(musb, ep_num);
1637 }
1638 }
1639
1640 reg >>= 1;
1641 ep_num++;
1642 }
1643
1644 /* TX on endpoints 1-15 */
1645 reg = musb->int_tx >> 1;
1646 ep_num = 1;
1647 while (reg) {
1648 if (reg & 1) {
1649 /* musb_ep_select(musb->mregs, ep_num); */
1650 /* REVISIT just retval |= ep->tx_irq(...) */
1651 retval = IRQ_HANDLED;
1652 if (devctl & MUSB_DEVCTL_HM) {
1653 if (is_host_capable())
1654 musb_host_tx(musb, ep_num);
1655 } else {
1656 if (is_peripheral_capable())
1657 musb_g_tx(musb, ep_num);
1658 }
1659 }
1660 reg >>= 1;
1661 ep_num++;
1662 }
1663
1664 return retval;
1665 }
1666
1667
1668 #ifndef CONFIG_MUSB_PIO_ONLY
1669 static int __initdata use_dma = 1;
1670
1671 /* "modprobe ... use_dma=0" etc */
1672 module_param(use_dma, bool, 0);
1673 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1674
1675 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1676 {
1677 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1678
1679 /* called with controller lock already held */
1680
1681 if (!epnum) {
1682 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1683 if (!is_cppi_enabled()) {
1684 /* endpoint 0 */
1685 if (devctl & MUSB_DEVCTL_HM)
1686 musb_h_ep0_irq(musb);
1687 else
1688 musb_g_ep0_irq(musb);
1689 }
1690 #endif
1691 } else {
1692 /* endpoints 1..15 */
1693 if (transmit) {
1694 if (devctl & MUSB_DEVCTL_HM) {
1695 if (is_host_capable())
1696 musb_host_tx(musb, epnum);
1697 } else {
1698 if (is_peripheral_capable())
1699 musb_g_tx(musb, epnum);
1700 }
1701 } else {
1702 /* receive */
1703 if (devctl & MUSB_DEVCTL_HM) {
1704 if (is_host_capable())
1705 musb_host_rx(musb, epnum);
1706 } else {
1707 if (is_peripheral_capable())
1708 musb_g_rx(musb, epnum);
1709 }
1710 }
1711 }
1712 }
1713
1714 #else
1715 #define use_dma 0
1716 #endif
1717
1718 /*-------------------------------------------------------------------------*/
1719
1720 #ifdef CONFIG_SYSFS
1721
1722 static ssize_t
1723 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1724 {
1725 struct musb *musb = dev_to_musb(dev);
1726 unsigned long flags;
1727 int ret = -EINVAL;
1728
1729 spin_lock_irqsave(&musb->lock, flags);
1730 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1731 spin_unlock_irqrestore(&musb->lock, flags);
1732
1733 return ret;
1734 }
1735
1736 static ssize_t
1737 musb_mode_store(struct device *dev, struct device_attribute *attr,
1738 const char *buf, size_t n)
1739 {
1740 struct musb *musb = dev_to_musb(dev);
1741 unsigned long flags;
1742 int status;
1743
1744 spin_lock_irqsave(&musb->lock, flags);
1745 if (sysfs_streq(buf, "host"))
1746 status = musb_platform_set_mode(musb, MUSB_HOST);
1747 else if (sysfs_streq(buf, "peripheral"))
1748 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1749 else if (sysfs_streq(buf, "otg"))
1750 status = musb_platform_set_mode(musb, MUSB_OTG);
1751 else
1752 status = -EINVAL;
1753 spin_unlock_irqrestore(&musb->lock, flags);
1754
1755 return (status == 0) ? n : status;
1756 }
1757 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1758
1759 static ssize_t
1760 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1761 const char *buf, size_t n)
1762 {
1763 struct musb *musb = dev_to_musb(dev);
1764 unsigned long flags;
1765 unsigned long val;
1766
1767 if (sscanf(buf, "%lu", &val) < 1) {
1768 dev_err(dev, "Invalid VBUS timeout ms value\n");
1769 return -EINVAL;
1770 }
1771
1772 spin_lock_irqsave(&musb->lock, flags);
1773 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1774 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1775 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1776 musb->is_active = 0;
1777 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1778 spin_unlock_irqrestore(&musb->lock, flags);
1779
1780 return n;
1781 }
1782
1783 static ssize_t
1784 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1785 {
1786 struct musb *musb = dev_to_musb(dev);
1787 unsigned long flags;
1788 unsigned long val;
1789 int vbus;
1790
1791 spin_lock_irqsave(&musb->lock, flags);
1792 val = musb->a_wait_bcon;
1793 /* FIXME get_vbus_status() is normally #defined as false...
1794 * and is effectively TUSB-specific.
1795 */
1796 vbus = musb_platform_get_vbus_status(musb);
1797 spin_unlock_irqrestore(&musb->lock, flags);
1798
1799 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1800 vbus ? "on" : "off", val);
1801 }
1802 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1803
1804 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1805
1806 /* Gadget drivers can't know that a host is connected so they might want
1807 * to start SRP, but users can. This allows userspace to trigger SRP.
1808 */
1809 static ssize_t
1810 musb_srp_store(struct device *dev, struct device_attribute *attr,
1811 const char *buf, size_t n)
1812 {
1813 struct musb *musb = dev_to_musb(dev);
1814 unsigned short srp;
1815
1816 if (sscanf(buf, "%hu", &srp) != 1
1817 || (srp != 1)) {
1818 dev_err(dev, "SRP: Value must be 1\n");
1819 return -EINVAL;
1820 }
1821
1822 if (srp == 1)
1823 musb_g_wakeup(musb);
1824
1825 return n;
1826 }
1827 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1828
1829 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1830
1831 static struct attribute *musb_attributes[] = {
1832 &dev_attr_mode.attr,
1833 &dev_attr_vbus.attr,
1834 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1835 &dev_attr_srp.attr,
1836 #endif
1837 NULL
1838 };
1839
1840 static const struct attribute_group musb_attr_group = {
1841 .attrs = musb_attributes,
1842 };
1843
1844 #endif /* sysfs */
1845
1846 /* Only used to provide driver mode change events */
1847 static void musb_irq_work(struct work_struct *data)
1848 {
1849 struct musb *musb = container_of(data, struct musb, irq_work);
1850 static int old_state;
1851
1852 if (musb->xceiv->state != old_state) {
1853 old_state = musb->xceiv->state;
1854 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1855 }
1856 }
1857
1858 /* --------------------------------------------------------------------------
1859 * Init support
1860 */
1861
1862 static struct musb *__init
1863 allocate_instance(struct device *dev,
1864 struct musb_hdrc_config *config, void __iomem *mbase)
1865 {
1866 struct musb *musb;
1867 struct musb_hw_ep *ep;
1868 int epnum;
1869 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1870 struct usb_hcd *hcd;
1871
1872 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1873 if (!hcd)
1874 return NULL;
1875 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1876
1877 musb = hcd_to_musb(hcd);
1878 INIT_LIST_HEAD(&musb->control);
1879 INIT_LIST_HEAD(&musb->in_bulk);
1880 INIT_LIST_HEAD(&musb->out_bulk);
1881
1882 hcd->uses_new_polling = 1;
1883 hcd->has_tt = 1;
1884
1885 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1886 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1887 #else
1888 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1889 if (!musb)
1890 return NULL;
1891 dev_set_drvdata(dev, musb);
1892
1893 #endif
1894
1895 musb->mregs = mbase;
1896 musb->ctrl_base = mbase;
1897 musb->nIrq = -ENODEV;
1898 musb->config = config;
1899 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1900 for (epnum = 0, ep = musb->endpoints;
1901 epnum < musb->config->num_eps;
1902 epnum++, ep++) {
1903 ep->musb = musb;
1904 ep->epnum = epnum;
1905 }
1906
1907 musb->controller = dev;
1908 return musb;
1909 }
1910
1911 static void musb_free(struct musb *musb)
1912 {
1913 /* this has multiple entry modes. it handles fault cleanup after
1914 * probe(), where things may be partially set up, as well as rmmod
1915 * cleanup after everything's been de-activated.
1916 */
1917
1918 #ifdef CONFIG_SYSFS
1919 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1920 #endif
1921
1922 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1923 musb_gadget_cleanup(musb);
1924 #endif
1925
1926 if (musb->nIrq >= 0) {
1927 if (musb->irq_wake)
1928 disable_irq_wake(musb->nIrq);
1929 free_irq(musb->nIrq, musb);
1930 }
1931 if (is_dma_capable() && musb->dma_controller) {
1932 struct dma_controller *c = musb->dma_controller;
1933
1934 (void) c->stop(c);
1935 dma_controller_destroy(c);
1936 }
1937
1938 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1939 usb_put_hcd(musb_to_hcd(musb));
1940 #else
1941 kfree(musb);
1942 #endif
1943 }
1944
1945 /*
1946 * Perform generic per-controller initialization.
1947 *
1948 * @pDevice: the controller (already clocked, etc)
1949 * @nIrq: irq
1950 * @mregs: virtual address of controller registers,
1951 * not yet corrected for platform-specific offsets
1952 */
1953 static int __init
1954 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1955 {
1956 int status;
1957 struct musb *musb;
1958 struct musb_hdrc_platform_data *plat = dev->platform_data;
1959
1960 /* The driver might handle more features than the board; OK.
1961 * Fail when the board needs a feature that's not enabled.
1962 */
1963 if (!plat) {
1964 dev_dbg(dev, "no platform_data?\n");
1965 status = -ENODEV;
1966 goto fail0;
1967 }
1968
1969 switch (plat->mode) {
1970 case MUSB_HOST:
1971 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1972 break;
1973 #else
1974 goto bad_config;
1975 #endif
1976 case MUSB_PERIPHERAL:
1977 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1978 break;
1979 #else
1980 goto bad_config;
1981 #endif
1982 case MUSB_OTG:
1983 #ifdef CONFIG_USB_MUSB_OTG
1984 break;
1985 #else
1986 bad_config:
1987 #endif
1988 default:
1989 dev_err(dev, "incompatible Kconfig role setting\n");
1990 status = -EINVAL;
1991 goto fail0;
1992 }
1993
1994 /* allocate */
1995 musb = allocate_instance(dev, plat->config, ctrl);
1996 if (!musb) {
1997 status = -ENOMEM;
1998 goto fail0;
1999 }
2000
2001 spin_lock_init(&musb->lock);
2002 musb->board_mode = plat->mode;
2003 musb->board_set_power = plat->set_power;
2004 musb->set_clock = plat->set_clock;
2005 musb->min_power = plat->min_power;
2006
2007 /* Clock usage is chip-specific ... functional clock (DaVinci,
2008 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2009 * code does is make sure a clock handle is available; platform
2010 * code manages it during start/stop and suspend/resume.
2011 */
2012 if (plat->clock) {
2013 musb->clock = clk_get(dev, plat->clock);
2014 if (IS_ERR(musb->clock)) {
2015 status = PTR_ERR(musb->clock);
2016 musb->clock = NULL;
2017 goto fail1;
2018 }
2019 }
2020
2021 /* The musb_platform_init() call:
2022 * - adjusts musb->mregs and musb->isr if needed,
2023 * - may initialize an integrated tranceiver
2024 * - initializes musb->xceiv, usually by otg_get_transceiver()
2025 * - activates clocks.
2026 * - stops powering VBUS
2027 * - assigns musb->board_set_vbus if host mode is enabled
2028 *
2029 * There are various transciever configurations. Blackfin,
2030 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2031 * external/discrete ones in various flavors (twl4030 family,
2032 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2033 */
2034 musb->isr = generic_interrupt;
2035 status = musb_platform_init(musb, plat->board_data);
2036 if (status < 0)
2037 goto fail2;
2038
2039 if (!musb->isr) {
2040 status = -ENODEV;
2041 goto fail3;
2042 }
2043
2044 if (!musb->xceiv->io_ops) {
2045 musb->xceiv->io_priv = musb->mregs;
2046 musb->xceiv->io_ops = &musb_ulpi_access;
2047 }
2048
2049 #ifndef CONFIG_MUSB_PIO_ONLY
2050 if (use_dma && dev->dma_mask) {
2051 struct dma_controller *c;
2052
2053 c = dma_controller_create(musb, musb->mregs);
2054 musb->dma_controller = c;
2055 if (c)
2056 (void) c->start(c);
2057 }
2058 #endif
2059 /* ideally this would be abstracted in platform setup */
2060 if (!is_dma_capable() || !musb->dma_controller)
2061 dev->dma_mask = NULL;
2062
2063 /* be sure interrupts are disabled before connecting ISR */
2064 musb_platform_disable(musb);
2065 musb_generic_disable(musb);
2066
2067 /* setup musb parts of the core (especially endpoints) */
2068 status = musb_core_init(plat->config->multipoint
2069 ? MUSB_CONTROLLER_MHDRC
2070 : MUSB_CONTROLLER_HDRC, musb);
2071 if (status < 0)
2072 goto fail3;
2073
2074 #ifdef CONFIG_USB_MUSB_OTG
2075 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2076 #endif
2077
2078 /* Init IRQ workqueue before request_irq */
2079 INIT_WORK(&musb->irq_work, musb_irq_work);
2080
2081 /* attach to the IRQ */
2082 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2083 dev_err(dev, "request_irq %d failed!\n", nIrq);
2084 status = -ENODEV;
2085 goto fail3;
2086 }
2087 musb->nIrq = nIrq;
2088 /* FIXME this handles wakeup irqs wrong */
2089 if (enable_irq_wake(nIrq) == 0) {
2090 musb->irq_wake = 1;
2091 device_init_wakeup(dev, 1);
2092 } else {
2093 musb->irq_wake = 0;
2094 }
2095
2096 /* host side needs more setup */
2097 if (is_host_enabled(musb)) {
2098 struct usb_hcd *hcd = musb_to_hcd(musb);
2099
2100 otg_set_host(musb->xceiv, &hcd->self);
2101
2102 if (is_otg_enabled(musb))
2103 hcd->self.otg_port = 1;
2104 musb->xceiv->host = &hcd->self;
2105 hcd->power_budget = 2 * (plat->power ? : 250);
2106
2107 /* program PHY to use external vBus if required */
2108 if (plat->extvbus) {
2109 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2110 busctl |= MUSB_ULPI_USE_EXTVBUS;
2111 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2112 }
2113 }
2114
2115 /* For the host-only role, we can activate right away.
2116 * (We expect the ID pin to be forcibly grounded!!)
2117 * Otherwise, wait till the gadget driver hooks up.
2118 */
2119 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2120 struct usb_hcd *hcd = musb_to_hcd(musb);
2121
2122 MUSB_HST_MODE(musb);
2123 musb->xceiv->default_a = 1;
2124 musb->xceiv->state = OTG_STATE_A_IDLE;
2125
2126 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2127
2128 hcd->self.uses_pio_for_control = 1;
2129 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2130 "HOST", status,
2131 musb_readb(musb->mregs, MUSB_DEVCTL),
2132 (musb_readb(musb->mregs, MUSB_DEVCTL)
2133 & MUSB_DEVCTL_BDEVICE
2134 ? 'B' : 'A'));
2135
2136 } else /* peripheral is enabled */ {
2137 MUSB_DEV_MODE(musb);
2138 musb->xceiv->default_a = 0;
2139 musb->xceiv->state = OTG_STATE_B_IDLE;
2140
2141 status = musb_gadget_setup(musb);
2142
2143 DBG(1, "%s mode, status %d, dev%02x\n",
2144 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2145 status,
2146 musb_readb(musb->mregs, MUSB_DEVCTL));
2147
2148 }
2149 if (status < 0)
2150 goto fail3;
2151
2152 status = musb_init_debugfs(musb);
2153 if (status < 0)
2154 goto fail4;
2155
2156 #ifdef CONFIG_SYSFS
2157 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2158 if (status)
2159 goto fail5;
2160 #endif
2161
2162 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2163 ({char *s;
2164 switch (musb->board_mode) {
2165 case MUSB_HOST: s = "Host"; break;
2166 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2167 default: s = "OTG"; break;
2168 }; s; }),
2169 ctrl,
2170 (is_dma_capable() && musb->dma_controller)
2171 ? "DMA" : "PIO",
2172 musb->nIrq);
2173
2174 return 0;
2175
2176 fail5:
2177 musb_exit_debugfs(musb);
2178
2179 fail4:
2180 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2181 usb_remove_hcd(musb_to_hcd(musb));
2182 else
2183 musb_gadget_cleanup(musb);
2184
2185 fail3:
2186 if (musb->irq_wake)
2187 device_init_wakeup(dev, 0);
2188 musb_platform_exit(musb);
2189
2190 fail2:
2191 if (musb->clock)
2192 clk_put(musb->clock);
2193
2194 fail1:
2195 dev_err(musb->controller,
2196 "musb_init_controller failed with status %d\n", status);
2197
2198 musb_free(musb);
2199
2200 fail0:
2201
2202 return status;
2203
2204 }
2205
2206 /*-------------------------------------------------------------------------*/
2207
2208 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2209 * bridge to a platform device; this driver then suffices.
2210 */
2211
2212 #ifndef CONFIG_MUSB_PIO_ONLY
2213 static u64 *orig_dma_mask;
2214 #endif
2215
2216 static int __init musb_probe(struct platform_device *pdev)
2217 {
2218 struct device *dev = &pdev->dev;
2219 int irq = platform_get_irq(pdev, 0);
2220 int status;
2221 struct resource *iomem;
2222 void __iomem *base;
2223
2224 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2225 if (!iomem || irq == 0)
2226 return -ENODEV;
2227
2228 base = ioremap(iomem->start, resource_size(iomem));
2229 if (!base) {
2230 dev_err(dev, "ioremap failed\n");
2231 return -ENOMEM;
2232 }
2233
2234 #ifndef CONFIG_MUSB_PIO_ONLY
2235 /* clobbered by use_dma=n */
2236 orig_dma_mask = dev->dma_mask;
2237 #endif
2238 status = musb_init_controller(dev, irq, base);
2239 if (status < 0)
2240 iounmap(base);
2241
2242 return status;
2243 }
2244
2245 static int __exit musb_remove(struct platform_device *pdev)
2246 {
2247 struct musb *musb = dev_to_musb(&pdev->dev);
2248 void __iomem *ctrl_base = musb->ctrl_base;
2249
2250 /* this gets called on rmmod.
2251 * - Host mode: host may still be active
2252 * - Peripheral mode: peripheral is deactivated (or never-activated)
2253 * - OTG mode: both roles are deactivated (or never-activated)
2254 */
2255 musb_exit_debugfs(musb);
2256 musb_shutdown(pdev);
2257
2258 musb_free(musb);
2259 iounmap(ctrl_base);
2260 device_init_wakeup(&pdev->dev, 0);
2261 #ifndef CONFIG_MUSB_PIO_ONLY
2262 pdev->dev.dma_mask = orig_dma_mask;
2263 #endif
2264 return 0;
2265 }
2266
2267 #ifdef CONFIG_PM
2268
2269 static struct musb_context_registers musb_context;
2270
2271 void musb_save_context(struct musb *musb)
2272 {
2273 int i;
2274 void __iomem *musb_base = musb->mregs;
2275 void __iomem *epio;
2276
2277 if (is_host_enabled(musb)) {
2278 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2279 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2280 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2281 }
2282 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2283 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2284 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2285 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2286 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2287 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2288
2289 for (i = 0; i < musb->config->num_eps; ++i) {
2290 epio = musb->endpoints[i].regs;
2291 musb_context.index_regs[i].txmaxp =
2292 musb_readw(epio, MUSB_TXMAXP);
2293 musb_context.index_regs[i].txcsr =
2294 musb_readw(epio, MUSB_TXCSR);
2295 musb_context.index_regs[i].rxmaxp =
2296 musb_readw(epio, MUSB_RXMAXP);
2297 musb_context.index_regs[i].rxcsr =
2298 musb_readw(epio, MUSB_RXCSR);
2299
2300 if (musb->dyn_fifo) {
2301 musb_context.index_regs[i].txfifoadd =
2302 musb_read_txfifoadd(musb_base);
2303 musb_context.index_regs[i].rxfifoadd =
2304 musb_read_rxfifoadd(musb_base);
2305 musb_context.index_regs[i].txfifosz =
2306 musb_read_txfifosz(musb_base);
2307 musb_context.index_regs[i].rxfifosz =
2308 musb_read_rxfifosz(musb_base);
2309 }
2310 if (is_host_enabled(musb)) {
2311 musb_context.index_regs[i].txtype =
2312 musb_readb(epio, MUSB_TXTYPE);
2313 musb_context.index_regs[i].txinterval =
2314 musb_readb(epio, MUSB_TXINTERVAL);
2315 musb_context.index_regs[i].rxtype =
2316 musb_readb(epio, MUSB_RXTYPE);
2317 musb_context.index_regs[i].rxinterval =
2318 musb_readb(epio, MUSB_RXINTERVAL);
2319
2320 musb_context.index_regs[i].txfunaddr =
2321 musb_read_txfunaddr(musb_base, i);
2322 musb_context.index_regs[i].txhubaddr =
2323 musb_read_txhubaddr(musb_base, i);
2324 musb_context.index_regs[i].txhubport =
2325 musb_read_txhubport(musb_base, i);
2326
2327 musb_context.index_regs[i].rxfunaddr =
2328 musb_read_rxfunaddr(musb_base, i);
2329 musb_context.index_regs[i].rxhubaddr =
2330 musb_read_rxhubaddr(musb_base, i);
2331 musb_context.index_regs[i].rxhubport =
2332 musb_read_rxhubport(musb_base, i);
2333 }
2334 }
2335
2336 musb_platform_save_context(musb, &musb_context);
2337 }
2338
2339 void musb_restore_context(struct musb *musb)
2340 {
2341 int i;
2342 void __iomem *musb_base = musb->mregs;
2343 void __iomem *ep_target_regs;
2344 void __iomem *epio;
2345
2346 musb_platform_restore_context(musb, &musb_context);
2347
2348 if (is_host_enabled(musb)) {
2349 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2350 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2351 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2352 }
2353 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2354 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2355 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2356 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2357 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2358
2359 for (i = 0; i < musb->config->num_eps; ++i) {
2360 epio = musb->endpoints[i].regs;
2361 musb_writew(epio, MUSB_TXMAXP,
2362 musb_context.index_regs[i].txmaxp);
2363 musb_writew(epio, MUSB_TXCSR,
2364 musb_context.index_regs[i].txcsr);
2365 musb_writew(epio, MUSB_RXMAXP,
2366 musb_context.index_regs[i].rxmaxp);
2367 musb_writew(epio, MUSB_RXCSR,
2368 musb_context.index_regs[i].rxcsr);
2369
2370 if (musb->dyn_fifo) {
2371 musb_write_txfifosz(musb_base,
2372 musb_context.index_regs[i].txfifosz);
2373 musb_write_rxfifosz(musb_base,
2374 musb_context.index_regs[i].rxfifosz);
2375 musb_write_txfifoadd(musb_base,
2376 musb_context.index_regs[i].txfifoadd);
2377 musb_write_rxfifoadd(musb_base,
2378 musb_context.index_regs[i].rxfifoadd);
2379 }
2380
2381 if (is_host_enabled(musb)) {
2382 musb_writeb(epio, MUSB_TXTYPE,
2383 musb_context.index_regs[i].txtype);
2384 musb_writeb(epio, MUSB_TXINTERVAL,
2385 musb_context.index_regs[i].txinterval);
2386 musb_writeb(epio, MUSB_RXTYPE,
2387 musb_context.index_regs[i].rxtype);
2388 musb_writeb(epio, MUSB_RXINTERVAL,
2389
2390 musb_context.index_regs[i].rxinterval);
2391 musb_write_txfunaddr(musb_base, i,
2392 musb_context.index_regs[i].txfunaddr);
2393 musb_write_txhubaddr(musb_base, i,
2394 musb_context.index_regs[i].txhubaddr);
2395 musb_write_txhubport(musb_base, i,
2396 musb_context.index_regs[i].txhubport);
2397
2398 ep_target_regs =
2399 musb_read_target_reg_base(i, musb_base);
2400
2401 musb_write_rxfunaddr(ep_target_regs,
2402 musb_context.index_regs[i].rxfunaddr);
2403 musb_write_rxhubaddr(ep_target_regs,
2404 musb_context.index_regs[i].rxhubaddr);
2405 musb_write_rxhubport(ep_target_regs,
2406 musb_context.index_regs[i].rxhubport);
2407 }
2408 }
2409 }
2410
2411 static int musb_suspend(struct device *dev)
2412 {
2413 struct platform_device *pdev = to_platform_device(dev);
2414 unsigned long flags;
2415 struct musb *musb = dev_to_musb(&pdev->dev);
2416
2417 spin_lock_irqsave(&musb->lock, flags);
2418
2419 if (is_peripheral_active(musb)) {
2420 /* FIXME force disconnect unless we know USB will wake
2421 * the system up quickly enough to respond ...
2422 */
2423 } else if (is_host_active(musb)) {
2424 /* we know all the children are suspended; sometimes
2425 * they will even be wakeup-enabled.
2426 */
2427 }
2428
2429 musb_save_context(musb);
2430
2431 if (musb->clock) {
2432 if (musb->set_clock)
2433 musb->set_clock(musb->clock, 0);
2434 else
2435 clk_disable(musb->clock);
2436 }
2437 spin_unlock_irqrestore(&musb->lock, flags);
2438 return 0;
2439 }
2440
2441 static int musb_resume_noirq(struct device *dev)
2442 {
2443 struct platform_device *pdev = to_platform_device(dev);
2444 struct musb *musb = dev_to_musb(&pdev->dev);
2445
2446 if (musb->clock) {
2447 if (musb->set_clock)
2448 musb->set_clock(musb->clock, 1);
2449 else
2450 clk_enable(musb->clock);
2451 }
2452
2453 musb_restore_context(musb);
2454
2455 /* for static cmos like DaVinci, register values were preserved
2456 * unless for some reason the whole soc powered down or the USB
2457 * module got reset through the PSC (vs just being disabled).
2458 */
2459 return 0;
2460 }
2461
2462 static const struct dev_pm_ops musb_dev_pm_ops = {
2463 .suspend = musb_suspend,
2464 .resume_noirq = musb_resume_noirq,
2465 };
2466
2467 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2468 #else
2469 #define MUSB_DEV_PM_OPS NULL
2470 #endif
2471
2472 static struct platform_driver musb_driver = {
2473 .driver = {
2474 .name = (char *)musb_driver_name,
2475 .bus = &platform_bus_type,
2476 .owner = THIS_MODULE,
2477 .pm = MUSB_DEV_PM_OPS,
2478 },
2479 .remove = __exit_p(musb_remove),
2480 .shutdown = musb_shutdown,
2481 };
2482
2483 /*-------------------------------------------------------------------------*/
2484
2485 static int __init musb_init(void)
2486 {
2487 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2488 if (usb_disabled())
2489 return 0;
2490 #endif
2491
2492 pr_info("%s: version " MUSB_VERSION ", "
2493 #ifdef CONFIG_MUSB_PIO_ONLY
2494 "pio"
2495 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2496 "cppi-dma"
2497 #elif defined(CONFIG_USB_INVENTRA_DMA)
2498 "musb-dma"
2499 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2500 "tusb-omap-dma"
2501 #else
2502 "?dma?"
2503 #endif
2504 ", "
2505 #ifdef CONFIG_USB_MUSB_OTG
2506 "otg (peripheral+host)"
2507 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2508 "peripheral"
2509 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2510 "host"
2511 #endif
2512 ", debug=%d\n",
2513 musb_driver_name, musb_debug);
2514 return platform_driver_probe(&musb_driver, musb_probe);
2515 }
2516
2517 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2518 * and before usb gadget and host-side drivers start to register
2519 */
2520 fs_initcall(musb_init);
2521
2522 static void __exit musb_cleanup(void)
2523 {
2524 platform_driver_unregister(&musb_driver);
2525 }
2526 module_exit(musb_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree