include/linux/i2c/twl.h

   1 /*
   2  * twl4030.h - header for TWL4030 PM and audio CODEC device
   3  *
   4  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   5  *
   6  * Based on tlv320aic23.c:
   7  * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  */
  24
  25 #ifndef __TWL_H_
  26 #define __TWL_H_
  27
  28 #include <linux/types.h>
  29 #include <linux/input/matrix_keypad.h>
  30
  31 /*
  32  * Using the twl4030 core we address registers using a pair
  33  *      { module id, relative register offset }
  34  * which that core then maps to the relevant
  35  *      { i2c slave, absolute register address }
  36  *
  37  * The module IDs are meaningful only to the twl4030 core code,
  38  * which uses them as array indices to look up the first register
  39  * address each module uses within a given i2c slave.
  40  */
  41
  42 /* Slave 0 (i2c address 0x48) */
  43 #define TWL4030_MODULE_USB              0x00
  44
  45 /* Slave 1 (i2c address 0x49) */
  46 #define TWL4030_MODULE_AUDIO_VOICE      0x01
  47 #define TWL4030_MODULE_GPIO             0x02
  48 #define TWL4030_MODULE_INTBR            0x03
  49 #define TWL4030_MODULE_PIH              0x04
  50 #define TWL4030_MODULE_TEST             0x05
  51
  52 /* Slave 2 (i2c address 0x4a) */
  53 #define TWL4030_MODULE_KEYPAD           0x06
  54 #define TWL4030_MODULE_MADC             0x07
  55 #define TWL4030_MODULE_INTERRUPTS       0x08
  56 #define TWL4030_MODULE_LED              0x09
  57 #define TWL4030_MODULE_MAIN_CHARGE      0x0A
  58 #define TWL4030_MODULE_PRECHARGE        0x0B
  59 #define TWL4030_MODULE_PWM0             0x0C
  60 #define TWL4030_MODULE_PWM1             0x0D
  61 #define TWL4030_MODULE_PWMA             0x0E
  62 #define TWL4030_MODULE_PWMB             0x0F
  63
  64 #define TWL5031_MODULE_ACCESSORY        0x10
  65 #define TWL5031_MODULE_INTERRUPTS       0x11
  66
  67 /* Slave 3 (i2c address 0x4b) */
  68 #define TWL4030_MODULE_BACKUP           0x12
  69 #define TWL4030_MODULE_INT              0x13
  70 #define TWL4030_MODULE_PM_MASTER        0x14
  71 #define TWL4030_MODULE_PM_RECEIVER      0x15
  72 #define TWL4030_MODULE_RTC              0x16
  73 #define TWL4030_MODULE_SECURED_REG      0x17
  74
  75 #define TWL_MODULE_USB          TWL4030_MODULE_USB
  76 #define TWL_MODULE_AUDIO_VOICE  TWL4030_MODULE_AUDIO_VOICE
  77 #define TWL_MODULE_PIH          TWL4030_MODULE_PIH
  78 #define TWL_MODULE_MADC         TWL4030_MODULE_MADC
  79 #define TWL_MODULE_MAIN_CHARGE  TWL4030_MODULE_MAIN_CHARGE
  80 #define TWL_MODULE_PM_MASTER    TWL4030_MODULE_PM_MASTER
  81 #define TWL_MODULE_PM_RECEIVER  TWL4030_MODULE_PM_RECEIVER
  82 #define TWL_MODULE_RTC          TWL4030_MODULE_RTC
  83 #define TWL_MODULE_PWM          TWL4030_MODULE_PWM0
  84
  85 #define TWL6030_MODULE_ID0      0x0D
  86 #define TWL6030_MODULE_ID1      0x0E
  87 #define TWL6030_MODULE_ID2      0x0F
  88
  89 #define GPIO_INTR_OFFSET        0
  90 #define KEYPAD_INTR_OFFSET      1
  91 #define BCI_INTR_OFFSET         2
  92 #define MADC_INTR_OFFSET        3
  93 #define USB_INTR_OFFSET         4
  94 #define BCI_PRES_INTR_OFFSET    9
  95 #define USB_PRES_INTR_OFFSET    10
  96 #define RTC_INTR_OFFSET         11
  97
  98 /*
  99  * Offset from TWL6030_IRQ_BASE / pdata->irq_base
 100  */
 101 #define PWR_INTR_OFFSET         0
 102 #define HOTDIE_INTR_OFFSET      12
 103 #define SMPSLDO_INTR_OFFSET     13
 104 #define BATDETECT_INTR_OFFSET   14
 105 #define SIMDETECT_INTR_OFFSET   15
 106 #define MMCDETECT_INTR_OFFSET   16
 107 #define GASGAUGE_INTR_OFFSET    17
 108 #define USBOTG_INTR_OFFSET      4
 109 #define CHARGER_INTR_OFFSET     2
 110 #define RSV_INTR_OFFSET         0
 111
 112 /* INT register offsets */
 113 #define REG_INT_STS_A                   0x00
 114 #define REG_INT_STS_B                   0x01
 115 #define REG_INT_STS_C                   0x02
 116
 117 #define REG_INT_MSK_LINE_A              0x03
 118 #define REG_INT_MSK_LINE_B              0x04
 119 #define REG_INT_MSK_LINE_C              0x05
 120
 121 #define REG_INT_MSK_STS_A               0x06
 122 #define REG_INT_MSK_STS_B               0x07
 123 #define REG_INT_MSK_STS_C               0x08
 124
 125 /* MASK INT REG GROUP A */
 126 #define TWL6030_PWR_INT_MASK            0x07
 127 #define TWL6030_RTC_INT_MASK            0x18
 128 #define TWL6030_HOTDIE_INT_MASK         0x20
 129 #define TWL6030_SMPSLDOA_INT_MASK       0xC0
 130
 131 /* MASK INT REG GROUP B */
 132 #define TWL6030_SMPSLDOB_INT_MASK       0x01
 133 #define TWL6030_BATDETECT_INT_MASK      0x02
 134 #define TWL6030_SIMDETECT_INT_MASK      0x04
 135 #define TWL6030_MMCDETECT_INT_MASK      0x08
 136 #define TWL6030_GPADC_INT_MASK          0x60
 137 #define TWL6030_GASGAUGE_INT_MASK       0x80
 138
 139 /* MASK INT REG GROUP C */
 140 #define TWL6030_USBOTG_INT_MASK         0x0F
 141 #define TWL6030_CHARGER_CTRL_INT_MASK   0x10
 142 #define TWL6030_CHARGER_FAULT_INT_MASK  0x60
 143
 144
 145 #define TWL4030_CLASS_ID                0x4030
 146 #define TWL6030_CLASS_ID                0x6030
 147 unsigned int twl_rev(void);
 148 #define GET_TWL_REV (twl_rev())
 149 #define TWL_CLASS_IS(class, id)                 \
 150 static inline int twl_class_is_ ##class(void)   \
 151 {                                               \
 152         return ((id) == (GET_TWL_REV)) ? 1 : 0; \
 153 }
 154
 155 TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
 156 TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
 157
 158 /*
 159  * Read and write single 8-bit registers
 160  */
 161 int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
 162 int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
 163
 164 /*
 165  * Read and write several 8-bit registers at once.
 166  *
 167  * IMPORTANT:  For twl_i2c_write(), allocate num_bytes + 1
 168  * for the value, and populate your data starting at offset 1.
 169  */
 170 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
 171 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
 172
 173 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
 174 int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
 175
 176 /*----------------------------------------------------------------------*/
 177
 178 /*
 179  * NOTE:  at up to 1024 registers, this is a big chip.
 180  *
 181  * Avoid putting register declarations in this file, instead of into
 182  * a driver-private file, unless some of the registers in a block
 183  * need to be shared with other drivers.  One example is blocks that
 184  * have Secondary IRQ Handler (SIH) registers.
 185  */
 186
 187 #define TWL4030_SIH_CTRL_EXCLEN_MASK    BIT(0)
 188 #define TWL4030_SIH_CTRL_PENDDIS_MASK   BIT(1)
 189 #define TWL4030_SIH_CTRL_COR_MASK       BIT(2)
 190
 191 /*----------------------------------------------------------------------*/
 192
 193 /*
 194  * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
 195  */
 196
 197 #define REG_GPIODATAIN1                 0x0
 198 #define REG_GPIODATAIN2                 0x1
 199 #define REG_GPIODATAIN3                 0x2
 200 #define REG_GPIODATADIR1                0x3
 201 #define REG_GPIODATADIR2                0x4
 202 #define REG_GPIODATADIR3                0x5
 203 #define REG_GPIODATAOUT1                0x6
 204 #define REG_GPIODATAOUT2                0x7
 205 #define REG_GPIODATAOUT3                0x8
 206 #define REG_CLEARGPIODATAOUT1           0x9
 207 #define REG_CLEARGPIODATAOUT2           0xA
 208 #define REG_CLEARGPIODATAOUT3           0xB
 209 #define REG_SETGPIODATAOUT1             0xC
 210 #define REG_SETGPIODATAOUT2             0xD
 211 #define REG_SETGPIODATAOUT3             0xE
 212 #define REG_GPIO_DEBEN1                 0xF
 213 #define REG_GPIO_DEBEN2                 0x10
 214 #define REG_GPIO_DEBEN3                 0x11
 215 #define REG_GPIO_CTRL                   0x12
 216 #define REG_GPIOPUPDCTR1                0x13
 217 #define REG_GPIOPUPDCTR2                0x14
 218 #define REG_GPIOPUPDCTR3                0x15
 219 #define REG_GPIOPUPDCTR4                0x16
 220 #define REG_GPIOPUPDCTR5                0x17
 221 #define REG_GPIO_ISR1A                  0x19
 222 #define REG_GPIO_ISR2A                  0x1A
 223 #define REG_GPIO_ISR3A                  0x1B
 224 #define REG_GPIO_IMR1A                  0x1C
 225 #define REG_GPIO_IMR2A                  0x1D
 226 #define REG_GPIO_IMR3A                  0x1E
 227 #define REG_GPIO_ISR1B                  0x1F
 228 #define REG_GPIO_ISR2B                  0x20
 229 #define REG_GPIO_ISR3B                  0x21
 230 #define REG_GPIO_IMR1B                  0x22
 231 #define REG_GPIO_IMR2B                  0x23
 232 #define REG_GPIO_IMR3B                  0x24
 233 #define REG_GPIO_EDR1                   0x28
 234 #define REG_GPIO_EDR2                   0x29
 235 #define REG_GPIO_EDR3                   0x2A
 236 #define REG_GPIO_EDR4                   0x2B
 237 #define REG_GPIO_EDR5                   0x2C
 238 #define REG_GPIO_SIH_CTRL               0x2D
 239
 240 /* Up to 18 signals are available as GPIOs, when their
 241  * pins are not assigned to another use (such as ULPI/USB).
 242  */
 243 #define TWL4030_GPIO_MAX                18
 244
 245 /*----------------------------------------------------------------------*/
 246
 247 /*Interface Bit Register (INTBR) offsets
 248  *(Use TWL_4030_MODULE_INTBR)
 249  */
 250
 251 #define REG_GPPUPDCTR1                  0x0F
 252
 253 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
 254
 255 #define I2C_SCL_CTRL_PU                 BIT(0)
 256 #define I2C_SDA_CTRL_PU                 BIT(2)
 257 #define SR_I2C_SCL_CTRL_PU              BIT(4)
 258 #define SR_I2C_SDA_CTRL_PU              BIT(6)
 259
 260 /*----------------------------------------------------------------------*/
 261
 262 /*
 263  * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
 264  * ... SIH/interrupt only
 265  */
 266
 267 #define TWL4030_KEYPAD_KEYP_ISR1        0x11
 268 #define TWL4030_KEYPAD_KEYP_IMR1        0x12
 269 #define TWL4030_KEYPAD_KEYP_ISR2        0x13
 270 #define TWL4030_KEYPAD_KEYP_IMR2        0x14
 271 #define TWL4030_KEYPAD_KEYP_SIR         0x15    /* test register */
 272 #define TWL4030_KEYPAD_KEYP_EDR         0x16
 273 #define TWL4030_KEYPAD_KEYP_SIH_CTRL    0x17
 274
 275 /*----------------------------------------------------------------------*/
 276
 277 /*
 278  * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
 279  * ... SIH/interrupt only
 280  */
 281
 282 #define TWL4030_MADC_ISR1               0x61
 283 #define TWL4030_MADC_IMR1               0x62
 284 #define TWL4030_MADC_ISR2               0x63
 285 #define TWL4030_MADC_IMR2               0x64
 286 #define TWL4030_MADC_SIR                0x65    /* test register */
 287 #define TWL4030_MADC_EDR                0x66
 288 #define TWL4030_MADC_SIH_CTRL           0x67
 289
 290 /*----------------------------------------------------------------------*/
 291
 292 /*
 293  * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
 294  */
 295
 296 #define TWL4030_INTERRUPTS_BCIISR1A     0x0
 297 #define TWL4030_INTERRUPTS_BCIISR2A     0x1
 298 #define TWL4030_INTERRUPTS_BCIIMR1A     0x2
 299 #define TWL4030_INTERRUPTS_BCIIMR2A     0x3
 300 #define TWL4030_INTERRUPTS_BCIISR1B     0x4
 301 #define TWL4030_INTERRUPTS_BCIISR2B     0x5
 302 #define TWL4030_INTERRUPTS_BCIIMR1B     0x6
 303 #define TWL4030_INTERRUPTS_BCIIMR2B     0x7
 304 #define TWL4030_INTERRUPTS_BCISIR1      0x8     /* test register */
 305 #define TWL4030_INTERRUPTS_BCISIR2      0x9     /* test register */
 306 #define TWL4030_INTERRUPTS_BCIEDR1      0xa
 307 #define TWL4030_INTERRUPTS_BCIEDR2      0xb
 308 #define TWL4030_INTERRUPTS_BCIEDR3      0xc
 309 #define TWL4030_INTERRUPTS_BCISIHCTRL   0xd
 310
 311 /*----------------------------------------------------------------------*/
 312
 313 /*
 314  * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
 315  */
 316
 317 #define TWL4030_INT_PWR_ISR1            0x0
 318 #define TWL4030_INT_PWR_IMR1            0x1
 319 #define TWL4030_INT_PWR_ISR2            0x2
 320 #define TWL4030_INT_PWR_IMR2            0x3
 321 #define TWL4030_INT_PWR_SIR             0x4     /* test register */
 322 #define TWL4030_INT_PWR_EDR1            0x5
 323 #define TWL4030_INT_PWR_EDR2            0x6
 324 #define TWL4030_INT_PWR_SIH_CTRL        0x7
 325
 326 /*----------------------------------------------------------------------*/
 327
 328 /*
 329  * Accessory Interrupts
 330  */
 331 #define TWL5031_ACIIMR_LSB              0x05
 332 #define TWL5031_ACIIMR_MSB              0x06
 333 #define TWL5031_ACIIDR_LSB              0x07
 334 #define TWL5031_ACIIDR_MSB              0x08
 335 #define TWL5031_ACCISR1                 0x0F
 336 #define TWL5031_ACCIMR1                 0x10
 337 #define TWL5031_ACCISR2                 0x11
 338 #define TWL5031_ACCIMR2                 0x12
 339 #define TWL5031_ACCSIR                  0x13
 340 #define TWL5031_ACCEDR1                 0x14
 341 #define TWL5031_ACCSIHCTRL              0x15
 342
 343 /*----------------------------------------------------------------------*/
 344
 345 /*
 346  * Battery Charger Controller
 347  */
 348
 349 #define TWL5031_INTERRUPTS_BCIISR1      0x0
 350 #define TWL5031_INTERRUPTS_BCIIMR1      0x1
 351 #define TWL5031_INTERRUPTS_BCIISR2      0x2
 352 #define TWL5031_INTERRUPTS_BCIIMR2      0x3
 353 #define TWL5031_INTERRUPTS_BCISIR       0x4
 354 #define TWL5031_INTERRUPTS_BCIEDR1      0x5
 355 #define TWL5031_INTERRUPTS_BCIEDR2      0x6
 356 #define TWL5031_INTERRUPTS_BCISIHCTRL   0x7
 357
 358 /*----------------------------------------------------------------------*/
 359
 360 /*
 361  * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
 362  */
 363
 364 #define TWL4030_PM_MASTER_CFG_P1_TRANSITION     0x00
 365 #define TWL4030_PM_MASTER_CFG_P2_TRANSITION     0x01
 366 #define TWL4030_PM_MASTER_CFG_P3_TRANSITION     0x02
 367 #define TWL4030_PM_MASTER_CFG_P123_TRANSITION   0x03
 368 #define TWL4030_PM_MASTER_STS_BOOT              0x04
 369 #define TWL4030_PM_MASTER_CFG_BOOT              0x05
 370 #define TWL4030_PM_MASTER_SHUNDAN               0x06
 371 #define TWL4030_PM_MASTER_BOOT_BCI              0x07
 372 #define TWL4030_PM_MASTER_CFG_PWRANA1           0x08
 373 #define TWL4030_PM_MASTER_CFG_PWRANA2           0x09
 374 #define TWL4030_PM_MASTER_BACKUP_MISC_STS       0x0b
 375 #define TWL4030_PM_MASTER_BACKUP_MISC_CFG       0x0c
 376 #define TWL4030_PM_MASTER_BACKUP_MISC_TST       0x0d
 377 #define TWL4030_PM_MASTER_PROTECT_KEY           0x0e
 378 #define TWL4030_PM_MASTER_STS_HW_CONDITIONS     0x0f
 379 #define TWL4030_PM_MASTER_P1_SW_EVENTS          0x10
 380 #define TWL4030_PM_MASTER_P2_SW_EVENTS          0x11
 381 #define TWL4030_PM_MASTER_P3_SW_EVENTS          0x12
 382 #define TWL4030_PM_MASTER_STS_P123_STATE        0x13
 383 #define TWL4030_PM_MASTER_PB_CFG                0x14
 384 #define TWL4030_PM_MASTER_PB_WORD_MSB           0x15
 385 #define TWL4030_PM_MASTER_PB_WORD_LSB           0x16
 386 #define TWL4030_PM_MASTER_SEQ_ADD_W2P           0x1c
 387 #define TWL4030_PM_MASTER_SEQ_ADD_P2A           0x1d
 388 #define TWL4030_PM_MASTER_SEQ_ADD_A2W           0x1e
 389 #define TWL4030_PM_MASTER_SEQ_ADD_A2S           0x1f
 390 #define TWL4030_PM_MASTER_SEQ_ADD_S2A12         0x20
 391 #define TWL4030_PM_MASTER_SEQ_ADD_S2A3          0x21
 392 #define TWL4030_PM_MASTER_SEQ_ADD_WARM          0x22
 393 #define TWL4030_PM_MASTER_MEMORY_ADDRESS        0x23
 394 #define TWL4030_PM_MASTER_MEMORY_DATA           0x24
 395
 396 #define TWL4030_PM_MASTER_KEY_CFG1              0xc0
 397 #define TWL4030_PM_MASTER_KEY_CFG2              0x0c
 398
 399 #define TWL4030_PM_MASTER_KEY_TST1              0xe0
 400 #define TWL4030_PM_MASTER_KEY_TST2              0x0e
 401
 402 #define TWL4030_PM_MASTER_GLOBAL_TST            0xb6
 403
 404 /*----------------------------------------------------------------------*/
 405
 406 /* Power bus message definitions */
 407
 408 /* The TWL4030/5030 splits its power-management resources (the various
 409  * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
 410  * P3. These groups can then be configured to transition between sleep, wait-on
 411  * and active states by sending messages to the power bus.  See Section 5.4.2
 412  * Power Resources of TWL4030 TRM
 413  */
 414
 415 /* Processor groups */
 416 #define DEV_GRP_NULL            0x0
 417 #define DEV_GRP_P1              0x1     /* P1: all OMAP devices */
 418 #define DEV_GRP_P2              0x2     /* P2: all Modem devices */
 419 #define DEV_GRP_P3              0x4     /* P3: all peripheral devices */
 420
 421 /* Resource groups */
 422 #define RES_GRP_RES             0x0     /* Reserved */
 423 #define RES_GRP_PP              0x1     /* Power providers */
 424 #define RES_GRP_RC              0x2     /* Reset and control */
 425 #define RES_GRP_PP_RC           0x3
 426 #define RES_GRP_PR              0x4     /* Power references */
 427 #define RES_GRP_PP_PR           0x5
 428 #define RES_GRP_RC_PR           0x6
 429 #define RES_GRP_ALL             0x7     /* All resource groups */
 430
 431 #define RES_TYPE2_R0            0x0
 432
 433 #define RES_TYPE_ALL            0x7
 434
 435 /* Resource states */
 436 #define RES_STATE_WRST          0xF
 437 #define RES_STATE_ACTIVE        0xE
 438 #define RES_STATE_SLEEP         0x8
 439 #define RES_STATE_OFF           0x0
 440
 441 /* Power resources */
 442
 443 /* Power providers */
 444 #define RES_VAUX1               1
 445 #define RES_VAUX2               2
 446 #define RES_VAUX3               3
 447 #define RES_VAUX4               4
 448 #define RES_VMMC1               5
 449 #define RES_VMMC2               6
 450 #define RES_VPLL1               7
 451 #define RES_VPLL2               8
 452 #define RES_VSIM                9
 453 #define RES_VDAC                10
 454 #define RES_VINTANA1            11
 455 #define RES_VINTANA2            12
 456 #define RES_VINTDIG             13
 457 #define RES_VIO                 14
 458 #define RES_VDD1                15
 459 #define RES_VDD2                16
 460 #define RES_VUSB_1V5            17
 461 #define RES_VUSB_1V8            18
 462 #define RES_VUSB_3V1            19
 463 #define RES_VUSBCP              20
 464 #define RES_REGEN               21
 465 /* Reset and control */
 466 #define RES_NRES_PWRON          22
 467 #define RES_CLKEN               23
 468 #define RES_SYSEN               24
 469 #define RES_HFCLKOUT            25
 470 #define RES_32KCLKOUT           26
 471 #define RES_RESET               27
 472 /* Power Reference */
 473 #define RES_Main_Ref            28
 474
 475 #define TOTAL_RESOURCES         28
 476 /*
 477  * Power Bus Message Format ... these can be sent individually by Linux,
 478  * but are usually part of downloaded scripts that are run when various
 479  * power events are triggered.
 480  *
 481  *  Broadcast Message (16 Bits):
 482  *    DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
 483  *    RES_STATE[3:0]
 484  *
 485  *  Singular Message (16 Bits):
 486  *    DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
 487  */
 488
 489 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
 490         ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
 491         | (type) << 4 | (state))
 492
 493 #define MSG_SINGULAR(devgrp, id, state) \
 494         ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
 495
 496 #define MSG_BROADCAST_ALL(devgrp, state) \
 497         ((devgrp) << 5 | (state))
 498
 499 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
 500 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
 501 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
 502 /*----------------------------------------------------------------------*/
 503
 504 struct twl4030_clock_init_data {
 505         bool ck32k_lowpwr_enable;
 506 };
 507
 508 struct twl4030_bci_platform_data {
 509         int *battery_tmp_tbl;
 510         unsigned int tblsize;
 511 };
 512
 513 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
 514 struct twl4030_gpio_platform_data {
 515         int             gpio_base;
 516         unsigned        irq_base, irq_end;
 517
 518         /* package the two LED signals as output-only GPIOs? */
 519         bool            use_leds;
 520
 521         /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
 522         u8              mmc_cd;
 523
 524         /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
 525         u32             debounce;
 526
 527         /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
 528          * should be enabled.  Else, if that bit is set in "pulldowns",
 529          * that pulldown is enabled.  Don't waste power by letting any
 530          * digital inputs float...
 531          */
 532         u32             pullups;
 533         u32             pulldowns;
 534
 535         int             (*setup)(struct device *dev,
 536                                 unsigned gpio, unsigned ngpio);
 537         int             (*teardown)(struct device *dev,
 538                                 unsigned gpio, unsigned ngpio);
 539 };
 540
 541 struct twl4030_madc_platform_data {
 542         int             irq_line;
 543 };
 544
 545 /* Boards have unique mappings of {row, col} --> keycode.
 546  * Column and row are 8 bits each, but range only from 0..7.
 547  * a PERSISTENT_KEY is "always on" and never reported.
 548  */
 549 #define PERSISTENT_KEY(r, c)    KEY((r), (c), KEY_RESERVED)
 550
 551 struct twl4030_keypad_data {
 552         const struct matrix_keymap_data *keymap_data;
 553         unsigned rows;
 554         unsigned cols;
 555         bool rep;
 556 };
 557
 558 enum twl4030_usb_mode {
 559         T2_USB_MODE_ULPI = 1,
 560         T2_USB_MODE_CEA2011_3PIN = 2,
 561 };
 562
 563 struct twl4030_usb_data {
 564         enum twl4030_usb_mode   usb_mode;
 565 };
 566
 567 struct twl4030_ins {
 568         u16 pmb_message;
 569         u8 delay;
 570 };
 571
 572 struct twl4030_script {
 573         struct twl4030_ins *script;
 574         unsigned size;
 575         u8 flags;
 576 #define TWL4030_WRST_SCRIPT     (1<<0)
 577 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
 578 #define TWL4030_WAKEUP3_SCRIPT  (1<<2)
 579 #define TWL4030_SLEEP_SCRIPT    (1<<3)
 580 };
 581
 582 struct twl4030_resconfig {
 583         u8 resource;
 584         u8 devgroup;    /* Processor group that Power resource belongs to */
 585         u8 type;        /* Power resource addressed, 6 / broadcast message */
 586         u8 type2;       /* Power resource addressed, 3 / broadcast message */
 587         u8 remap_off;   /* off state remapping */
 588         u8 remap_sleep; /* sleep state remapping */
 589 };
 590
 591 struct twl4030_power_data {
 592         struct twl4030_script **scripts;
 593         unsigned num;
 594         struct twl4030_resconfig *resource_config;
 595 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
 596 };
 597
 598 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
 599 extern int twl4030_remove_script(u8 flags);
 600
 601 struct twl4030_codec_audio_data {
 602         unsigned int audio_mclk; /* not used, will be removed */
 603         unsigned int digimic_delay; /* in ms */
 604         unsigned int ramp_delay_value;
 605         unsigned int offset_cncl_path;
 606         unsigned int check_defaults:1;
 607         unsigned int reset_registers:1;
 608         unsigned int hs_extmute:1;
 609         void (*set_hs_extmute)(int mute);
 610 };
 611
 612 struct twl4030_codec_vibra_data {
 613         unsigned int    audio_mclk;
 614         unsigned int    coexist;
 615 };
 616
 617 struct twl4030_codec_data {
 618         unsigned int    audio_mclk;
 619         struct twl4030_codec_audio_data         *audio;
 620         struct twl4030_codec_vibra_data         *vibra;
 621
 622         /* twl6040 */
 623         int audpwron_gpio;      /* audio power-on gpio */
 624         int naudint_irq;        /* audio interrupt */
 625 };
 626
 627 struct twl4030_platform_data {
 628         unsigned                                irq_base, irq_end;
 629         struct twl4030_clock_init_data          *clock;
 630         struct twl4030_bci_platform_data        *bci;
 631         struct twl4030_gpio_platform_data       *gpio;
 632         struct twl4030_madc_platform_data       *madc;
 633         struct twl4030_keypad_data              *keypad;
 634         struct twl4030_usb_data                 *usb;
 635         struct twl4030_power_data               *power;
 636         struct twl4030_codec_data               *codec;
 637
 638         /* Common LDO regulators for TWL4030/TWL6030 */
 639         struct regulator_init_data              *vdac;
 640         struct regulator_init_data              *vaux1;
 641         struct regulator_init_data              *vaux2;
 642         struct regulator_init_data              *vaux3;
 643         /* TWL4030 LDO regulators */
 644         struct regulator_init_data              *vpll1;
 645         struct regulator_init_data              *vpll2;
 646         struct regulator_init_data              *vmmc1;
 647         struct regulator_init_data              *vmmc2;
 648         struct regulator_init_data              *vsim;
 649         struct regulator_init_data              *vaux4;
 650         struct regulator_init_data              *vio;
 651         struct regulator_init_data              *vdd1;
 652         struct regulator_init_data              *vdd2;
 653         struct regulator_init_data              *vintana1;
 654         struct regulator_init_data              *vintana2;
 655         struct regulator_init_data              *vintdig;
 656         /* TWL6030 LDO regulators */
 657         struct regulator_init_data              *vmmc;
 658         struct regulator_init_data              *vpp;
 659         struct regulator_init_data              *vusim;
 660         struct regulator_init_data              *vana;
 661         struct regulator_init_data              *vcxio;
 662         struct regulator_init_data              *vusb;
 663 };
 664
 665 /*----------------------------------------------------------------------*/
 666
 667 int twl4030_sih_setup(int module);
 668
 669 /* Offsets to Power Registers */
 670 #define TWL4030_VDAC_DEV_GRP            0x3B
 671 #define TWL4030_VDAC_DEDICATED          0x3E
 672 #define TWL4030_VAUX1_DEV_GRP           0x17
 673 #define TWL4030_VAUX1_DEDICATED         0x1A
 674 #define TWL4030_VAUX2_DEV_GRP           0x1B
 675 #define TWL4030_VAUX2_DEDICATED         0x1E
 676 #define TWL4030_VAUX3_DEV_GRP           0x1F
 677 #define TWL4030_VAUX3_DEDICATED         0x22
 678
 679 static inline int twl4030charger_usb_en(int enable) { return 0; }
 680
 681 /*----------------------------------------------------------------------*/
 682
 683 /* Linux-specific regulator identifiers ... for now, we only support
 684  * the LDOs, and leave the three buck converters alone.  VDD1 and VDD2
 685  * need to tie into hardware based voltage scaling (cpufreq etc), while
 686  * VIO is generally fixed.
 687  */
 688
 689 /* TWL4030 SMPS/LDO's */
 690 /* EXTERNAL dc-to-dc buck converters */
 691 #define TWL4030_REG_VDD1        0
 692 #define TWL4030_REG_VDD2        1
 693 #define TWL4030_REG_VIO         2
 694
 695 /* EXTERNAL LDOs */
 696 #define TWL4030_REG_VDAC        3
 697 #define TWL4030_REG_VPLL1       4
 698 #define TWL4030_REG_VPLL2       5       /* not on all chips */
 699 #define TWL4030_REG_VMMC1       6
 700 #define TWL4030_REG_VMMC2       7       /* not on all chips */
 701 #define TWL4030_REG_VSIM        8       /* not on all chips */
 702 #define TWL4030_REG_VAUX1       9       /* not on all chips */
 703 #define TWL4030_REG_VAUX2_4030  10      /* (twl4030-specific) */
 704 #define TWL4030_REG_VAUX2       11      /* (twl5030 and newer) */
 705 #define TWL4030_REG_VAUX3       12      /* not on all chips */
 706 #define TWL4030_REG_VAUX4       13      /* not on all chips */
 707
 708 /* INTERNAL LDOs */
 709 #define TWL4030_REG_VINTANA1    14
 710 #define TWL4030_REG_VINTANA2    15
 711 #define TWL4030_REG_VINTDIG     16
 712 #define TWL4030_REG_VUSB1V5     17
 713 #define TWL4030_REG_VUSB1V8     18
 714 #define TWL4030_REG_VUSB3V1     19
 715
 716 /* TWL6030 SMPS/LDO's */
 717 /* EXTERNAL dc-to-dc buck convertor controllable via SR */
 718 #define TWL6030_REG_VDD1        30
 719 #define TWL6030_REG_VDD2        31
 720 #define TWL6030_REG_VDD3        32
 721
 722 /* Non SR compliant dc-to-dc buck convertors */
 723 #define TWL6030_REG_VMEM        33
 724 #define TWL6030_REG_V2V1        34
 725 #define TWL6030_REG_V1V29       35
 726 #define TWL6030_REG_V1V8        36
 727
 728 /* EXTERNAL LDOs */
 729 #define TWL6030_REG_VAUX1_6030  37
 730 #define TWL6030_REG_VAUX2_6030  38
 731 #define TWL6030_REG_VAUX3_6030  39
 732 #define TWL6030_REG_VMMC        40
 733 #define TWL6030_REG_VPP         41
 734 #define TWL6030_REG_VUSIM       42
 735 #define TWL6030_REG_VANA        43
 736 #define TWL6030_REG_VCXIO       44
 737 #define TWL6030_REG_VDAC        45
 738 #define TWL6030_REG_VUSB        46
 739
 740 /* INTERNAL LDOs */
 741 #define TWL6030_REG_VRTC        47
 742
 743 #endif /* End of __TWL4030_H */