| blob | fdfaf0f618f14cb9b8a934fb2868ce256fe16c31 |
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
72 /******************\
73 * Internal defines *
74 \******************/
76 /* Module info */
85 /* Known PCI ids */
106 };
109 /* Known SREVs */
147 };
188 /* XR missing */
189 };
191 /*
192 * Prototypes - PCI stack related functions
193 */
197 #ifdef CONFIG_PM
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
203 #else
204 #define ATH5K_PM_OPS NULL
213 };
217 /*
218 * Prototypes - MAC 802.11 stack related functions
219 */
237 u64 multicast);
254 u32 changes);
277 };
279 /*
280 * Prototypes - Internal functions
281 */
282 /* Attach detach */
287 /* Channel/mode setup */
300 /* Descriptor setup */
305 /* Buffers setup */
313 {
318 PCI_DMA_TODEVICE);
321 }
325 {
333 PCI_DMA_FROMDEVICE);
336 }
339 /* Queues setup */
348 /* Rx handling */
356 /* Tx handling */
360 /* Beacon handling */
369 {
376 }
378 /* Interrupt handling */
387 /*
388 * Module init/exit functions
389 */
390 static int __init
392 {
401 }
404 }
406 static void __exit
408 {
412 }
418 /********************\
419 * PCI Initialization *
420 \********************/
424 {
438 }
439 }
442 }
444 {
447 }
450 {
453 }
458 };
460 static int __devinit
463 {
469 u8 csz;
475 }
477 /* XXX 32-bit addressing only */
482 }
484 /*
485 * Cache line size is used to size and align various
486 * structures used to communicate with the hardware.
487 */
490 /*
491 * Linux 2.4.18 (at least) writes the cache line size
492 * register as a 16-bit wide register which is wrong.
493 * We must have this setup properly for rx buffer
494 * DMA to work so force a reasonable value here if it
495 * comes up zero.
496 */
499 }
500 /*
501 * The default setting of latency timer yields poor results,
502 * set it to the value used by other systems. It may be worth
503 * tweaking this setting more.
504 */
507 /* Enable bus mastering */
510 /*
511 * Disable the RETRY_TIMEOUT register (0x41) to keep
512 * PCI Tx retries from interfering with C3 CPU state.
513 */
520 }
527 }
529 /*
530 * Allocate hw (mac80211 main struct)
531 * and hw->priv (driver private data)
532 */
538 }
542 /* Initialize driver private data */
545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
546 IEEE80211_HW_SIGNAL_DBM |
547 IEEE80211_HW_NOISE_DBM;
563 /*
564 * Mark the device as detached to avoid processing
565 * interrupts until setup is complete.
566 */
577 /* Set private data */
580 /* Setup interrupt handler */
585 }
587 /*If we passed the test malloc a ath5k_hw struct*/
593 }
603 /* Initialize device */
607 }
609 /* set up multi-rate retry capabilities */
613 }
615 /* Finish private driver data initialization */
626 /* Single chip radio (!RF5111) */
629 /* No 5GHz support -> report 2GHz radio */
636 /* No 2GHz support (5110 and some
637 * 5Ghz only cards) -> report 5Ghz radio */
644 /* Multiband radio */
651 }
652 }
653 /* Multi chip radio (RF5111 - RF2111) ->
654 * report both 2GHz/5GHz radios */
665 }
666 }
669 /* ready to process interrupts */
673 err_ah:
675 err_irq:
677 err_free_ah:
679 err_free:
681 err_map:
683 err_reg:
685 err_dis:
687 err:
689 }
691 static void __devexit
693 {
706 }
708 #ifdef CONFIG_PM
710 {
716 }
719 {
724 /*
725 * Suspend/Resume resets the PCI configuration space, so we have to
726 * re-disable the RETRY_TIMEOUT register (0x41) to keep
727 * PCI Tx retries from interfering with C3 CPU state
728 */
733 }
737 /***********************\
738 * Driver Initialization *
739 \***********************/
742 {
748 }
750 static int
752 {
761 /*
762 * Check if the MAC has multi-rate retry support.
763 * We do this by trying to setup a fake extended
764 * descriptor. MAC's that don't have support will
765 * return false w/o doing anything. MAC's that do
766 * support it will return true w/o doing anything.
767 */
774 /*
775 * Collect the channel list. The 802.11 layer
776 * is resposible for filtering this list based
777 * on settings like the phy mode and regulatory
778 * domain restrictions.
779 */
784 }
786 /* NB: setup here so ath5k_rate_update is happy */
789 else
792 /*
793 * Allocate tx+rx descriptors and populate the lists.
794 */
799 }
801 /*
802 * Allocate hardware transmit queues: one queue for
803 * beacon frames and one data queue for each QoS
804 * priority. Note that hw functions handle reseting
805 * these queues at the needed time.
806 */
811 }
818 }
825 }
838 }
841 /* All MAC address bits matter for ACKs */
850 }
856 }
864 err_queues:
866 err_bhal:
868 err_desc:
870 err:
872 }
874 static void
876 {
879 /*
880 * NB: the order of these is important:
881 * o call the 802.11 layer before detaching ath5k_hw to
882 * insure callbacks into the driver to delete global
883 * key cache entries can be handled
884 * o reclaim the tx queue data structures after calling
885 * the 802.11 layer as we'll get called back to reclaim
886 * node state and potentially want to use them
887 * o to cleanup the tx queues the hal is called, so detach
888 * it last
889 * XXX: ??? detach ath5k_hw ???
890 * Other than that, it's straightforward...
891 */
898 /*
899 * NB: can't reclaim these until after ieee80211_ifdetach
900 * returns because we'll get called back to reclaim node
901 * state and potentially want to use them.
902 */
903 }
908 /********************\
909 * Channel/mode setup *
910 \********************/
912 /*
913 * Convert IEEE channel number to MHz frequency.
914 */
917 {
920 else
922 }
924 /*
925 * Returns true for the channel numbers used without all_channels modparam.
926 */
928 {
930 /* UNII 1,2 */
932 /* midband */
934 /* UNII-3 */
936 }
938 static unsigned int
943 {
952 /* 1..220, but 2GHz frequencies are filtered by check_channel */
965 }
971 /* Check if channel is supported by the chipset */
978 /* Write channel info and increment counter */
994 }
996 count++;
997 max--;
998 }
1001 }
1003 static void
1005 {
1006 u8 i;
1015 }
1016 }
1018 static int
1020 {
1030 /* 2GHz band */
1036 /* G mode */
1049 /* B mode */
1054 /* 5211 only supports B rates and uses 4bit rate codes
1055 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1056 * fix them up here:
1057 */
1064 }
1065 }
1074 }
1077 /* 5GHz band, A mode */
1092 }
1098 }
1100 /*
1101 * Set/change channels. We always reset the chip.
1102 * To accomplish this we must first cleanup any pending DMA,
1103 * then restart stuff after a la ath5k_init.
1104 *
1105 * Called with sc->lock.
1106 */
1107 static int
1109 {
1113 /*
1114 * To switch channels clear any pending DMA operations;
1115 * wait long enough for the RX fifo to drain, reset the
1116 * hardware at the new frequency, and then re-enable
1117 * the relevant bits of the h/w.
1118 */
1120 }
1122 static void
1124 {
1131 }
1132 }
1134 static void
1136 {
1138 u32 rfilt;
1142 /* configure rx filter */
1149 /* configure operational mode */
1153 }
1157 {
1160 /* return base rate on errors */
1170 }
1172 /***************\
1173 * Buffers setup *
1174 \***************/
1176 static
1178 {
1182 /*
1183 * Allocate buffer with headroom_needed space for the
1184 * fake physical layer header at the start.
1185 */
1188 GFP_ATOMIC);
1194 }
1198 PCI_DMA_FROMDEVICE);
1203 }
1205 }
1207 static int
1209 {
1219 }
1221 /*
1222 * Setup descriptors. For receive we always terminate
1223 * the descriptor list with a self-linked entry so we'll
1224 * not get overrun under high load (as can happen with a
1225 * 5212 when ANI processing enables PHY error frames).
1226 *
1227 * To insure the last descriptor is self-linked we create
1228 * each descriptor as self-linked and add it to the end. As
1229 * each additional descriptor is added the previous self-linked
1230 * entry is ``fixed'' naturally. This should be safe even
1231 * if DMA is happening. When processing RX interrupts we
1232 * never remove/process the last, self-linked, entry on the
1233 * descriptor list. This insures the hardware always has
1234 * someplace to write a new frame.
1235 */
1247 }
1249 static int
1252 {
1261 u16 hw_rate;
1264 u8 rc_flags;
1268 /* XXX endianness */
1270 PCI_DMA_TODEVICE);
1283 /* FIXME: If we are in g mode and rate is a CCK rate
1284 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1285 * from tx power (value is in dB units already) */
1289 }
1295 }
1301 }
1305 hw_rate,
1320 }
1344 err_unmap:
1347 }
1349 /*******************\
1350 * Descriptors setup *
1351 \*******************/
1353 static int
1355 {
1358 dma_addr_t da;
1362 /* allocate descriptors */
1370 }
1382 }
1390 }
1399 }
1401 /* beacon buffer */
1407 err_free:
1409 err:
1412 }
1414 static void
1416 {
1425 /* Free memory associated with all descriptors */
1430 }
1436 /**************\
1437 * Queues setup *
1438 \**************/
1443 {
1451 };
1454 /*
1455 * Enable interrupts only for EOL and DESC conditions.
1456 * We mark tx descriptors to receive a DESC interrupt
1457 * when a tx queue gets deep; otherwise waiting for the
1458 * EOL to reap descriptors. Note that this is done to
1459 * reduce interrupt load and this only defers reaping
1460 * descriptors, never transmitting frames. Aside from
1461 * reducing interrupts this also permits more concurrency.
1462 * The only potential downside is if the tx queue backs
1463 * up in which case the top half of the kernel may backup
1464 * due to a lack of tx descriptors.
1465 */
1467 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1470 /*
1471 * NB: don't print a message, this happens
1472 * normally on parts with too few tx queues
1473 */
1475 }
1481 }
1489 }
1491 }
1493 static int
1495 {
1500 /* NB: for dynamic turbo, don't enable any other interrupts */
1502 };
1505 }
1507 static int
1509 {
1519 /*
1520 * Always burst out beacon and CAB traffic
1521 * (aifs = cwmin = cwmax = 0)
1522 */
1527 /*
1528 * Adhoc mode; backoff between 0 and (2 * cw_min).
1529 */
1533 }
1544 }
1547 }
1549 static void
1551 {
1554 /*
1555 * NB: this assumes output has been stopped and
1556 * we do not need to block ath5k_tx_tasklet
1557 */
1569 }
1572 }
1574 /*
1575 * Drain the transmit queues and reclaim resources.
1576 */
1577 static void
1579 {
1583 /* XXX return value */
1585 /* don't touch the hardware if marked invalid */
1598 }
1599 }
1605 }
1607 static void
1609 {
1617 }
1618 }
1623 /*************\
1624 * RX Handling *
1625 \*************/
1627 /*
1628 * Enable the receive h/w following a reset.
1629 */
1630 static int
1632 {
1650 }
1651 }
1661 err:
1663 }
1665 /*
1666 * Disable the receive h/w in preparation for a reset.
1667 */
1668 static void
1670 {
1680 }
1682 static unsigned int
1685 {
1695 /* Apparently when a default key is used to decrypt the packet
1696 the hw does not set the index used to decrypt. In such cases
1697 get the index from the packet. */
1706 }
1709 }
1712 static void
1715 {
1718 u32 hw_tu;
1724 /*
1725 * Received an IBSS beacon with the same BSSID. Hardware *must*
1726 * have updated the local TSF. We have to work around various
1727 * hardware bugs, though...
1728 */
1740 /*
1741 * Sometimes the HW will give us a wrong tstamp in the rx
1742 * status, causing the timestamp extension to go wrong.
1743 * (This seems to happen especially with beacon frames bigger
1744 * than 78 byte (incl. FCS))
1745 * But we know that the receive timestamp must be later than the
1746 * timestamp of the beacon since HW must have synced to that.
1747 *
1748 * NOTE: here we assume mactime to be after the frame was
1749 * received, not like mac80211 which defines it at the start.
1750 */
1757 }
1759 /*
1760 * Local TSF might have moved higher than our beacon timers,
1761 * in that case we have to update them to continue sending
1762 * beacons. This also takes care of synchronizing beacon sending
1763 * times with other stations.
1764 */
1767 }
1768 }
1770 static void
1772 {
1776 dma_addr_t next_skb_addr;
1791 }
1800 /* bail if HW is still using self-linked descriptor */
1811 }
1816 }
1822 /*
1823 * Decrypt error. If the error occurred
1824 * because there was no hardware key, then
1825 * let the frame through so the upper layers
1826 * can process it. This is necessary for 5210
1827 * parts which have no way to setup a ``clear''
1828 * key cache entry.
1829 *
1830 * XXX do key cache faulting
1831 */
1835 }
1839 }
1841 /* let crypto-error packets fall through in MNTR */
1846 }
1847 accept:
1850 /*
1851 * If we can't replace bf->skb with a new skb under memory
1852 * pressure, just skip this packet
1853 */
1858 PCI_DMA_FROMDEVICE);
1861 /* The MAC header is padded to have 32-bit boundary if the
1862 * packet payload is non-zero. The general calculation for
1863 * padsize would take into account odd header lengths:
1864 * padsize = (4 - hdrlen % 4) % 4; However, since only
1865 * even-length headers are used, padding can only be 0 or 2
1866 * bytes and we can optimize this a bit. In addition, we must
1867 * not try to remove padding from short control frames that do
1868 * not have payload. */
1874 }
1877 /*
1878 * always extend the mac timestamp, since this information is
1879 * also needed for proper IBSS merging.
1880 *
1881 * XXX: it might be too late to do it here, since rs_tstamp is
1882 * 15bit only. that means TSF extension has to be done within
1883 * 32768usec (about 32ms). it might be necessary to move this to
1884 * the interrupt handler, like it is done in madwifi.
1885 *
1886 * Unfortunately we don't know when the hardware takes the rx
1887 * timestamp (beginning of phy frame, data frame, end of rx?).
1888 * The only thing we know is that it is hardware specific...
1889 * On AR5213 it seems the rx timestamp is at the end of the
1890 * frame, but i'm not sure.
1891 *
1892 * NOTE: mac80211 defines mactime at the beginning of the first
1893 * data symbol. Since we don't have any time references it's
1894 * impossible to comply to that. This affects IBSS merge only
1895 * right now, so it's not too bad...
1896 */
1916 /* check beacons in IBSS mode */
1924 next:
1927 unlock:
1929 }
1934 /*************\
1935 * TX Handling *
1936 \*************/
1938 static void
1940 {
1959 }
1966 PCI_DMA_TODEVICE);
1979 }
1980 }
1982 /* count the successful attempt as well */
1992 }
2002 }
2008 }
2010 static void
2012 {
2019 }
2022 /*****************\
2023 * Beacon handling *
2024 \*****************/
2026 /*
2027 * Setup the beacon frame for transmit.
2028 */
2029 static int
2031 {
2037 u8 antenna;
2038 u32 flags;
2041 PCI_DMA_TODEVICE);
2048 }
2060 /*
2061 * If we use multiple antennas on AP and use
2062 * the Sectored AP scenario, switch antenna every
2063 * 4 beacons to make sure everybody hears our AP.
2064 * When a client tries to associate, hw will keep
2065 * track of the tx antenna to be used for this client
2066 * automaticaly, based on ACKed packets.
2067 *
2068 * Note: AP still listens and transmits RTS on the
2069 * default antenna which is supposed to be an omni.
2070 *
2071 * Note2: On sectored scenarios it's possible to have
2072 * multiple antennas (1omni -the default- and 14 sectors)
2073 * so if we choose to actually support this mode we need
2074 * to allow user to set how many antennas we have and tweak
2075 * the code below to send beacons on all of them.
2076 */
2081 /* FIXME: If we are in g mode and rate is a CCK rate
2082 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2083 * from tx power (value is in dB units already) */
2095 err_unmap:
2098 }
2100 /*
2101 * Transmit a beacon frame at SWBA. Dynamic updates to the
2102 * frame contents are done as needed and the slot time is
2103 * also adjusted based on current state.
2104 *
2105 * This is called from software irq context (beacontq or restq
2106 * tasklets) or user context from ath5k_beacon_config.
2107 */
2108 static void
2110 {
2121 }
2122 /*
2123 * Check if the previous beacon has gone out. If
2124 * not don't don't try to post another, skip this
2125 * period and wait for the next. Missed beacons
2126 * indicate a problem and should not occur. If we
2127 * miss too many consecutive beacons reset the device.
2128 */
2138 }
2140 }
2146 }
2148 /*
2149 * Stop any current dma and put the new frame on the queue.
2150 * This should never fail since we check above that no frames
2151 * are still pending on the queue.
2152 */
2155 /* NB: hw still stops DMA, so proceed */
2156 }
2158 /* refresh the beacon for AP mode */
2171 }
2174 }
2177 /**
2178 * ath5k_beacon_update_timers - update beacon timers
2179 *
2180 * @sc: struct ath5k_softc pointer we are operating on
2181 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2182 * beacon timer update based on the current HW TSF.
2183 *
2184 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2185 * of a received beacon or the current local hardware TSF and write it to the
2186 * beacon timer registers.
2187 *
2188 * This is called in a variety of situations, e.g. when a beacon is received,
2189 * when a TSF update has been detected, but also when an new IBSS is created or
2190 * when we otherwise know we have to update the timers, but we keep it in this
2191 * function to have it all together in one place.
2192 */
2193 static void
2195 {
2198 u64 hw_tsf;
2204 /* beacon TSF converted to TU */
2207 /* current TSF converted to TU */
2211 #define FUDGE 3
2212 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2214 /*
2215 * no beacons received, called internally.
2216 * just need to refresh timers based on HW TSF.
2217 */
2220 /*
2221 * no beacon received, probably called by ath5k_reset_tsf().
2222 * reset TSF to start with 0.
2223 */
2227 /*
2228 * beacon received, SW merge happend but HW TSF not yet updated.
2229 * not possible to reconfigure timers yet, but next time we
2230 * receive a beacon with the same BSSID, the hardware will
2231 * automatically update the TSF and then we need to reconfigure
2232 * the timers.
2233 */
2238 /*
2239 * most important case for beacon synchronization between STA.
2240 *
2241 * beacon received and HW TSF has been already updated by HW.
2242 * update next TBTT based on the TSF of the beacon, but make
2243 * sure it is ahead of our local TSF timer.
2244 */
2246 }
2247 #undef FUDGE
2254 /*
2255 * debugging output last in order to preserve the time critical aspect
2256 * of this function
2257 */
2264 else
2276 }
2279 /**
2280 * ath5k_beacon_config - Configure the beacon queues and interrupts
2281 *
2282 * @sc: struct ath5k_softc pointer we are operating on
2283 *
2284 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2285 * interrupts to detect TSF updates only.
2286 */
2287 static void
2289 {
2298 /*
2299 * In IBSS mode we use a self-linked tx descriptor and let the
2300 * hardware send the beacons automatically. We have to load it
2301 * only once here.
2302 * We use the SWBA interrupt only to keep track of the beacon
2303 * timers in order to detect automatic TSF updates.
2304 */
2316 }
2321 }
2324 {
2327 /*
2328 * Software beacon alert--time to send a beacon.
2329 *
2330 * In IBSS mode we use this interrupt just to
2331 * keep track of the next TBTT (target beacon
2332 * transmission time) in order to detect wether
2333 * automatic TSF updates happened.
2334 */
2336 /* XXX: only if VEOL suppported */
2340 "SWBA nexttbtt: %x hw_tu: %x "
2349 }
2350 }
2353 /********************\
2354 * Interrupt handling *
2355 \********************/
2357 static int
2359 {
2367 /*
2368 * Stop anything previously setup. This is safe
2369 * no matter this is the first time through or not.
2370 */
2373 /* Set PHY calibration interval */
2376 /*
2377 * The basic interface to setting the hardware in a good
2378 * state is ``reset''. On return the hardware is known to
2379 * be powered up and with interrupts disabled. This must
2380 * be followed by initialization of the appropriate bits
2381 * and then setup of the interrupt mask.
2382 */
2394 /*
2395 * Reset the key cache since some parts do not reset the
2396 * contents on initial power up or resume from suspend.
2397 */
2401 /* Set ack to be sent at low bit-rates */
2404 done:
2408 }
2410 static int
2412 {
2418 /*
2419 * Shutdown the hardware and driver:
2420 * stop output from above
2421 * disable interrupts
2422 * turn off timers
2423 * turn off the radio
2424 * clear transmit machinery
2425 * clear receive machinery
2426 * drain and release tx queues
2427 * reclaim beacon resources
2428 * power down hardware
2429 *
2430 * Note that some of this work is not possible if the
2431 * hardware is gone (invalid).
2432 */
2439 }
2448 }
2450 /*
2451 * Stop the device, grabbing the top-level lock to protect
2452 * against concurrent entry through ath5k_init (which can happen
2453 * if another thread does a system call and the thread doing the
2454 * stop is preempted).
2455 */
2456 static int
2458 {
2464 /*
2465 * Don't set the card in full sleep mode!
2466 *
2467 * a) When the device is in this state it must be carefully
2468 * woken up or references to registers in the PCI clock
2469 * domain may freeze the bus (and system). This varies
2470 * by chip and is mostly an issue with newer parts
2471 * (madwifi sources mentioned srev >= 0x78) that go to
2472 * sleep more quickly.
2473 *
2474 * b) On older chips full sleep results a weird behaviour
2475 * during wakeup. I tested various cards with srev < 0x78
2476 * and they don't wake up after module reload, a second
2477 * module reload is needed to bring the card up again.
2478 *
2479 * Until we figure out what's going on don't enable
2480 * full chip reset on any chip (this is what Legacy HAL
2481 * and Sam's HAL do anyway). Instead Perform a full reset
2482 * on the device (same as initial state after attach) and
2483 * leave it idle (keep MAC/BB on warm reset) */
2488 }
2503 }
2505 static irqreturn_t
2507 {
2522 /*
2523 * Fatal errors are unrecoverable.
2524 * Typically these are caused by DMA errors.
2525 */
2532 }
2534 /*
2535 * NB: the hardware should re-read the link when
2536 * RXE bit is written, but it doesn't work at
2537 * least on older hardware revs.
2538 */
2540 }
2542 /* bump tx trigger level */
2544 }
2551 /* TODO */
2552 }
2555 }
2557 /*
2558 * These stats are also used for ANI i think
2559 * so how about updating them more often ?
2560 */
2562 }
2566 }
2575 }
2577 static void
2579 {
2583 }
2585 /*
2586 * Periodically recalibrate the PHY to account
2587 * for temperature/environment changes.
2588 */
2589 static void
2591 {
2595 /* Only full calibration for now */
2599 /* Stop queues so that calibration
2600 * doesn't interfere with tx */
2608 /*
2609 * Rfgain is out of bounds, reset the chip
2610 * to load new gain values.
2611 */
2614 }
2622 /* Wake queues */
2625 }
2628 /********************\
2629 * Mac80211 functions *
2630 \********************/
2632 static int
2634 {
2638 }
2642 {
2654 /*
2655 * the hardware expects the header padded to 4 byte boundaries
2656 * if this is not the case we add the padding after the header
2657 */
2666 }
2669 }
2677 }
2694 }
2697 drop_packet:
2700 }
2702 /*
2703 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2704 * and change to the given channel.
2705 */
2706 static int
2708 {
2721 }
2726 }
2732 }
2734 /*
2735 * Change channels and update the h/w rate map if we're switching;
2736 * e.g. 11a to 11b/g.
2737 *
2738 * We may be doing a reset in response to an ioctl that changes the
2739 * channel so update any state that might change as a result.
2740 *
2741 * XXX needed?
2742 */
2743 /* ath5k_chan_change(sc, c); */
2746 /* intrs are enabled by ath5k_beacon_config */
2749 err:
2751 }
2753 static int
2755 {
2763 }
2766 {
2768 }
2771 {
2773 }
2777 {
2785 }
2800 }
2806 end:
2809 }
2811 static void
2814 {
2824 end:
2826 }
2828 /*
2829 * TODO: Phy disable/diversity etc
2830 */
2831 static int
2833 {
2845 }
2851 /* Half dB steps */
2853 }
2855 /* TODO:
2856 * 1) Move this on config_interface and handle each case
2857 * separately eg. when we have only one STA vif, use
2858 * AR5K_ANTMODE_SINGLE_AP
2859 *
2860 * 2) Allow the user to change antenna mode eg. when only
2861 * one antenna is present
2862 *
2863 * 3) Allow the user to set default/tx antenna when possible
2864 *
2865 * 4) Default mode should handle 90% of the cases, together
2866 * with fixed a/b and single AP modes we should be able to
2867 * handle 99%. Sectored modes are extreme cases and i still
2868 * haven't found a usage for them. If we decide to support them,
2869 * then we must allow the user to set how many tx antennas we
2870 * have available
2871 */
2874 unlock:
2877 }
2881 {
2884 u8 pos;
2892 /* calculate XOR of eight 6-bit values */
2899 /* XXX: we might be able to just do this instead,
2900 * but not sure, needs testing, if we do use this we'd
2901 * neet to inform below to not reset the mcast */
2902 /* ath5k_hw_set_mcast_filterindex(ah,
2903 * mclist->dmi_addr[5]); */
2905 }
2908 }
2910 #define SUPPORTED_FIF_FLAGS \
2911 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2912 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2913 FIF_BCN_PRBRESP_PROMISC
2914 /*
2915 * o always accept unicast, broadcast, and multicast traffic
2916 * o multicast traffic for all BSSIDs will be enabled if mac80211
2917 * says it should be
2918 * o maintain current state of phy ofdm or phy cck error reception.
2919 * If the hardware detects any of these type of errors then
2920 * ath5k_hw_get_rx_filter() will pass to us the respective
2921 * hardware filters to be able to receive these type of frames.
2922 * o probe request frames are accepted only when operating in
2923 * hostap, adhoc, or monitor modes
2924 * o enable promiscuous mode according to the interface state
2925 * o accept beacons:
2926 * - when operating in adhoc mode so the 802.11 layer creates
2927 * node table entries for peers,
2928 * - when operating in station mode for collecting rssi data when
2929 * the station is otherwise quiet, or
2930 * - when scanning
2931 */
2935 u64 multicast)
2936 {
2946 /* Only deal with supported flags */
2950 /* If HW detects any phy or radar errors, leave those filters on.
2951 * Also, always enable Unicast, Broadcasts and Multicast
2952 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2955 AR5K_RX_FILTER_MCAST);
2963 }
2964 }
2966 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2970 }
2972 /* This is the best we can do */
2976 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2977 * and probes for any BSSID, this needs testing */
2981 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2982 * set we should only pass on control frames for this
2983 * station. This needs testing. I believe right now this
2984 * enables *all* control frames, which is OK.. but
2985 * but we should see if we can improve on granularity */
2989 /* Additional settings per mode -- this is per ath5k */
2991 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2997 AR5K_RX_FILTER_BEACON |
2998 AR5K_RX_FILTER_PROBEREQ |
2999 AR5K_RX_FILTER_PROM;
3004 AR5K_RX_FILTER_BEACON;
3011 }
3013 /* Set filters */
3016 /* Set multicast bits */
3018 /* Set the cached hw filter flags, this will alter actually
3019 * be set in HW */
3023 }
3025 static int
3029 {
3053 }
3064 }
3068 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3077 }
3079 unlock:
3083 }
3085 static int
3088 {
3092 /* Force update */
3098 }
3100 static int
3103 {
3109 }
3111 static u64
3113 {
3117 }
3119 static void
3121 {
3125 }
3127 static void
3129 {
3132 /*
3133 * in IBSS mode we need to update the beacon timers too.
3134 * this will also reset the TSF if we call it with 0
3135 */
3138 else
3140 }
3142 /*
3143 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3144 * this is called only once at config_bss time, for AP we do it every
3145 * SWBA interrupt so that the TIM will reflect buffered frames.
3146 *
3147 * Called with the beacon lock.
3148 */
3149 static int
3151 {
3159 }
3166 }
3175 out:
3177 }
3179 static void
3181 {
3184 u32 rfilt;
3188 else
3192 }
3197 u32 changes)
3198 {
3209 /* Cache for later use during resets */
3214 }
3231 /* Once ANI is available you would start it here */
3232 }
3233 }
3239 }
3245 BSS_CHANGED_BEACON_INT))
3248 unlock:
3250 }
3253 {
3257 }
3260 {
3264 }