include/asm-mips/war.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
   7  */
   8 #ifndef _ASM_WAR_H
   9 #define _ASM_WAR_H
  10
  11 #include <war.h>
  12
  13 /*
  14  * Another R4600 erratum.  Due to the lack of errata information the exact
  15  * technical details aren't known.  I've experimentally found that disabling
  16  * interrupts during indexed I-cache flushes seems to be sufficient to deal
  17  * with the issue.
  18  */
  19 #ifndef R4600_V1_INDEX_ICACHEOP_WAR
  20 #error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
  21 #endif
  22
  23 /*
  24  * Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
  25  *
  26  *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
  27  *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
  28  *      executed if there is no other dcache activity. If the dcache is
  29  *      accessed for another instruction immeidately preceding when these
  30  *      cache instructions are executing, it is possible that the dcache
  31  *      tag match outputs used by these cache instructions will be
  32  *      incorrect. These cache instructions should be preceded by at least
  33  *      four instructions that are not any kind of load or store
  34  *      instruction.
  35  *
  36  *      This is not allowed:    lw
  37  *                              nop
  38  *                              nop
  39  *                              nop
  40  *                              cache       Hit_Writeback_Invalidate_D
  41  *
  42  *      This is allowed:        lw
  43  *                              nop
  44  *                              nop
  45  *                              nop
  46  *                              nop
  47  *                              cache       Hit_Writeback_Invalidate_D
  48  */
  49 #ifndef R4600_V1_HIT_CACHEOP_WAR
  50 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
  51 #endif
  52
  53
  54 /*
  55  * Writeback and invalidate the primary cache dcache before DMA.
  56  *
  57  * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
  58  * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
  59  * operate correctly if the internal data cache refill buffer is empty.  These
  60  * CACHE instructions should be separated from any potential data cache miss
  61  * by a load instruction to an uncached address to empty the response buffer."
  62  * (Revision 2.0 device errata from IDT available on http://www.idt.com/
  63  * in .pdf format.)
  64  */
  65 #ifndef R4600_V2_HIT_CACHEOP_WAR
  66 #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
  67 #endif
  68
  69 /*
  70  * When an interrupt happens on a CP0 register read instruction, CPU may
  71  * lock up or read corrupted values of CP0 registers after it enters
  72  * the exception handler.
  73  *
  74  * This workaround makes sure that we read a "safe" CP0 register as the
  75  * first thing in the exception handler, which breaks one of the
  76  * pre-conditions for this problem.
  77  */
  78 #ifndef R5432_CP0_INTERRUPT_WAR
  79 #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
  80 #endif
  81
  82 /*
  83  * Workaround for the Sibyte M3 errata the text of which can be found at
  84  *
  85  *   http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
  86  *
  87  * This will enable the use of a special TLB refill handler which does a
  88  * consistency check on the information in c0_badvaddr and c0_entryhi and
  89  * will just return and take the exception again if the information was
  90  * found to be inconsistent.
  91  */
  92 #ifndef BCM1250_M3_WAR
  93 #error Check setting of BCM1250_M3_WAR for your platform
  94 #endif
  95
  96 /*
  97  * This is a DUART workaround related to glitches around register accesses
  98  */
  99 #ifndef SIBYTE_1956_WAR
 100 #error Check setting of SIBYTE_1956_WAR for your platform
 101 #endif
 102
 103 /*
 104  * Fill buffers not flushed on CACHE instructions
 105  *
 106  * Hit_Invalidate_I cacheops invalidate an icache line but the refill
 107  * for that line can get stale data from the fill buffer instead of
 108  * accessing memory if the previous icache miss was also to that line.
 109  *
 110  * Workaround: generate an icache refill from a different line
 111  *
 112  * Affects:
 113  *  MIPS 4K             RTL revision <3.0, PRID revision <4
 114  */
 115 #ifndef MIPS4K_ICACHE_REFILL_WAR
 116 #error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
 117 #endif
 118
 119 /*
 120  * Missing implicit forced flush of evictions caused by CACHE
 121  * instruction
 122  *
 123  * Evictions caused by a CACHE instructions are not forced on to the
 124  * bus. The BIU gives higher priority to fetches than to the data from
 125  * the eviction buffer and no collision detection is performed between
 126  * fetches and pending data from the eviction buffer.
 127  *
 128  * Workaround: Execute a SYNC instruction after the cache instruction
 129  *
 130  * Affects:
 131  *   MIPS 5Kc,5Kf       RTL revision <2.3, PRID revision <8
 132  *   MIPS 20Kc          RTL revision <4.0, PRID revision <?
 133  */
 134 #ifndef MIPS_CACHE_SYNC_WAR
 135 #error Check setting of MIPS_CACHE_SYNC_WAR for your platform
 136 #endif
 137
 138 /*
 139  * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
 140  * the line which this instruction itself exists, the following
 141  * operation is not guaranteed."
 142  *
 143  * Workaround: do two phase flushing for Index_Invalidate_I
 144  */
 145 #ifndef TX49XX_ICACHE_INDEX_INV_WAR
 146 #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
 147 #endif
 148
 149 /*
 150  * On the RM9000 there is a problem which makes the CreateDirtyExclusive
 151  * eache operation unusable on SMP systems.
 152  */
 153 #ifndef RM9000_CDEX_SMP_WAR
 154 #error Check setting of RM9000_CDEX_SMP_WAR for your platform
 155 #endif
 156
 157 /*
 158  * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
 159  * opposes it being called that) where invalid instructions in the same
 160  * I-cache line worth of instructions being fetched may case spurious
 161  * exceptions.
 162  */
 163 #ifndef ICACHE_REFILLS_WORKAROUND_WAR
 164 #error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
 165 #endif
 166
 167 /*
 168  * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
 169  * may cause ll / sc and lld / scd sequences to execute non-atomically.
 170  */
 171 #ifndef R10000_LLSC_WAR
 172 #error Check setting of R10000_LLSC_WAR for your platform
 173 #endif
 174
 175 /*
 176  * 34K core erratum: "Problems Executing the TLBR Instruction"
 177  */
 178 #ifndef MIPS34K_MISSED_ITLB_WAR
 179 #error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
 180 #endif
 181
 182 #endif /* _ASM_WAR_H */