2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/smp_lock.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/reboot.h>
34 #include <linux/usb.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
38 #include "../core/hcd.h"
40 #include <asm/byteorder.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
47 /*-------------------------------------------------------------------------*/
50 * EHCI hc_driver implementation ... experimental, incomplete.
51 * Based on the final 1.0 register interface specification.
53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 * Next comes "CardBay", using USB 2.0 signals.
57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 * Special thanks to Intel and VIA for providing host controllers to
59 * test this driver on, and Cypress (including In-System Design) for
60 * providing early devices for those host controllers to talk to!
64 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
65 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
66 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
67 * <sojkam@centrum.cz>, updates by DB).
69 * 2002-11-29 Correct handling for hw async_next register.
70 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
71 * only scheduling is different, no arbitrary limitations.
72 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
73 * clean up HC run state handshaking.
74 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
75 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
76 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
77 * 2002-05-07 Some error path cleanups to report better errors; wmb();
78 * use non-CVS version id; better iso bandwidth claim.
79 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
80 * errors in submit path. Bugfixes to interrupt scheduling/processing.
81 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
82 * more checking to generic hcd framework (db). Make it work with
83 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
84 * 2002-01-14 Minor cleanup; version synch.
85 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
86 * 2002-01-04 Control/Bulk queuing behaves.
88 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
89 * 2001-June Works with usb-storage and NEC EHCI on 2.4
92 #define DRIVER_VERSION "10 Dec 2004"
93 #define DRIVER_AUTHOR "David Brownell"
94 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
96 static const char hcd_name
[] = "ehci_hcd";
99 #undef EHCI_VERBOSE_DEBUG
100 #undef EHCI_URB_TRACE
106 /* magic numbers that can affect system performance */
107 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
108 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
109 #define EHCI_TUNE_RL_TT 0
110 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
111 #define EHCI_TUNE_MULT_TT 1
112 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
114 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
115 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
116 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
117 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
119 /* Initial IRQ latency: faster than hw default */
120 static int log2_irq_thresh
= 0; // 0 to 6
121 module_param (log2_irq_thresh
, int, S_IRUGO
);
122 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
124 /* initial park setting: slower than hw default */
125 static unsigned park
= 0;
126 module_param (park
, uint
, S_IRUGO
);
127 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
129 /* for flakey hardware, ignore overcurrent indicators */
130 static int ignore_oc
= 0;
131 module_param (ignore_oc
, bool, S_IRUGO
);
132 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
134 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
136 /*-------------------------------------------------------------------------*/
139 #include "ehci-dbg.c"
141 /*-------------------------------------------------------------------------*/
144 * handshake - spin reading hc until handshake completes or fails
145 * @ptr: address of hc register to be read
146 * @mask: bits to look at in result of read
147 * @done: value of those bits when handshake succeeds
148 * @usec: timeout in microseconds
150 * Returns negative errno, or zero on success
152 * Success happens when the "mask" bits have the specified value (hardware
153 * handshake done). There are two failure modes: "usec" have passed (major
154 * hardware flakeout), or the register reads as all-ones (hardware removed).
156 * That last failure should_only happen in cases like physical cardbus eject
157 * before driver shutdown. But it also seems to be caused by bugs in cardbus
158 * bridge shutdown: shutting down the bridge before the devices using it.
160 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
161 u32 mask
, u32 done
, int usec
)
166 result
= ehci_readl(ehci
, ptr
);
167 if (result
== ~(u32
)0) /* card removed */
178 /* force HC to halt state from unknown (EHCI spec section 2.3) */
179 static int ehci_halt (struct ehci_hcd
*ehci
)
181 u32 temp
= ehci_readl(ehci
, &ehci
->regs
->status
);
183 /* disable any irqs left enabled by previous code */
184 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
186 if ((temp
& STS_HALT
) != 0)
189 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
191 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
192 return handshake (ehci
, &ehci
->regs
->status
,
193 STS_HALT
, STS_HALT
, 16 * 125);
196 /* put TDI/ARC silicon into EHCI mode */
197 static void tdi_reset (struct ehci_hcd
*ehci
)
199 u32 __iomem
*reg_ptr
;
202 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + 0x68);
203 tmp
= ehci_readl(ehci
, reg_ptr
);
205 ehci_writel(ehci
, tmp
, reg_ptr
);
208 /* reset a non-running (STS_HALT == 1) controller */
209 static int ehci_reset (struct ehci_hcd
*ehci
)
212 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
214 command
|= CMD_RESET
;
215 dbg_cmd (ehci
, "reset", command
);
216 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
217 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
218 ehci
->next_statechange
= jiffies
;
219 retval
= handshake (ehci
, &ehci
->regs
->command
,
220 CMD_RESET
, 0, 250 * 1000);
225 if (ehci_is_TDI(ehci
))
231 /* idle the controller (from running) */
232 static void ehci_quiesce (struct ehci_hcd
*ehci
)
237 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
241 /* wait for any schedule enables/disables to take effect */
242 temp
= ehci_readl(ehci
, &ehci
->regs
->command
) << 10;
243 temp
&= STS_ASS
| STS_PSS
;
244 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
245 temp
, 16 * 125) != 0) {
246 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
250 /* then disable anything that's still active */
251 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
252 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
253 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
255 /* hardware can take 16 microframes to turn off ... */
256 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
258 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
263 /*-------------------------------------------------------------------------*/
265 static void ehci_work(struct ehci_hcd
*ehci
);
267 #include "ehci-hub.c"
268 #include "ehci-mem.c"
270 #include "ehci-sched.c"
272 /*-------------------------------------------------------------------------*/
274 static void ehci_watchdog (unsigned long param
)
276 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
279 spin_lock_irqsave (&ehci
->lock
, flags
);
281 /* lost IAA irqs wedge things badly; seen with a vt8235 */
283 u32 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
284 if (status
& STS_IAA
) {
285 ehci_vdbg (ehci
, "lost IAA\n");
286 COUNT (ehci
->stats
.lost_iaa
);
287 ehci_writel(ehci
, STS_IAA
, &ehci
->regs
->status
);
288 ehci
->reclaim_ready
= 1;
292 /* stop async processing after it's idled a bit */
293 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
294 start_unlink_async (ehci
, ehci
->async
);
296 /* ehci could run by timer, without IRQs ... */
299 spin_unlock_irqrestore (&ehci
->lock
, flags
);
302 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
303 * The firmware seems to think that powering off is a wakeup event!
304 * This routine turns off remote wakeup and everything else, on all ports.
306 static void ehci_turn_off_all_ports(struct ehci_hcd
*ehci
)
308 int port
= HCS_N_PORTS(ehci
->hcs_params
);
311 ehci_writel(ehci
, PORT_RWC_BITS
,
312 &ehci
->regs
->port_status
[port
]);
315 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
316 * This forcibly disables dma and IRQs, helping kexec and other cases
317 * where the next system software may expect clean state.
320 ehci_shutdown (struct usb_hcd
*hcd
)
322 struct ehci_hcd
*ehci
;
324 ehci
= hcd_to_ehci (hcd
);
325 (void) ehci_halt (ehci
);
326 ehci_turn_off_all_ports(ehci
);
328 /* make BIOS/etc use companion controller during reboot */
329 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
331 /* unblock posted writes */
332 ehci_readl(ehci
, &ehci
->regs
->configured_flag
);
335 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
339 if (!HCS_PPC (ehci
->hcs_params
))
342 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
343 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
344 (void) ehci_hub_control(ehci_to_hcd(ehci
),
345 is_on
? SetPortFeature
: ClearPortFeature
,
351 /*-------------------------------------------------------------------------*/
354 * ehci_work is called from some interrupts, timers, and so on.
355 * it calls driver completion functions, after dropping ehci->lock.
357 static void ehci_work (struct ehci_hcd
*ehci
)
359 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
360 if (ehci
->reclaim_ready
)
361 end_unlink_async (ehci
);
363 /* another CPU may drop ehci->lock during a schedule scan while
364 * it reports urb completions. this flag guards against bogus
365 * attempts at re-entrant schedule scanning.
371 if (ehci
->next_uframe
!= -1)
372 scan_periodic (ehci
);
375 /* the IO watchdog guards against hardware or driver bugs that
376 * misplace IRQs, and should let us run completely without IRQs.
377 * such lossage has been observed on both VT6202 and VT8235.
379 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
380 (ehci
->async
->qh_next
.ptr
!= NULL
||
381 ehci
->periodic_sched
!= 0))
382 timer_action (ehci
, TIMER_IO_WATCHDOG
);
385 static void ehci_stop (struct usb_hcd
*hcd
)
387 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
389 ehci_dbg (ehci
, "stop\n");
391 /* Turn off port power on all root hub ports. */
392 ehci_port_power (ehci
, 0);
394 /* no more interrupts ... */
395 del_timer_sync (&ehci
->watchdog
);
397 spin_lock_irq(&ehci
->lock
);
398 if (HC_IS_RUNNING (hcd
->state
))
402 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
403 spin_unlock_irq(&ehci
->lock
);
405 /* let companion controllers work when we aren't */
406 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
408 remove_companion_file(ehci
);
409 remove_debug_files (ehci
);
411 /* root hub is shut down separately (first, when possible) */
412 spin_lock_irq (&ehci
->lock
);
415 spin_unlock_irq (&ehci
->lock
);
416 ehci_mem_cleanup (ehci
);
419 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
420 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
421 ehci
->stats
.lost_iaa
);
422 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
423 ehci
->stats
.complete
, ehci
->stats
.unlink
);
426 dbg_status (ehci
, "ehci_stop completed",
427 ehci_readl(ehci
, &ehci
->regs
->status
));
430 /* one-time init, only for memory state */
431 static int ehci_init(struct usb_hcd
*hcd
)
433 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
438 spin_lock_init(&ehci
->lock
);
440 init_timer(&ehci
->watchdog
);
441 ehci
->watchdog
.function
= ehci_watchdog
;
442 ehci
->watchdog
.data
= (unsigned long) ehci
;
445 * hw default: 1K periodic list heads, one per frame.
446 * periodic_size can shrink by USBCMD update if hcc_params allows.
448 ehci
->periodic_size
= DEFAULT_I_TDPS
;
449 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
452 /* controllers may cache some of the periodic schedule ... */
453 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
454 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
456 else // N microframes cached
457 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
459 ehci
->reclaim
= NULL
;
460 ehci
->reclaim_ready
= 0;
461 ehci
->next_uframe
= -1;
464 * dedicate a qh for the async ring head, since we couldn't unlink
465 * a 'real' qh without stopping the async schedule [4.8]. use it
466 * as the 'reclamation list head' too.
467 * its dummy is used in hw_alt_next of many tds, to prevent the qh
468 * from automatically advancing to the next td after short reads.
470 ehci
->async
->qh_next
.qh
= NULL
;
471 ehci
->async
->hw_next
= QH_NEXT(ehci
->async
->qh_dma
);
472 ehci
->async
->hw_info1
= cpu_to_le32(QH_HEAD
);
473 ehci
->async
->hw_token
= cpu_to_le32(QTD_STS_HALT
);
474 ehci
->async
->hw_qtd_next
= EHCI_LIST_END
;
475 ehci
->async
->qh_state
= QH_STATE_LINKED
;
476 ehci
->async
->hw_alt_next
= QTD_NEXT(ehci
->async
->dummy
->qtd_dma
);
478 /* clear interrupt enables, set irq latency */
479 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
481 temp
= 1 << (16 + log2_irq_thresh
);
482 if (HCC_CANPARK(hcc_params
)) {
483 /* HW default park == 3, on hardware that supports it (like
484 * NVidia and ALI silicon), maximizes throughput on the async
485 * schedule by avoiding QH fetches between transfers.
487 * With fast usb storage devices and NForce2, "park" seems to
488 * make problems: throughput reduction (!), data errors...
491 park
= min(park
, (unsigned) 3);
495 ehci_dbg(ehci
, "park %d\n", park
);
497 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
498 /* periodic schedule size can be smaller than default */
500 temp
|= (EHCI_TUNE_FLS
<< 2);
501 switch (EHCI_TUNE_FLS
) {
502 case 0: ehci
->periodic_size
= 1024; break;
503 case 1: ehci
->periodic_size
= 512; break;
504 case 2: ehci
->periodic_size
= 256; break;
508 ehci
->command
= temp
;
513 /* start HC running; it's halted, ehci_init() has been run (once) */
514 static int ehci_run (struct usb_hcd
*hcd
)
516 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
521 hcd
->uses_new_polling
= 1;
524 /* EHCI spec section 4.1 */
525 if ((retval
= ehci_reset(ehci
)) != 0) {
526 ehci_mem_cleanup(ehci
);
529 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
530 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
533 * hcc_params controls whether ehci->regs->segment must (!!!)
534 * be used; it constrains QH/ITD/SITD and QTD locations.
535 * pci_pool consistent memory always uses segment zero.
536 * streaming mappings for I/O buffers, like pci_map_single(),
537 * can return segments above 4GB, if the device allows.
539 * NOTE: the dma mask is visible through dma_supported(), so
540 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
541 * Scsi_Host.highmem_io, and so forth. It's readonly to all
542 * host side drivers though.
544 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
545 if (HCC_64BIT_ADDR(hcc_params
)) {
546 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
548 // this is deeply broken on almost all architectures
549 if (!dma_set_mask(hcd
->self
.controller
, DMA_64BIT_MASK
))
550 ehci_info(ehci
, "enabled 64bit DMA\n");
555 // Philips, Intel, and maybe others need CMD_RUN before the
556 // root hub will detect new devices (why?); NEC doesn't
557 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
558 ehci
->command
|= CMD_RUN
;
559 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
560 dbg_cmd (ehci
, "init", ehci
->command
);
563 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
564 * are explicitly handed to companion controller(s), so no TT is
565 * involved with the root hub. (Except where one is integrated,
566 * and there's no companion controller unless maybe for USB OTG.)
568 hcd
->state
= HC_STATE_RUNNING
;
569 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
570 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
572 temp
= HC_VERSION(ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
574 "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
575 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
576 temp
>> 8, temp
& 0xff, DRIVER_VERSION
,
577 ignore_oc
? ", overcurrent ignored" : "");
579 ehci_writel(ehci
, INTR_MASK
,
580 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
582 /* GRR this is run-once init(), being done every time the HC starts.
583 * So long as they're part of class devices, we can't do it init()
584 * since the class device isn't created that early.
586 create_debug_files(ehci
);
587 create_companion_file(ehci
);
592 /*-------------------------------------------------------------------------*/
594 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
596 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
597 u32 status
, pcd_status
= 0;
600 spin_lock (&ehci
->lock
);
602 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
604 /* e.g. cardbus physical eject */
605 if (status
== ~(u32
) 0) {
606 ehci_dbg (ehci
, "device removed\n");
611 if (!status
) { /* irq sharing? */
612 spin_unlock(&ehci
->lock
);
616 /* clear (just) interrupts */
617 ehci_writel(ehci
, status
, &ehci
->regs
->status
);
618 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted write */
621 #ifdef EHCI_VERBOSE_DEBUG
622 /* unrequested/ignored: Frame List Rollover */
623 dbg_status (ehci
, "irq", status
);
626 /* INT, ERR, and IAA interrupt rates can be throttled */
628 /* normal [4.15.1.2] or error [4.15.1.1] completion */
629 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
630 if (likely ((status
& STS_ERR
) == 0))
631 COUNT (ehci
->stats
.normal
);
633 COUNT (ehci
->stats
.error
);
637 /* complete the unlinking of some qh [4.15.2.3] */
638 if (status
& STS_IAA
) {
639 COUNT (ehci
->stats
.reclaim
);
640 ehci
->reclaim_ready
= 1;
644 /* remote wakeup [4.3.1] */
645 if (status
& STS_PCD
) {
646 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
649 /* resume root hub? */
650 if (!(ehci_readl(ehci
, &ehci
->regs
->command
) & CMD_RUN
))
651 usb_hcd_resume_root_hub(hcd
);
654 int pstatus
= ehci_readl(ehci
,
655 &ehci
->regs
->port_status
[i
]);
657 if (pstatus
& PORT_OWNER
)
659 if (!(pstatus
& PORT_RESUME
)
660 || ehci
->reset_done
[i
] != 0)
663 /* start 20 msec resume signaling from this port,
664 * and make khubd collect PORT_STAT_C_SUSPEND to
665 * stop that signaling.
667 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
668 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
672 /* PCI errors [4.15.2.4] */
673 if (unlikely ((status
& STS_FATAL
) != 0)) {
674 /* bogus "fatal" IRQs appear on some chips... why? */
675 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
676 dbg_cmd (ehci
, "fatal", ehci_readl(ehci
,
677 &ehci
->regs
->command
));
678 dbg_status (ehci
, "fatal", status
);
679 if (status
& STS_HALT
) {
680 ehci_err (ehci
, "fatal error\n");
683 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
684 /* generic layer kills/unlinks all urbs, then
685 * uses ehci_stop to clean up the rest
693 spin_unlock (&ehci
->lock
);
694 if (pcd_status
& STS_PCD
)
695 usb_hcd_poll_rh_status(hcd
);
699 /*-------------------------------------------------------------------------*/
702 * non-error returns are a promise to giveback() the urb later
703 * we drop ownership so next owner (or urb unlink) can get it
705 * urb + dev is in hcd.self.controller.urb_list
706 * we're queueing TDs onto software and hardware lists
708 * hcd-specific init for hcpriv hasn't been done yet
710 * NOTE: control, bulk, and interrupt share the same code to append TDs
711 * to a (possibly active) QH, and the same QH scanning code.
713 static int ehci_urb_enqueue (
715 struct usb_host_endpoint
*ep
,
719 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
720 struct list_head qtd_list
;
722 INIT_LIST_HEAD (&qtd_list
);
724 switch (usb_pipetype (urb
->pipe
)) {
725 // case PIPE_CONTROL:
728 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
730 return submit_async (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
733 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
735 return intr_submit (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
737 case PIPE_ISOCHRONOUS
:
738 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
739 return itd_submit (ehci
, urb
, mem_flags
);
741 return sitd_submit (ehci
, urb
, mem_flags
);
745 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
747 /* if we need to use IAA and it's busy, defer */
748 if (qh
->qh_state
== QH_STATE_LINKED
750 && HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)) {
751 struct ehci_qh
*last
;
753 for (last
= ehci
->reclaim
;
755 last
= last
->reclaim
)
757 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
760 /* bypass IAA if the hc can't care */
761 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
762 end_unlink_async (ehci
);
764 /* something else might have unlinked the qh by now */
765 if (qh
->qh_state
== QH_STATE_LINKED
)
766 start_unlink_async (ehci
, qh
);
769 /* remove from hardware lists
770 * completions normally happen asynchronously
773 static int ehci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
775 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
779 spin_lock_irqsave (&ehci
->lock
, flags
);
780 switch (usb_pipetype (urb
->pipe
)) {
781 // case PIPE_CONTROL:
784 qh
= (struct ehci_qh
*) urb
->hcpriv
;
787 unlink_async (ehci
, qh
);
791 qh
= (struct ehci_qh
*) urb
->hcpriv
;
794 switch (qh
->qh_state
) {
795 case QH_STATE_LINKED
:
796 intr_deschedule (ehci
, qh
);
799 qh_completions (ehci
, qh
);
802 ehci_dbg (ehci
, "bogus qh %p state %d\n",
807 /* reschedule QH iff another request is queued */
808 if (!list_empty (&qh
->qtd_list
)
809 && HC_IS_RUNNING (hcd
->state
)) {
812 status
= qh_schedule (ehci
, qh
);
813 spin_unlock_irqrestore (&ehci
->lock
, flags
);
816 // shouldn't happen often, but ...
817 // FIXME kill those tds' urbs
818 err ("can't reschedule qh %p, err %d",
825 case PIPE_ISOCHRONOUS
:
828 // wait till next completion, do it then.
829 // completion irqs can wait up to 1024 msec,
833 spin_unlock_irqrestore (&ehci
->lock
, flags
);
837 /*-------------------------------------------------------------------------*/
839 // bulk qh holds the data toggle
842 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
844 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
846 struct ehci_qh
*qh
, *tmp
;
848 /* ASSERT: any requests/urbs are being unlinked */
849 /* ASSERT: nobody can be submitting urbs for this any more */
852 spin_lock_irqsave (&ehci
->lock
, flags
);
857 /* endpoints can be iso streams. for now, we don't
858 * accelerate iso completions ... so spin a while.
860 if (qh
->hw_info1
== 0) {
861 ehci_vdbg (ehci
, "iso delay\n");
865 if (!HC_IS_RUNNING (hcd
->state
))
866 qh
->qh_state
= QH_STATE_IDLE
;
867 switch (qh
->qh_state
) {
868 case QH_STATE_LINKED
:
869 for (tmp
= ehci
->async
->qh_next
.qh
;
871 tmp
= tmp
->qh_next
.qh
)
873 /* periodic qh self-unlinks on empty */
876 unlink_async (ehci
, qh
);
878 case QH_STATE_UNLINK
: /* wait for hw to finish? */
880 spin_unlock_irqrestore (&ehci
->lock
, flags
);
881 schedule_timeout_uninterruptible(1);
883 case QH_STATE_IDLE
: /* fully unlinked */
884 if (list_empty (&qh
->qtd_list
)) {
888 /* else FALL THROUGH */
891 /* caller was supposed to have unlinked any requests;
892 * that's not our job. just leak this memory.
894 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
895 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
896 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
901 spin_unlock_irqrestore (&ehci
->lock
, flags
);
905 static int ehci_get_frame (struct usb_hcd
*hcd
)
907 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
908 return (ehci_readl(ehci
, &ehci
->regs
->frame_index
) >> 3) %
912 /*-------------------------------------------------------------------------*/
914 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
916 MODULE_DESCRIPTION (DRIVER_INFO
);
917 MODULE_AUTHOR (DRIVER_AUTHOR
);
918 MODULE_LICENSE ("GPL");
921 #include "ehci-pci.c"
922 #define PCI_DRIVER ehci_pci_driver
925 #ifdef CONFIG_MPC834x
926 #include "ehci-fsl.c"
927 #define PLATFORM_DRIVER ehci_fsl_driver
930 #ifdef CONFIG_SOC_AU1200
931 #include "ehci-au1xxx.c"
932 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
935 #ifdef CONFIG_PPC_PS3
936 #include "ehci-ps3.c"
937 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_sb_driver
940 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
941 !defined(PS3_SYSTEM_BUS_DRIVER)
942 #error "missing bus glue for ehci-hcd"
945 static int __init
ehci_hcd_init(void)
949 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
951 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
952 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
954 #ifdef PLATFORM_DRIVER
955 retval
= platform_driver_register(&PLATFORM_DRIVER
);
961 retval
= pci_register_driver(&PCI_DRIVER
);
963 #ifdef PLATFORM_DRIVER
964 platform_driver_unregister(&PLATFORM_DRIVER
);
970 #ifdef PS3_SYSTEM_BUS_DRIVER
971 retval
= ps3_system_bus_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
973 #ifdef PLATFORM_DRIVER
974 platform_driver_unregister(&PLATFORM_DRIVER
);
977 pci_unregister_driver(&PCI_DRIVER
);
985 module_init(ehci_hcd_init
);
987 static void __exit
ehci_hcd_cleanup(void)
989 #ifdef PLATFORM_DRIVER
990 platform_driver_unregister(&PLATFORM_DRIVER
);
993 pci_unregister_driver(&PCI_DRIVER
);
995 #ifdef PS3_SYSTEM_BUS_DRIVER
996 ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
999 module_exit(ehci_hcd_cleanup
);