2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
51 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
52 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
53 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file_priv
);
56 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= i915_gem_alloc_object(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 drm_gem_object_unreference_unlocked(obj
);
135 args
->handle
= handle
;
141 fast_shmem_read(struct page
**pages
,
142 loff_t page_base
, int page_offset
,
149 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
152 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
153 kunmap_atomic(vaddr
, KM_USER0
);
161 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
163 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
164 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
166 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
167 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
171 slow_shmem_copy(struct page
*dst_page
,
173 struct page
*src_page
,
177 char *dst_vaddr
, *src_vaddr
;
179 dst_vaddr
= kmap(dst_page
);
180 src_vaddr
= kmap(src_page
);
182 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
189 slow_shmem_bit17_copy(struct page
*gpu_page
,
191 struct page
*cpu_page
,
196 char *gpu_vaddr
, *cpu_vaddr
;
198 /* Use the unswizzled path if this page isn't affected. */
199 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
201 return slow_shmem_copy(cpu_page
, cpu_offset
,
202 gpu_page
, gpu_offset
, length
);
204 return slow_shmem_copy(gpu_page
, gpu_offset
,
205 cpu_page
, cpu_offset
, length
);
208 gpu_vaddr
= kmap(gpu_page
);
209 cpu_vaddr
= kmap(cpu_page
);
211 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
212 * XORing with the other bits (A9 for Y, A9 and A10 for X)
215 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
216 int this_length
= min(cacheline_end
- gpu_offset
, length
);
217 int swizzled_gpu_offset
= gpu_offset
^ 64;
220 memcpy(cpu_vaddr
+ cpu_offset
,
221 gpu_vaddr
+ swizzled_gpu_offset
,
224 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
225 cpu_vaddr
+ cpu_offset
,
228 cpu_offset
+= this_length
;
229 gpu_offset
+= this_length
;
230 length
-= this_length
;
238 * This is the fast shmem pread path, which attempts to copy_from_user directly
239 * from the backing pages of the object to the user's address space. On a
240 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
243 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
244 struct drm_i915_gem_pread
*args
,
245 struct drm_file
*file_priv
)
247 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
249 loff_t offset
, page_base
;
250 char __user
*user_data
;
251 int page_offset
, page_length
;
254 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
257 mutex_lock(&dev
->struct_mutex
);
259 ret
= i915_gem_object_get_pages(obj
, 0);
263 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
268 obj_priv
= to_intel_bo(obj
);
269 offset
= args
->offset
;
272 /* Operation in this page
274 * page_base = page offset within aperture
275 * page_offset = offset within page
276 * page_length = bytes to copy for this page
278 page_base
= (offset
& ~(PAGE_SIZE
-1));
279 page_offset
= offset
& (PAGE_SIZE
-1);
280 page_length
= remain
;
281 if ((page_offset
+ remain
) > PAGE_SIZE
)
282 page_length
= PAGE_SIZE
- page_offset
;
284 ret
= fast_shmem_read(obj_priv
->pages
,
285 page_base
, page_offset
,
286 user_data
, page_length
);
290 remain
-= page_length
;
291 user_data
+= page_length
;
292 offset
+= page_length
;
296 i915_gem_object_put_pages(obj
);
298 mutex_unlock(&dev
->struct_mutex
);
304 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
308 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
310 /* If we've insufficient memory to map in the pages, attempt
311 * to make some space by throwing out some old buffers.
313 if (ret
== -ENOMEM
) {
314 struct drm_device
*dev
= obj
->dev
;
316 ret
= i915_gem_evict_something(dev
, obj
->size
);
320 ret
= i915_gem_object_get_pages(obj
, 0);
327 * This is the fallback shmem pread path, which allocates temporary storage
328 * in kernel space to copy_to_user into outside of the struct_mutex, so we
329 * can copy out of the object's backing pages while holding the struct mutex
330 * and not take page faults.
333 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
334 struct drm_i915_gem_pread
*args
,
335 struct drm_file
*file_priv
)
337 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
338 struct mm_struct
*mm
= current
->mm
;
339 struct page
**user_pages
;
341 loff_t offset
, pinned_pages
, i
;
342 loff_t first_data_page
, last_data_page
, num_pages
;
343 int shmem_page_index
, shmem_page_offset
;
344 int data_page_index
, data_page_offset
;
347 uint64_t data_ptr
= args
->data_ptr
;
348 int do_bit17_swizzling
;
352 /* Pin the user pages containing the data. We can't fault while
353 * holding the struct mutex, yet we want to hold it while
354 * dereferencing the user data.
356 first_data_page
= data_ptr
/ PAGE_SIZE
;
357 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
358 num_pages
= last_data_page
- first_data_page
+ 1;
360 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
361 if (user_pages
== NULL
)
364 down_read(&mm
->mmap_sem
);
365 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
366 num_pages
, 1, 0, user_pages
, NULL
);
367 up_read(&mm
->mmap_sem
);
368 if (pinned_pages
< num_pages
) {
370 goto fail_put_user_pages
;
373 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
375 mutex_lock(&dev
->struct_mutex
);
377 ret
= i915_gem_object_get_pages_or_evict(obj
);
381 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
386 obj_priv
= to_intel_bo(obj
);
387 offset
= args
->offset
;
390 /* Operation in this page
392 * shmem_page_index = page number within shmem file
393 * shmem_page_offset = offset within page in shmem file
394 * data_page_index = page number in get_user_pages return
395 * data_page_offset = offset with data_page_index page.
396 * page_length = bytes to copy for this page
398 shmem_page_index
= offset
/ PAGE_SIZE
;
399 shmem_page_offset
= offset
& ~PAGE_MASK
;
400 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
401 data_page_offset
= data_ptr
& ~PAGE_MASK
;
403 page_length
= remain
;
404 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
405 page_length
= PAGE_SIZE
- shmem_page_offset
;
406 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
407 page_length
= PAGE_SIZE
- data_page_offset
;
409 if (do_bit17_swizzling
) {
410 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
412 user_pages
[data_page_index
],
417 slow_shmem_copy(user_pages
[data_page_index
],
419 obj_priv
->pages
[shmem_page_index
],
424 remain
-= page_length
;
425 data_ptr
+= page_length
;
426 offset
+= page_length
;
430 i915_gem_object_put_pages(obj
);
432 mutex_unlock(&dev
->struct_mutex
);
434 for (i
= 0; i
< pinned_pages
; i
++) {
435 SetPageDirty(user_pages
[i
]);
436 page_cache_release(user_pages
[i
]);
438 drm_free_large(user_pages
);
444 * Reads data from the object referenced by handle.
446 * On error, the contents of *data are undefined.
449 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
450 struct drm_file
*file_priv
)
452 struct drm_i915_gem_pread
*args
= data
;
453 struct drm_gem_object
*obj
;
454 struct drm_i915_gem_object
*obj_priv
;
457 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
460 obj_priv
= to_intel_bo(obj
);
462 /* Bounds check source.
464 * XXX: This could use review for overflow issues...
466 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
467 args
->offset
+ args
->size
> obj
->size
) {
468 drm_gem_object_unreference_unlocked(obj
);
472 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
473 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
475 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
477 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
481 drm_gem_object_unreference_unlocked(obj
);
486 /* This is the fast write path which cannot handle
487 * page faults in the source data
491 fast_user_write(struct io_mapping
*mapping
,
492 loff_t page_base
, int page_offset
,
493 char __user
*user_data
,
497 unsigned long unwritten
;
499 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
500 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
502 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
508 /* Here's the write path which can sleep for
513 slow_kernel_write(struct io_mapping
*mapping
,
514 loff_t gtt_base
, int gtt_offset
,
515 struct page
*user_page
, int user_offset
,
518 char __iomem
*dst_vaddr
;
521 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
522 src_vaddr
= kmap(user_page
);
524 memcpy_toio(dst_vaddr
+ gtt_offset
,
525 src_vaddr
+ user_offset
,
529 io_mapping_unmap(dst_vaddr
);
533 fast_shmem_write(struct page
**pages
,
534 loff_t page_base
, int page_offset
,
539 unsigned long unwritten
;
541 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
544 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
545 kunmap_atomic(vaddr
, KM_USER0
);
553 * This is the fast pwrite path, where we copy the data directly from the
554 * user into the GTT, uncached.
557 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
558 struct drm_i915_gem_pwrite
*args
,
559 struct drm_file
*file_priv
)
561 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
564 loff_t offset
, page_base
;
565 char __user
*user_data
;
566 int page_offset
, page_length
;
569 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
571 if (!access_ok(VERIFY_READ
, user_data
, remain
))
575 mutex_lock(&dev
->struct_mutex
);
576 ret
= i915_gem_object_pin(obj
, 0);
578 mutex_unlock(&dev
->struct_mutex
);
581 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
585 obj_priv
= to_intel_bo(obj
);
586 offset
= obj_priv
->gtt_offset
+ args
->offset
;
589 /* Operation in this page
591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
595 page_base
= (offset
& ~(PAGE_SIZE
-1));
596 page_offset
= offset
& (PAGE_SIZE
-1);
597 page_length
= remain
;
598 if ((page_offset
+ remain
) > PAGE_SIZE
)
599 page_length
= PAGE_SIZE
- page_offset
;
601 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
602 page_offset
, user_data
, page_length
);
604 /* If we get a fault while copying data, then (presumably) our
605 * source page isn't available. Return the error and we'll
606 * retry in the slow path.
611 remain
-= page_length
;
612 user_data
+= page_length
;
613 offset
+= page_length
;
617 i915_gem_object_unpin(obj
);
618 mutex_unlock(&dev
->struct_mutex
);
624 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
625 * the memory and maps it using kmap_atomic for copying.
627 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
628 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
631 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
632 struct drm_i915_gem_pwrite
*args
,
633 struct drm_file
*file_priv
)
635 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
636 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
638 loff_t gtt_page_base
, offset
;
639 loff_t first_data_page
, last_data_page
, num_pages
;
640 loff_t pinned_pages
, i
;
641 struct page
**user_pages
;
642 struct mm_struct
*mm
= current
->mm
;
643 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
645 uint64_t data_ptr
= args
->data_ptr
;
649 /* Pin the user pages containing the data. We can't fault while
650 * holding the struct mutex, and all of the pwrite implementations
651 * want to hold it while dereferencing the user data.
653 first_data_page
= data_ptr
/ PAGE_SIZE
;
654 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
655 num_pages
= last_data_page
- first_data_page
+ 1;
657 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
658 if (user_pages
== NULL
)
661 down_read(&mm
->mmap_sem
);
662 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
663 num_pages
, 0, 0, user_pages
, NULL
);
664 up_read(&mm
->mmap_sem
);
665 if (pinned_pages
< num_pages
) {
667 goto out_unpin_pages
;
670 mutex_lock(&dev
->struct_mutex
);
671 ret
= i915_gem_object_pin(obj
, 0);
675 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
677 goto out_unpin_object
;
679 obj_priv
= to_intel_bo(obj
);
680 offset
= obj_priv
->gtt_offset
+ args
->offset
;
683 /* Operation in this page
685 * gtt_page_base = page offset within aperture
686 * gtt_page_offset = offset within page in aperture
687 * data_page_index = page number in get_user_pages return
688 * data_page_offset = offset with data_page_index page.
689 * page_length = bytes to copy for this page
691 gtt_page_base
= offset
& PAGE_MASK
;
692 gtt_page_offset
= offset
& ~PAGE_MASK
;
693 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
694 data_page_offset
= data_ptr
& ~PAGE_MASK
;
696 page_length
= remain
;
697 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
698 page_length
= PAGE_SIZE
- gtt_page_offset
;
699 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
700 page_length
= PAGE_SIZE
- data_page_offset
;
702 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
703 gtt_page_base
, gtt_page_offset
,
704 user_pages
[data_page_index
],
708 remain
-= page_length
;
709 offset
+= page_length
;
710 data_ptr
+= page_length
;
714 i915_gem_object_unpin(obj
);
716 mutex_unlock(&dev
->struct_mutex
);
718 for (i
= 0; i
< pinned_pages
; i
++)
719 page_cache_release(user_pages
[i
]);
720 drm_free_large(user_pages
);
726 * This is the fast shmem pwrite path, which attempts to directly
727 * copy_from_user into the kmapped pages backing the object.
730 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
731 struct drm_i915_gem_pwrite
*args
,
732 struct drm_file
*file_priv
)
734 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
736 loff_t offset
, page_base
;
737 char __user
*user_data
;
738 int page_offset
, page_length
;
741 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
744 mutex_lock(&dev
->struct_mutex
);
746 ret
= i915_gem_object_get_pages(obj
, 0);
750 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
754 obj_priv
= to_intel_bo(obj
);
755 offset
= args
->offset
;
759 /* Operation in this page
761 * page_base = page offset within aperture
762 * page_offset = offset within page
763 * page_length = bytes to copy for this page
765 page_base
= (offset
& ~(PAGE_SIZE
-1));
766 page_offset
= offset
& (PAGE_SIZE
-1);
767 page_length
= remain
;
768 if ((page_offset
+ remain
) > PAGE_SIZE
)
769 page_length
= PAGE_SIZE
- page_offset
;
771 ret
= fast_shmem_write(obj_priv
->pages
,
772 page_base
, page_offset
,
773 user_data
, page_length
);
777 remain
-= page_length
;
778 user_data
+= page_length
;
779 offset
+= page_length
;
783 i915_gem_object_put_pages(obj
);
785 mutex_unlock(&dev
->struct_mutex
);
791 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
792 * the memory and maps it using kmap_atomic for copying.
794 * This avoids taking mmap_sem for faulting on the user's address while the
795 * struct_mutex is held.
798 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
799 struct drm_i915_gem_pwrite
*args
,
800 struct drm_file
*file_priv
)
802 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
803 struct mm_struct
*mm
= current
->mm
;
804 struct page
**user_pages
;
806 loff_t offset
, pinned_pages
, i
;
807 loff_t first_data_page
, last_data_page
, num_pages
;
808 int shmem_page_index
, shmem_page_offset
;
809 int data_page_index
, data_page_offset
;
812 uint64_t data_ptr
= args
->data_ptr
;
813 int do_bit17_swizzling
;
817 /* Pin the user pages containing the data. We can't fault while
818 * holding the struct mutex, and all of the pwrite implementations
819 * want to hold it while dereferencing the user data.
821 first_data_page
= data_ptr
/ PAGE_SIZE
;
822 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
823 num_pages
= last_data_page
- first_data_page
+ 1;
825 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
826 if (user_pages
== NULL
)
829 down_read(&mm
->mmap_sem
);
830 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
831 num_pages
, 0, 0, user_pages
, NULL
);
832 up_read(&mm
->mmap_sem
);
833 if (pinned_pages
< num_pages
) {
835 goto fail_put_user_pages
;
838 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
840 mutex_lock(&dev
->struct_mutex
);
842 ret
= i915_gem_object_get_pages_or_evict(obj
);
846 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
850 obj_priv
= to_intel_bo(obj
);
851 offset
= args
->offset
;
855 /* Operation in this page
857 * shmem_page_index = page number within shmem file
858 * shmem_page_offset = offset within page in shmem file
859 * data_page_index = page number in get_user_pages return
860 * data_page_offset = offset with data_page_index page.
861 * page_length = bytes to copy for this page
863 shmem_page_index
= offset
/ PAGE_SIZE
;
864 shmem_page_offset
= offset
& ~PAGE_MASK
;
865 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
866 data_page_offset
= data_ptr
& ~PAGE_MASK
;
868 page_length
= remain
;
869 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
870 page_length
= PAGE_SIZE
- shmem_page_offset
;
871 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
872 page_length
= PAGE_SIZE
- data_page_offset
;
874 if (do_bit17_swizzling
) {
875 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
877 user_pages
[data_page_index
],
882 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
884 user_pages
[data_page_index
],
889 remain
-= page_length
;
890 data_ptr
+= page_length
;
891 offset
+= page_length
;
895 i915_gem_object_put_pages(obj
);
897 mutex_unlock(&dev
->struct_mutex
);
899 for (i
= 0; i
< pinned_pages
; i
++)
900 page_cache_release(user_pages
[i
]);
901 drm_free_large(user_pages
);
907 * Writes data to the object referenced by handle.
909 * On error, the contents of the buffer that were to be modified are undefined.
912 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
913 struct drm_file
*file_priv
)
915 struct drm_i915_gem_pwrite
*args
= data
;
916 struct drm_gem_object
*obj
;
917 struct drm_i915_gem_object
*obj_priv
;
920 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
923 obj_priv
= to_intel_bo(obj
);
925 /* Bounds check destination.
927 * XXX: This could use review for overflow issues...
929 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
930 args
->offset
+ args
->size
> obj
->size
) {
931 drm_gem_object_unreference_unlocked(obj
);
935 /* We can only do the GTT pwrite on untiled buffers, as otherwise
936 * it would end up going through the fenced access, and we'll get
937 * different detiling behavior between reading and writing.
938 * pread/pwrite currently are reading and writing from the CPU
939 * perspective, requiring manual detiling by the client.
941 if (obj_priv
->phys_obj
)
942 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
943 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
944 dev
->gtt_total
!= 0 &&
945 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
946 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
947 if (ret
== -EFAULT
) {
948 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
951 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
952 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
954 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
955 if (ret
== -EFAULT
) {
956 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
963 DRM_INFO("pwrite failed %d\n", ret
);
966 drm_gem_object_unreference_unlocked(obj
);
972 * Called when user space prepares to use an object with the CPU, either
973 * through the mmap ioctl's mapping or a GTT mapping.
976 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
977 struct drm_file
*file_priv
)
979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
980 struct drm_i915_gem_set_domain
*args
= data
;
981 struct drm_gem_object
*obj
;
982 struct drm_i915_gem_object
*obj_priv
;
983 uint32_t read_domains
= args
->read_domains
;
984 uint32_t write_domain
= args
->write_domain
;
987 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
990 /* Only handle setting domains to types used by the CPU. */
991 if (write_domain
& I915_GEM_GPU_DOMAINS
)
994 if (read_domains
& I915_GEM_GPU_DOMAINS
)
997 /* Having something in the write domain implies it's in the read
998 * domain, and only that read domain. Enforce that in the request.
1000 if (write_domain
!= 0 && read_domains
!= write_domain
)
1003 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1006 obj_priv
= to_intel_bo(obj
);
1008 mutex_lock(&dev
->struct_mutex
);
1010 intel_mark_busy(dev
, obj
);
1013 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1014 obj
, obj
->size
, read_domains
, write_domain
);
1016 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1017 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1019 /* Update the LRU on the fence for the CPU access that's
1022 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1023 struct drm_i915_fence_reg
*reg
=
1024 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1025 list_move_tail(®
->lru_list
,
1026 &dev_priv
->mm
.fence_list
);
1029 /* Silently promote "you're not bound, there was nothing to do"
1030 * to success, since the client was just asking us to
1031 * make sure everything was done.
1036 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1039 drm_gem_object_unreference(obj
);
1040 mutex_unlock(&dev
->struct_mutex
);
1045 * Called when user space has done writes to this buffer
1048 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1049 struct drm_file
*file_priv
)
1051 struct drm_i915_gem_sw_finish
*args
= data
;
1052 struct drm_gem_object
*obj
;
1053 struct drm_i915_gem_object
*obj_priv
;
1056 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1059 mutex_lock(&dev
->struct_mutex
);
1060 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1062 mutex_unlock(&dev
->struct_mutex
);
1067 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1068 __func__
, args
->handle
, obj
, obj
->size
);
1070 obj_priv
= to_intel_bo(obj
);
1072 /* Pinned buffers may be scanout, so flush the cache */
1073 if (obj_priv
->pin_count
)
1074 i915_gem_object_flush_cpu_write_domain(obj
);
1076 drm_gem_object_unreference(obj
);
1077 mutex_unlock(&dev
->struct_mutex
);
1082 * Maps the contents of an object, returning the address it is mapped
1085 * While the mapping holds a reference on the contents of the object, it doesn't
1086 * imply a ref on the object itself.
1089 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1090 struct drm_file
*file_priv
)
1092 struct drm_i915_gem_mmap
*args
= data
;
1093 struct drm_gem_object
*obj
;
1097 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1100 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1104 offset
= args
->offset
;
1106 down_write(¤t
->mm
->mmap_sem
);
1107 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1108 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1110 up_write(¤t
->mm
->mmap_sem
);
1111 drm_gem_object_unreference_unlocked(obj
);
1112 if (IS_ERR((void *)addr
))
1115 args
->addr_ptr
= (uint64_t) addr
;
1121 * i915_gem_fault - fault a page into the GTT
1122 * vma: VMA in question
1125 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1126 * from userspace. The fault handler takes care of binding the object to
1127 * the GTT (if needed), allocating and programming a fence register (again,
1128 * only if needed based on whether the old reg is still valid or the object
1129 * is tiled) and inserting a new PTE into the faulting process.
1131 * Note that the faulting process may involve evicting existing objects
1132 * from the GTT and/or fence registers to make room. So performance may
1133 * suffer if the GTT working set is large or there are few fence registers
1136 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1138 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1139 struct drm_device
*dev
= obj
->dev
;
1140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1141 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1142 pgoff_t page_offset
;
1145 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1147 /* We don't use vmf->pgoff since that has the fake offset */
1148 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1151 /* Now bind it into the GTT if needed */
1152 mutex_lock(&dev
->struct_mutex
);
1153 if (!obj_priv
->gtt_space
) {
1154 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1158 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1160 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1165 /* Need a new fence register? */
1166 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1167 ret
= i915_gem_object_get_fence_reg(obj
);
1172 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1175 /* Finally, remap it using the new GTT offset */
1176 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1178 mutex_unlock(&dev
->struct_mutex
);
1183 return VM_FAULT_NOPAGE
;
1186 return VM_FAULT_OOM
;
1188 return VM_FAULT_SIGBUS
;
1193 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1194 * @obj: obj in question
1196 * GEM memory mapping works by handing back to userspace a fake mmap offset
1197 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1198 * up the object based on the offset and sets up the various memory mapping
1201 * This routine allocates and attaches a fake offset for @obj.
1204 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1206 struct drm_device
*dev
= obj
->dev
;
1207 struct drm_gem_mm
*mm
= dev
->mm_private
;
1208 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1209 struct drm_map_list
*list
;
1210 struct drm_local_map
*map
;
1213 /* Set the object up for mmap'ing */
1214 list
= &obj
->map_list
;
1215 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1220 map
->type
= _DRM_GEM
;
1221 map
->size
= obj
->size
;
1224 /* Get a DRM GEM mmap offset allocated... */
1225 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1226 obj
->size
/ PAGE_SIZE
, 0, 0);
1227 if (!list
->file_offset_node
) {
1228 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1233 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1234 obj
->size
/ PAGE_SIZE
, 0);
1235 if (!list
->file_offset_node
) {
1240 list
->hash
.key
= list
->file_offset_node
->start
;
1241 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1242 DRM_ERROR("failed to add to map hash\n");
1247 /* By now we should be all set, any drm_mmap request on the offset
1248 * below will get to our mmap & fault handler */
1249 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1254 drm_mm_put_block(list
->file_offset_node
);
1262 * i915_gem_release_mmap - remove physical page mappings
1263 * @obj: obj in question
1265 * Preserve the reservation of the mmapping with the DRM core code, but
1266 * relinquish ownership of the pages back to the system.
1268 * It is vital that we remove the page mapping if we have mapped a tiled
1269 * object through the GTT and then lose the fence register due to
1270 * resource pressure. Similarly if the object has been moved out of the
1271 * aperture, than pages mapped into userspace must be revoked. Removing the
1272 * mapping will then trigger a page fault on the next user access, allowing
1273 * fixup by i915_gem_fault().
1276 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1278 struct drm_device
*dev
= obj
->dev
;
1279 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1281 if (dev
->dev_mapping
)
1282 unmap_mapping_range(dev
->dev_mapping
,
1283 obj_priv
->mmap_offset
, obj
->size
, 1);
1287 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1289 struct drm_device
*dev
= obj
->dev
;
1290 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1291 struct drm_gem_mm
*mm
= dev
->mm_private
;
1292 struct drm_map_list
*list
;
1294 list
= &obj
->map_list
;
1295 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1297 if (list
->file_offset_node
) {
1298 drm_mm_put_block(list
->file_offset_node
);
1299 list
->file_offset_node
= NULL
;
1307 obj_priv
->mmap_offset
= 0;
1311 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1312 * @obj: object to check
1314 * Return the required GTT alignment for an object, taking into account
1315 * potential fence register mapping if needed.
1318 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1320 struct drm_device
*dev
= obj
->dev
;
1321 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1325 * Minimum alignment is 4k (GTT page size), but might be greater
1326 * if a fence register is needed for the object.
1328 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1332 * Previous chips need to be aligned to the size of the smallest
1333 * fence register that can contain the object.
1340 for (i
= start
; i
< obj
->size
; i
<<= 1)
1347 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1349 * @data: GTT mapping ioctl data
1350 * @file_priv: GEM object info
1352 * Simply returns the fake offset to userspace so it can mmap it.
1353 * The mmap call will end up in drm_gem_mmap(), which will set things
1354 * up so we can get faults in the handler above.
1356 * The fault handler will take care of binding the object into the GTT
1357 * (since it may have been evicted to make room for something), allocating
1358 * a fence register, and mapping the appropriate aperture address into
1362 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1363 struct drm_file
*file_priv
)
1365 struct drm_i915_gem_mmap_gtt
*args
= data
;
1366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1367 struct drm_gem_object
*obj
;
1368 struct drm_i915_gem_object
*obj_priv
;
1371 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1374 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1378 mutex_lock(&dev
->struct_mutex
);
1380 obj_priv
= to_intel_bo(obj
);
1382 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1383 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1384 drm_gem_object_unreference(obj
);
1385 mutex_unlock(&dev
->struct_mutex
);
1390 if (!obj_priv
->mmap_offset
) {
1391 ret
= i915_gem_create_mmap_offset(obj
);
1393 drm_gem_object_unreference(obj
);
1394 mutex_unlock(&dev
->struct_mutex
);
1399 args
->offset
= obj_priv
->mmap_offset
;
1402 * Pull it into the GTT so that we have a page list (makes the
1403 * initial fault faster and any subsequent flushing possible).
1405 if (!obj_priv
->agp_mem
) {
1406 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1408 drm_gem_object_unreference(obj
);
1409 mutex_unlock(&dev
->struct_mutex
);
1412 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1415 drm_gem_object_unreference(obj
);
1416 mutex_unlock(&dev
->struct_mutex
);
1422 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1424 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1425 int page_count
= obj
->size
/ PAGE_SIZE
;
1428 BUG_ON(obj_priv
->pages_refcount
== 0);
1429 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1431 if (--obj_priv
->pages_refcount
!= 0)
1434 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1435 i915_gem_object_save_bit_17_swizzle(obj
);
1437 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1438 obj_priv
->dirty
= 0;
1440 for (i
= 0; i
< page_count
; i
++) {
1441 if (obj_priv
->dirty
)
1442 set_page_dirty(obj_priv
->pages
[i
]);
1444 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1445 mark_page_accessed(obj_priv
->pages
[i
]);
1447 page_cache_release(obj_priv
->pages
[i
]);
1449 obj_priv
->dirty
= 0;
1451 drm_free_large(obj_priv
->pages
);
1452 obj_priv
->pages
= NULL
;
1456 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
,
1457 struct intel_ring_buffer
*ring
)
1459 struct drm_device
*dev
= obj
->dev
;
1460 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1461 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1462 BUG_ON(ring
== NULL
);
1463 obj_priv
->ring
= ring
;
1465 /* Add a reference if we're newly entering the active list. */
1466 if (!obj_priv
->active
) {
1467 drm_gem_object_reference(obj
);
1468 obj_priv
->active
= 1;
1470 /* Move from whatever list we were on to the tail of execution. */
1471 spin_lock(&dev_priv
->mm
.active_list_lock
);
1472 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1473 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1474 obj_priv
->last_rendering_seqno
= seqno
;
1478 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1480 struct drm_device
*dev
= obj
->dev
;
1481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1482 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1484 BUG_ON(!obj_priv
->active
);
1485 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1486 obj_priv
->last_rendering_seqno
= 0;
1489 /* Immediately discard the backing storage */
1491 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1493 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1494 struct inode
*inode
;
1496 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1497 if (inode
->i_op
->truncate
)
1498 inode
->i_op
->truncate (inode
);
1500 obj_priv
->madv
= __I915_MADV_PURGED
;
1504 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1506 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1510 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1512 struct drm_device
*dev
= obj
->dev
;
1513 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1514 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1516 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1517 if (obj_priv
->pin_count
!= 0)
1518 list_del_init(&obj_priv
->list
);
1520 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1522 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1524 obj_priv
->last_rendering_seqno
= 0;
1525 obj_priv
->ring
= NULL
;
1526 if (obj_priv
->active
) {
1527 obj_priv
->active
= 0;
1528 drm_gem_object_unreference(obj
);
1530 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1534 i915_gem_process_flushing_list(struct drm_device
*dev
,
1535 uint32_t flush_domains
, uint32_t seqno
,
1536 struct intel_ring_buffer
*ring
)
1538 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1539 struct drm_i915_gem_object
*obj_priv
, *next
;
1541 list_for_each_entry_safe(obj_priv
, next
,
1542 &dev_priv
->mm
.gpu_write_list
,
1544 struct drm_gem_object
*obj
= &obj_priv
->base
;
1546 if ((obj
->write_domain
& flush_domains
) ==
1547 obj
->write_domain
&&
1548 obj_priv
->ring
->ring_flag
== ring
->ring_flag
) {
1549 uint32_t old_write_domain
= obj
->write_domain
;
1551 obj
->write_domain
= 0;
1552 list_del_init(&obj_priv
->gpu_write_list
);
1553 i915_gem_object_move_to_active(obj
, seqno
, ring
);
1555 /* update the fence lru list */
1556 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1557 struct drm_i915_fence_reg
*reg
=
1558 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1559 list_move_tail(®
->lru_list
,
1560 &dev_priv
->mm
.fence_list
);
1563 trace_i915_gem_object_change_domain(obj
,
1571 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1572 uint32_t flush_domains
, struct intel_ring_buffer
*ring
)
1574 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1575 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1576 struct drm_i915_gem_request
*request
;
1580 if (file_priv
!= NULL
)
1581 i915_file_priv
= file_priv
->driver_priv
;
1583 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1584 if (request
== NULL
)
1587 seqno
= ring
->add_request(dev
, ring
, file_priv
, flush_domains
);
1589 request
->seqno
= seqno
;
1590 request
->ring
= ring
;
1591 request
->emitted_jiffies
= jiffies
;
1592 was_empty
= list_empty(&ring
->request_list
);
1593 list_add_tail(&request
->list
, &ring
->request_list
);
1595 if (i915_file_priv
) {
1596 list_add_tail(&request
->client_list
,
1597 &i915_file_priv
->mm
.request_list
);
1599 INIT_LIST_HEAD(&request
->client_list
);
1602 /* Associate any objects on the flushing list matching the write
1603 * domain we're flushing with our flush.
1605 if (flush_domains
!= 0)
1606 i915_gem_process_flushing_list(dev
, flush_domains
, seqno
, ring
);
1608 if (!dev_priv
->mm
.suspended
) {
1609 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1611 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1617 * Command execution barrier
1619 * Ensures that all commands in the ring are finished
1620 * before signalling the CPU
1623 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1625 uint32_t flush_domains
= 0;
1627 /* The sampler always gets flushed on i965 (sigh) */
1629 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1631 ring
->flush(dev
, ring
,
1632 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1633 return flush_domains
;
1637 * Moves buffers associated only with the given active seqno from the active
1638 * to inactive list, potentially freeing them.
1641 i915_gem_retire_request(struct drm_device
*dev
,
1642 struct drm_i915_gem_request
*request
)
1644 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1646 trace_i915_gem_request_retire(dev
, request
->seqno
);
1648 /* Move any buffers on the active list that are no longer referenced
1649 * by the ringbuffer to the flushing/inactive lists as appropriate.
1651 spin_lock(&dev_priv
->mm
.active_list_lock
);
1652 while (!list_empty(&request
->ring
->active_list
)) {
1653 struct drm_gem_object
*obj
;
1654 struct drm_i915_gem_object
*obj_priv
;
1656 obj_priv
= list_first_entry(&request
->ring
->active_list
,
1657 struct drm_i915_gem_object
,
1659 obj
= &obj_priv
->base
;
1661 /* If the seqno being retired doesn't match the oldest in the
1662 * list, then the oldest in the list must still be newer than
1665 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1669 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1670 __func__
, request
->seqno
, obj
);
1673 if (obj
->write_domain
!= 0)
1674 i915_gem_object_move_to_flushing(obj
);
1676 /* Take a reference on the object so it won't be
1677 * freed while the spinlock is held. The list
1678 * protection for this spinlock is safe when breaking
1679 * the lock like this since the next thing we do
1680 * is just get the head of the list again.
1682 drm_gem_object_reference(obj
);
1683 i915_gem_object_move_to_inactive(obj
);
1684 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1685 drm_gem_object_unreference(obj
);
1686 spin_lock(&dev_priv
->mm
.active_list_lock
);
1690 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1694 * Returns true if seq1 is later than seq2.
1697 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1699 return (int32_t)(seq1
- seq2
) >= 0;
1703 i915_get_gem_seqno(struct drm_device
*dev
,
1704 struct intel_ring_buffer
*ring
)
1706 return ring
->get_gem_seqno(dev
, ring
);
1710 * This function clears the request list as sequence numbers are passed.
1713 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1714 struct intel_ring_buffer
*ring
)
1716 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1719 if (!ring
->status_page
.page_addr
1720 || list_empty(&ring
->request_list
))
1723 seqno
= i915_get_gem_seqno(dev
, ring
);
1725 while (!list_empty(&ring
->request_list
)) {
1726 struct drm_i915_gem_request
*request
;
1727 uint32_t retiring_seqno
;
1729 request
= list_first_entry(&ring
->request_list
,
1730 struct drm_i915_gem_request
,
1732 retiring_seqno
= request
->seqno
;
1734 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1735 atomic_read(&dev_priv
->mm
.wedged
)) {
1736 i915_gem_retire_request(dev
, request
);
1738 list_del(&request
->list
);
1739 list_del(&request
->client_list
);
1745 if (unlikely (dev_priv
->trace_irq_seqno
&&
1746 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1748 ring
->user_irq_put(dev
, ring
);
1749 dev_priv
->trace_irq_seqno
= 0;
1754 i915_gem_retire_requests(struct drm_device
*dev
)
1756 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1758 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1759 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1761 /* We must be careful that during unbind() we do not
1762 * accidentally infinitely recurse into retire requests.
1764 * retire -> free -> unbind -> wait -> retire_ring
1766 list_for_each_entry_safe(obj_priv
, tmp
,
1767 &dev_priv
->mm
.deferred_free_list
,
1769 i915_gem_free_object_tail(&obj_priv
->base
);
1772 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1774 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1778 i915_gem_retire_work_handler(struct work_struct
*work
)
1780 drm_i915_private_t
*dev_priv
;
1781 struct drm_device
*dev
;
1783 dev_priv
= container_of(work
, drm_i915_private_t
,
1784 mm
.retire_work
.work
);
1785 dev
= dev_priv
->dev
;
1787 mutex_lock(&dev
->struct_mutex
);
1788 i915_gem_retire_requests(dev
);
1790 if (!dev_priv
->mm
.suspended
&&
1791 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1793 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1794 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1795 mutex_unlock(&dev
->struct_mutex
);
1799 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1800 int interruptible
, struct intel_ring_buffer
*ring
)
1802 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1808 if (atomic_read(&dev_priv
->mm
.wedged
))
1811 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1812 if (HAS_PCH_SPLIT(dev
))
1813 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1815 ier
= I915_READ(IER
);
1817 DRM_ERROR("something (likely vbetool) disabled "
1818 "interrupts, re-enabling\n");
1819 i915_driver_irq_preinstall(dev
);
1820 i915_driver_irq_postinstall(dev
);
1823 trace_i915_gem_request_wait_begin(dev
, seqno
);
1825 ring
->waiting_gem_seqno
= seqno
;
1826 ring
->user_irq_get(dev
, ring
);
1828 ret
= wait_event_interruptible(ring
->irq_queue
,
1830 ring
->get_gem_seqno(dev
, ring
), seqno
)
1831 || atomic_read(&dev_priv
->mm
.wedged
));
1833 wait_event(ring
->irq_queue
,
1835 ring
->get_gem_seqno(dev
, ring
), seqno
)
1836 || atomic_read(&dev_priv
->mm
.wedged
));
1838 ring
->user_irq_put(dev
, ring
);
1839 ring
->waiting_gem_seqno
= 0;
1841 trace_i915_gem_request_wait_end(dev
, seqno
);
1843 if (atomic_read(&dev_priv
->mm
.wedged
))
1846 if (ret
&& ret
!= -ERESTARTSYS
)
1847 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1848 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
));
1850 /* Directly dispatch request retiring. While we have the work queue
1851 * to handle this, the waiter on a request often wants an associated
1852 * buffer to have made it to the inactive list, and we would need
1853 * a separate wait queue to handle that.
1856 i915_gem_retire_requests_ring(dev
, ring
);
1862 * Waits for a sequence number to be signaled, and cleans up the
1863 * request and object lists appropriately for that event.
1866 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1867 struct intel_ring_buffer
*ring
)
1869 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1873 i915_gem_flush(struct drm_device
*dev
,
1874 uint32_t invalidate_domains
,
1875 uint32_t flush_domains
)
1877 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1878 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1879 drm_agp_chipset_flush(dev
);
1880 dev_priv
->render_ring
.flush(dev
, &dev_priv
->render_ring
,
1885 dev_priv
->bsd_ring
.flush(dev
, &dev_priv
->bsd_ring
,
1891 i915_gem_flush_ring(struct drm_device
*dev
,
1892 uint32_t invalidate_domains
,
1893 uint32_t flush_domains
,
1894 struct intel_ring_buffer
*ring
)
1896 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1897 drm_agp_chipset_flush(dev
);
1898 ring
->flush(dev
, ring
,
1904 * Ensures that all rendering to the object has completed and the object is
1905 * safe to unbind from the GTT or access from the CPU.
1908 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1910 struct drm_device
*dev
= obj
->dev
;
1911 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1914 /* This function only exists to support waiting for existing rendering,
1915 * not for emitting required flushes.
1917 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1919 /* If there is rendering queued on the buffer being evicted, wait for
1922 if (obj_priv
->active
) {
1924 DRM_INFO("%s: object %p wait for seqno %08x\n",
1925 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1927 ret
= i915_wait_request(dev
,
1928 obj_priv
->last_rendering_seqno
, obj_priv
->ring
);
1937 * Unbinds an object from the GTT aperture.
1940 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1942 struct drm_device
*dev
= obj
->dev
;
1943 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1944 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1948 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1949 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1951 if (obj_priv
->gtt_space
== NULL
)
1954 if (obj_priv
->pin_count
!= 0) {
1955 DRM_ERROR("Attempting to unbind pinned buffer\n");
1959 /* blow away mappings if mapped through GTT */
1960 i915_gem_release_mmap(obj
);
1962 /* Move the object to the CPU domain to ensure that
1963 * any possible CPU writes while it's not in the GTT
1964 * are flushed when we go to remap it. This will
1965 * also ensure that all pending GPU writes are finished
1968 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1969 if (ret
== -ERESTARTSYS
)
1971 /* Continue on if we fail due to EIO, the GPU is hung so we
1972 * should be safe and we need to cleanup or else we might
1973 * cause memory corruption through use-after-free.
1976 BUG_ON(obj_priv
->active
);
1978 /* release the fence reg _after_ flushing */
1979 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1980 i915_gem_clear_fence_reg(obj
);
1982 if (obj_priv
->agp_mem
!= NULL
) {
1983 drm_unbind_agp(obj_priv
->agp_mem
);
1984 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1985 obj_priv
->agp_mem
= NULL
;
1988 i915_gem_object_put_pages(obj
);
1989 BUG_ON(obj_priv
->pages_refcount
);
1991 if (obj_priv
->gtt_space
) {
1992 atomic_dec(&dev
->gtt_count
);
1993 atomic_sub(obj
->size
, &dev
->gtt_memory
);
1995 drm_mm_put_block(obj_priv
->gtt_space
);
1996 obj_priv
->gtt_space
= NULL
;
1999 /* Remove ourselves from the LRU list if present. */
2000 spin_lock(&dev_priv
->mm
.active_list_lock
);
2001 if (!list_empty(&obj_priv
->list
))
2002 list_del_init(&obj_priv
->list
);
2003 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2005 if (i915_gem_object_is_purgeable(obj_priv
))
2006 i915_gem_object_truncate(obj
);
2008 trace_i915_gem_object_unbind(obj
);
2013 static struct drm_gem_object
*
2014 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2016 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2017 struct drm_i915_gem_object
*obj_priv
;
2018 struct drm_gem_object
*best
= NULL
;
2019 struct drm_gem_object
*first
= NULL
;
2021 /* Try to find the smallest clean object */
2022 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2023 struct drm_gem_object
*obj
= &obj_priv
->base
;
2024 if (obj
->size
>= min_size
) {
2025 if ((!obj_priv
->dirty
||
2026 i915_gem_object_is_purgeable(obj_priv
)) &&
2027 (!best
|| obj
->size
< best
->size
)) {
2029 if (best
->size
== min_size
)
2037 return best
? best
: first
;
2041 i915_gpu_idle(struct drm_device
*dev
)
2043 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2045 uint32_t seqno1
, seqno2
;
2048 spin_lock(&dev_priv
->mm
.active_list_lock
);
2049 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2050 list_empty(&dev_priv
->render_ring
.active_list
) &&
2052 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2053 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2058 /* Flush everything onto the inactive list. */
2059 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2060 seqno1
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2061 &dev_priv
->render_ring
);
2064 ret
= i915_wait_request(dev
, seqno1
, &dev_priv
->render_ring
);
2067 seqno2
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2068 &dev_priv
->bsd_ring
);
2072 ret
= i915_wait_request(dev
, seqno2
, &dev_priv
->bsd_ring
);
2082 i915_gem_evict_everything(struct drm_device
*dev
)
2084 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2088 spin_lock(&dev_priv
->mm
.active_list_lock
);
2089 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2090 list_empty(&dev_priv
->mm
.flushing_list
) &&
2091 list_empty(&dev_priv
->render_ring
.active_list
) &&
2093 || list_empty(&dev_priv
->bsd_ring
.active_list
)));
2094 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2099 /* Flush everything (on to the inactive lists) and evict */
2100 ret
= i915_gpu_idle(dev
);
2104 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2106 ret
= i915_gem_evict_from_inactive_list(dev
);
2110 spin_lock(&dev_priv
->mm
.active_list_lock
);
2111 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2112 list_empty(&dev_priv
->mm
.flushing_list
) &&
2113 list_empty(&dev_priv
->render_ring
.active_list
) &&
2115 || list_empty(&dev_priv
->bsd_ring
.active_list
)));
2116 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2117 BUG_ON(!lists_empty
);
2123 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2125 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2126 struct drm_gem_object
*obj
;
2129 struct intel_ring_buffer
*render_ring
= &dev_priv
->render_ring
;
2130 struct intel_ring_buffer
*bsd_ring
= &dev_priv
->bsd_ring
;
2132 i915_gem_retire_requests(dev
);
2134 /* If there's an inactive buffer available now, grab it
2137 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2139 struct drm_i915_gem_object
*obj_priv
;
2142 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2144 obj_priv
= to_intel_bo(obj
);
2145 BUG_ON(obj_priv
->pin_count
!= 0);
2146 BUG_ON(obj_priv
->active
);
2148 /* Wait on the rendering and unbind the buffer. */
2149 return i915_gem_object_unbind(obj
);
2152 /* If we didn't get anything, but the ring is still processing
2153 * things, wait for the next to finish and hopefully leave us
2154 * a buffer to evict.
2156 if (!list_empty(&render_ring
->request_list
)) {
2157 struct drm_i915_gem_request
*request
;
2159 request
= list_first_entry(&render_ring
->request_list
,
2160 struct drm_i915_gem_request
,
2163 ret
= i915_wait_request(dev
,
2164 request
->seqno
, request
->ring
);
2171 if (HAS_BSD(dev
) && !list_empty(&bsd_ring
->request_list
)) {
2172 struct drm_i915_gem_request
*request
;
2174 request
= list_first_entry(&bsd_ring
->request_list
,
2175 struct drm_i915_gem_request
,
2178 ret
= i915_wait_request(dev
,
2179 request
->seqno
, request
->ring
);
2186 /* If we didn't have anything on the request list but there
2187 * are buffers awaiting a flush, emit one and try again.
2188 * When we wait on it, those buffers waiting for that flush
2189 * will get moved to inactive.
2191 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2192 struct drm_i915_gem_object
*obj_priv
;
2194 /* Find an object that we can immediately reuse */
2195 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2196 obj
= &obj_priv
->base
;
2197 if (obj
->size
>= min_size
)
2206 i915_gem_flush_ring(dev
,
2210 seqno
= i915_add_request(dev
, NULL
,
2219 /* If we didn't do any of the above, there's no single buffer
2220 * large enough to swap out for the new one, so just evict
2221 * everything and start again. (This should be rare.)
2223 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2224 return i915_gem_evict_from_inactive_list(dev
);
2226 return i915_gem_evict_everything(dev
);
2231 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2234 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2236 struct address_space
*mapping
;
2237 struct inode
*inode
;
2240 BUG_ON(obj_priv
->pages_refcount
2241 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2243 if (obj_priv
->pages_refcount
++ != 0)
2246 /* Get the list of pages out of our struct file. They'll be pinned
2247 * at this point until we release them.
2249 page_count
= obj
->size
/ PAGE_SIZE
;
2250 BUG_ON(obj_priv
->pages
!= NULL
);
2251 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2252 if (obj_priv
->pages
== NULL
) {
2253 obj_priv
->pages_refcount
--;
2257 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2258 mapping
= inode
->i_mapping
;
2259 for (i
= 0; i
< page_count
; i
++) {
2260 page
= read_cache_page_gfp(mapping
, i
,
2268 obj_priv
->pages
[i
] = page
;
2271 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2272 i915_gem_object_do_bit_17_swizzle(obj
);
2278 page_cache_release(obj_priv
->pages
[i
]);
2280 drm_free_large(obj_priv
->pages
);
2281 obj_priv
->pages
= NULL
;
2282 obj_priv
->pages_refcount
--;
2283 return PTR_ERR(page
);
2286 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2288 struct drm_gem_object
*obj
= reg
->obj
;
2289 struct drm_device
*dev
= obj
->dev
;
2290 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2291 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2292 int regnum
= obj_priv
->fence_reg
;
2295 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2297 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2298 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2299 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2301 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2302 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2303 val
|= I965_FENCE_REG_VALID
;
2305 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2308 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2310 struct drm_gem_object
*obj
= reg
->obj
;
2311 struct drm_device
*dev
= obj
->dev
;
2312 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2313 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2314 int regnum
= obj_priv
->fence_reg
;
2317 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2319 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2320 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2321 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2322 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2323 val
|= I965_FENCE_REG_VALID
;
2325 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2328 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2330 struct drm_gem_object
*obj
= reg
->obj
;
2331 struct drm_device
*dev
= obj
->dev
;
2332 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2333 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2334 int regnum
= obj_priv
->fence_reg
;
2336 uint32_t fence_reg
, val
;
2339 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2340 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2341 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2342 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2346 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2347 HAS_128_BYTE_Y_TILING(dev
))
2352 /* Note: pitch better be a power of two tile widths */
2353 pitch_val
= obj_priv
->stride
/ tile_width
;
2354 pitch_val
= ffs(pitch_val
) - 1;
2356 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2357 HAS_128_BYTE_Y_TILING(dev
))
2358 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2360 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2362 val
= obj_priv
->gtt_offset
;
2363 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2364 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2365 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2366 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2367 val
|= I830_FENCE_REG_VALID
;
2370 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2372 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2373 I915_WRITE(fence_reg
, val
);
2376 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2378 struct drm_gem_object
*obj
= reg
->obj
;
2379 struct drm_device
*dev
= obj
->dev
;
2380 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2381 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2382 int regnum
= obj_priv
->fence_reg
;
2385 uint32_t fence_size_bits
;
2387 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2388 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2389 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2390 __func__
, obj_priv
->gtt_offset
);
2394 pitch_val
= obj_priv
->stride
/ 128;
2395 pitch_val
= ffs(pitch_val
) - 1;
2396 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2398 val
= obj_priv
->gtt_offset
;
2399 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2400 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2401 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2402 WARN_ON(fence_size_bits
& ~0x00000f00);
2403 val
|= fence_size_bits
;
2404 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2405 val
|= I830_FENCE_REG_VALID
;
2407 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2410 static int i915_find_fence_reg(struct drm_device
*dev
)
2412 struct drm_i915_fence_reg
*reg
= NULL
;
2413 struct drm_i915_gem_object
*obj_priv
= NULL
;
2414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2415 struct drm_gem_object
*obj
= NULL
;
2418 /* First try to find a free reg */
2420 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2421 reg
= &dev_priv
->fence_regs
[i
];
2425 obj_priv
= to_intel_bo(reg
->obj
);
2426 if (!obj_priv
->pin_count
)
2433 /* None available, try to steal one or wait for a user to finish */
2434 i
= I915_FENCE_REG_NONE
;
2435 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2438 obj_priv
= to_intel_bo(obj
);
2440 if (obj_priv
->pin_count
)
2444 i
= obj_priv
->fence_reg
;
2448 BUG_ON(i
== I915_FENCE_REG_NONE
);
2450 /* We only have a reference on obj from the active list. put_fence_reg
2451 * might drop that one, causing a use-after-free in it. So hold a
2452 * private reference to obj like the other callers of put_fence_reg
2453 * (set_tiling ioctl) do. */
2454 drm_gem_object_reference(obj
);
2455 ret
= i915_gem_object_put_fence_reg(obj
);
2456 drm_gem_object_unreference(obj
);
2464 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2465 * @obj: object to map through a fence reg
2467 * When mapping objects through the GTT, userspace wants to be able to write
2468 * to them without having to worry about swizzling if the object is tiled.
2470 * This function walks the fence regs looking for a free one for @obj,
2471 * stealing one if it can't find any.
2473 * It then sets up the reg based on the object's properties: address, pitch
2474 * and tiling format.
2477 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2479 struct drm_device
*dev
= obj
->dev
;
2480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2481 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2482 struct drm_i915_fence_reg
*reg
= NULL
;
2485 /* Just update our place in the LRU if our fence is getting used. */
2486 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2487 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2488 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2492 switch (obj_priv
->tiling_mode
) {
2493 case I915_TILING_NONE
:
2494 WARN(1, "allocating a fence for non-tiled object?\n");
2497 if (!obj_priv
->stride
)
2499 WARN((obj_priv
->stride
& (512 - 1)),
2500 "object 0x%08x is X tiled but has non-512B pitch\n",
2501 obj_priv
->gtt_offset
);
2504 if (!obj_priv
->stride
)
2506 WARN((obj_priv
->stride
& (128 - 1)),
2507 "object 0x%08x is Y tiled but has non-128B pitch\n",
2508 obj_priv
->gtt_offset
);
2512 ret
= i915_find_fence_reg(dev
);
2516 obj_priv
->fence_reg
= ret
;
2517 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2518 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2523 sandybridge_write_fence_reg(reg
);
2524 else if (IS_I965G(dev
))
2525 i965_write_fence_reg(reg
);
2526 else if (IS_I9XX(dev
))
2527 i915_write_fence_reg(reg
);
2529 i830_write_fence_reg(reg
);
2531 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2532 obj_priv
->tiling_mode
);
2538 * i915_gem_clear_fence_reg - clear out fence register info
2539 * @obj: object to clear
2541 * Zeroes out the fence register itself and clears out the associated
2542 * data structures in dev_priv and obj_priv.
2545 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2547 struct drm_device
*dev
= obj
->dev
;
2548 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2549 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2550 struct drm_i915_fence_reg
*reg
=
2551 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2554 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2555 (obj_priv
->fence_reg
* 8), 0);
2556 } else if (IS_I965G(dev
)) {
2557 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2561 if (obj_priv
->fence_reg
< 8)
2562 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2564 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2567 I915_WRITE(fence_reg
, 0);
2571 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2572 list_del_init(®
->lru_list
);
2576 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2577 * to the buffer to finish, and then resets the fence register.
2578 * @obj: tiled object holding a fence register.
2580 * Zeroes out the fence register itself and clears out the associated
2581 * data structures in dev_priv and obj_priv.
2584 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2586 struct drm_device
*dev
= obj
->dev
;
2587 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2589 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2592 /* If we've changed tiling, GTT-mappings of the object
2593 * need to re-fault to ensure that the correct fence register
2594 * setup is in place.
2596 i915_gem_release_mmap(obj
);
2598 /* On the i915, GPU access to tiled buffers is via a fence,
2599 * therefore we must wait for any outstanding access to complete
2600 * before clearing the fence.
2602 if (!IS_I965G(dev
)) {
2605 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2609 ret
= i915_gem_object_wait_rendering(obj
);
2614 i915_gem_object_flush_gtt_write_domain(obj
);
2615 i915_gem_clear_fence_reg (obj
);
2621 * Finds free space in the GTT aperture and binds the object there.
2624 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2626 struct drm_device
*dev
= obj
->dev
;
2627 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2628 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2629 struct drm_mm_node
*free_space
;
2630 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2633 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2634 DRM_ERROR("Attempting to bind a purgeable object\n");
2639 alignment
= i915_gem_get_gtt_alignment(obj
);
2640 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2641 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2645 /* If the object is bigger than the entire aperture, reject it early
2646 * before evicting everything in a vain attempt to find space.
2648 if (obj
->size
> dev
->gtt_total
) {
2649 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2654 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2655 obj
->size
, alignment
, 0);
2656 if (free_space
!= NULL
) {
2657 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2659 if (obj_priv
->gtt_space
!= NULL
)
2660 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2662 if (obj_priv
->gtt_space
== NULL
) {
2663 /* If the gtt is empty and we're still having trouble
2664 * fitting our object in, we're out of memory.
2667 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2669 ret
= i915_gem_evict_something(dev
, obj
->size
);
2677 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2678 obj
->size
, obj_priv
->gtt_offset
);
2680 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2682 drm_mm_put_block(obj_priv
->gtt_space
);
2683 obj_priv
->gtt_space
= NULL
;
2685 if (ret
== -ENOMEM
) {
2686 /* first try to clear up some space from the GTT */
2687 ret
= i915_gem_evict_something(dev
, obj
->size
);
2689 /* now try to shrink everyone else */
2704 /* Create an AGP memory structure pointing at our pages, and bind it
2707 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2709 obj
->size
>> PAGE_SHIFT
,
2710 obj_priv
->gtt_offset
,
2711 obj_priv
->agp_type
);
2712 if (obj_priv
->agp_mem
== NULL
) {
2713 i915_gem_object_put_pages(obj
);
2714 drm_mm_put_block(obj_priv
->gtt_space
);
2715 obj_priv
->gtt_space
= NULL
;
2717 ret
= i915_gem_evict_something(dev
, obj
->size
);
2723 atomic_inc(&dev
->gtt_count
);
2724 atomic_add(obj
->size
, &dev
->gtt_memory
);
2726 /* Assert that the object is not currently in any GPU domain. As it
2727 * wasn't in the GTT, there shouldn't be any way it could have been in
2730 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2731 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2733 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2739 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2741 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2743 /* If we don't have a page list set up, then we're not pinned
2744 * to GPU, and we can ignore the cache flush because it'll happen
2745 * again at bind time.
2747 if (obj_priv
->pages
== NULL
)
2750 trace_i915_gem_object_clflush(obj
);
2752 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2755 /** Flushes any GPU write domain for the object if it's dirty. */
2757 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2759 struct drm_device
*dev
= obj
->dev
;
2760 uint32_t old_write_domain
;
2761 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2763 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2766 /* Queue the GPU write cache flushing we need. */
2767 old_write_domain
= obj
->write_domain
;
2768 i915_gem_flush(dev
, 0, obj
->write_domain
);
2769 if (i915_add_request(dev
, NULL
, obj
->write_domain
, obj_priv
->ring
) == 0)
2772 trace_i915_gem_object_change_domain(obj
,
2778 /** Flushes the GTT write domain for the object if it's dirty. */
2780 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2782 uint32_t old_write_domain
;
2784 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2787 /* No actual flushing is required for the GTT write domain. Writes
2788 * to it immediately go to main memory as far as we know, so there's
2789 * no chipset flush. It also doesn't land in render cache.
2791 old_write_domain
= obj
->write_domain
;
2792 obj
->write_domain
= 0;
2794 trace_i915_gem_object_change_domain(obj
,
2799 /** Flushes the CPU write domain for the object if it's dirty. */
2801 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2803 struct drm_device
*dev
= obj
->dev
;
2804 uint32_t old_write_domain
;
2806 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2809 i915_gem_clflush_object(obj
);
2810 drm_agp_chipset_flush(dev
);
2811 old_write_domain
= obj
->write_domain
;
2812 obj
->write_domain
= 0;
2814 trace_i915_gem_object_change_domain(obj
,
2820 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2824 switch (obj
->write_domain
) {
2825 case I915_GEM_DOMAIN_GTT
:
2826 i915_gem_object_flush_gtt_write_domain(obj
);
2828 case I915_GEM_DOMAIN_CPU
:
2829 i915_gem_object_flush_cpu_write_domain(obj
);
2832 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2840 * Moves a single object to the GTT read, and possibly write domain.
2842 * This function returns when the move is complete, including waiting on
2846 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2848 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2849 uint32_t old_write_domain
, old_read_domains
;
2852 /* Not valid to be called on unbound objects. */
2853 if (obj_priv
->gtt_space
== NULL
)
2856 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2860 /* Wait on any GPU rendering and flushing to occur. */
2861 ret
= i915_gem_object_wait_rendering(obj
);
2865 old_write_domain
= obj
->write_domain
;
2866 old_read_domains
= obj
->read_domains
;
2868 /* If we're writing through the GTT domain, then CPU and GPU caches
2869 * will need to be invalidated at next use.
2872 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2874 i915_gem_object_flush_cpu_write_domain(obj
);
2876 /* It should now be out of any other write domains, and we can update
2877 * the domain values for our changes.
2879 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2880 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2882 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2883 obj_priv
->dirty
= 1;
2886 trace_i915_gem_object_change_domain(obj
,
2894 * Prepare buffer for display plane. Use uninterruptible for possible flush
2895 * wait, as in modesetting process we're not supposed to be interrupted.
2898 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2900 struct drm_device
*dev
= obj
->dev
;
2901 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2902 uint32_t old_write_domain
, old_read_domains
;
2905 /* Not valid to be called on unbound objects. */
2906 if (obj_priv
->gtt_space
== NULL
)
2909 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2913 /* Wait on any GPU rendering and flushing to occur. */
2914 if (obj_priv
->active
) {
2916 DRM_INFO("%s: object %p wait for seqno %08x\n",
2917 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2919 ret
= i915_do_wait_request(dev
,
2920 obj_priv
->last_rendering_seqno
,
2927 i915_gem_object_flush_cpu_write_domain(obj
);
2929 old_write_domain
= obj
->write_domain
;
2930 old_read_domains
= obj
->read_domains
;
2932 /* It should now be out of any other write domains, and we can update
2933 * the domain values for our changes.
2935 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2936 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2937 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2938 obj_priv
->dirty
= 1;
2940 trace_i915_gem_object_change_domain(obj
,
2948 * Moves a single object to the CPU read, and possibly write domain.
2950 * This function returns when the move is complete, including waiting on
2954 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2956 uint32_t old_write_domain
, old_read_domains
;
2959 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2963 /* Wait on any GPU rendering and flushing to occur. */
2964 ret
= i915_gem_object_wait_rendering(obj
);
2968 i915_gem_object_flush_gtt_write_domain(obj
);
2970 /* If we have a partially-valid cache of the object in the CPU,
2971 * finish invalidating it and free the per-page flags.
2973 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2975 old_write_domain
= obj
->write_domain
;
2976 old_read_domains
= obj
->read_domains
;
2978 /* Flush the CPU cache if it's still invalid. */
2979 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2980 i915_gem_clflush_object(obj
);
2982 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2985 /* It should now be out of any other write domains, and we can update
2986 * the domain values for our changes.
2988 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2990 /* If we're writing through the CPU, then the GPU read domains will
2991 * need to be invalidated at next use.
2994 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2995 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2998 trace_i915_gem_object_change_domain(obj
,
3006 * Set the next domain for the specified object. This
3007 * may not actually perform the necessary flushing/invaliding though,
3008 * as that may want to be batched with other set_domain operations
3010 * This is (we hope) the only really tricky part of gem. The goal
3011 * is fairly simple -- track which caches hold bits of the object
3012 * and make sure they remain coherent. A few concrete examples may
3013 * help to explain how it works. For shorthand, we use the notation
3014 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3015 * a pair of read and write domain masks.
3017 * Case 1: the batch buffer
3023 * 5. Unmapped from GTT
3026 * Let's take these a step at a time
3029 * Pages allocated from the kernel may still have
3030 * cache contents, so we set them to (CPU, CPU) always.
3031 * 2. Written by CPU (using pwrite)
3032 * The pwrite function calls set_domain (CPU, CPU) and
3033 * this function does nothing (as nothing changes)
3035 * This function asserts that the object is not
3036 * currently in any GPU-based read or write domains
3038 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3039 * As write_domain is zero, this function adds in the
3040 * current read domains (CPU+COMMAND, 0).
3041 * flush_domains is set to CPU.
3042 * invalidate_domains is set to COMMAND
3043 * clflush is run to get data out of the CPU caches
3044 * then i915_dev_set_domain calls i915_gem_flush to
3045 * emit an MI_FLUSH and drm_agp_chipset_flush
3046 * 5. Unmapped from GTT
3047 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3048 * flush_domains and invalidate_domains end up both zero
3049 * so no flushing/invalidating happens
3053 * Case 2: The shared render buffer
3057 * 3. Read/written by GPU
3058 * 4. set_domain to (CPU,CPU)
3059 * 5. Read/written by CPU
3060 * 6. Read/written by GPU
3063 * Same as last example, (CPU, CPU)
3065 * Nothing changes (assertions find that it is not in the GPU)
3066 * 3. Read/written by GPU
3067 * execbuffer calls set_domain (RENDER, RENDER)
3068 * flush_domains gets CPU
3069 * invalidate_domains gets GPU
3071 * MI_FLUSH and drm_agp_chipset_flush
3072 * 4. set_domain (CPU, CPU)
3073 * flush_domains gets GPU
3074 * invalidate_domains gets CPU
3075 * wait_rendering (obj) to make sure all drawing is complete.
3076 * This will include an MI_FLUSH to get the data from GPU
3078 * clflush (obj) to invalidate the CPU cache
3079 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3080 * 5. Read/written by CPU
3081 * cache lines are loaded and dirtied
3082 * 6. Read written by GPU
3083 * Same as last GPU access
3085 * Case 3: The constant buffer
3090 * 4. Updated (written) by CPU again
3099 * flush_domains = CPU
3100 * invalidate_domains = RENDER
3103 * drm_agp_chipset_flush
3104 * 4. Updated (written) by CPU again
3106 * flush_domains = 0 (no previous write domain)
3107 * invalidate_domains = 0 (no new read domains)
3110 * flush_domains = CPU
3111 * invalidate_domains = RENDER
3114 * drm_agp_chipset_flush
3117 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3119 struct drm_device
*dev
= obj
->dev
;
3120 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3121 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3122 uint32_t invalidate_domains
= 0;
3123 uint32_t flush_domains
= 0;
3124 uint32_t old_read_domains
;
3126 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3127 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3129 intel_mark_busy(dev
, obj
);
3132 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3134 obj
->read_domains
, obj
->pending_read_domains
,
3135 obj
->write_domain
, obj
->pending_write_domain
);
3138 * If the object isn't moving to a new write domain,
3139 * let the object stay in multiple read domains
3141 if (obj
->pending_write_domain
== 0)
3142 obj
->pending_read_domains
|= obj
->read_domains
;
3144 obj_priv
->dirty
= 1;
3147 * Flush the current write domain if
3148 * the new read domains don't match. Invalidate
3149 * any read domains which differ from the old
3152 if (obj
->write_domain
&&
3153 obj
->write_domain
!= obj
->pending_read_domains
) {
3154 flush_domains
|= obj
->write_domain
;
3155 invalidate_domains
|=
3156 obj
->pending_read_domains
& ~obj
->write_domain
;
3159 * Invalidate any read caches which may have
3160 * stale data. That is, any new read domains.
3162 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3163 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3165 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3166 __func__
, flush_domains
, invalidate_domains
);
3168 i915_gem_clflush_object(obj
);
3171 old_read_domains
= obj
->read_domains
;
3173 /* The actual obj->write_domain will be updated with
3174 * pending_write_domain after we emit the accumulated flush for all
3175 * of our domain changes in execbuffers (which clears objects'
3176 * write_domains). So if we have a current write domain that we
3177 * aren't changing, set pending_write_domain to that.
3179 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3180 obj
->pending_write_domain
= obj
->write_domain
;
3181 obj
->read_domains
= obj
->pending_read_domains
;
3183 if (flush_domains
& I915_GEM_GPU_DOMAINS
) {
3184 if (obj_priv
->ring
== &dev_priv
->render_ring
)
3185 dev_priv
->flush_rings
|= FLUSH_RENDER_RING
;
3186 else if (obj_priv
->ring
== &dev_priv
->bsd_ring
)
3187 dev_priv
->flush_rings
|= FLUSH_BSD_RING
;
3190 dev
->invalidate_domains
|= invalidate_domains
;
3191 dev
->flush_domains
|= flush_domains
;
3193 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3195 obj
->read_domains
, obj
->write_domain
,
3196 dev
->invalidate_domains
, dev
->flush_domains
);
3199 trace_i915_gem_object_change_domain(obj
,
3205 * Moves the object from a partially CPU read to a full one.
3207 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3208 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3211 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3213 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3215 if (!obj_priv
->page_cpu_valid
)
3218 /* If we're partially in the CPU read domain, finish moving it in.
3220 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3223 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3224 if (obj_priv
->page_cpu_valid
[i
])
3226 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3230 /* Free the page_cpu_valid mappings which are now stale, whether
3231 * or not we've got I915_GEM_DOMAIN_CPU.
3233 kfree(obj_priv
->page_cpu_valid
);
3234 obj_priv
->page_cpu_valid
= NULL
;
3238 * Set the CPU read domain on a range of the object.
3240 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3241 * not entirely valid. The page_cpu_valid member of the object flags which
3242 * pages have been flushed, and will be respected by
3243 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3244 * of the whole object.
3246 * This function returns when the move is complete, including waiting on
3250 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3251 uint64_t offset
, uint64_t size
)
3253 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3254 uint32_t old_read_domains
;
3257 if (offset
== 0 && size
== obj
->size
)
3258 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3260 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3264 /* Wait on any GPU rendering and flushing to occur. */
3265 ret
= i915_gem_object_wait_rendering(obj
);
3268 i915_gem_object_flush_gtt_write_domain(obj
);
3270 /* If we're already fully in the CPU read domain, we're done. */
3271 if (obj_priv
->page_cpu_valid
== NULL
&&
3272 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3275 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3276 * newly adding I915_GEM_DOMAIN_CPU
3278 if (obj_priv
->page_cpu_valid
== NULL
) {
3279 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3281 if (obj_priv
->page_cpu_valid
== NULL
)
3283 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3284 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3286 /* Flush the cache on any pages that are still invalid from the CPU's
3289 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3291 if (obj_priv
->page_cpu_valid
[i
])
3294 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3296 obj_priv
->page_cpu_valid
[i
] = 1;
3299 /* It should now be out of any other write domains, and we can update
3300 * the domain values for our changes.
3302 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3304 old_read_domains
= obj
->read_domains
;
3305 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3307 trace_i915_gem_object_change_domain(obj
,
3315 * Pin an object to the GTT and evaluate the relocations landing in it.
3318 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3319 struct drm_file
*file_priv
,
3320 struct drm_i915_gem_exec_object2
*entry
,
3321 struct drm_i915_gem_relocation_entry
*relocs
)
3323 struct drm_device
*dev
= obj
->dev
;
3324 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3325 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3327 void __iomem
*reloc_page
;
3330 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3331 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3333 /* Check fence reg constraints and rebind if necessary */
3335 !i915_gem_object_fence_offset_ok(obj
,
3336 obj_priv
->tiling_mode
)) {
3337 ret
= i915_gem_object_unbind(obj
);
3342 /* Choose the GTT offset for our buffer and put it there. */
3343 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3348 * Pre-965 chips need a fence register set up in order to
3349 * properly handle blits to/from tiled surfaces.
3352 ret
= i915_gem_object_get_fence_reg(obj
);
3354 i915_gem_object_unpin(obj
);
3359 entry
->offset
= obj_priv
->gtt_offset
;
3361 /* Apply the relocations, using the GTT aperture to avoid cache
3362 * flushing requirements.
3364 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3365 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3366 struct drm_gem_object
*target_obj
;
3367 struct drm_i915_gem_object
*target_obj_priv
;
3368 uint32_t reloc_val
, reloc_offset
;
3369 uint32_t __iomem
*reloc_entry
;
3371 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3372 reloc
->target_handle
);
3373 if (target_obj
== NULL
) {
3374 i915_gem_object_unpin(obj
);
3377 target_obj_priv
= to_intel_bo(target_obj
);
3380 DRM_INFO("%s: obj %p offset %08x target %d "
3381 "read %08x write %08x gtt %08x "
3382 "presumed %08x delta %08x\n",
3385 (int) reloc
->offset
,
3386 (int) reloc
->target_handle
,
3387 (int) reloc
->read_domains
,
3388 (int) reloc
->write_domain
,
3389 (int) target_obj_priv
->gtt_offset
,
3390 (int) reloc
->presumed_offset
,
3394 /* The target buffer should have appeared before us in the
3395 * exec_object list, so it should have a GTT space bound by now.
3397 if (target_obj_priv
->gtt_space
== NULL
) {
3398 DRM_ERROR("No GTT space found for object %d\n",
3399 reloc
->target_handle
);
3400 drm_gem_object_unreference(target_obj
);
3401 i915_gem_object_unpin(obj
);
3405 /* Validate that the target is in a valid r/w GPU domain */
3406 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3407 DRM_ERROR("reloc with multiple write domains: "
3408 "obj %p target %d offset %d "
3409 "read %08x write %08x",
3410 obj
, reloc
->target_handle
,
3411 (int) reloc
->offset
,
3412 reloc
->read_domains
,
3413 reloc
->write_domain
);
3416 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3417 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3418 DRM_ERROR("reloc with read/write CPU domains: "
3419 "obj %p target %d offset %d "
3420 "read %08x write %08x",
3421 obj
, reloc
->target_handle
,
3422 (int) reloc
->offset
,
3423 reloc
->read_domains
,
3424 reloc
->write_domain
);
3425 drm_gem_object_unreference(target_obj
);
3426 i915_gem_object_unpin(obj
);
3429 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3430 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3431 DRM_ERROR("Write domain conflict: "
3432 "obj %p target %d offset %d "
3433 "new %08x old %08x\n",
3434 obj
, reloc
->target_handle
,
3435 (int) reloc
->offset
,
3436 reloc
->write_domain
,
3437 target_obj
->pending_write_domain
);
3438 drm_gem_object_unreference(target_obj
);
3439 i915_gem_object_unpin(obj
);
3443 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3444 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3446 /* If the relocation already has the right value in it, no
3447 * more work needs to be done.
3449 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3450 drm_gem_object_unreference(target_obj
);
3454 /* Check that the relocation address is valid... */
3455 if (reloc
->offset
> obj
->size
- 4) {
3456 DRM_ERROR("Relocation beyond object bounds: "
3457 "obj %p target %d offset %d size %d.\n",
3458 obj
, reloc
->target_handle
,
3459 (int) reloc
->offset
, (int) obj
->size
);
3460 drm_gem_object_unreference(target_obj
);
3461 i915_gem_object_unpin(obj
);
3464 if (reloc
->offset
& 3) {
3465 DRM_ERROR("Relocation not 4-byte aligned: "
3466 "obj %p target %d offset %d.\n",
3467 obj
, reloc
->target_handle
,
3468 (int) reloc
->offset
);
3469 drm_gem_object_unreference(target_obj
);
3470 i915_gem_object_unpin(obj
);
3474 /* and points to somewhere within the target object. */
3475 if (reloc
->delta
>= target_obj
->size
) {
3476 DRM_ERROR("Relocation beyond target object bounds: "
3477 "obj %p target %d delta %d size %d.\n",
3478 obj
, reloc
->target_handle
,
3479 (int) reloc
->delta
, (int) target_obj
->size
);
3480 drm_gem_object_unreference(target_obj
);
3481 i915_gem_object_unpin(obj
);
3485 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3487 drm_gem_object_unreference(target_obj
);
3488 i915_gem_object_unpin(obj
);
3492 /* Map the page containing the relocation we're going to
3495 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3496 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3500 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3501 (reloc_offset
& (PAGE_SIZE
- 1)));
3502 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3505 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3506 obj
, (unsigned int) reloc
->offset
,
3507 readl(reloc_entry
), reloc_val
);
3509 writel(reloc_val
, reloc_entry
);
3510 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3512 /* The updated presumed offset for this entry will be
3513 * copied back out to the user.
3515 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3517 drm_gem_object_unreference(target_obj
);
3522 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3527 /* Throttle our rendering by waiting until the ring has completed our requests
3528 * emitted over 20 msec ago.
3530 * Note that if we were to use the current jiffies each time around the loop,
3531 * we wouldn't escape the function with any frames outstanding if the time to
3532 * render a frame was over 20ms.
3534 * This should get us reasonable parallelism between CPU and GPU but also
3535 * relatively low latency when blocking on a particular request to finish.
3538 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3540 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3542 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3544 mutex_lock(&dev
->struct_mutex
);
3545 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3546 struct drm_i915_gem_request
*request
;
3548 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3549 struct drm_i915_gem_request
,
3552 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3555 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3559 mutex_unlock(&dev
->struct_mutex
);
3565 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3566 uint32_t buffer_count
,
3567 struct drm_i915_gem_relocation_entry
**relocs
)
3569 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3573 for (i
= 0; i
< buffer_count
; i
++) {
3574 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3576 reloc_count
+= exec_list
[i
].relocation_count
;
3579 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3580 if (*relocs
== NULL
) {
3581 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3585 for (i
= 0; i
< buffer_count
; i
++) {
3586 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3588 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3590 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3592 exec_list
[i
].relocation_count
*
3595 drm_free_large(*relocs
);
3600 reloc_index
+= exec_list
[i
].relocation_count
;
3607 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3608 uint32_t buffer_count
,
3609 struct drm_i915_gem_relocation_entry
*relocs
)
3611 uint32_t reloc_count
= 0, i
;
3617 for (i
= 0; i
< buffer_count
; i
++) {
3618 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3621 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3623 unwritten
= copy_to_user(user_relocs
,
3624 &relocs
[reloc_count
],
3625 exec_list
[i
].relocation_count
*
3633 reloc_count
+= exec_list
[i
].relocation_count
;
3637 drm_free_large(relocs
);
3643 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3644 uint64_t exec_offset
)
3646 uint32_t exec_start
, exec_len
;
3648 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3649 exec_len
= (uint32_t) exec
->batch_len
;
3651 if ((exec_start
| exec_len
) & 0x7)
3661 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3662 struct drm_gem_object
**object_list
,
3665 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3666 struct drm_i915_gem_object
*obj_priv
;
3671 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3672 &wait
, TASK_INTERRUPTIBLE
);
3673 for (i
= 0; i
< count
; i
++) {
3674 obj_priv
= to_intel_bo(object_list
[i
]);
3675 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3681 if (!signal_pending(current
)) {
3682 mutex_unlock(&dev
->struct_mutex
);
3684 mutex_lock(&dev
->struct_mutex
);
3690 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3697 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3698 struct drm_file
*file_priv
,
3699 struct drm_i915_gem_execbuffer2
*args
,
3700 struct drm_i915_gem_exec_object2
*exec_list
)
3702 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3703 struct drm_gem_object
**object_list
= NULL
;
3704 struct drm_gem_object
*batch_obj
;
3705 struct drm_i915_gem_object
*obj_priv
;
3706 struct drm_clip_rect
*cliprects
= NULL
;
3707 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3708 int ret
= 0, ret2
, i
, pinned
= 0;
3709 uint64_t exec_offset
;
3710 uint32_t seqno
, flush_domains
, reloc_index
;
3711 int pin_tries
, flips
;
3713 struct intel_ring_buffer
*ring
= NULL
;
3716 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3717 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3719 if (args
->flags
& I915_EXEC_BSD
) {
3720 if (!HAS_BSD(dev
)) {
3721 DRM_ERROR("execbuf with wrong flag\n");
3724 ring
= &dev_priv
->bsd_ring
;
3726 ring
= &dev_priv
->render_ring
;
3729 if (args
->buffer_count
< 1) {
3730 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3733 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3734 if (object_list
== NULL
) {
3735 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3736 args
->buffer_count
);
3741 if (args
->num_cliprects
!= 0) {
3742 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3744 if (cliprects
== NULL
) {
3749 ret
= copy_from_user(cliprects
,
3750 (struct drm_clip_rect __user
*)
3751 (uintptr_t) args
->cliprects_ptr
,
3752 sizeof(*cliprects
) * args
->num_cliprects
);
3754 DRM_ERROR("copy %d cliprects failed: %d\n",
3755 args
->num_cliprects
, ret
);
3760 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3765 mutex_lock(&dev
->struct_mutex
);
3767 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3769 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3770 mutex_unlock(&dev
->struct_mutex
);
3775 if (dev_priv
->mm
.suspended
) {
3776 mutex_unlock(&dev
->struct_mutex
);
3781 /* Look up object handles */
3783 for (i
= 0; i
< args
->buffer_count
; i
++) {
3784 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3785 exec_list
[i
].handle
);
3786 if (object_list
[i
] == NULL
) {
3787 DRM_ERROR("Invalid object handle %d at index %d\n",
3788 exec_list
[i
].handle
, i
);
3789 /* prevent error path from reading uninitialized data */
3790 args
->buffer_count
= i
+ 1;
3795 obj_priv
= to_intel_bo(object_list
[i
]);
3796 if (obj_priv
->in_execbuffer
) {
3797 DRM_ERROR("Object %p appears more than once in object list\n",
3799 /* prevent error path from reading uninitialized data */
3800 args
->buffer_count
= i
+ 1;
3804 obj_priv
->in_execbuffer
= true;
3805 flips
+= atomic_read(&obj_priv
->pending_flip
);
3809 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3810 args
->buffer_count
);
3815 /* Pin and relocate */
3816 for (pin_tries
= 0; ; pin_tries
++) {
3820 for (i
= 0; i
< args
->buffer_count
; i
++) {
3821 object_list
[i
]->pending_read_domains
= 0;
3822 object_list
[i
]->pending_write_domain
= 0;
3823 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3826 &relocs
[reloc_index
]);
3830 reloc_index
+= exec_list
[i
].relocation_count
;
3836 /* error other than GTT full, or we've already tried again */
3837 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3838 if (ret
!= -ERESTARTSYS
) {
3839 unsigned long long total_size
= 0;
3841 for (i
= 0; i
< args
->buffer_count
; i
++) {
3842 obj_priv
= to_intel_bo(object_list
[i
]);
3844 total_size
+= object_list
[i
]->size
;
3846 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3847 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3849 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3850 pinned
+1, args
->buffer_count
,
3851 total_size
, num_fences
,
3853 DRM_ERROR("%d objects [%d pinned], "
3854 "%d object bytes [%d pinned], "
3855 "%d/%d gtt bytes\n",
3856 atomic_read(&dev
->object_count
),
3857 atomic_read(&dev
->pin_count
),
3858 atomic_read(&dev
->object_memory
),
3859 atomic_read(&dev
->pin_memory
),
3860 atomic_read(&dev
->gtt_memory
),
3866 /* unpin all of our buffers */
3867 for (i
= 0; i
< pinned
; i
++)
3868 i915_gem_object_unpin(object_list
[i
]);
3871 /* evict everyone we can from the aperture */
3872 ret
= i915_gem_evict_everything(dev
);
3873 if (ret
&& ret
!= -ENOSPC
)
3877 /* Set the pending read domains for the batch buffer to COMMAND */
3878 batch_obj
= object_list
[args
->buffer_count
-1];
3879 if (batch_obj
->pending_write_domain
) {
3880 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3884 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3886 /* Sanity check the batch buffer, prior to moving objects */
3887 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3888 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3890 DRM_ERROR("execbuf with invalid offset/length\n");
3894 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3896 /* Zero the global flush/invalidate flags. These
3897 * will be modified as new domains are computed
3900 dev
->invalidate_domains
= 0;
3901 dev
->flush_domains
= 0;
3902 dev_priv
->flush_rings
= 0;
3904 for (i
= 0; i
< args
->buffer_count
; i
++) {
3905 struct drm_gem_object
*obj
= object_list
[i
];
3907 /* Compute new gpu domains and update invalidate/flush */
3908 i915_gem_object_set_to_gpu_domain(obj
);
3911 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3913 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3915 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3917 dev
->invalidate_domains
,
3918 dev
->flush_domains
);
3921 dev
->invalidate_domains
,
3922 dev
->flush_domains
);
3923 if (dev_priv
->flush_rings
& FLUSH_RENDER_RING
)
3924 (void)i915_add_request(dev
, file_priv
,
3926 &dev_priv
->render_ring
);
3927 if (dev_priv
->flush_rings
& FLUSH_BSD_RING
)
3928 (void)i915_add_request(dev
, file_priv
,
3930 &dev_priv
->bsd_ring
);
3933 for (i
= 0; i
< args
->buffer_count
; i
++) {
3934 struct drm_gem_object
*obj
= object_list
[i
];
3935 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3936 uint32_t old_write_domain
= obj
->write_domain
;
3938 obj
->write_domain
= obj
->pending_write_domain
;
3939 if (obj
->write_domain
)
3940 list_move_tail(&obj_priv
->gpu_write_list
,
3941 &dev_priv
->mm
.gpu_write_list
);
3943 list_del_init(&obj_priv
->gpu_write_list
);
3945 trace_i915_gem_object_change_domain(obj
,
3950 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3953 for (i
= 0; i
< args
->buffer_count
; i
++) {
3954 i915_gem_object_check_coherency(object_list
[i
],
3955 exec_list
[i
].handle
);
3960 i915_gem_dump_object(batch_obj
,
3966 /* Exec the batchbuffer */
3967 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3968 cliprects
, exec_offset
);
3970 DRM_ERROR("dispatch failed %d\n", ret
);
3975 * Ensure that the commands in the batch buffer are
3976 * finished before the interrupt fires
3978 flush_domains
= i915_retire_commands(dev
, ring
);
3980 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3983 * Get a seqno representing the execution of the current buffer,
3984 * which we can wait on. We would like to mitigate these interrupts,
3985 * likely by only creating seqnos occasionally (so that we have
3986 * *some* interrupts representing completion of buffers that we can
3987 * wait on when trying to clear up gtt space).
3989 seqno
= i915_add_request(dev
, file_priv
, flush_domains
, ring
);
3991 for (i
= 0; i
< args
->buffer_count
; i
++) {
3992 struct drm_gem_object
*obj
= object_list
[i
];
3993 obj_priv
= to_intel_bo(obj
);
3995 i915_gem_object_move_to_active(obj
, seqno
, ring
);
3997 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
4001 i915_dump_lru(dev
, __func__
);
4004 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4007 for (i
= 0; i
< pinned
; i
++)
4008 i915_gem_object_unpin(object_list
[i
]);
4010 for (i
= 0; i
< args
->buffer_count
; i
++) {
4011 if (object_list
[i
]) {
4012 obj_priv
= to_intel_bo(object_list
[i
]);
4013 obj_priv
->in_execbuffer
= false;
4015 drm_gem_object_unreference(object_list
[i
]);
4018 mutex_unlock(&dev
->struct_mutex
);
4021 /* Copy the updated relocations out regardless of current error
4022 * state. Failure to update the relocs would mean that the next
4023 * time userland calls execbuf, it would do so with presumed offset
4024 * state that didn't match the actual object state.
4026 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
4029 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
4035 drm_free_large(object_list
);
4042 * Legacy execbuffer just creates an exec2 list from the original exec object
4043 * list array and passes it to the real function.
4046 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4047 struct drm_file
*file_priv
)
4049 struct drm_i915_gem_execbuffer
*args
= data
;
4050 struct drm_i915_gem_execbuffer2 exec2
;
4051 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4052 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4056 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4057 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4060 if (args
->buffer_count
< 1) {
4061 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4065 /* Copy in the exec list from userland */
4066 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4067 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4068 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4069 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4070 args
->buffer_count
);
4071 drm_free_large(exec_list
);
4072 drm_free_large(exec2_list
);
4075 ret
= copy_from_user(exec_list
,
4076 (struct drm_i915_relocation_entry __user
*)
4077 (uintptr_t) args
->buffers_ptr
,
4078 sizeof(*exec_list
) * args
->buffer_count
);
4080 DRM_ERROR("copy %d exec entries failed %d\n",
4081 args
->buffer_count
, ret
);
4082 drm_free_large(exec_list
);
4083 drm_free_large(exec2_list
);
4087 for (i
= 0; i
< args
->buffer_count
; i
++) {
4088 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4089 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4090 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4091 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4092 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4094 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4096 exec2_list
[i
].flags
= 0;
4099 exec2
.buffers_ptr
= args
->buffers_ptr
;
4100 exec2
.buffer_count
= args
->buffer_count
;
4101 exec2
.batch_start_offset
= args
->batch_start_offset
;
4102 exec2
.batch_len
= args
->batch_len
;
4103 exec2
.DR1
= args
->DR1
;
4104 exec2
.DR4
= args
->DR4
;
4105 exec2
.num_cliprects
= args
->num_cliprects
;
4106 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4107 exec2
.flags
= I915_EXEC_RENDER
;
4109 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4111 /* Copy the new buffer offsets back to the user's exec list. */
4112 for (i
= 0; i
< args
->buffer_count
; i
++)
4113 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4114 /* ... and back out to userspace */
4115 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4116 (uintptr_t) args
->buffers_ptr
,
4118 sizeof(*exec_list
) * args
->buffer_count
);
4121 DRM_ERROR("failed to copy %d exec entries "
4122 "back to user (%d)\n",
4123 args
->buffer_count
, ret
);
4127 drm_free_large(exec_list
);
4128 drm_free_large(exec2_list
);
4133 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4134 struct drm_file
*file_priv
)
4136 struct drm_i915_gem_execbuffer2
*args
= data
;
4137 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4141 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4142 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4145 if (args
->buffer_count
< 1) {
4146 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4150 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4151 if (exec2_list
== NULL
) {
4152 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4153 args
->buffer_count
);
4156 ret
= copy_from_user(exec2_list
,
4157 (struct drm_i915_relocation_entry __user
*)
4158 (uintptr_t) args
->buffers_ptr
,
4159 sizeof(*exec2_list
) * args
->buffer_count
);
4161 DRM_ERROR("copy %d exec entries failed %d\n",
4162 args
->buffer_count
, ret
);
4163 drm_free_large(exec2_list
);
4167 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4169 /* Copy the new buffer offsets back to the user's exec list. */
4170 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4171 (uintptr_t) args
->buffers_ptr
,
4173 sizeof(*exec2_list
) * args
->buffer_count
);
4176 DRM_ERROR("failed to copy %d exec entries "
4177 "back to user (%d)\n",
4178 args
->buffer_count
, ret
);
4182 drm_free_large(exec2_list
);
4187 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4189 struct drm_device
*dev
= obj
->dev
;
4190 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4193 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4195 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4197 if (obj_priv
->gtt_space
!= NULL
) {
4199 alignment
= i915_gem_get_gtt_alignment(obj
);
4200 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4201 ret
= i915_gem_object_unbind(obj
);
4207 if (obj_priv
->gtt_space
== NULL
) {
4208 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4213 obj_priv
->pin_count
++;
4215 /* If the object is not active and not pending a flush,
4216 * remove it from the inactive list
4218 if (obj_priv
->pin_count
== 1) {
4219 atomic_inc(&dev
->pin_count
);
4220 atomic_add(obj
->size
, &dev
->pin_memory
);
4221 if (!obj_priv
->active
&&
4222 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4223 !list_empty(&obj_priv
->list
))
4224 list_del_init(&obj_priv
->list
);
4226 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4232 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4234 struct drm_device
*dev
= obj
->dev
;
4235 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4236 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4238 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4239 obj_priv
->pin_count
--;
4240 BUG_ON(obj_priv
->pin_count
< 0);
4241 BUG_ON(obj_priv
->gtt_space
== NULL
);
4243 /* If the object is no longer pinned, and is
4244 * neither active nor being flushed, then stick it on
4247 if (obj_priv
->pin_count
== 0) {
4248 if (!obj_priv
->active
&&
4249 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4250 list_move_tail(&obj_priv
->list
,
4251 &dev_priv
->mm
.inactive_list
);
4252 atomic_dec(&dev
->pin_count
);
4253 atomic_sub(obj
->size
, &dev
->pin_memory
);
4255 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4259 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4260 struct drm_file
*file_priv
)
4262 struct drm_i915_gem_pin
*args
= data
;
4263 struct drm_gem_object
*obj
;
4264 struct drm_i915_gem_object
*obj_priv
;
4267 mutex_lock(&dev
->struct_mutex
);
4269 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4271 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4273 mutex_unlock(&dev
->struct_mutex
);
4276 obj_priv
= to_intel_bo(obj
);
4278 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4279 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4280 drm_gem_object_unreference(obj
);
4281 mutex_unlock(&dev
->struct_mutex
);
4285 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4286 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4288 drm_gem_object_unreference(obj
);
4289 mutex_unlock(&dev
->struct_mutex
);
4293 obj_priv
->user_pin_count
++;
4294 obj_priv
->pin_filp
= file_priv
;
4295 if (obj_priv
->user_pin_count
== 1) {
4296 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4298 drm_gem_object_unreference(obj
);
4299 mutex_unlock(&dev
->struct_mutex
);
4304 /* XXX - flush the CPU caches for pinned objects
4305 * as the X server doesn't manage domains yet
4307 i915_gem_object_flush_cpu_write_domain(obj
);
4308 args
->offset
= obj_priv
->gtt_offset
;
4309 drm_gem_object_unreference(obj
);
4310 mutex_unlock(&dev
->struct_mutex
);
4316 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4317 struct drm_file
*file_priv
)
4319 struct drm_i915_gem_pin
*args
= data
;
4320 struct drm_gem_object
*obj
;
4321 struct drm_i915_gem_object
*obj_priv
;
4323 mutex_lock(&dev
->struct_mutex
);
4325 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4327 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4329 mutex_unlock(&dev
->struct_mutex
);
4333 obj_priv
= to_intel_bo(obj
);
4334 if (obj_priv
->pin_filp
!= file_priv
) {
4335 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4337 drm_gem_object_unreference(obj
);
4338 mutex_unlock(&dev
->struct_mutex
);
4341 obj_priv
->user_pin_count
--;
4342 if (obj_priv
->user_pin_count
== 0) {
4343 obj_priv
->pin_filp
= NULL
;
4344 i915_gem_object_unpin(obj
);
4347 drm_gem_object_unreference(obj
);
4348 mutex_unlock(&dev
->struct_mutex
);
4353 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4354 struct drm_file
*file_priv
)
4356 struct drm_i915_gem_busy
*args
= data
;
4357 struct drm_gem_object
*obj
;
4358 struct drm_i915_gem_object
*obj_priv
;
4360 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4362 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4367 mutex_lock(&dev
->struct_mutex
);
4368 /* Update the active list for the hardware's current position.
4369 * Otherwise this only updates on a delayed timer or when irqs are
4370 * actually unmasked, and our working set ends up being larger than
4373 i915_gem_retire_requests(dev
);
4375 obj_priv
= to_intel_bo(obj
);
4376 /* Don't count being on the flushing list against the object being
4377 * done. Otherwise, a buffer left on the flushing list but not getting
4378 * flushed (because nobody's flushing that domain) won't ever return
4379 * unbusy and get reused by libdrm's bo cache. The other expected
4380 * consumer of this interface, OpenGL's occlusion queries, also specs
4381 * that the objects get unbusy "eventually" without any interference.
4383 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4385 drm_gem_object_unreference(obj
);
4386 mutex_unlock(&dev
->struct_mutex
);
4391 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4392 struct drm_file
*file_priv
)
4394 return i915_gem_ring_throttle(dev
, file_priv
);
4398 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4399 struct drm_file
*file_priv
)
4401 struct drm_i915_gem_madvise
*args
= data
;
4402 struct drm_gem_object
*obj
;
4403 struct drm_i915_gem_object
*obj_priv
;
4405 switch (args
->madv
) {
4406 case I915_MADV_DONTNEED
:
4407 case I915_MADV_WILLNEED
:
4413 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4415 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4420 mutex_lock(&dev
->struct_mutex
);
4421 obj_priv
= to_intel_bo(obj
);
4423 if (obj_priv
->pin_count
) {
4424 drm_gem_object_unreference(obj
);
4425 mutex_unlock(&dev
->struct_mutex
);
4427 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4431 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4432 obj_priv
->madv
= args
->madv
;
4434 /* if the object is no longer bound, discard its backing storage */
4435 if (i915_gem_object_is_purgeable(obj_priv
) &&
4436 obj_priv
->gtt_space
== NULL
)
4437 i915_gem_object_truncate(obj
);
4439 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4441 drm_gem_object_unreference(obj
);
4442 mutex_unlock(&dev
->struct_mutex
);
4447 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4450 struct drm_i915_gem_object
*obj
;
4452 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4456 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4461 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4462 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4464 obj
->agp_type
= AGP_USER_MEMORY
;
4465 obj
->base
.driver_private
= NULL
;
4466 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4467 INIT_LIST_HEAD(&obj
->list
);
4468 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4469 obj
->madv
= I915_MADV_WILLNEED
;
4471 trace_i915_gem_object_create(&obj
->base
);
4476 int i915_gem_init_object(struct drm_gem_object
*obj
)
4483 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4485 struct drm_device
*dev
= obj
->dev
;
4486 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4487 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4490 ret
= i915_gem_object_unbind(obj
);
4491 if (ret
== -ERESTARTSYS
) {
4492 list_move(&obj_priv
->list
,
4493 &dev_priv
->mm
.deferred_free_list
);
4497 if (obj_priv
->mmap_offset
)
4498 i915_gem_free_mmap_offset(obj
);
4500 drm_gem_object_release(obj
);
4502 kfree(obj_priv
->page_cpu_valid
);
4503 kfree(obj_priv
->bit_17
);
4507 void i915_gem_free_object(struct drm_gem_object
*obj
)
4509 struct drm_device
*dev
= obj
->dev
;
4510 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4512 trace_i915_gem_object_destroy(obj
);
4514 while (obj_priv
->pin_count
> 0)
4515 i915_gem_object_unpin(obj
);
4517 if (obj_priv
->phys_obj
)
4518 i915_gem_detach_phys_object(dev
, obj
);
4520 i915_gem_free_object_tail(obj
);
4523 /** Unbinds all inactive objects. */
4525 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4527 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4529 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4530 struct drm_gem_object
*obj
;
4533 obj
= &list_first_entry(&dev_priv
->mm
.inactive_list
,
4534 struct drm_i915_gem_object
,
4537 ret
= i915_gem_object_unbind(obj
);
4539 DRM_ERROR("Error unbinding object: %d\n", ret
);
4548 i915_gem_idle(struct drm_device
*dev
)
4550 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4553 mutex_lock(&dev
->struct_mutex
);
4555 if (dev_priv
->mm
.suspended
||
4556 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4558 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4559 mutex_unlock(&dev
->struct_mutex
);
4563 ret
= i915_gpu_idle(dev
);
4565 mutex_unlock(&dev
->struct_mutex
);
4569 /* Under UMS, be paranoid and evict. */
4570 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4571 ret
= i915_gem_evict_from_inactive_list(dev
);
4573 mutex_unlock(&dev
->struct_mutex
);
4578 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4579 * We need to replace this with a semaphore, or something.
4580 * And not confound mm.suspended!
4582 dev_priv
->mm
.suspended
= 1;
4583 del_timer(&dev_priv
->hangcheck_timer
);
4585 i915_kernel_lost_context(dev
);
4586 i915_gem_cleanup_ringbuffer(dev
);
4588 mutex_unlock(&dev
->struct_mutex
);
4590 /* Cancel the retire work handler, which should be idle now. */
4591 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4597 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4598 * over cache flushing.
4601 i915_gem_init_pipe_control(struct drm_device
*dev
)
4603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4604 struct drm_gem_object
*obj
;
4605 struct drm_i915_gem_object
*obj_priv
;
4608 obj
= i915_gem_alloc_object(dev
, 4096);
4610 DRM_ERROR("Failed to allocate seqno page\n");
4614 obj_priv
= to_intel_bo(obj
);
4615 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4617 ret
= i915_gem_object_pin(obj
, 4096);
4621 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4622 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4623 if (dev_priv
->seqno_page
== NULL
)
4626 dev_priv
->seqno_obj
= obj
;
4627 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4632 i915_gem_object_unpin(obj
);
4634 drm_gem_object_unreference(obj
);
4641 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4643 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4644 struct drm_gem_object
*obj
;
4645 struct drm_i915_gem_object
*obj_priv
;
4647 obj
= dev_priv
->seqno_obj
;
4648 obj_priv
= to_intel_bo(obj
);
4649 kunmap(obj_priv
->pages
[0]);
4650 i915_gem_object_unpin(obj
);
4651 drm_gem_object_unreference(obj
);
4652 dev_priv
->seqno_obj
= NULL
;
4654 dev_priv
->seqno_page
= NULL
;
4658 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4660 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4663 dev_priv
->render_ring
= render_ring
;
4665 if (!I915_NEED_GFX_HWS(dev
)) {
4666 dev_priv
->render_ring
.status_page
.page_addr
4667 = dev_priv
->status_page_dmah
->vaddr
;
4668 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4672 if (HAS_PIPE_CONTROL(dev
)) {
4673 ret
= i915_gem_init_pipe_control(dev
);
4678 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4680 goto cleanup_pipe_control
;
4683 dev_priv
->bsd_ring
= bsd_ring
;
4684 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4686 goto cleanup_render_ring
;
4691 cleanup_render_ring
:
4692 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4693 cleanup_pipe_control
:
4694 if (HAS_PIPE_CONTROL(dev
))
4695 i915_gem_cleanup_pipe_control(dev
);
4700 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4702 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4704 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4706 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4707 if (HAS_PIPE_CONTROL(dev
))
4708 i915_gem_cleanup_pipe_control(dev
);
4712 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4713 struct drm_file
*file_priv
)
4715 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4718 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4721 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4722 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4723 atomic_set(&dev_priv
->mm
.wedged
, 0);
4726 mutex_lock(&dev
->struct_mutex
);
4727 dev_priv
->mm
.suspended
= 0;
4729 ret
= i915_gem_init_ringbuffer(dev
);
4731 mutex_unlock(&dev
->struct_mutex
);
4735 spin_lock(&dev_priv
->mm
.active_list_lock
);
4736 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4737 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4738 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4740 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4741 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4742 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4743 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4744 mutex_unlock(&dev
->struct_mutex
);
4746 ret
= drm_irq_install(dev
);
4748 goto cleanup_ringbuffer
;
4753 mutex_lock(&dev
->struct_mutex
);
4754 i915_gem_cleanup_ringbuffer(dev
);
4755 dev_priv
->mm
.suspended
= 1;
4756 mutex_unlock(&dev
->struct_mutex
);
4762 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4763 struct drm_file
*file_priv
)
4765 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4768 drm_irq_uninstall(dev
);
4769 return i915_gem_idle(dev
);
4773 i915_gem_lastclose(struct drm_device
*dev
)
4777 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4780 ret
= i915_gem_idle(dev
);
4782 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4786 i915_gem_load(struct drm_device
*dev
)
4789 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4791 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4792 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4793 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4794 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4795 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4796 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4797 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4798 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4800 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4801 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4803 for (i
= 0; i
< 16; i
++)
4804 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4805 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4806 i915_gem_retire_work_handler
);
4807 spin_lock(&shrink_list_lock
);
4808 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4809 spin_unlock(&shrink_list_lock
);
4811 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4813 u32 tmp
= I915_READ(MI_ARB_STATE
);
4814 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4815 /* arb state is a masked write, so set bit + bit in mask */
4816 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4817 I915_WRITE(MI_ARB_STATE
, tmp
);
4821 /* Old X drivers will take 0-2 for front, back, depth buffers */
4822 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4823 dev_priv
->fence_reg_start
= 3;
4825 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4826 dev_priv
->num_fence_regs
= 16;
4828 dev_priv
->num_fence_regs
= 8;
4830 /* Initialize fence registers to zero */
4831 if (IS_I965G(dev
)) {
4832 for (i
= 0; i
< 16; i
++)
4833 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4835 for (i
= 0; i
< 8; i
++)
4836 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4837 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4838 for (i
= 0; i
< 8; i
++)
4839 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4841 i915_gem_detect_bit_6_swizzle(dev
);
4842 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4846 * Create a physically contiguous memory object for this object
4847 * e.g. for cursor + overlay regs
4849 int i915_gem_init_phys_object(struct drm_device
*dev
,
4852 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4853 struct drm_i915_gem_phys_object
*phys_obj
;
4856 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4859 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4865 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4866 if (!phys_obj
->handle
) {
4871 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4874 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4882 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4885 struct drm_i915_gem_phys_object
*phys_obj
;
4887 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4890 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4891 if (phys_obj
->cur_obj
) {
4892 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4896 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4898 drm_pci_free(dev
, phys_obj
->handle
);
4900 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4903 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4907 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4908 i915_gem_free_phys_object(dev
, i
);
4911 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4912 struct drm_gem_object
*obj
)
4914 struct drm_i915_gem_object
*obj_priv
;
4919 obj_priv
= to_intel_bo(obj
);
4920 if (!obj_priv
->phys_obj
)
4923 ret
= i915_gem_object_get_pages(obj
, 0);
4927 page_count
= obj
->size
/ PAGE_SIZE
;
4929 for (i
= 0; i
< page_count
; i
++) {
4930 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4931 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4933 memcpy(dst
, src
, PAGE_SIZE
);
4934 kunmap_atomic(dst
, KM_USER0
);
4936 drm_clflush_pages(obj_priv
->pages
, page_count
);
4937 drm_agp_chipset_flush(dev
);
4939 i915_gem_object_put_pages(obj
);
4941 obj_priv
->phys_obj
->cur_obj
= NULL
;
4942 obj_priv
->phys_obj
= NULL
;
4946 i915_gem_attach_phys_object(struct drm_device
*dev
,
4947 struct drm_gem_object
*obj
, int id
)
4949 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4950 struct drm_i915_gem_object
*obj_priv
;
4955 if (id
> I915_MAX_PHYS_OBJECT
)
4958 obj_priv
= to_intel_bo(obj
);
4960 if (obj_priv
->phys_obj
) {
4961 if (obj_priv
->phys_obj
->id
== id
)
4963 i915_gem_detach_phys_object(dev
, obj
);
4967 /* create a new object */
4968 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4969 ret
= i915_gem_init_phys_object(dev
, id
,
4972 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4977 /* bind to the object */
4978 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4979 obj_priv
->phys_obj
->cur_obj
= obj
;
4981 ret
= i915_gem_object_get_pages(obj
, 0);
4983 DRM_ERROR("failed to get page list\n");
4987 page_count
= obj
->size
/ PAGE_SIZE
;
4989 for (i
= 0; i
< page_count
; i
++) {
4990 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4991 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4993 memcpy(dst
, src
, PAGE_SIZE
);
4994 kunmap_atomic(src
, KM_USER0
);
4997 i915_gem_object_put_pages(obj
);
5005 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
5006 struct drm_i915_gem_pwrite
*args
,
5007 struct drm_file
*file_priv
)
5009 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5012 char __user
*user_data
;
5014 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5015 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5017 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
5018 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
5022 drm_agp_chipset_flush(dev
);
5026 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
5028 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
5030 /* Clean up our request list when the client is going away, so that
5031 * later retire_requests won't dereference our soon-to-be-gone
5034 mutex_lock(&dev
->struct_mutex
);
5035 while (!list_empty(&i915_file_priv
->mm
.request_list
))
5036 list_del_init(i915_file_priv
->mm
.request_list
.next
);
5037 mutex_unlock(&dev
->struct_mutex
);
5041 i915_gpu_is_active(struct drm_device
*dev
)
5043 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5046 spin_lock(&dev_priv
->mm
.active_list_lock
);
5047 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
5048 list_empty(&dev_priv
->render_ring
.active_list
);
5050 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
5051 spin_unlock(&dev_priv
->mm
.active_list_lock
);
5053 return !lists_empty
;
5057 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
5059 drm_i915_private_t
*dev_priv
, *next_dev
;
5060 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
5062 int would_deadlock
= 1;
5064 /* "fast-path" to count number of available objects */
5065 if (nr_to_scan
== 0) {
5066 spin_lock(&shrink_list_lock
);
5067 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5068 struct drm_device
*dev
= dev_priv
->dev
;
5070 if (mutex_trylock(&dev
->struct_mutex
)) {
5071 list_for_each_entry(obj_priv
,
5072 &dev_priv
->mm
.inactive_list
,
5075 mutex_unlock(&dev
->struct_mutex
);
5078 spin_unlock(&shrink_list_lock
);
5080 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5083 spin_lock(&shrink_list_lock
);
5086 /* first scan for clean buffers */
5087 list_for_each_entry_safe(dev_priv
, next_dev
,
5088 &shrink_list
, mm
.shrink_list
) {
5089 struct drm_device
*dev
= dev_priv
->dev
;
5091 if (! mutex_trylock(&dev
->struct_mutex
))
5094 spin_unlock(&shrink_list_lock
);
5095 i915_gem_retire_requests(dev
);
5097 list_for_each_entry_safe(obj_priv
, next_obj
,
5098 &dev_priv
->mm
.inactive_list
,
5100 if (i915_gem_object_is_purgeable(obj_priv
)) {
5101 i915_gem_object_unbind(&obj_priv
->base
);
5102 if (--nr_to_scan
<= 0)
5107 spin_lock(&shrink_list_lock
);
5108 mutex_unlock(&dev
->struct_mutex
);
5112 if (nr_to_scan
<= 0)
5116 /* second pass, evict/count anything still on the inactive list */
5117 list_for_each_entry_safe(dev_priv
, next_dev
,
5118 &shrink_list
, mm
.shrink_list
) {
5119 struct drm_device
*dev
= dev_priv
->dev
;
5121 if (! mutex_trylock(&dev
->struct_mutex
))
5124 spin_unlock(&shrink_list_lock
);
5126 list_for_each_entry_safe(obj_priv
, next_obj
,
5127 &dev_priv
->mm
.inactive_list
,
5129 if (nr_to_scan
> 0) {
5130 i915_gem_object_unbind(&obj_priv
->base
);
5136 spin_lock(&shrink_list_lock
);
5137 mutex_unlock(&dev
->struct_mutex
);
5146 * We are desperate for pages, so as a last resort, wait
5147 * for the GPU to finish and discard whatever we can.
5148 * This has a dramatic impact to reduce the number of
5149 * OOM-killer events whilst running the GPU aggressively.
5151 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5152 struct drm_device
*dev
= dev_priv
->dev
;
5154 if (!mutex_trylock(&dev
->struct_mutex
))
5157 spin_unlock(&shrink_list_lock
);
5159 if (i915_gpu_is_active(dev
)) {
5164 spin_lock(&shrink_list_lock
);
5165 mutex_unlock(&dev
->struct_mutex
);
5172 spin_unlock(&shrink_list_lock
);
5177 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5182 static struct shrinker shrinker
= {
5183 .shrink
= i915_gem_shrink
,
5184 .seeks
= DEFAULT_SEEKS
,
5188 i915_gem_shrinker_init(void)
5190 register_shrinker(&shrinker
);
5194 i915_gem_shrinker_exit(void)
5196 unregister_shrinker(&shrinker
);