arch/m32r/platforms/opsput/setup.c

   1 /*
   2  *  linux/arch/m32r/platforms/opsput/setup.c
   3  *
   4  *  Setup routines for Renesas OPSPUT Board
   5  *
   6  *  Copyright (c) 2002-2005
   7  *      Hiroyuki Kondo, Hirokazu Takata,
   8  *      Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General
  11  *  Public License.  See the file "COPYING" in the main directory of this
  12  *  archive for more details.
  13  */
  14
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <asm/system.h>
  21 #include <asm/m32r.h>
  22 #include <asm/io.h>
  23
  24 /*
  25  * OPSP Interrupt Control Unit (Level 1)
  26  */
  27 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  28
  29 icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
  30
  31 static void disable_opsput_irq(unsigned int irq)
  32 {
  33         unsigned long port, data;
  34
  35         port = irq2port(irq);
  36         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  37         outl(data, port);
  38 }
  39
  40 static void enable_opsput_irq(unsigned int irq)
  41 {
  42         unsigned long port, data;
  43
  44         port = irq2port(irq);
  45         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  46         outl(data, port);
  47 }
  48
  49 static void mask_opsput(struct irq_data *data)
  50 {
  51         disable_opsput_irq(data->irq);
  52 }
  53
  54 static void unmask_opsput(struct irq_data *data)
  55 {
  56         enable_opsput_irq(data->irq);
  57 }
  58
  59 static void shutdown_opsput(struct irq_data *data)
  60 {
  61         unsigned long port;
  62
  63         port = irq2port(data->irq);
  64         outl(M32R_ICUCR_ILEVEL7, port);
  65 }
  66
  67 static struct irq_chip opsput_irq_type =
  68 {
  69         .name           = "OPSPUT-IRQ",
  70         .irq_shutdown   = shutdown_opsput,
  71         .irq_mask       = mask_opsput,
  72         .irq_unmask     = unmask_opsput,
  73 };
  74
  75 /*
  76  * Interrupt Control Unit of PLD on OPSPUT (Level 2)
  77  */
  78 #define irq2pldirq(x)           ((x) - OPSPUT_PLD_IRQ_BASE)
  79 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
  80                                  (((x) - 1) * sizeof(unsigned short)))
  81
  82 typedef struct {
  83         unsigned short icucr;  /* ICU Control Register */
  84 } pld_icu_data_t;
  85
  86 static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
  87
  88 static void disable_opsput_pld_irq(unsigned int irq)
  89 {
  90         unsigned long port, data;
  91         unsigned int pldirq;
  92
  93         pldirq = irq2pldirq(irq);
  94         port = pldirq2port(pldirq);
  95         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
  96         outw(data, port);
  97 }
  98
  99 static void enable_opsput_pld_irq(unsigned int irq)
 100 {
 101         unsigned long port, data;
 102         unsigned int pldirq;
 103
 104         pldirq = irq2pldirq(irq);
 105         port = pldirq2port(pldirq);
 106         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 107         outw(data, port);
 108 }
 109
 110 static void mask_and_ack_opsput_pld(unsigned int irq)
 111 {
 112         disable_opsput_pld_irq(irq);
 113 //      mask_and_ack_opsput(M32R_IRQ_INT1);
 114 }
 115
 116 static void end_opsput_pld_irq(unsigned int irq)
 117 {
 118         enable_opsput_pld_irq(irq);
 119         enable_opsput_irq(M32R_IRQ_INT1);
 120 }
 121
 122 static unsigned int startup_opsput_pld_irq(unsigned int irq)
 123 {
 124         enable_opsput_pld_irq(irq);
 125         return (0);
 126 }
 127
 128 static void shutdown_opsput_pld_irq(unsigned int irq)
 129 {
 130         unsigned long port;
 131         unsigned int pldirq;
 132
 133         pldirq = irq2pldirq(irq);
 134 //      shutdown_opsput_irq(M32R_IRQ_INT1);
 135         port = pldirq2port(pldirq);
 136         outw(PLD_ICUCR_ILEVEL7, port);
 137 }
 138
 139 static struct irq_chip opsput_pld_irq_type =
 140 {
 141         .name = "OPSPUT-PLD-IRQ",
 142         .startup = startup_opsput_pld_irq,
 143         .shutdown = shutdown_opsput_pld_irq,
 144         .enable = enable_opsput_pld_irq,
 145         .disable = disable_opsput_pld_irq,
 146         .ack = mask_and_ack_opsput_pld,
 147         .end = end_opsput_pld_irq
 148 };
 149
 150 /*
 151  * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
 152  */
 153 #define irq2lanpldirq(x)        ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
 154 #define lanpldirq2port(x)       (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
 155                                  (((x) - 1) * sizeof(unsigned short)))
 156
 157 static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
 158
 159 static void disable_opsput_lanpld_irq(unsigned int irq)
 160 {
 161         unsigned long port, data;
 162         unsigned int pldirq;
 163
 164         pldirq = irq2lanpldirq(irq);
 165         port = lanpldirq2port(pldirq);
 166         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 167         outw(data, port);
 168 }
 169
 170 static void enable_opsput_lanpld_irq(unsigned int irq)
 171 {
 172         unsigned long port, data;
 173         unsigned int pldirq;
 174
 175         pldirq = irq2lanpldirq(irq);
 176         port = lanpldirq2port(pldirq);
 177         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 178         outw(data, port);
 179 }
 180
 181 static void mask_and_ack_opsput_lanpld(unsigned int irq)
 182 {
 183         disable_opsput_lanpld_irq(irq);
 184 }
 185
 186 static void end_opsput_lanpld_irq(unsigned int irq)
 187 {
 188         enable_opsput_lanpld_irq(irq);
 189         enable_opsput_irq(M32R_IRQ_INT0);
 190 }
 191
 192 static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
 193 {
 194         enable_opsput_lanpld_irq(irq);
 195         return (0);
 196 }
 197
 198 static void shutdown_opsput_lanpld_irq(unsigned int irq)
 199 {
 200         unsigned long port;
 201         unsigned int pldirq;
 202
 203         pldirq = irq2lanpldirq(irq);
 204         port = lanpldirq2port(pldirq);
 205         outw(PLD_ICUCR_ILEVEL7, port);
 206 }
 207
 208 static struct irq_chip opsput_lanpld_irq_type =
 209 {
 210         .name = "OPSPUT-PLD-LAN-IRQ",
 211         .startup = startup_opsput_lanpld_irq,
 212         .shutdown = shutdown_opsput_lanpld_irq,
 213         .enable = enable_opsput_lanpld_irq,
 214         .disable = disable_opsput_lanpld_irq,
 215         .ack = mask_and_ack_opsput_lanpld,
 216         .end = end_opsput_lanpld_irq
 217 };
 218
 219 /*
 220  * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
 221  */
 222 #define irq2lcdpldirq(x)        ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
 223 #define lcdpldirq2port(x)       (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
 224                                  (((x) - 1) * sizeof(unsigned short)))
 225
 226 static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
 227
 228 static void disable_opsput_lcdpld_irq(unsigned int irq)
 229 {
 230         unsigned long port, data;
 231         unsigned int pldirq;
 232
 233         pldirq = irq2lcdpldirq(irq);
 234         port = lcdpldirq2port(pldirq);
 235         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 236         outw(data, port);
 237 }
 238
 239 static void enable_opsput_lcdpld_irq(unsigned int irq)
 240 {
 241         unsigned long port, data;
 242         unsigned int pldirq;
 243
 244         pldirq = irq2lcdpldirq(irq);
 245         port = lcdpldirq2port(pldirq);
 246         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 247         outw(data, port);
 248 }
 249
 250 static void mask_and_ack_opsput_lcdpld(unsigned int irq)
 251 {
 252         disable_opsput_lcdpld_irq(irq);
 253 }
 254
 255 static void end_opsput_lcdpld_irq(unsigned int irq)
 256 {
 257         enable_opsput_lcdpld_irq(irq);
 258         enable_opsput_irq(M32R_IRQ_INT2);
 259 }
 260
 261 static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
 262 {
 263         enable_opsput_lcdpld_irq(irq);
 264         return (0);
 265 }
 266
 267 static void shutdown_opsput_lcdpld_irq(unsigned int irq)
 268 {
 269         unsigned long port;
 270         unsigned int pldirq;
 271
 272         pldirq = irq2lcdpldirq(irq);
 273         port = lcdpldirq2port(pldirq);
 274         outw(PLD_ICUCR_ILEVEL7, port);
 275 }
 276
 277 static struct irq_chip opsput_lcdpld_irq_type =
 278 {
 279         "OPSPUT-PLD-LCD-IRQ",
 280         startup_opsput_lcdpld_irq,
 281         shutdown_opsput_lcdpld_irq,
 282         enable_opsput_lcdpld_irq,
 283         disable_opsput_lcdpld_irq,
 284         mask_and_ack_opsput_lcdpld,
 285         end_opsput_lcdpld_irq
 286 };
 287
 288 void __init init_IRQ(void)
 289 {
 290 #if defined(CONFIG_SMC91X)
 291         /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
 292         set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type);
 293         lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;     /* "H" edge sense */
 294         disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
 295 #endif  /* CONFIG_SMC91X */
 296
 297         /* MFT2 : system timer */
 298         set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
 299                                  handle_level_irq);
 300         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 301         disable_opsput_irq(M32R_IRQ_MFT2);
 302
 303         /* SIO0 : receive */
 304         set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
 305                                  handle_level_irq);
 306         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 307         disable_opsput_irq(M32R_IRQ_SIO0_R);
 308
 309         /* SIO0 : send */
 310         set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
 311                                  handle_level_irq);
 312         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 313         disable_opsput_irq(M32R_IRQ_SIO0_S);
 314
 315         /* SIO1 : receive */
 316         set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
 317                                  handle_level_irq);
 318         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 319         disable_opsput_irq(M32R_IRQ_SIO1_R);
 320
 321         /* SIO1 : send */
 322         set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
 323                                  handle_level_irq);
 324         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 325         disable_opsput_irq(M32R_IRQ_SIO1_S);
 326
 327         /* DMA1 : */
 328         set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
 329                                  handle_level_irq);
 330         icu_data[M32R_IRQ_DMA1].icucr = 0;
 331         disable_opsput_irq(M32R_IRQ_DMA1);
 332
 333 #ifdef CONFIG_SERIAL_M32R_PLDSIO
 334         /* INT#1: SIO0 Receive on PLD */
 335         set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type);
 336         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 337         disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
 338
 339         /* INT#1: SIO0 Send on PLD */
 340         set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type);
 341         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 342         disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
 343 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
 344
 345         /* INT#1: CFC IREQ on PLD */
 346         set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type);
 347         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
 348         disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
 349
 350         /* INT#1: CFC Insert on PLD */
 351         set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type);
 352         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
 353         disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
 354
 355         /* INT#1: CFC Eject on PLD */
 356         set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type);
 357         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
 358         disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
 359
 360         /*
 361          * INT0# is used for LAN, DIO
 362          * We enable it here.
 363          */
 364         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 365         enable_opsput_irq(M32R_IRQ_INT0);
 366
 367         /*
 368          * INT1# is used for UART, MMC, CF Controller in FPGA.
 369          * We enable it here.
 370          */
 371         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 372         enable_opsput_irq(M32R_IRQ_INT1);
 373
 374 #if defined(CONFIG_USB)
 375         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
 376
 377     set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type);
 378     lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;    /* "L" level sense */
 379     disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
 380 #endif
 381         /*
 382          * INT2# is used for BAT, USB, AUDIO
 383          * We enable it here.
 384          */
 385         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
 386         enable_opsput_irq(M32R_IRQ_INT2);
 387
 388 #if defined(CONFIG_VIDEO_M32R_AR)
 389         /*
 390          * INT3# is used for AR
 391          */
 392         set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
 393                                  handle_level_irq);
 394         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
 395         disable_opsput_irq(M32R_IRQ_INT3);
 396 #endif /* CONFIG_VIDEO_M32R_AR */
 397 }
 398
 399 #if defined(CONFIG_SMC91X)
 400
 401 #define LAN_IOSTART     0x300
 402 #define LAN_IOEND       0x320
 403 static struct resource smc91x_resources[] = {
 404         [0] = {
 405                 .start  = (LAN_IOSTART),
 406                 .end    = (LAN_IOEND),
 407                 .flags  = IORESOURCE_MEM,
 408         },
 409         [1] = {
 410                 .start  = OPSPUT_LAN_IRQ_LAN,
 411                 .end    = OPSPUT_LAN_IRQ_LAN,
 412                 .flags  = IORESOURCE_IRQ,
 413         }
 414 };
 415
 416 static struct platform_device smc91x_device = {
 417         .name           = "smc91x",
 418         .id             = 0,
 419         .num_resources  = ARRAY_SIZE(smc91x_resources),
 420         .resource       = smc91x_resources,
 421 };
 422 #endif
 423
 424 #if defined(CONFIG_FB_S1D13XXX)
 425
 426 #include <video/s1d13xxxfb.h>
 427 #include <asm/s1d13806.h>
 428
 429 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
 430         .initregs               = s1d13xxxfb_initregs,
 431         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
 432         .platform_init_video    = NULL,
 433 #ifdef CONFIG_PM
 434         .platform_suspend_video = NULL,
 435         .platform_resume_video  = NULL,
 436 #endif
 437 };
 438
 439 static struct resource s1d13xxxfb_resources[] = {
 440         [0] = {
 441                 .start  = 0x10600000UL,
 442                 .end    = 0x1073FFFFUL,
 443                 .flags  = IORESOURCE_MEM,
 444         },
 445         [1] = {
 446                 .start  = 0x10400000UL,
 447                 .end    = 0x104001FFUL,
 448                 .flags  = IORESOURCE_MEM,
 449         }
 450 };
 451
 452 static struct platform_device s1d13xxxfb_device = {
 453         .name           = S1D_DEVICENAME,
 454         .id             = 0,
 455         .dev            = {
 456                 .platform_data  = &s1d13xxxfb_data,
 457         },
 458         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
 459         .resource       = s1d13xxxfb_resources,
 460 };
 461 #endif
 462
 463 static int __init platform_init(void)
 464 {
 465 #if defined(CONFIG_SMC91X)
 466         platform_device_register(&smc91x_device);
 467 #endif
 468 #if defined(CONFIG_FB_S1D13XXX)
 469         platform_device_register(&s1d13xxxfb_device);
 470 #endif
 471         return 0;
 472 }
 473 arch_initcall(platform_init);