drivers/ide/opti621.c

   1 /*
   2  *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
   3  */
   4
   5 /*
   6  * Authors:
   7  * Jaromir Koutek <miri@punknet.cz>,
   8  * Jan Harkes <jaharkes@cwi.nl>,
   9  * Mark Lord <mlord@pobox.com>
  10  * Some parts of code are from ali14xx.c and from rz1000.c.
  11  *
  12  * OPTi is trademark of OPTi, Octek is trademark of Octek.
  13  *
  14  * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
  15  * and disassembled/traced setupvic.exe (DOS program).
  16  * It increases kernel code about 2 kB.
  17  * I don't have this card no more, but I hope I can get some in case
  18  * of needed development.
  19  * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
  20  * It has a place for a secondary connector in circuit, but nothing
  21  * is there. Also BIOS says no address for
  22  * secondary controller (see bellow in ide_init_opti621).
  23  * I've only tested this on my system, which only has one disk.
  24  * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
  25  * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
  26  * lockups). I tried the OCTEK double speed CD-ROM and
  27  * it does not work! But I can't boot DOS also, so it's probably
  28  * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
  29  * problems) and Seagate 1GB (as slave, WD as master). My experiences
  30  * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
  31  * it slows to about 100kB/s! I don't know why and I have
  32  * not this drive now, so I can't try it again.
  33  * I write this driver because I lost the paper ("manual") with
  34  * settings of jumpers on the card and I have to boot Linux with
  35  * Loadlin except LILO, cause I have to run the setupvic.exe program
  36  * already or I get disk errors (my test: rpm -Vf
  37  * /usr/X11R6/bin/XF86_SVGA - or any big file).
  38  * Some numbers from hdparm -t /dev/hda:
  39  * Timing buffer-cache reads:   32 MB in  3.02 seconds =10.60 MB/sec
  40  * Timing buffered disk reads:  16 MB in  5.52 seconds = 2.90 MB/sec
  41  * I have 4 Megs/s before, but I don't know why (maybe changes
  42  * in hdparm test).
  43  * After release of 0.1, I got some successful reports, so it might work.
  44  *
  45  * The main problem with OPTi is that some timings for master
  46  * and slave must be the same. For example, if you have master
  47  * PIO 3 and slave PIO 0, driver have to set some timings of
  48  * master for PIO 0. Second problem is that opti621_set_pio_mode
  49  * got only one drive to set, but have to set both drives.
  50  * This is solved in compute_pios. If you don't set
  51  * the second drive, compute_pios use ide_get_best_pio_mode
  52  * for autoselect mode (you can change it to PIO 0, if you want).
  53  * If you then set the second drive to another PIO, the old value
  54  * (automatically selected) will be overrided by yours.
  55  * There is a 25/33MHz switch in configuration
  56  * register, but driver is written for use at any frequency.
  57  *
  58  * Version 0.1, Nov 8, 1996
  59  * by Jaromir Koutek, for 2.1.8.
  60  * Initial version of driver.
  61  *
  62  * Version 0.2
  63  * Number 0.2 skipped.
  64  *
  65  * Version 0.3, Nov 29, 1997
  66  * by Mark Lord (probably), for 2.1.68
  67  * Updates for use with new IDE block driver.
  68  *
  69  * Version 0.4, Dec 14, 1997
  70  * by Jan Harkes
  71  * Fixed some errors and cleaned the code.
  72  *
  73  * Version 0.5, Jan 2, 1998
  74  * by Jaromir Koutek
  75  * Updates for use with (again) new IDE block driver.
  76  * Update of documentation.
  77  *
  78  * Version 0.6, Jan 2, 1999
  79  * by Jaromir Koutek
  80  * Reversed to version 0.3 of the driver, because
  81  * 0.5 doesn't work.
  82  */
  83
  84 #include <linux/types.h>
  85 #include <linux/module.h>
  86 #include <linux/kernel.h>
  87 #include <linux/pci.h>
  88 #include <linux/ide.h>
  89
  90 #include <asm/io.h>
  91
  92 #define DRV_NAME "opti621"
  93
  94 #define READ_REG 0      /* index of Read cycle timing register */
  95 #define WRITE_REG 1     /* index of Write cycle timing register */
  96 #define CNTRL_REG 3     /* index of Control register */
  97 #define STRAP_REG 5     /* index of Strap register */
  98 #define MISC_REG 6      /* index of Miscellaneous register */
  99
 100 static int reg_base;
 101
 102 static DEFINE_SPINLOCK(opti621_lock);
 103
 104 /* Write value to register reg, base of register
 105  * is at reg_base (0x1f0 primary, 0x170 secondary,
 106  * if not changed by PCI configuration).
 107  * This is from setupvic.exe program.
 108  */
 109 static void write_reg(u8 value, int reg)
 110 {
 111         inw(reg_base + 1);
 112         inw(reg_base + 1);
 113         outb(3, reg_base + 2);
 114         outb(value, reg_base + reg);
 115         outb(0x83, reg_base + 2);
 116 }
 117
 118 /* Read value from register reg, base of register
 119  * is at reg_base (0x1f0 primary, 0x170 secondary,
 120  * if not changed by PCI configuration).
 121  * This is from setupvic.exe program.
 122  */
 123 static u8 read_reg(int reg)
 124 {
 125         u8 ret = 0;
 126
 127         inw(reg_base + 1);
 128         inw(reg_base + 1);
 129         outb(3, reg_base + 2);
 130         ret = inb(reg_base + reg);
 131         outb(0x83, reg_base + 2);
 132
 133         return ret;
 134 }
 135
 136 static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
 137 {
 138         ide_hwif_t *hwif = drive->hwif;
 139         ide_drive_t *pair = ide_get_pair_dev(drive);
 140         unsigned long flags;
 141         unsigned long mode = XFER_PIO_0 + pio, pair_mode;
 142         u8 tim, misc, addr_pio = pio, clk;
 143
 144         /* DRDY is default 2 (by OPTi Databook) */
 145         static const u8 addr_timings[2][5] = {
 146                 { 0x20, 0x10, 0x00, 0x00, 0x00 },       /* 33 MHz */
 147                 { 0x10, 0x10, 0x00, 0x00, 0x00 },       /* 25 MHz */
 148         };
 149         static const u8 data_rec_timings[2][5] = {
 150                 { 0x5b, 0x45, 0x32, 0x21, 0x20 },       /* 33 MHz */
 151                 { 0x48, 0x34, 0x21, 0x10, 0x10 }        /* 25 MHz */
 152         };
 153
 154         ide_set_drivedata(drive, (void *)mode);
 155
 156         if (pair) {
 157                 pair_mode = (unsigned long)ide_get_drivedata(pair);
 158                 if (pair_mode && pair_mode < mode)
 159                         addr_pio = pair_mode - XFER_PIO_0;
 160         }
 161
 162         spin_lock_irqsave(&opti621_lock, flags);
 163
 164         reg_base = hwif->io_ports.data_addr;
 165
 166         /* allow Register-B */
 167         outb(0xc0, reg_base + CNTRL_REG);
 168         /* hmm, setupvic.exe does this ;-) */
 169         outb(0xff, reg_base + 5);
 170         /* if reads 0xff, adapter not exist? */
 171         (void)inb(reg_base + CNTRL_REG);
 172         /* if reads 0xc0, no interface exist? */
 173         read_reg(CNTRL_REG);
 174
 175         /* check CLK speed */
 176         clk = read_reg(STRAP_REG) & 1;
 177
 178         printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
 179
 180         tim  = data_rec_timings[clk][pio];
 181         misc = addr_timings[clk][addr_pio];
 182
 183         /* select Index-0/1 for Register-A/B */
 184         write_reg(drive->dn & 1, MISC_REG);
 185         /* set read cycle timings */
 186         write_reg(tim, READ_REG);
 187         /* set write cycle timings */
 188         write_reg(tim, WRITE_REG);
 189
 190         /* use Register-A for drive 0 */
 191         /* use Register-B for drive 1 */
 192         write_reg(0x85, CNTRL_REG);
 193
 194         /* set address setup, DRDY timings,   */
 195         /*  and read prefetch for both drives */
 196         write_reg(misc, MISC_REG);
 197
 198         spin_unlock_irqrestore(&opti621_lock, flags);
 199 }
 200
 201 static const struct ide_port_ops opti621_port_ops = {
 202         .set_pio_mode           = opti621_set_pio_mode,
 203 };
 204
 205 static const struct ide_port_info opti621_chipset __devinitdata = {
 206         .name           = DRV_NAME,
 207         .enablebits     = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
 208         .port_ops       = &opti621_port_ops,
 209         .host_flags     = IDE_HFLAG_NO_DMA,
 210         .pio_mask       = ATA_PIO4,
 211 };
 212
 213 static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 214 {
 215         return ide_pci_init_one(dev, &opti621_chipset, NULL);
 216 }
 217
 218 static const struct pci_device_id opti621_pci_tbl[] = {
 219         { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
 220         { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
 221         { 0, },
 222 };
 223 MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
 224
 225 static struct pci_driver opti621_pci_driver = {
 226         .name           = "Opti621_IDE",
 227         .id_table       = opti621_pci_tbl,
 228         .probe          = opti621_init_one,
 229         .remove         = ide_pci_remove,
 230         .suspend        = ide_pci_suspend,
 231         .resume         = ide_pci_resume,
 232 };
 233
 234 static int __init opti621_ide_init(void)
 235 {
 236         return ide_pci_register_driver(&opti621_pci_driver);
 237 }
 238
 239 static void __exit opti621_ide_exit(void)
 240 {
 241         pci_unregister_driver(&opti621_pci_driver);
 242 }
 243
 244 module_init(opti621_ide_init);
 245 module_exit(opti621_ide_exit);
 246
 247 MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
 248 MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
 249 MODULE_LICENSE("GPL");