1 #include "amd64_edac.h"
4 static struct edac_pci_ctl_info
*amd64_ctl_pci
;
6 static int report_gart_errors
;
7 module_param(report_gart_errors
, int, 0644);
10 * Set by command line parameter. If BIOS has enabled the ECC, this override is
11 * cleared to prevent re-enabling the hardware by this driver.
13 static int ecc_enable_override
;
14 module_param(ecc_enable_override
, int, 0644);
16 /* Lookup table for all possible MC control instances */
18 static struct mem_ctl_info
*mci_lookup
[EDAC_MAX_NUMNODES
];
19 static struct amd64_pvt
*pvt_lookup
[EDAC_MAX_NUMNODES
];
22 * Address to DRAM bank mapping: see F2x80 for K8 and F2x[1,0]80 for Fam10 and
25 static int ddr2_dbam_revCG
[] = {
35 static int ddr2_dbam_revD
[] = {
47 static int ddr2_dbam
[] = { [0] = 128,
56 static int ddr3_dbam
[] = { [0] = -1,
67 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
68 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
71 *FIXME: Produce a better mapping/linearisation.
74 struct scrubrate scrubrates
[] = {
75 { 0x01, 1600000000UL},
97 { 0x00, 0UL}, /* scrubbing off */
101 * Memory scrubber control interface. For K8, memory scrubbing is handled by
102 * hardware and can involve L2 cache, dcache as well as the main memory. With
103 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
106 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
107 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
108 * bytes/sec for the setting.
110 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
111 * other archs, we might not have access to the caches directly.
115 * scan the scrub rate mapping table for a close or matching bandwidth value to
116 * issue. If requested is too big, then use last maximum value found.
118 static int amd64_search_set_scrub_rate(struct pci_dev
*ctl
, u32 new_bw
,
125 * map the configured rate (new_bw) to a value specific to the AMD64
126 * memory controller and apply to register. Search for the first
127 * bandwidth entry that is greater or equal than the setting requested
128 * and program that. If at last entry, turn off DRAM scrubbing.
130 for (i
= 0; i
< ARRAY_SIZE(scrubrates
); i
++) {
132 * skip scrub rates which aren't recommended
133 * (see F10 BKDG, F3x58)
135 if (scrubrates
[i
].scrubval
< min_scrubrate
)
138 if (scrubrates
[i
].bandwidth
<= new_bw
)
142 * if no suitable bandwidth found, turn off DRAM scrubbing
143 * entirely by falling back to the last element in the
148 scrubval
= scrubrates
[i
].scrubval
;
150 edac_printk(KERN_DEBUG
, EDAC_MC
,
151 "Setting scrub rate bandwidth: %u\n",
152 scrubrates
[i
].bandwidth
);
154 edac_printk(KERN_DEBUG
, EDAC_MC
, "Turning scrubbing off.\n");
156 pci_write_bits32(ctl
, K8_SCRCTRL
, scrubval
, 0x001F);
161 static int amd64_set_scrub_rate(struct mem_ctl_info
*mci
, u32
*bandwidth
)
163 struct amd64_pvt
*pvt
= mci
->pvt_info
;
164 u32 min_scrubrate
= 0x0;
166 switch (boot_cpu_data
.x86
) {
168 min_scrubrate
= K8_MIN_SCRUB_RATE_BITS
;
171 min_scrubrate
= F10_MIN_SCRUB_RATE_BITS
;
174 min_scrubrate
= F11_MIN_SCRUB_RATE_BITS
;
178 amd64_printk(KERN_ERR
, "Unsupported family!\n");
181 return amd64_search_set_scrub_rate(pvt
->misc_f3_ctl
, *bandwidth
,
185 static int amd64_get_scrub_rate(struct mem_ctl_info
*mci
, u32
*bw
)
187 struct amd64_pvt
*pvt
= mci
->pvt_info
;
191 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_SCRCTRL
, &scrubval
);
193 scrubval
= scrubval
& 0x001F;
195 edac_printk(KERN_DEBUG
, EDAC_MC
,
196 "pci-read, sdram scrub control value: %d \n", scrubval
);
198 for (i
= 0; ARRAY_SIZE(scrubrates
); i
++) {
199 if (scrubrates
[i
].scrubval
== scrubval
) {
200 *bw
= scrubrates
[i
].bandwidth
;
209 /* Map from a CSROW entry to the mask entry that operates on it */
210 static inline u32
amd64_map_to_dcs_mask(struct amd64_pvt
*pvt
, int csrow
)
212 if (boot_cpu_data
.x86
== 0xf && pvt
->ext_model
< K8_REV_F
)
218 /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
219 static u32
amd64_get_dct_base(struct amd64_pvt
*pvt
, int dct
, int csrow
)
222 return pvt
->dcsb0
[csrow
];
224 return pvt
->dcsb1
[csrow
];
228 * Return the 'mask' address the i'th CS entry. This function is needed because
229 * there number of DCSM registers on Rev E and prior vs Rev F and later is
232 static u32
amd64_get_dct_mask(struct amd64_pvt
*pvt
, int dct
, int csrow
)
235 return pvt
->dcsm0
[amd64_map_to_dcs_mask(pvt
, csrow
)];
237 return pvt
->dcsm1
[amd64_map_to_dcs_mask(pvt
, csrow
)];
242 * In *base and *limit, pass back the full 40-bit base and limit physical
243 * addresses for the node given by node_id. This information is obtained from
244 * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The
245 * base and limit addresses are of type SysAddr, as defined at the start of
246 * section 3.4.4 (p. 70). They are the lowest and highest physical addresses
247 * in the address range they represent.
249 static void amd64_get_base_and_limit(struct amd64_pvt
*pvt
, int node_id
,
250 u64
*base
, u64
*limit
)
252 *base
= pvt
->dram_base
[node_id
];
253 *limit
= pvt
->dram_limit
[node_id
];
257 * Return 1 if the SysAddr given by sys_addr matches the base/limit associated
260 static int amd64_base_limit_match(struct amd64_pvt
*pvt
,
261 u64 sys_addr
, int node_id
)
263 u64 base
, limit
, addr
;
265 amd64_get_base_and_limit(pvt
, node_id
, &base
, &limit
);
267 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
268 * all ones if the most significant implemented address bit is 1.
269 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
270 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
271 * Application Programming.
273 addr
= sys_addr
& 0x000000ffffffffffull
;
275 return (addr
>= base
) && (addr
<= limit
);
279 * Attempt to map a SysAddr to a node. On success, return a pointer to the
280 * mem_ctl_info structure for the node that the SysAddr maps to.
282 * On failure, return NULL.
284 static struct mem_ctl_info
*find_mc_by_sys_addr(struct mem_ctl_info
*mci
,
287 struct amd64_pvt
*pvt
;
292 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
293 * 3.4.4.2) registers to map the SysAddr to a node ID.
298 * The value of this field should be the same for all DRAM Base
299 * registers. Therefore we arbitrarily choose to read it from the
300 * register for node 0.
302 intlv_en
= pvt
->dram_IntlvEn
[0];
305 for (node_id
= 0; node_id
< DRAM_REG_COUNT
; node_id
++) {
306 if (amd64_base_limit_match(pvt
, sys_addr
, node_id
))
312 if (unlikely((intlv_en
!= 0x01) &&
313 (intlv_en
!= 0x03) &&
314 (intlv_en
!= 0x07))) {
315 amd64_printk(KERN_WARNING
, "junk value of 0x%x extracted from "
316 "IntlvEn field of DRAM Base Register for node 0: "
317 "this probably indicates a BIOS bug.\n", intlv_en
);
321 bits
= (((u32
) sys_addr
) >> 12) & intlv_en
;
323 for (node_id
= 0; ; ) {
324 if ((pvt
->dram_IntlvSel
[node_id
] & intlv_en
) == bits
)
325 break; /* intlv_sel field matches */
327 if (++node_id
>= DRAM_REG_COUNT
)
331 /* sanity test for sys_addr */
332 if (unlikely(!amd64_base_limit_match(pvt
, sys_addr
, node_id
))) {
333 amd64_printk(KERN_WARNING
,
334 "%s(): sys_addr 0x%llx falls outside base/limit "
335 "address range for node %d with node interleaving "
337 __func__
, sys_addr
, node_id
);
342 return edac_mc_find(node_id
);
345 debugf2("sys_addr 0x%lx doesn't match any node\n",
346 (unsigned long)sys_addr
);
352 * Extract the DRAM CS base address from selected csrow register.
354 static u64
base_from_dct_base(struct amd64_pvt
*pvt
, int csrow
)
356 return ((u64
) (amd64_get_dct_base(pvt
, 0, csrow
) & pvt
->dcsb_base
)) <<
361 * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way.
363 static u64
mask_from_dct_mask(struct amd64_pvt
*pvt
, int csrow
)
365 u64 dcsm_bits
, other_bits
;
368 /* Extract bits from DRAM CS Mask. */
369 dcsm_bits
= amd64_get_dct_mask(pvt
, 0, csrow
) & pvt
->dcsm_mask
;
371 other_bits
= pvt
->dcsm_mask
;
372 other_bits
= ~(other_bits
<< pvt
->dcs_shift
);
375 * The extracted bits from DCSM belong in the spaces represented by
376 * the cleared bits in other_bits.
378 mask
= (dcsm_bits
<< pvt
->dcs_shift
) | other_bits
;
384 * @input_addr is an InputAddr associated with the node given by mci. Return the
385 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
387 static int input_addr_to_csrow(struct mem_ctl_info
*mci
, u64 input_addr
)
389 struct amd64_pvt
*pvt
;
396 * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS
397 * base/mask register pair, test the condition shown near the start of
398 * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
400 for (csrow
= 0; csrow
< pvt
->cs_count
; csrow
++) {
402 /* This DRAM chip select is disabled on this node */
403 if ((pvt
->dcsb0
[csrow
] & K8_DCSB_CS_ENABLE
) == 0)
406 base
= base_from_dct_base(pvt
, csrow
);
407 mask
= ~mask_from_dct_mask(pvt
, csrow
);
409 if ((input_addr
& mask
) == (base
& mask
)) {
410 debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",
411 (unsigned long)input_addr
, csrow
,
418 debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",
419 (unsigned long)input_addr
, pvt
->mc_node_id
);
425 * Return the base value defined by the DRAM Base register for the node
426 * represented by mci. This function returns the full 40-bit value despite the
427 * fact that the register only stores bits 39-24 of the value. See section
428 * 3.4.4.1 (BKDG #26094, K8, revA-E)
430 static inline u64
get_dram_base(struct mem_ctl_info
*mci
)
432 struct amd64_pvt
*pvt
= mci
->pvt_info
;
434 return pvt
->dram_base
[pvt
->mc_node_id
];
438 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
439 * for the node represented by mci. Info is passed back in *hole_base,
440 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
441 * info is invalid. Info may be invalid for either of the following reasons:
443 * - The revision of the node is not E or greater. In this case, the DRAM Hole
444 * Address Register does not exist.
446 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
447 * indicating that its contents are not valid.
449 * The values passed back in *hole_base, *hole_offset, and *hole_size are
450 * complete 32-bit values despite the fact that the bitfields in the DHAR
451 * only represent bits 31-24 of the base and offset values.
453 int amd64_get_dram_hole_info(struct mem_ctl_info
*mci
, u64
*hole_base
,
454 u64
*hole_offset
, u64
*hole_size
)
456 struct amd64_pvt
*pvt
= mci
->pvt_info
;
459 /* only revE and later have the DRAM Hole Address Register */
460 if (boot_cpu_data
.x86
== 0xf && pvt
->ext_model
< K8_REV_E
) {
461 debugf1(" revision %d for node %d does not support DHAR\n",
462 pvt
->ext_model
, pvt
->mc_node_id
);
466 /* only valid for Fam10h */
467 if (boot_cpu_data
.x86
== 0x10 &&
468 (pvt
->dhar
& F10_DRAM_MEM_HOIST_VALID
) == 0) {
469 debugf1(" Dram Memory Hoisting is DISABLED on this system\n");
473 if ((pvt
->dhar
& DHAR_VALID
) == 0) {
474 debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n",
479 /* This node has Memory Hoisting */
481 /* +------------------+--------------------+--------------------+-----
482 * | memory | DRAM hole | relocated |
483 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
485 * | | | [0x100000000, |
486 * | | | (0x100000000+ |
487 * | | | (0xffffffff-x))] |
488 * +------------------+--------------------+--------------------+-----
490 * Above is a diagram of physical memory showing the DRAM hole and the
491 * relocated addresses from the DRAM hole. As shown, the DRAM hole
492 * starts at address x (the base address) and extends through address
493 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
494 * addresses in the hole so that they start at 0x100000000.
497 base
= dhar_base(pvt
->dhar
);
500 *hole_size
= (0x1ull
<< 32) - base
;
502 if (boot_cpu_data
.x86
> 0xf)
503 *hole_offset
= f10_dhar_offset(pvt
->dhar
);
505 *hole_offset
= k8_dhar_offset(pvt
->dhar
);
507 debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
508 pvt
->mc_node_id
, (unsigned long)*hole_base
,
509 (unsigned long)*hole_offset
, (unsigned long)*hole_size
);
513 EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info
);
516 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
517 * assumed that sys_addr maps to the node given by mci.
519 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
520 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
521 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
522 * then it is also involved in translating a SysAddr to a DramAddr. Sections
523 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
524 * These parts of the documentation are unclear. I interpret them as follows:
526 * When node n receives a SysAddr, it processes the SysAddr as follows:
528 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
529 * Limit registers for node n. If the SysAddr is not within the range
530 * specified by the base and limit values, then node n ignores the Sysaddr
531 * (since it does not map to node n). Otherwise continue to step 2 below.
533 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
534 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
535 * the range of relocated addresses (starting at 0x100000000) from the DRAM
536 * hole. If not, skip to step 3 below. Else get the value of the
537 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
538 * offset defined by this value from the SysAddr.
540 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
541 * Base register for node n. To obtain the DramAddr, subtract the base
542 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
544 static u64
sys_addr_to_dram_addr(struct mem_ctl_info
*mci
, u64 sys_addr
)
546 u64 dram_base
, hole_base
, hole_offset
, hole_size
, dram_addr
;
549 dram_base
= get_dram_base(mci
);
551 ret
= amd64_get_dram_hole_info(mci
, &hole_base
, &hole_offset
,
554 if ((sys_addr
>= (1ull << 32)) &&
555 (sys_addr
< ((1ull << 32) + hole_size
))) {
556 /* use DHAR to translate SysAddr to DramAddr */
557 dram_addr
= sys_addr
- hole_offset
;
559 debugf2("using DHAR to translate SysAddr 0x%lx to "
561 (unsigned long)sys_addr
,
562 (unsigned long)dram_addr
);
569 * Translate the SysAddr to a DramAddr as shown near the start of
570 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
571 * only deals with 40-bit values. Therefore we discard bits 63-40 of
572 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
573 * discard are all 1s. Otherwise the bits we discard are all 0s. See
574 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
575 * Programmer's Manual Volume 1 Application Programming.
577 dram_addr
= (sys_addr
& 0xffffffffffull
) - dram_base
;
579 debugf2("using DRAM Base register to translate SysAddr 0x%lx to "
580 "DramAddr 0x%lx\n", (unsigned long)sys_addr
,
581 (unsigned long)dram_addr
);
586 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
587 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
588 * for node interleaving.
590 static int num_node_interleave_bits(unsigned intlv_en
)
592 static const int intlv_shift_table
[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
595 BUG_ON(intlv_en
> 7);
596 n
= intlv_shift_table
[intlv_en
];
600 /* Translate the DramAddr given by @dram_addr to an InputAddr. */
601 static u64
dram_addr_to_input_addr(struct mem_ctl_info
*mci
, u64 dram_addr
)
603 struct amd64_pvt
*pvt
;
610 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
611 * concerning translating a DramAddr to an InputAddr.
613 intlv_shift
= num_node_interleave_bits(pvt
->dram_IntlvEn
[0]);
614 input_addr
= ((dram_addr
>> intlv_shift
) & 0xffffff000ull
) +
617 debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
618 intlv_shift
, (unsigned long)dram_addr
,
619 (unsigned long)input_addr
);
625 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
626 * assumed that @sys_addr maps to the node given by mci.
628 static u64
sys_addr_to_input_addr(struct mem_ctl_info
*mci
, u64 sys_addr
)
633 dram_addr_to_input_addr(mci
, sys_addr_to_dram_addr(mci
, sys_addr
));
635 debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
636 (unsigned long)sys_addr
, (unsigned long)input_addr
);
643 * @input_addr is an InputAddr associated with the node represented by mci.
644 * Translate @input_addr to a DramAddr and return the result.
646 static u64
input_addr_to_dram_addr(struct mem_ctl_info
*mci
, u64 input_addr
)
648 struct amd64_pvt
*pvt
;
649 int node_id
, intlv_shift
;
654 * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
655 * shows how to translate a DramAddr to an InputAddr. Here we reverse
656 * this procedure. When translating from a DramAddr to an InputAddr, the
657 * bits used for node interleaving are discarded. Here we recover these
658 * bits from the IntlvSel field of the DRAM Limit register (section
659 * 3.4.4.2) for the node that input_addr is associated with.
662 node_id
= pvt
->mc_node_id
;
663 BUG_ON((node_id
< 0) || (node_id
> 7));
665 intlv_shift
= num_node_interleave_bits(pvt
->dram_IntlvEn
[0]);
667 if (intlv_shift
== 0) {
668 debugf1(" InputAddr 0x%lx translates to DramAddr of "
669 "same value\n", (unsigned long)input_addr
);
674 bits
= ((input_addr
& 0xffffff000ull
) << intlv_shift
) +
675 (input_addr
& 0xfff);
677 intlv_sel
= pvt
->dram_IntlvSel
[node_id
] & ((1 << intlv_shift
) - 1);
678 dram_addr
= bits
+ (intlv_sel
<< 12);
680 debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx "
681 "(%d node interleave bits)\n", (unsigned long)input_addr
,
682 (unsigned long)dram_addr
, intlv_shift
);
688 * @dram_addr is a DramAddr that maps to the node represented by mci. Convert
689 * @dram_addr to a SysAddr.
691 static u64
dram_addr_to_sys_addr(struct mem_ctl_info
*mci
, u64 dram_addr
)
693 struct amd64_pvt
*pvt
= mci
->pvt_info
;
694 u64 hole_base
, hole_offset
, hole_size
, base
, limit
, sys_addr
;
697 ret
= amd64_get_dram_hole_info(mci
, &hole_base
, &hole_offset
,
700 if ((dram_addr
>= hole_base
) &&
701 (dram_addr
< (hole_base
+ hole_size
))) {
702 sys_addr
= dram_addr
+ hole_offset
;
704 debugf1("using DHAR to translate DramAddr 0x%lx to "
705 "SysAddr 0x%lx\n", (unsigned long)dram_addr
,
706 (unsigned long)sys_addr
);
712 amd64_get_base_and_limit(pvt
, pvt
->mc_node_id
, &base
, &limit
);
713 sys_addr
= dram_addr
+ base
;
716 * The sys_addr we have computed up to this point is a 40-bit value
717 * because the k8 deals with 40-bit values. However, the value we are
718 * supposed to return is a full 64-bit physical address. The AMD
719 * x86-64 architecture specifies that the most significant implemented
720 * address bit through bit 63 of a physical address must be either all
721 * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a
722 * 64-bit value below. See section 3.4.2 of AMD publication 24592:
723 * AMD x86-64 Architecture Programmer's Manual Volume 1 Application
726 sys_addr
|= ~((sys_addr
& (1ull << 39)) - 1);
728 debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
729 pvt
->mc_node_id
, (unsigned long)dram_addr
,
730 (unsigned long)sys_addr
);
736 * @input_addr is an InputAddr associated with the node given by mci. Translate
737 * @input_addr to a SysAddr.
739 static inline u64
input_addr_to_sys_addr(struct mem_ctl_info
*mci
,
742 return dram_addr_to_sys_addr(mci
,
743 input_addr_to_dram_addr(mci
, input_addr
));
747 * Find the minimum and maximum InputAddr values that map to the given @csrow.
748 * Pass back these values in *input_addr_min and *input_addr_max.
750 static void find_csrow_limits(struct mem_ctl_info
*mci
, int csrow
,
751 u64
*input_addr_min
, u64
*input_addr_max
)
753 struct amd64_pvt
*pvt
;
757 BUG_ON((csrow
< 0) || (csrow
>= pvt
->cs_count
));
759 base
= base_from_dct_base(pvt
, csrow
);
760 mask
= mask_from_dct_mask(pvt
, csrow
);
762 *input_addr_min
= base
& ~mask
;
763 *input_addr_max
= base
| mask
| pvt
->dcs_mask_notused
;
766 /* Map the Error address to a PAGE and PAGE OFFSET. */
767 static inline void error_address_to_page_and_offset(u64 error_address
,
768 u32
*page
, u32
*offset
)
770 *page
= (u32
) (error_address
>> PAGE_SHIFT
);
771 *offset
= ((u32
) error_address
) & ~PAGE_MASK
;
775 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
776 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
777 * of a node that detected an ECC memory error. mci represents the node that
778 * the error address maps to (possibly different from the node that detected
779 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
782 static int sys_addr_to_csrow(struct mem_ctl_info
*mci
, u64 sys_addr
)
786 csrow
= input_addr_to_csrow(mci
, sys_addr_to_input_addr(mci
, sys_addr
));
789 amd64_mc_printk(mci
, KERN_ERR
,
790 "Failed to translate InputAddr to csrow for "
791 "address 0x%lx\n", (unsigned long)sys_addr
);
795 static int get_channel_from_ecc_syndrome(struct mem_ctl_info
*, u16
);
797 static void amd64_cpu_display_info(struct amd64_pvt
*pvt
)
799 if (boot_cpu_data
.x86
== 0x11)
800 edac_printk(KERN_DEBUG
, EDAC_MC
, "F11h CPU detected\n");
801 else if (boot_cpu_data
.x86
== 0x10)
802 edac_printk(KERN_DEBUG
, EDAC_MC
, "F10h CPU detected\n");
803 else if (boot_cpu_data
.x86
== 0xf)
804 edac_printk(KERN_DEBUG
, EDAC_MC
, "%s detected\n",
805 (pvt
->ext_model
>= K8_REV_F
) ?
806 "Rev F or later" : "Rev E or earlier");
808 /* we'll hardly ever ever get here */
809 edac_printk(KERN_ERR
, EDAC_MC
, "Unknown cpu!\n");
813 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
816 static enum edac_type
amd64_determine_edac_cap(struct amd64_pvt
*pvt
)
819 enum dev_type edac_cap
= EDAC_FLAG_NONE
;
821 bit
= (boot_cpu_data
.x86
> 0xf || pvt
->ext_model
>= K8_REV_F
)
825 if (pvt
->dclr0
& BIT(bit
))
826 edac_cap
= EDAC_FLAG_SECDED
;
832 static void amd64_debug_display_dimm_sizes(int ctrl
, struct amd64_pvt
*pvt
);
834 static void amd64_dump_dramcfg_low(u32 dclr
, int chan
)
836 debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan
, dclr
);
838 debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
839 (dclr
& BIT(16)) ? "un" : "",
840 (dclr
& BIT(19)) ? "yes" : "no");
842 debugf1(" PAR/ERR parity: %s\n",
843 (dclr
& BIT(8)) ? "enabled" : "disabled");
845 debugf1(" DCT 128bit mode width: %s\n",
846 (dclr
& BIT(11)) ? "128b" : "64b");
848 debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
849 (dclr
& BIT(12)) ? "yes" : "no",
850 (dclr
& BIT(13)) ? "yes" : "no",
851 (dclr
& BIT(14)) ? "yes" : "no",
852 (dclr
& BIT(15)) ? "yes" : "no");
855 /* Display and decode various NB registers for debug purposes. */
856 static void amd64_dump_misc_regs(struct amd64_pvt
*pvt
)
860 debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt
->nbcap
);
862 debugf1(" NB two channel DRAM capable: %s\n",
863 (pvt
->nbcap
& K8_NBCAP_DCT_DUAL
) ? "yes" : "no");
865 debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n",
866 (pvt
->nbcap
& K8_NBCAP_SECDED
) ? "yes" : "no",
867 (pvt
->nbcap
& K8_NBCAP_CHIPKILL
) ? "yes" : "no");
869 amd64_dump_dramcfg_low(pvt
->dclr0
, 0);
871 debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt
->online_spare
);
873 debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, "
876 dhar_base(pvt
->dhar
),
877 (boot_cpu_data
.x86
== 0xf) ? k8_dhar_offset(pvt
->dhar
)
878 : f10_dhar_offset(pvt
->dhar
));
880 debugf1(" DramHoleValid: %s\n",
881 (pvt
->dhar
& DHAR_VALID
) ? "yes" : "no");
883 /* everything below this point is Fam10h and above */
884 if (boot_cpu_data
.x86
== 0xf) {
885 amd64_debug_display_dimm_sizes(0, pvt
);
889 /* Only if NOT ganged does dclr1 have valid info */
890 if (!dct_ganging_enabled(pvt
))
891 amd64_dump_dramcfg_low(pvt
->dclr1
, 1);
894 * Determine if ganged and then dump memory sizes for first controller,
895 * and if NOT ganged dump info for 2nd controller.
897 ganged
= dct_ganging_enabled(pvt
);
899 amd64_debug_display_dimm_sizes(0, pvt
);
902 amd64_debug_display_dimm_sizes(1, pvt
);
905 /* Read in both of DBAM registers */
906 static void amd64_read_dbam_reg(struct amd64_pvt
*pvt
)
908 amd64_read_pci_cfg(pvt
->dram_f2_ctl
, DBAM0
, &pvt
->dbam0
);
910 if (boot_cpu_data
.x86
>= 0x10)
911 amd64_read_pci_cfg(pvt
->dram_f2_ctl
, DBAM1
, &pvt
->dbam1
);
915 * NOTE: CPU Revision Dependent code: Rev E and Rev F
917 * Set the DCSB and DCSM mask values depending on the CPU revision value. Also
918 * set the shift factor for the DCSB and DCSM values.
920 * ->dcs_mask_notused, RevE:
922 * To find the max InputAddr for the csrow, start with the base address and set
923 * all bits that are "don't care" bits in the test at the start of section
926 * The "don't care" bits are all set bits in the mask and all bits in the gaps
927 * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS
928 * represents bits [24:20] and [12:0], which are all bits in the above-mentioned
931 * ->dcs_mask_notused, RevF and later:
933 * To find the max InputAddr for the csrow, start with the base address and set
934 * all bits that are "don't care" bits in the test at the start of NPT section
937 * The "don't care" bits are all set bits in the mask and all bits in the gaps
938 * between bit ranges [36:27] and [21:13].
940 * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0],
941 * which are all bits in the above-mentioned gaps.
943 static void amd64_set_dct_base_and_mask(struct amd64_pvt
*pvt
)
946 if (boot_cpu_data
.x86
== 0xf && pvt
->ext_model
< K8_REV_F
) {
947 pvt
->dcsb_base
= REV_E_DCSB_BASE_BITS
;
948 pvt
->dcsm_mask
= REV_E_DCSM_MASK_BITS
;
949 pvt
->dcs_mask_notused
= REV_E_DCS_NOTUSED_BITS
;
950 pvt
->dcs_shift
= REV_E_DCS_SHIFT
;
954 pvt
->dcsb_base
= REV_F_F1Xh_DCSB_BASE_BITS
;
955 pvt
->dcsm_mask
= REV_F_F1Xh_DCSM_MASK_BITS
;
956 pvt
->dcs_mask_notused
= REV_F_F1Xh_DCS_NOTUSED_BITS
;
957 pvt
->dcs_shift
= REV_F_F1Xh_DCS_SHIFT
;
959 if (boot_cpu_data
.x86
== 0x11) {
970 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers
972 static void amd64_read_dct_base_mask(struct amd64_pvt
*pvt
)
976 amd64_set_dct_base_and_mask(pvt
);
978 for (cs
= 0; cs
< pvt
->cs_count
; cs
++) {
979 reg
= K8_DCSB0
+ (cs
* 4);
980 if (!amd64_read_pci_cfg(pvt
->dram_f2_ctl
, reg
, &pvt
->dcsb0
[cs
]))
981 debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n",
982 cs
, pvt
->dcsb0
[cs
], reg
);
984 /* If DCT are NOT ganged, then read in DCT1's base */
985 if (boot_cpu_data
.x86
>= 0x10 && !dct_ganging_enabled(pvt
)) {
986 reg
= F10_DCSB1
+ (cs
* 4);
987 if (!amd64_read_pci_cfg(pvt
->dram_f2_ctl
, reg
,
989 debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n",
990 cs
, pvt
->dcsb1
[cs
], reg
);
996 for (cs
= 0; cs
< pvt
->num_dcsm
; cs
++) {
997 reg
= K8_DCSM0
+ (cs
* 4);
998 if (!amd64_read_pci_cfg(pvt
->dram_f2_ctl
, reg
, &pvt
->dcsm0
[cs
]))
999 debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n",
1000 cs
, pvt
->dcsm0
[cs
], reg
);
1002 /* If DCT are NOT ganged, then read in DCT1's mask */
1003 if (boot_cpu_data
.x86
>= 0x10 && !dct_ganging_enabled(pvt
)) {
1004 reg
= F10_DCSM1
+ (cs
* 4);
1005 if (!amd64_read_pci_cfg(pvt
->dram_f2_ctl
, reg
,
1007 debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n",
1008 cs
, pvt
->dcsm1
[cs
], reg
);
1015 static enum mem_type
amd64_determine_memory_type(struct amd64_pvt
*pvt
)
1019 if (boot_cpu_data
.x86
>= 0x10 || pvt
->ext_model
>= K8_REV_F
) {
1020 if (pvt
->dchr0
& DDR3_MODE
)
1021 type
= (pvt
->dclr0
& BIT(16)) ? MEM_DDR3
: MEM_RDDR3
;
1023 type
= (pvt
->dclr0
& BIT(16)) ? MEM_DDR2
: MEM_RDDR2
;
1025 type
= (pvt
->dclr0
& BIT(18)) ? MEM_DDR
: MEM_RDDR
;
1028 debugf1(" Memory type is: %s\n", edac_mem_types
[type
]);
1034 * Read the DRAM Configuration Low register. It differs between CG, D & E revs
1035 * and the later RevF memory controllers (DDR vs DDR2)
1038 * number of memory channels in operation
1040 * contents of the DCL0_LOW register
1042 static int k8_early_channel_count(struct amd64_pvt
*pvt
)
1046 err
= amd64_read_pci_cfg(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
1050 if ((boot_cpu_data
.x86_model
>> 4) >= K8_REV_F
) {
1051 /* RevF (NPT) and later */
1052 flag
= pvt
->dclr0
& F10_WIDTH_128
;
1054 /* RevE and earlier */
1055 flag
= pvt
->dclr0
& REVE_WIDTH_128
;
1061 return (flag
) ? 2 : 1;
1064 /* extract the ERROR ADDRESS for the K8 CPUs */
1065 static u64
k8_get_error_address(struct mem_ctl_info
*mci
,
1066 struct err_regs
*info
)
1068 return (((u64
) (info
->nbeah
& 0xff)) << 32) +
1069 (info
->nbeal
& ~0x03);
1073 * Read the Base and Limit registers for K8 based Memory controllers; extract
1074 * fields from the 'raw' reg into separate data fields
1076 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN
1078 static void k8_read_dram_base_limit(struct amd64_pvt
*pvt
, int dram
)
1081 u32 off
= dram
<< 3; /* 8 bytes between DRAM entries */
1083 amd64_read_pci_cfg(pvt
->addr_f1_ctl
, K8_DRAM_BASE_LOW
+ off
, &low
);
1085 /* Extract parts into separate data entries */
1086 pvt
->dram_base
[dram
] = ((u64
) low
& 0xFFFF0000) << 8;
1087 pvt
->dram_IntlvEn
[dram
] = (low
>> 8) & 0x7;
1088 pvt
->dram_rw_en
[dram
] = (low
& 0x3);
1090 amd64_read_pci_cfg(pvt
->addr_f1_ctl
, K8_DRAM_LIMIT_LOW
+ off
, &low
);
1093 * Extract parts into separate data entries. Limit is the HIGHEST memory
1094 * location of the region, so lower 24 bits need to be all ones
1096 pvt
->dram_limit
[dram
] = (((u64
) low
& 0xFFFF0000) << 8) | 0x00FFFFFF;
1097 pvt
->dram_IntlvSel
[dram
] = (low
>> 8) & 0x7;
1098 pvt
->dram_DstNode
[dram
] = (low
& 0x7);
1101 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info
*mci
,
1102 struct err_regs
*info
,
1105 struct mem_ctl_info
*src_mci
;
1106 unsigned short syndrome
;
1110 /* Extract the syndrome parts and form a 16-bit syndrome */
1111 syndrome
= HIGH_SYNDROME(info
->nbsl
) << 8;
1112 syndrome
|= LOW_SYNDROME(info
->nbsh
);
1114 /* CHIPKILL enabled */
1115 if (info
->nbcfg
& K8_NBCFG_CHIPKILL
) {
1116 channel
= get_channel_from_ecc_syndrome(mci
, syndrome
);
1119 * Syndrome didn't map, so we don't know which of the
1120 * 2 DIMMs is in error. So we need to ID 'both' of them
1123 amd64_mc_printk(mci
, KERN_WARNING
,
1124 "unknown syndrome 0x%x - possible error "
1125 "reporting race\n", syndrome
);
1126 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1131 * non-chipkill ecc mode
1133 * The k8 documentation is unclear about how to determine the
1134 * channel number when using non-chipkill memory. This method
1135 * was obtained from email communication with someone at AMD.
1136 * (Wish the email was placed in this comment - norsk)
1138 channel
= ((sys_addr
& BIT(3)) != 0);
1142 * Find out which node the error address belongs to. This may be
1143 * different from the node that detected the error.
1145 src_mci
= find_mc_by_sys_addr(mci
, sys_addr
);
1147 amd64_mc_printk(mci
, KERN_ERR
,
1148 "failed to map error address 0x%lx to a node\n",
1149 (unsigned long)sys_addr
);
1150 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1154 /* Now map the sys_addr to a CSROW */
1155 csrow
= sys_addr_to_csrow(src_mci
, sys_addr
);
1157 edac_mc_handle_ce_no_info(src_mci
, EDAC_MOD_STR
);
1159 error_address_to_page_and_offset(sys_addr
, &page
, &offset
);
1161 edac_mc_handle_ce(src_mci
, page
, offset
, syndrome
, csrow
,
1162 channel
, EDAC_MOD_STR
);
1166 static int k8_dbam_to_chip_select(struct amd64_pvt
*pvt
, int cs_mode
)
1170 if (pvt
->ext_model
>= K8_REV_F
)
1171 dbam_map
= ddr2_dbam
;
1172 else if (pvt
->ext_model
>= K8_REV_D
)
1173 dbam_map
= ddr2_dbam_revD
;
1175 dbam_map
= ddr2_dbam_revCG
;
1177 return dbam_map
[cs_mode
];
1181 * Get the number of DCT channels in use.
1184 * number of Memory Channels in operation
1186 * contents of the DCL0_LOW register
1188 static int f10_early_channel_count(struct amd64_pvt
*pvt
)
1190 int dbams
[] = { DBAM0
, DBAM1
};
1191 int i
, j
, channels
= 0;
1194 /* If we are in 128 bit mode, then we are using 2 channels */
1195 if (pvt
->dclr0
& F10_WIDTH_128
) {
1201 * Need to check if in unganged mode: In such, there are 2 channels,
1202 * but they are not in 128 bit mode and thus the above 'dclr0' status
1205 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1206 * their CSEnable bit on. If so, then SINGLE DIMM case.
1208 debugf0("Data width is not 128 bits - need more decoding\n");
1211 * Check DRAM Bank Address Mapping values for each DIMM to see if there
1212 * is more than just one DIMM present in unganged mode. Need to check
1213 * both controllers since DIMMs can be placed in either one.
1215 for (i
= 0; i
< ARRAY_SIZE(dbams
); i
++) {
1216 if (amd64_read_pci_cfg(pvt
->dram_f2_ctl
, dbams
[i
], &dbam
))
1219 for (j
= 0; j
< 4; j
++) {
1220 if (DBAM_DIMM(j
, dbam
) > 0) {
1230 debugf0("MCT channel count: %d\n", channels
);
1239 static int f10_dbam_to_chip_select(struct amd64_pvt
*pvt
, int cs_mode
)
1243 if (pvt
->dchr0
& DDR3_MODE
|| pvt
->dchr1
& DDR3_MODE
)
1244 dbam_map
= ddr3_dbam
;
1246 dbam_map
= ddr2_dbam
;
1248 return dbam_map
[cs_mode
];
1251 /* Enable extended configuration access via 0xCF8 feature */
1252 static void amd64_setup(struct amd64_pvt
*pvt
)
1256 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, ®
);
1258 pvt
->flags
.cf8_extcfg
= !!(reg
& F10_NB_CFG_LOW_ENABLE_EXT_CFG
);
1259 reg
|= F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1260 pci_write_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, reg
);
1263 /* Restore the extended configuration access via 0xCF8 feature */
1264 static void amd64_teardown(struct amd64_pvt
*pvt
)
1268 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, ®
);
1270 reg
&= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1271 if (pvt
->flags
.cf8_extcfg
)
1272 reg
|= F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1273 pci_write_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, reg
);
1276 static u64
f10_get_error_address(struct mem_ctl_info
*mci
,
1277 struct err_regs
*info
)
1279 return (((u64
) (info
->nbeah
& 0xffff)) << 32) +
1280 (info
->nbeal
& ~0x01);
1284 * Read the Base and Limit registers for F10 based Memory controllers. Extract
1285 * fields from the 'raw' reg into separate data fields.
1287 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN.
1289 static void f10_read_dram_base_limit(struct amd64_pvt
*pvt
, int dram
)
1291 u32 high_offset
, low_offset
, high_base
, low_base
, high_limit
, low_limit
;
1293 low_offset
= K8_DRAM_BASE_LOW
+ (dram
<< 3);
1294 high_offset
= F10_DRAM_BASE_HIGH
+ (dram
<< 3);
1296 /* read the 'raw' DRAM BASE Address register */
1297 amd64_read_pci_cfg(pvt
->addr_f1_ctl
, low_offset
, &low_base
);
1299 /* Read from the ECS data register */
1300 amd64_read_pci_cfg(pvt
->addr_f1_ctl
, high_offset
, &high_base
);
1302 /* Extract parts into separate data entries */
1303 pvt
->dram_rw_en
[dram
] = (low_base
& 0x3);
1305 if (pvt
->dram_rw_en
[dram
] == 0)
1308 pvt
->dram_IntlvEn
[dram
] = (low_base
>> 8) & 0x7;
1310 pvt
->dram_base
[dram
] = (((u64
)high_base
& 0x000000FF) << 40) |
1311 (((u64
)low_base
& 0xFFFF0000) << 8);
1313 low_offset
= K8_DRAM_LIMIT_LOW
+ (dram
<< 3);
1314 high_offset
= F10_DRAM_LIMIT_HIGH
+ (dram
<< 3);
1316 /* read the 'raw' LIMIT registers */
1317 amd64_read_pci_cfg(pvt
->addr_f1_ctl
, low_offset
, &low_limit
);
1319 /* Read from the ECS data register for the HIGH portion */
1320 amd64_read_pci_cfg(pvt
->addr_f1_ctl
, high_offset
, &high_limit
);
1322 pvt
->dram_DstNode
[dram
] = (low_limit
& 0x7);
1323 pvt
->dram_IntlvSel
[dram
] = (low_limit
>> 8) & 0x7;
1326 * Extract address values and form a LIMIT address. Limit is the HIGHEST
1327 * memory location of the region, so low 24 bits need to be all ones.
1329 pvt
->dram_limit
[dram
] = (((u64
)high_limit
& 0x000000FF) << 40) |
1330 (((u64
) low_limit
& 0xFFFF0000) << 8) |
1334 static void f10_read_dram_ctl_register(struct amd64_pvt
*pvt
)
1337 if (!amd64_read_pci_cfg(pvt
->dram_f2_ctl
, F10_DCTL_SEL_LOW
,
1338 &pvt
->dram_ctl_select_low
)) {
1339 debugf0("F2x110 (DCTL Sel. Low): 0x%08x, "
1340 "High range addresses at: 0x%x\n",
1341 pvt
->dram_ctl_select_low
,
1342 dct_sel_baseaddr(pvt
));
1344 debugf0(" DCT mode: %s, All DCTs on: %s\n",
1345 (dct_ganging_enabled(pvt
) ? "ganged" : "unganged"),
1346 (dct_dram_enabled(pvt
) ? "yes" : "no"));
1348 if (!dct_ganging_enabled(pvt
))
1349 debugf0(" Address range split per DCT: %s\n",
1350 (dct_high_range_enabled(pvt
) ? "yes" : "no"));
1352 debugf0(" DCT data interleave for ECC: %s, "
1353 "DRAM cleared since last warm reset: %s\n",
1354 (dct_data_intlv_enabled(pvt
) ? "enabled" : "disabled"),
1355 (dct_memory_cleared(pvt
) ? "yes" : "no"));
1357 debugf0(" DCT channel interleave: %s, "
1358 "DCT interleave bits selector: 0x%x\n",
1359 (dct_interleave_enabled(pvt
) ? "enabled" : "disabled"),
1360 dct_sel_interleave_addr(pvt
));
1363 amd64_read_pci_cfg(pvt
->dram_f2_ctl
, F10_DCTL_SEL_HIGH
,
1364 &pvt
->dram_ctl_select_high
);
1368 * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1369 * Interleaving Modes.
1371 static u32
f10_determine_channel(struct amd64_pvt
*pvt
, u64 sys_addr
,
1372 int hi_range_sel
, u32 intlv_en
)
1374 u32 cs
, temp
, dct_sel_high
= (pvt
->dram_ctl_select_low
>> 1) & 1;
1376 if (dct_ganging_enabled(pvt
))
1378 else if (hi_range_sel
)
1380 else if (dct_interleave_enabled(pvt
)) {
1382 * see F2x110[DctSelIntLvAddr] - channel interleave mode
1384 if (dct_sel_interleave_addr(pvt
) == 0)
1385 cs
= sys_addr
>> 6 & 1;
1386 else if ((dct_sel_interleave_addr(pvt
) >> 1) & 1) {
1387 temp
= hweight_long((u32
) ((sys_addr
>> 16) & 0x1F)) % 2;
1389 if (dct_sel_interleave_addr(pvt
) & 1)
1390 cs
= (sys_addr
>> 9 & 1) ^ temp
;
1392 cs
= (sys_addr
>> 6 & 1) ^ temp
;
1393 } else if (intlv_en
& 4)
1394 cs
= sys_addr
>> 15 & 1;
1395 else if (intlv_en
& 2)
1396 cs
= sys_addr
>> 14 & 1;
1397 else if (intlv_en
& 1)
1398 cs
= sys_addr
>> 13 & 1;
1400 cs
= sys_addr
>> 12 & 1;
1401 } else if (dct_high_range_enabled(pvt
) && !dct_ganging_enabled(pvt
))
1402 cs
= ~dct_sel_high
& 1;
1409 static inline u32
f10_map_intlv_en_to_shift(u32 intlv_en
)
1413 else if (intlv_en
== 3)
1415 else if (intlv_en
== 7)
1421 /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */
1422 static inline u64
f10_get_base_addr_offset(u64 sys_addr
, int hi_range_sel
,
1423 u32 dct_sel_base_addr
,
1424 u64 dct_sel_base_off
,
1425 u32 hole_valid
, u32 hole_off
,
1431 if (!(dct_sel_base_addr
& 0xFFFFF800) &&
1432 hole_valid
&& (sys_addr
>= 0x100000000ULL
))
1433 chan_off
= hole_off
<< 16;
1435 chan_off
= dct_sel_base_off
;
1437 if (hole_valid
&& (sys_addr
>= 0x100000000ULL
))
1438 chan_off
= hole_off
<< 16;
1440 chan_off
= dram_base
& 0xFFFFF8000000ULL
;
1443 return (sys_addr
& 0x0000FFFFFFFFFFC0ULL
) -
1444 (chan_off
& 0x0000FFFFFF800000ULL
);
1447 /* Hack for the time being - Can we get this from BIOS?? */
1448 #define CH0SPARE_RANK 0
1449 #define CH1SPARE_RANK 1
1452 * checks if the csrow passed in is marked as SPARED, if so returns the new
1455 static inline int f10_process_possible_spare(int csrow
,
1456 u32 cs
, struct amd64_pvt
*pvt
)
1461 /* Depending on channel, isolate respective SPARING info */
1463 swap_done
= F10_ONLINE_SPARE_SWAPDONE1(pvt
->online_spare
);
1464 bad_dram_cs
= F10_ONLINE_SPARE_BADDRAM_CS1(pvt
->online_spare
);
1465 if (swap_done
&& (csrow
== bad_dram_cs
))
1466 csrow
= CH1SPARE_RANK
;
1468 swap_done
= F10_ONLINE_SPARE_SWAPDONE0(pvt
->online_spare
);
1469 bad_dram_cs
= F10_ONLINE_SPARE_BADDRAM_CS0(pvt
->online_spare
);
1470 if (swap_done
&& (csrow
== bad_dram_cs
))
1471 csrow
= CH0SPARE_RANK
;
1477 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
1478 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
1481 * -EINVAL: NOT FOUND
1482 * 0..csrow = Chip-Select Row
1484 static int f10_lookup_addr_in_dct(u32 in_addr
, u32 nid
, u32 cs
)
1486 struct mem_ctl_info
*mci
;
1487 struct amd64_pvt
*pvt
;
1488 u32 cs_base
, cs_mask
;
1489 int cs_found
= -EINVAL
;
1492 mci
= mci_lookup
[nid
];
1496 pvt
= mci
->pvt_info
;
1498 debugf1("InputAddr=0x%x channelselect=%d\n", in_addr
, cs
);
1500 for (csrow
= 0; csrow
< pvt
->cs_count
; csrow
++) {
1502 cs_base
= amd64_get_dct_base(pvt
, cs
, csrow
);
1503 if (!(cs_base
& K8_DCSB_CS_ENABLE
))
1507 * We have an ENABLED CSROW, Isolate just the MASK bits of the
1508 * target: [28:19] and [13:5], which map to [36:27] and [21:13]
1509 * of the actual address.
1511 cs_base
&= REV_F_F1Xh_DCSB_BASE_BITS
;
1514 * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and
1515 * [4:0] to become ON. Then mask off bits [28:0] ([36:8])
1517 cs_mask
= amd64_get_dct_mask(pvt
, cs
, csrow
);
1519 debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n",
1520 csrow
, cs_base
, cs_mask
);
1522 cs_mask
= (cs_mask
| 0x0007C01F) & 0x1FFFFFFF;
1524 debugf1(" Final CSMask=0x%x\n", cs_mask
);
1525 debugf1(" (InputAddr & ~CSMask)=0x%x "
1526 "(CSBase & ~CSMask)=0x%x\n",
1527 (in_addr
& ~cs_mask
), (cs_base
& ~cs_mask
));
1529 if ((in_addr
& ~cs_mask
) == (cs_base
& ~cs_mask
)) {
1530 cs_found
= f10_process_possible_spare(csrow
, cs
, pvt
);
1532 debugf1(" MATCH csrow=%d\n", cs_found
);
1539 /* For a given @dram_range, check if @sys_addr falls within it. */
1540 static int f10_match_to_this_node(struct amd64_pvt
*pvt
, int dram_range
,
1541 u64 sys_addr
, int *nid
, int *chan_sel
)
1543 int node_id
, cs_found
= -EINVAL
, high_range
= 0;
1544 u32 intlv_en
, intlv_sel
, intlv_shift
, hole_off
;
1545 u32 hole_valid
, tmp
, dct_sel_base
, channel
;
1546 u64 dram_base
, chan_addr
, dct_sel_base_off
;
1548 dram_base
= pvt
->dram_base
[dram_range
];
1549 intlv_en
= pvt
->dram_IntlvEn
[dram_range
];
1551 node_id
= pvt
->dram_DstNode
[dram_range
];
1552 intlv_sel
= pvt
->dram_IntlvSel
[dram_range
];
1554 debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
1555 dram_range
, dram_base
, sys_addr
, pvt
->dram_limit
[dram_range
]);
1558 * This assumes that one node's DHAR is the same as all the other
1561 hole_off
= (pvt
->dhar
& 0x0000FF80);
1562 hole_valid
= (pvt
->dhar
& 0x1);
1563 dct_sel_base_off
= (pvt
->dram_ctl_select_high
& 0xFFFFFC00) << 16;
1565 debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n",
1566 hole_off
, hole_valid
, intlv_sel
);
1569 (intlv_sel
!= ((sys_addr
>> 12) & intlv_en
)))
1572 dct_sel_base
= dct_sel_baseaddr(pvt
);
1575 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
1576 * select between DCT0 and DCT1.
1578 if (dct_high_range_enabled(pvt
) &&
1579 !dct_ganging_enabled(pvt
) &&
1580 ((sys_addr
>> 27) >= (dct_sel_base
>> 11)))
1583 channel
= f10_determine_channel(pvt
, sys_addr
, high_range
, intlv_en
);
1585 chan_addr
= f10_get_base_addr_offset(sys_addr
, high_range
, dct_sel_base
,
1586 dct_sel_base_off
, hole_valid
,
1587 hole_off
, dram_base
);
1589 intlv_shift
= f10_map_intlv_en_to_shift(intlv_en
);
1591 /* remove Node ID (in case of memory interleaving) */
1592 tmp
= chan_addr
& 0xFC0;
1594 chan_addr
= ((chan_addr
>> intlv_shift
) & 0xFFFFFFFFF000ULL
) | tmp
;
1596 /* remove channel interleave and hash */
1597 if (dct_interleave_enabled(pvt
) &&
1598 !dct_high_range_enabled(pvt
) &&
1599 !dct_ganging_enabled(pvt
)) {
1600 if (dct_sel_interleave_addr(pvt
) != 1)
1601 chan_addr
= (chan_addr
>> 1) & 0xFFFFFFFFFFFFFFC0ULL
;
1603 tmp
= chan_addr
& 0xFC0;
1604 chan_addr
= ((chan_addr
& 0xFFFFFFFFFFFFC000ULL
) >> 1)
1609 debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n",
1610 chan_addr
, (u32
)(chan_addr
>> 8));
1612 cs_found
= f10_lookup_addr_in_dct(chan_addr
>> 8, node_id
, channel
);
1614 if (cs_found
>= 0) {
1616 *chan_sel
= channel
;
1621 static int f10_translate_sysaddr_to_cs(struct amd64_pvt
*pvt
, u64 sys_addr
,
1622 int *node
, int *chan_sel
)
1624 int dram_range
, cs_found
= -EINVAL
;
1625 u64 dram_base
, dram_limit
;
1627 for (dram_range
= 0; dram_range
< DRAM_REG_COUNT
; dram_range
++) {
1629 if (!pvt
->dram_rw_en
[dram_range
])
1632 dram_base
= pvt
->dram_base
[dram_range
];
1633 dram_limit
= pvt
->dram_limit
[dram_range
];
1635 if ((dram_base
<= sys_addr
) && (sys_addr
<= dram_limit
)) {
1637 cs_found
= f10_match_to_this_node(pvt
, dram_range
,
1648 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
1649 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
1651 * The @sys_addr is usually an error address received from the hardware
1654 static void f10_map_sysaddr_to_csrow(struct mem_ctl_info
*mci
,
1655 struct err_regs
*info
,
1658 struct amd64_pvt
*pvt
= mci
->pvt_info
;
1660 unsigned short syndrome
;
1661 int nid
, csrow
, chan
= 0;
1663 csrow
= f10_translate_sysaddr_to_cs(pvt
, sys_addr
, &nid
, &chan
);
1666 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1670 error_address_to_page_and_offset(sys_addr
, &page
, &offset
);
1672 syndrome
= HIGH_SYNDROME(info
->nbsl
) << 8;
1673 syndrome
|= LOW_SYNDROME(info
->nbsh
);
1676 * We need the syndromes for channel detection only when we're
1677 * ganged. Otherwise @chan should already contain the channel at
1680 if (dct_ganging_enabled(pvt
) && pvt
->nbcfg
& K8_NBCFG_CHIPKILL
)
1681 chan
= get_channel_from_ecc_syndrome(mci
, syndrome
);
1684 edac_mc_handle_ce(mci
, page
, offset
, syndrome
, csrow
, chan
,
1688 * Channel unknown, report all channels on this CSROW as failed.
1690 for (chan
= 0; chan
< mci
->csrows
[csrow
].nr_channels
; chan
++)
1691 edac_mc_handle_ce(mci
, page
, offset
, syndrome
,
1692 csrow
, chan
, EDAC_MOD_STR
);
1696 * debug routine to display the memory sizes of all logical DIMMs and its
1699 static void amd64_debug_display_dimm_sizes(int ctrl
, struct amd64_pvt
*pvt
)
1701 int dimm
, size0
, size1
;
1705 if (boot_cpu_data
.x86
== 0xf) {
1706 /* K8 families < revF not supported yet */
1707 if (pvt
->ext_model
< K8_REV_F
)
1713 debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1714 ctrl
, ctrl
? pvt
->dbam1
: pvt
->dbam0
);
1716 dbam
= ctrl
? pvt
->dbam1
: pvt
->dbam0
;
1717 dcsb
= ctrl
? pvt
->dcsb1
: pvt
->dcsb0
;
1719 edac_printk(KERN_DEBUG
, EDAC_MC
, "DCT%d chip selects:\n", ctrl
);
1721 /* Dump memory sizes for DIMM and its CSROWs */
1722 for (dimm
= 0; dimm
< 4; dimm
++) {
1725 if (dcsb
[dimm
*2] & K8_DCSB_CS_ENABLE
)
1726 size0
= pvt
->ops
->dbam_to_cs(pvt
, DBAM_DIMM(dimm
, dbam
));
1729 if (dcsb
[dimm
*2 + 1] & K8_DCSB_CS_ENABLE
)
1730 size1
= pvt
->ops
->dbam_to_cs(pvt
, DBAM_DIMM(dimm
, dbam
));
1732 edac_printk(KERN_DEBUG
, EDAC_MC
, " %d: %5dMB %d: %5dMB\n",
1733 dimm
* 2, size0
, dimm
* 2 + 1, size1
);
1738 * There currently are 3 types type of MC devices for AMD Athlon/Opterons
1739 * (as per PCI DEVICE_IDs):
1741 * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI
1742 * DEVICE ID, even though there is differences between the different Revisions
1745 * Family F10h and F11h.
1748 static struct amd64_family_type amd64_family_types
[] = {
1751 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP
,
1752 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_K8_NB_MISC
,
1754 .early_channel_count
= k8_early_channel_count
,
1755 .get_error_address
= k8_get_error_address
,
1756 .read_dram_base_limit
= k8_read_dram_base_limit
,
1757 .map_sysaddr_to_csrow
= k8_map_sysaddr_to_csrow
,
1758 .dbam_to_cs
= k8_dbam_to_chip_select
,
1762 .ctl_name
= "Family 10h",
1763 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_10H_NB_MAP
,
1764 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_10H_NB_MISC
,
1766 .early_channel_count
= f10_early_channel_count
,
1767 .get_error_address
= f10_get_error_address
,
1768 .read_dram_base_limit
= f10_read_dram_base_limit
,
1769 .read_dram_ctl_register
= f10_read_dram_ctl_register
,
1770 .map_sysaddr_to_csrow
= f10_map_sysaddr_to_csrow
,
1771 .dbam_to_cs
= f10_dbam_to_chip_select
,
1775 .ctl_name
= "Family 11h",
1776 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_11H_NB_MAP
,
1777 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_11H_NB_MISC
,
1779 .early_channel_count
= f10_early_channel_count
,
1780 .get_error_address
= f10_get_error_address
,
1781 .read_dram_base_limit
= f10_read_dram_base_limit
,
1782 .read_dram_ctl_register
= f10_read_dram_ctl_register
,
1783 .map_sysaddr_to_csrow
= f10_map_sysaddr_to_csrow
,
1784 .dbam_to_cs
= f10_dbam_to_chip_select
,
1789 static struct pci_dev
*pci_get_related_function(unsigned int vendor
,
1790 unsigned int device
,
1791 struct pci_dev
*related
)
1793 struct pci_dev
*dev
= NULL
;
1795 dev
= pci_get_device(vendor
, device
, dev
);
1797 if ((dev
->bus
->number
== related
->bus
->number
) &&
1798 (PCI_SLOT(dev
->devfn
) == PCI_SLOT(related
->devfn
)))
1800 dev
= pci_get_device(vendor
, device
, dev
);
1807 * These are tables of eigenvectors (one per line) which can be used for the
1808 * construction of the syndrome tables. The modified syndrome search algorithm
1809 * uses those to find the symbol in error and thus the DIMM.
1811 * Algorithm courtesy of Ross LaFetra from AMD.
1813 static u16 x4_vectors
[] = {
1814 0x2f57, 0x1afe, 0x66cc, 0xdd88,
1815 0x11eb, 0x3396, 0x7f4c, 0xeac8,
1816 0x0001, 0x0002, 0x0004, 0x0008,
1817 0x1013, 0x3032, 0x4044, 0x8088,
1818 0x106b, 0x30d6, 0x70fc, 0xe0a8,
1819 0x4857, 0xc4fe, 0x13cc, 0x3288,
1820 0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
1821 0x1f39, 0x251e, 0xbd6c, 0x6bd8,
1822 0x15c1, 0x2a42, 0x89ac, 0x4758,
1823 0x2b03, 0x1602, 0x4f0c, 0xca08,
1824 0x1f07, 0x3a0e, 0x6b04, 0xbd08,
1825 0x8ba7, 0x465e, 0x244c, 0x1cc8,
1826 0x2b87, 0x164e, 0x642c, 0xdc18,
1827 0x40b9, 0x80de, 0x1094, 0x20e8,
1828 0x27db, 0x1eb6, 0x9dac, 0x7b58,
1829 0x11c1, 0x2242, 0x84ac, 0x4c58,
1830 0x1be5, 0x2d7a, 0x5e34, 0xa718,
1831 0x4b39, 0x8d1e, 0x14b4, 0x28d8,
1832 0x4c97, 0xc87e, 0x11fc, 0x33a8,
1833 0x8e97, 0x497e, 0x2ffc, 0x1aa8,
1834 0x16b3, 0x3d62, 0x4f34, 0x8518,
1835 0x1e2f, 0x391a, 0x5cac, 0xf858,
1836 0x1d9f, 0x3b7a, 0x572c, 0xfe18,
1837 0x15f5, 0x2a5a, 0x5264, 0xa3b8,
1838 0x1dbb, 0x3b66, 0x715c, 0xe3f8,
1839 0x4397, 0xc27e, 0x17fc, 0x3ea8,
1840 0x1617, 0x3d3e, 0x6464, 0xb8b8,
1841 0x23ff, 0x12aa, 0xab6c, 0x56d8,
1842 0x2dfb, 0x1ba6, 0x913c, 0x7328,
1843 0x185d, 0x2ca6, 0x7914, 0x9e28,
1844 0x171b, 0x3e36, 0x7d7c, 0xebe8,
1845 0x4199, 0x82ee, 0x19f4, 0x2e58,
1846 0x4807, 0xc40e, 0x130c, 0x3208,
1847 0x1905, 0x2e0a, 0x5804, 0xac08,
1848 0x213f, 0x132a, 0xadfc, 0x5ba8,
1849 0x19a9, 0x2efe, 0xb5cc, 0x6f88,
1852 static u16 x8_vectors
[] = {
1853 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
1854 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
1855 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
1856 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
1857 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
1858 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
1859 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
1860 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
1861 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
1862 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
1863 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
1864 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
1865 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
1866 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
1867 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
1868 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
1869 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
1870 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
1871 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
1874 static int decode_syndrome(u16 syndrome
, u16
*vectors
, int num_vecs
,
1877 unsigned int i
, err_sym
;
1879 for (err_sym
= 0; err_sym
< num_vecs
/ v_dim
; err_sym
++) {
1881 int v_idx
= err_sym
* v_dim
;
1882 int v_end
= (err_sym
+ 1) * v_dim
;
1884 /* walk over all 16 bits of the syndrome */
1885 for (i
= 1; i
< (1U << 16); i
<<= 1) {
1887 /* if bit is set in that eigenvector... */
1888 if (v_idx
< v_end
&& vectors
[v_idx
] & i
) {
1889 u16 ev_comp
= vectors
[v_idx
++];
1891 /* ... and bit set in the modified syndrome, */
1901 /* can't get to zero, move to next symbol */
1906 debugf0("syndrome(%x) not found\n", syndrome
);
1910 static int map_err_sym_to_channel(int err_sym
, int sym_size
)
1923 return err_sym
>> 4;
1929 /* imaginary bits not in a DIMM */
1931 WARN(1, KERN_ERR
"Invalid error symbol: 0x%x\n",
1943 return err_sym
>> 3;
1949 static int get_channel_from_ecc_syndrome(struct mem_ctl_info
*mci
, u16 syndrome
)
1951 struct amd64_pvt
*pvt
= mci
->pvt_info
;
1955 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, 0x180, &value
);
1957 /* F3x180[EccSymbolSize]=1, x8 symbols */
1958 if (boot_cpu_data
.x86
== 0x10 &&
1959 boot_cpu_data
.x86_model
> 7 &&
1961 err_sym
= decode_syndrome(syndrome
, x8_vectors
,
1962 ARRAY_SIZE(x8_vectors
), 8);
1963 return map_err_sym_to_channel(err_sym
, 8);
1965 err_sym
= decode_syndrome(syndrome
, x4_vectors
,
1966 ARRAY_SIZE(x4_vectors
), 4);
1967 return map_err_sym_to_channel(err_sym
, 4);
1972 * Check for valid error in the NB Status High register. If so, proceed to read
1973 * NB Status Low, NB Address Low and NB Address High registers and store data
1974 * into error structure.
1977 * - 1: if hardware regs contains valid error info
1978 * - 0: if no valid error is indicated
1980 static int amd64_get_error_info_regs(struct mem_ctl_info
*mci
,
1981 struct err_regs
*regs
)
1983 struct amd64_pvt
*pvt
;
1984 struct pci_dev
*misc_f3_ctl
;
1986 pvt
= mci
->pvt_info
;
1987 misc_f3_ctl
= pvt
->misc_f3_ctl
;
1989 if (amd64_read_pci_cfg(misc_f3_ctl
, K8_NBSH
, ®s
->nbsh
))
1992 if (!(regs
->nbsh
& K8_NBSH_VALID_BIT
))
1995 /* valid error, read remaining error information registers */
1996 if (amd64_read_pci_cfg(misc_f3_ctl
, K8_NBSL
, ®s
->nbsl
) ||
1997 amd64_read_pci_cfg(misc_f3_ctl
, K8_NBEAL
, ®s
->nbeal
) ||
1998 amd64_read_pci_cfg(misc_f3_ctl
, K8_NBEAH
, ®s
->nbeah
) ||
1999 amd64_read_pci_cfg(misc_f3_ctl
, K8_NBCFG
, ®s
->nbcfg
))
2006 * This function is called to retrieve the error data from hardware and store it
2007 * in the info structure.
2010 * - 1: if a valid error is found
2011 * - 0: if no error is found
2013 static int amd64_get_error_info(struct mem_ctl_info
*mci
,
2014 struct err_regs
*info
)
2016 struct amd64_pvt
*pvt
;
2017 struct err_regs regs
;
2019 pvt
= mci
->pvt_info
;
2021 if (!amd64_get_error_info_regs(mci
, info
))
2025 * Here's the problem with the K8's EDAC reporting: There are four
2026 * registers which report pieces of error information. They are shared
2027 * between CEs and UEs. Furthermore, contrary to what is stated in the
2028 * BKDG, the overflow bit is never used! Every error always updates the
2029 * reporting registers.
2031 * Can you see the race condition? All four error reporting registers
2032 * must be read before a new error updates them! There is no way to read
2033 * all four registers atomically. The best than can be done is to detect
2034 * that a race has occured and then report the error without any kind of
2037 * What is still positive is that errors are still reported and thus
2038 * problems can still be detected - just not localized because the
2039 * syndrome and address are spread out across registers.
2041 * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev.
2042 * UEs and CEs should have separate register sets with proper overflow
2043 * bits that are used! At very least the problem can be fixed by
2044 * honoring the ErrValid bit in 'nbsh' and not updating registers - just
2045 * set the overflow bit - unless the current error is CE and the new
2046 * error is UE which would be the only situation for overwriting the
2052 /* Use info from the second read - most current */
2053 if (unlikely(!amd64_get_error_info_regs(mci
, info
)))
2056 /* clear the error bits in hardware */
2057 pci_write_bits32(pvt
->misc_f3_ctl
, K8_NBSH
, 0, K8_NBSH_VALID_BIT
);
2059 /* Check for the possible race condition */
2060 if ((regs
.nbsh
!= info
->nbsh
) ||
2061 (regs
.nbsl
!= info
->nbsl
) ||
2062 (regs
.nbeah
!= info
->nbeah
) ||
2063 (regs
.nbeal
!= info
->nbeal
)) {
2064 amd64_mc_printk(mci
, KERN_WARNING
,
2065 "hardware STATUS read access race condition "
2073 * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
2074 * ADDRESS and process.
2076 static void amd64_handle_ce(struct mem_ctl_info
*mci
,
2077 struct err_regs
*info
)
2079 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2082 /* Ensure that the Error Address is VALID */
2083 if ((info
->nbsh
& K8_NBSH_VALID_ERROR_ADDR
) == 0) {
2084 amd64_mc_printk(mci
, KERN_ERR
,
2085 "HW has no ERROR_ADDRESS available\n");
2086 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
2090 sys_addr
= pvt
->ops
->get_error_address(mci
, info
);
2092 amd64_mc_printk(mci
, KERN_ERR
,
2093 "CE ERROR_ADDRESS= 0x%llx\n", sys_addr
);
2095 pvt
->ops
->map_sysaddr_to_csrow(mci
, info
, sys_addr
);
2098 /* Handle any Un-correctable Errors (UEs) */
2099 static void amd64_handle_ue(struct mem_ctl_info
*mci
,
2100 struct err_regs
*info
)
2102 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2103 struct mem_ctl_info
*log_mci
, *src_mci
= NULL
;
2110 if ((info
->nbsh
& K8_NBSH_VALID_ERROR_ADDR
) == 0) {
2111 amd64_mc_printk(mci
, KERN_CRIT
,
2112 "HW has no ERROR_ADDRESS available\n");
2113 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2117 sys_addr
= pvt
->ops
->get_error_address(mci
, info
);
2120 * Find out which node the error address belongs to. This may be
2121 * different from the node that detected the error.
2123 src_mci
= find_mc_by_sys_addr(mci
, sys_addr
);
2125 amd64_mc_printk(mci
, KERN_CRIT
,
2126 "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n",
2127 (unsigned long)sys_addr
);
2128 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2134 csrow
= sys_addr_to_csrow(log_mci
, sys_addr
);
2136 amd64_mc_printk(mci
, KERN_CRIT
,
2137 "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n",
2138 (unsigned long)sys_addr
);
2139 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2141 error_address_to_page_and_offset(sys_addr
, &page
, &offset
);
2142 edac_mc_handle_ue(log_mci
, page
, offset
, csrow
, EDAC_MOD_STR
);
2146 static inline void __amd64_decode_bus_error(struct mem_ctl_info
*mci
,
2147 struct err_regs
*info
)
2149 u32 ec
= ERROR_CODE(info
->nbsl
);
2150 u32 xec
= EXT_ERROR_CODE(info
->nbsl
);
2151 int ecc_type
= (info
->nbsh
>> 13) & 0x3;
2153 /* Bail early out if this was an 'observed' error */
2154 if (PP(ec
) == K8_NBSL_PP_OBS
)
2157 /* Do only ECC errors */
2158 if (xec
&& xec
!= F10_NBSL_EXT_ERR_ECC
)
2162 amd64_handle_ce(mci
, info
);
2163 else if (ecc_type
== 1)
2164 amd64_handle_ue(mci
, info
);
2167 * If main error is CE then overflow must be CE. If main error is UE
2168 * then overflow is unknown. We'll call the overflow a CE - if
2169 * panic_on_ue is set then we're already panic'ed and won't arrive
2170 * here. Else, then apparently someone doesn't think that UE's are
2173 if (info
->nbsh
& K8_NBSH_OVERFLOW
)
2174 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
"Error Overflow");
2177 void amd64_decode_bus_error(int node_id
, struct err_regs
*regs
)
2179 struct mem_ctl_info
*mci
= mci_lookup
[node_id
];
2181 __amd64_decode_bus_error(mci
, regs
);
2184 * Check the UE bit of the NB status high register, if set generate some
2185 * logs. If NOT a GART error, then process the event as a NO-INFO event.
2186 * If it was a GART error, skip that process.
2188 * FIXME: this should go somewhere else, if at all.
2190 if (regs
->nbsh
& K8_NBSH_UC_ERR
&& !report_gart_errors
)
2191 edac_mc_handle_ue_no_info(mci
, "UE bit is set");
2196 * The main polling 'check' function, called FROM the edac core to perform the
2197 * error checking and if an error is encountered, error processing.
2199 static void amd64_check(struct mem_ctl_info
*mci
)
2201 struct err_regs regs
;
2203 if (amd64_get_error_info(mci
, ®s
)) {
2204 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2205 amd_decode_nb_mce(pvt
->mc_node_id
, ®s
, 1);
2211 * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer
2212 * 2) AMD Family index value
2215 * Upon return of 0, the following filled in:
2217 * struct pvt->addr_f1_ctl
2218 * struct pvt->misc_f3_ctl
2220 * Filled in with related device funcitions of 'dram_f2_ctl'
2221 * These devices are "reserved" via the pci_get_device()
2223 * Upon return of 1 (error status):
2227 static int amd64_reserve_mc_sibling_devices(struct amd64_pvt
*pvt
, int mc_idx
)
2229 const struct amd64_family_type
*amd64_dev
= &amd64_family_types
[mc_idx
];
2231 /* Reserve the ADDRESS MAP Device */
2232 pvt
->addr_f1_ctl
= pci_get_related_function(pvt
->dram_f2_ctl
->vendor
,
2233 amd64_dev
->addr_f1_ctl
,
2236 if (!pvt
->addr_f1_ctl
) {
2237 amd64_printk(KERN_ERR
, "error address map device not found: "
2238 "vendor %x device 0x%x (broken BIOS?)\n",
2239 PCI_VENDOR_ID_AMD
, amd64_dev
->addr_f1_ctl
);
2243 /* Reserve the MISC Device */
2244 pvt
->misc_f3_ctl
= pci_get_related_function(pvt
->dram_f2_ctl
->vendor
,
2245 amd64_dev
->misc_f3_ctl
,
2248 if (!pvt
->misc_f3_ctl
) {
2249 pci_dev_put(pvt
->addr_f1_ctl
);
2250 pvt
->addr_f1_ctl
= NULL
;
2252 amd64_printk(KERN_ERR
, "error miscellaneous device not found: "
2253 "vendor %x device 0x%x (broken BIOS?)\n",
2254 PCI_VENDOR_ID_AMD
, amd64_dev
->misc_f3_ctl
);
2258 debugf1(" Addr Map device PCI Bus ID:\t%s\n",
2259 pci_name(pvt
->addr_f1_ctl
));
2260 debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n",
2261 pci_name(pvt
->dram_f2_ctl
));
2262 debugf1(" Misc device PCI Bus ID:\t%s\n",
2263 pci_name(pvt
->misc_f3_ctl
));
2268 static void amd64_free_mc_sibling_devices(struct amd64_pvt
*pvt
)
2270 pci_dev_put(pvt
->addr_f1_ctl
);
2271 pci_dev_put(pvt
->misc_f3_ctl
);
2275 * Retrieve the hardware registers of the memory controller (this includes the
2276 * 'Address Map' and 'Misc' device regs)
2278 static void amd64_read_mc_registers(struct amd64_pvt
*pvt
)
2284 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2285 * those are Read-As-Zero
2287 rdmsrl(MSR_K8_TOP_MEM1
, pvt
->top_mem
);
2288 debugf0(" TOP_MEM: 0x%016llx\n", pvt
->top_mem
);
2290 /* check first whether TOP_MEM2 is enabled */
2291 rdmsrl(MSR_K8_SYSCFG
, msr_val
);
2292 if (msr_val
& (1U << 21)) {
2293 rdmsrl(MSR_K8_TOP_MEM2
, pvt
->top_mem2
);
2294 debugf0(" TOP_MEM2: 0x%016llx\n", pvt
->top_mem2
);
2296 debugf0(" TOP_MEM2 disabled.\n");
2298 amd64_cpu_display_info(pvt
);
2300 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_NBCAP
, &pvt
->nbcap
);
2302 if (pvt
->ops
->read_dram_ctl_register
)
2303 pvt
->ops
->read_dram_ctl_register(pvt
);
2305 for (dram
= 0; dram
< DRAM_REG_COUNT
; dram
++) {
2307 * Call CPU specific READ function to get the DRAM Base and
2308 * Limit values from the DCT.
2310 pvt
->ops
->read_dram_base_limit(pvt
, dram
);
2313 * Only print out debug info on rows with both R and W Enabled.
2314 * Normal processing, compiler should optimize this whole 'if'
2315 * debug output block away.
2317 if (pvt
->dram_rw_en
[dram
] != 0) {
2318 debugf1(" DRAM-BASE[%d]: 0x%016llx "
2319 "DRAM-LIMIT: 0x%016llx\n",
2321 pvt
->dram_base
[dram
],
2322 pvt
->dram_limit
[dram
]);
2324 debugf1(" IntlvEn=%s %s %s "
2325 "IntlvSel=%d DstNode=%d\n",
2326 pvt
->dram_IntlvEn
[dram
] ?
2327 "Enabled" : "Disabled",
2328 (pvt
->dram_rw_en
[dram
] & 0x2) ? "W" : "!W",
2329 (pvt
->dram_rw_en
[dram
] & 0x1) ? "R" : "!R",
2330 pvt
->dram_IntlvSel
[dram
],
2331 pvt
->dram_DstNode
[dram
]);
2335 amd64_read_dct_base_mask(pvt
);
2337 amd64_read_pci_cfg(pvt
->addr_f1_ctl
, K8_DHAR
, &pvt
->dhar
);
2338 amd64_read_dbam_reg(pvt
);
2340 amd64_read_pci_cfg(pvt
->misc_f3_ctl
,
2341 F10_ONLINE_SPARE
, &pvt
->online_spare
);
2343 amd64_read_pci_cfg(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
2344 amd64_read_pci_cfg(pvt
->dram_f2_ctl
, F10_DCHR_0
, &pvt
->dchr0
);
2346 if (!dct_ganging_enabled(pvt
)) {
2347 amd64_read_pci_cfg(pvt
->dram_f2_ctl
, F10_DCLR_1
, &pvt
->dclr1
);
2348 amd64_read_pci_cfg(pvt
->dram_f2_ctl
, F10_DCHR_1
, &pvt
->dchr1
);
2350 amd64_dump_misc_regs(pvt
);
2354 * NOTE: CPU Revision Dependent code
2357 * @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1)
2358 * k8 private pointer to -->
2359 * DRAM Bank Address mapping register
2361 * DCL register where dual_channel_active is
2363 * The DBAM register consists of 4 sets of 4 bits each definitions:
2366 * 0-3 CSROWs 0 and 1
2367 * 4-7 CSROWs 2 and 3
2368 * 8-11 CSROWs 4 and 5
2369 * 12-15 CSROWs 6 and 7
2371 * Values range from: 0 to 15
2372 * The meaning of the values depends on CPU revision and dual-channel state,
2373 * see relevant BKDG more info.
2375 * The memory controller provides for total of only 8 CSROWs in its current
2376 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
2377 * single channel or two (2) DIMMs in dual channel mode.
2379 * The following code logic collapses the various tables for CSROW based on CPU
2383 * The number of PAGE_SIZE pages on the specified CSROW number it
2387 static u32
amd64_csrow_nr_pages(int csrow_nr
, struct amd64_pvt
*pvt
)
2389 u32 cs_mode
, nr_pages
;
2392 * The math on this doesn't look right on the surface because x/2*4 can
2393 * be simplified to x*2 but this expression makes use of the fact that
2394 * it is integral math where 1/2=0. This intermediate value becomes the
2395 * number of bits to shift the DBAM register to extract the proper CSROW
2398 cs_mode
= (pvt
->dbam0
>> ((csrow_nr
/ 2) * 4)) & 0xF;
2400 nr_pages
= pvt
->ops
->dbam_to_cs(pvt
, cs_mode
) << (20 - PAGE_SHIFT
);
2403 * If dual channel then double the memory size of single channel.
2404 * Channel count is 1 or 2
2406 nr_pages
<<= (pvt
->channel_count
- 1);
2408 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr
, cs_mode
);
2409 debugf0(" nr_pages= %u channel-count = %d\n",
2410 nr_pages
, pvt
->channel_count
);
2416 * Initialize the array of csrow attribute instances, based on the values
2417 * from pci config hardware registers.
2419 static int amd64_init_csrows(struct mem_ctl_info
*mci
)
2421 struct csrow_info
*csrow
;
2422 struct amd64_pvt
*pvt
;
2423 u64 input_addr_min
, input_addr_max
, sys_addr
;
2426 pvt
= mci
->pvt_info
;
2428 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_NBCFG
, &pvt
->nbcfg
);
2430 debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt
->nbcfg
,
2431 (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2432 (pvt
->nbcfg
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled"
2435 for (i
= 0; i
< pvt
->cs_count
; i
++) {
2436 csrow
= &mci
->csrows
[i
];
2438 if ((pvt
->dcsb0
[i
] & K8_DCSB_CS_ENABLE
) == 0) {
2439 debugf1("----CSROW %d EMPTY for node %d\n", i
,
2444 debugf1("----CSROW %d VALID for MC node %d\n",
2445 i
, pvt
->mc_node_id
);
2448 csrow
->nr_pages
= amd64_csrow_nr_pages(i
, pvt
);
2449 find_csrow_limits(mci
, i
, &input_addr_min
, &input_addr_max
);
2450 sys_addr
= input_addr_to_sys_addr(mci
, input_addr_min
);
2451 csrow
->first_page
= (u32
) (sys_addr
>> PAGE_SHIFT
);
2452 sys_addr
= input_addr_to_sys_addr(mci
, input_addr_max
);
2453 csrow
->last_page
= (u32
) (sys_addr
>> PAGE_SHIFT
);
2454 csrow
->page_mask
= ~mask_from_dct_mask(pvt
, i
);
2455 /* 8 bytes of resolution */
2457 csrow
->mtype
= amd64_determine_memory_type(pvt
);
2459 debugf1(" for MC node %d csrow %d:\n", pvt
->mc_node_id
, i
);
2460 debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n",
2461 (unsigned long)input_addr_min
,
2462 (unsigned long)input_addr_max
);
2463 debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n",
2464 (unsigned long)sys_addr
, csrow
->page_mask
);
2465 debugf1(" nr_pages: %u first_page: 0x%lx "
2466 "last_page: 0x%lx\n",
2467 (unsigned)csrow
->nr_pages
,
2468 csrow
->first_page
, csrow
->last_page
);
2471 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
2473 if (pvt
->nbcfg
& K8_NBCFG_ECC_ENABLE
)
2475 (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
) ?
2476 EDAC_S4ECD4ED
: EDAC_SECDED
;
2478 csrow
->edac_mode
= EDAC_NONE
;
2484 /* get all cores on this DCT */
2485 static void get_cpus_on_this_dct_cpumask(struct cpumask
*mask
, int nid
)
2489 for_each_online_cpu(cpu
)
2490 if (amd_get_nb_id(cpu
) == nid
)
2491 cpumask_set_cpu(cpu
, mask
);
2494 /* check MCG_CTL on all the cpus on this node */
2495 static bool amd64_nb_mce_bank_enabled_on_node(int nid
)
2499 int cpu
, nbe
, idx
= 0;
2502 if (!zalloc_cpumask_var(&mask
, GFP_KERNEL
)) {
2503 amd64_printk(KERN_WARNING
, "%s: error allocating mask\n",
2508 get_cpus_on_this_dct_cpumask(mask
, nid
);
2510 msrs
= kzalloc(sizeof(struct msr
) * cpumask_weight(mask
), GFP_KERNEL
);
2512 amd64_printk(KERN_WARNING
, "%s: error allocating msrs\n",
2514 free_cpumask_var(mask
);
2518 rdmsr_on_cpus(mask
, MSR_IA32_MCG_CTL
, msrs
);
2520 for_each_cpu(cpu
, mask
) {
2521 nbe
= msrs
[idx
].l
& K8_MSR_MCGCTL_NBE
;
2523 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2525 (nbe
? "enabled" : "disabled"));
2536 free_cpumask_var(mask
);
2540 static int amd64_toggle_ecc_err_reporting(struct amd64_pvt
*pvt
, bool on
)
2542 cpumask_var_t cmask
;
2543 struct msr
*msrs
= NULL
;
2546 if (!zalloc_cpumask_var(&cmask
, GFP_KERNEL
)) {
2547 amd64_printk(KERN_WARNING
, "%s: error allocating mask\n",
2552 get_cpus_on_this_dct_cpumask(cmask
, pvt
->mc_node_id
);
2554 msrs
= kzalloc(sizeof(struct msr
) * cpumask_weight(cmask
), GFP_KERNEL
);
2556 amd64_printk(KERN_WARNING
, "%s: error allocating msrs\n",
2561 rdmsr_on_cpus(cmask
, MSR_IA32_MCG_CTL
, msrs
);
2563 for_each_cpu(cpu
, cmask
) {
2566 if (msrs
[idx
].l
& K8_MSR_MCGCTL_NBE
)
2567 pvt
->flags
.ecc_report
= 1;
2569 msrs
[idx
].l
|= K8_MSR_MCGCTL_NBE
;
2572 * Turn off ECC reporting only when it was off before
2574 if (!pvt
->flags
.ecc_report
)
2575 msrs
[idx
].l
&= ~K8_MSR_MCGCTL_NBE
;
2579 wrmsr_on_cpus(cmask
, MSR_IA32_MCG_CTL
, msrs
);
2582 free_cpumask_var(cmask
);
2588 * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
2591 static void amd64_enable_ecc_error_reporting(struct mem_ctl_info
*mci
)
2593 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2594 u32 value
, mask
= K8_NBCTL_CECCEn
| K8_NBCTL_UECCEn
;
2596 if (!ecc_enable_override
)
2599 amd64_printk(KERN_WARNING
,
2600 "'ecc_enable_override' parameter is active, "
2601 "Enabling AMD ECC hardware now: CAUTION\n");
2603 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_NBCTL
, &value
);
2605 /* turn on UECCn and CECCEn bits */
2606 pvt
->old_nbctl
= value
& mask
;
2607 pvt
->nbctl_mcgctl_saved
= 1;
2610 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, value
);
2612 if (amd64_toggle_ecc_err_reporting(pvt
, ON
))
2613 amd64_printk(KERN_WARNING
, "Error enabling ECC reporting over "
2616 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2618 debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value
,
2619 (value
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2620 (value
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled");
2622 if (!(value
& K8_NBCFG_ECC_ENABLE
)) {
2623 amd64_printk(KERN_WARNING
,
2624 "This node reports that DRAM ECC is "
2625 "currently Disabled; ENABLING now\n");
2627 /* Attempt to turn on DRAM ECC Enable */
2628 value
|= K8_NBCFG_ECC_ENABLE
;
2629 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, value
);
2631 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2633 if (!(value
& K8_NBCFG_ECC_ENABLE
)) {
2634 amd64_printk(KERN_WARNING
,
2635 "Hardware rejects Enabling DRAM ECC checking\n"
2636 "Check memory DIMM configuration\n");
2638 amd64_printk(KERN_DEBUG
,
2639 "Hardware accepted DRAM ECC Enable\n");
2642 debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value
,
2643 (value
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2644 (value
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled");
2646 pvt
->ctl_error_info
.nbcfg
= value
;
2649 static void amd64_restore_ecc_error_reporting(struct amd64_pvt
*pvt
)
2651 u32 value
, mask
= K8_NBCTL_CECCEn
| K8_NBCTL_UECCEn
;
2653 if (!pvt
->nbctl_mcgctl_saved
)
2656 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_NBCTL
, &value
);
2658 value
|= pvt
->old_nbctl
;
2660 /* restore the NB Enable MCGCTL bit */
2661 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, value
);
2663 if (amd64_toggle_ecc_err_reporting(pvt
, OFF
))
2664 amd64_printk(KERN_WARNING
, "Error restoring ECC reporting over "
2669 * EDAC requires that the BIOS have ECC enabled before taking over the
2670 * processing of ECC errors. This is because the BIOS can properly initialize
2671 * the memory system completely. A command line option allows to force-enable
2672 * hardware ECC later in amd64_enable_ecc_error_reporting().
2674 static const char *ecc_warning
=
2675 "WARNING: ECC is disabled by BIOS. Module will NOT be loaded.\n"
2676 " Either Enable ECC in the BIOS, or set 'ecc_enable_override'.\n"
2677 " Also, use of the override can cause unknown side effects.\n";
2679 static int amd64_check_ecc_enabled(struct amd64_pvt
*pvt
)
2683 bool nb_mce_en
= false;
2685 amd64_read_pci_cfg(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2687 ecc_enabled
= !!(value
& K8_NBCFG_ECC_ENABLE
);
2689 amd64_printk(KERN_WARNING
, "This node reports that Memory ECC "
2690 "is currently disabled, set F3x%x[22] (%s).\n",
2691 K8_NBCFG
, pci_name(pvt
->misc_f3_ctl
));
2693 amd64_printk(KERN_INFO
, "ECC is enabled by BIOS.\n");
2695 nb_mce_en
= amd64_nb_mce_bank_enabled_on_node(pvt
->mc_node_id
);
2697 amd64_printk(KERN_WARNING
, "NB MCE bank disabled, set MSR "
2698 "0x%08x[4] on node %d to enable.\n",
2699 MSR_IA32_MCG_CTL
, pvt
->mc_node_id
);
2701 if (!ecc_enabled
|| !nb_mce_en
) {
2702 if (!ecc_enable_override
) {
2703 amd64_printk(KERN_WARNING
, "%s", ecc_warning
);
2707 /* CLEAR the override, since BIOS controlled it */
2708 ecc_enable_override
= 0;
2713 struct mcidev_sysfs_attribute sysfs_attrs
[ARRAY_SIZE(amd64_dbg_attrs
) +
2714 ARRAY_SIZE(amd64_inj_attrs
) +
2717 struct mcidev_sysfs_attribute terminator
= { .attr
= { .name
= NULL
} };
2719 static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info
*mci
)
2721 unsigned int i
= 0, j
= 0;
2723 for (; i
< ARRAY_SIZE(amd64_dbg_attrs
); i
++)
2724 sysfs_attrs
[i
] = amd64_dbg_attrs
[i
];
2726 for (j
= 0; j
< ARRAY_SIZE(amd64_inj_attrs
); j
++, i
++)
2727 sysfs_attrs
[i
] = amd64_inj_attrs
[j
];
2729 sysfs_attrs
[i
] = terminator
;
2731 mci
->mc_driver_sysfs_attributes
= sysfs_attrs
;
2734 static void amd64_setup_mci_misc_attributes(struct mem_ctl_info
*mci
)
2736 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2738 mci
->mtype_cap
= MEM_FLAG_DDR2
| MEM_FLAG_RDDR2
;
2739 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
;
2741 if (pvt
->nbcap
& K8_NBCAP_SECDED
)
2742 mci
->edac_ctl_cap
|= EDAC_FLAG_SECDED
;
2744 if (pvt
->nbcap
& K8_NBCAP_CHIPKILL
)
2745 mci
->edac_ctl_cap
|= EDAC_FLAG_S4ECD4ED
;
2747 mci
->edac_cap
= amd64_determine_edac_cap(pvt
);
2748 mci
->mod_name
= EDAC_MOD_STR
;
2749 mci
->mod_ver
= EDAC_AMD64_VERSION
;
2750 mci
->ctl_name
= get_amd_family_name(pvt
->mc_type_index
);
2751 mci
->dev_name
= pci_name(pvt
->dram_f2_ctl
);
2752 mci
->ctl_page_to_phys
= NULL
;
2754 /* IMPORTANT: Set the polling 'check' function in this module */
2755 mci
->edac_check
= amd64_check
;
2757 /* memory scrubber interface */
2758 mci
->set_sdram_scrub_rate
= amd64_set_scrub_rate
;
2759 mci
->get_sdram_scrub_rate
= amd64_get_scrub_rate
;
2763 * Init stuff for this DRAM Controller device.
2765 * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration
2766 * Space feature MUST be enabled on ALL Processors prior to actually reading
2767 * from the ECS registers. Since the loading of the module can occur on any
2768 * 'core', and cores don't 'see' all the other processors ECS data when the
2769 * others are NOT enabled. Our solution is to first enable ECS access in this
2770 * routine on all processors, gather some data in a amd64_pvt structure and
2771 * later come back in a finish-setup function to perform that final
2772 * initialization. See also amd64_init_2nd_stage() for that.
2774 static int amd64_probe_one_instance(struct pci_dev
*dram_f2_ctl
,
2777 struct amd64_pvt
*pvt
= NULL
;
2781 pvt
= kzalloc(sizeof(struct amd64_pvt
), GFP_KERNEL
);
2785 pvt
->mc_node_id
= get_node_id(dram_f2_ctl
);
2787 pvt
->dram_f2_ctl
= dram_f2_ctl
;
2788 pvt
->ext_model
= boot_cpu_data
.x86_model
>> 4;
2789 pvt
->mc_type_index
= mc_type_index
;
2790 pvt
->ops
= family_ops(mc_type_index
);
2793 * We have the dram_f2_ctl device as an argument, now go reserve its
2794 * sibling devices from the PCI system.
2797 err
= amd64_reserve_mc_sibling_devices(pvt
, mc_type_index
);
2802 err
= amd64_check_ecc_enabled(pvt
);
2807 * Key operation here: setup of HW prior to performing ops on it. Some
2808 * setup is required to access ECS data. After this is performed, the
2809 * 'teardown' function must be called upon error and normal exit paths.
2811 if (boot_cpu_data
.x86
>= 0x10)
2815 * Save the pointer to the private data for use in 2nd initialization
2818 pvt_lookup
[pvt
->mc_node_id
] = pvt
;
2823 amd64_free_mc_sibling_devices(pvt
);
2833 * This is the finishing stage of the init code. Needs to be performed after all
2834 * MCs' hardware have been prepped for accessing extended config space.
2836 static int amd64_init_2nd_stage(struct amd64_pvt
*pvt
)
2838 int node_id
= pvt
->mc_node_id
;
2839 struct mem_ctl_info
*mci
;
2842 amd64_read_mc_registers(pvt
);
2845 * We need to determine how many memory channels there are. Then use
2846 * that information for calculating the size of the dynamic instance
2847 * tables in the 'mci' structure
2849 pvt
->channel_count
= pvt
->ops
->early_channel_count(pvt
);
2850 if (pvt
->channel_count
< 0)
2854 mci
= edac_mc_alloc(0, pvt
->cs_count
, pvt
->channel_count
, node_id
);
2858 mci
->pvt_info
= pvt
;
2860 mci
->dev
= &pvt
->dram_f2_ctl
->dev
;
2861 amd64_setup_mci_misc_attributes(mci
);
2863 if (amd64_init_csrows(mci
))
2864 mci
->edac_cap
= EDAC_FLAG_NONE
;
2866 amd64_enable_ecc_error_reporting(mci
);
2867 amd64_set_mc_sysfs_attributes(mci
);
2870 if (edac_mc_add_mc(mci
)) {
2871 debugf1("failed edac_mc_add_mc()\n");
2875 mci_lookup
[node_id
] = mci
;
2876 pvt_lookup
[node_id
] = NULL
;
2878 /* register stuff with EDAC MCE */
2879 if (report_gart_errors
)
2880 amd_report_gart_errors(true);
2882 amd_register_ecc_decoder(amd64_decode_bus_error
);
2890 debugf0("failure to init 2nd stage: ret=%d\n", ret
);
2892 amd64_restore_ecc_error_reporting(pvt
);
2894 if (boot_cpu_data
.x86
> 0xf)
2895 amd64_teardown(pvt
);
2897 amd64_free_mc_sibling_devices(pvt
);
2899 kfree(pvt_lookup
[pvt
->mc_node_id
]);
2900 pvt_lookup
[node_id
] = NULL
;
2906 static int __devinit
amd64_init_one_instance(struct pci_dev
*pdev
,
2907 const struct pci_device_id
*mc_type
)
2911 debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev
),
2912 get_amd_family_name(mc_type
->driver_data
));
2914 ret
= pci_enable_device(pdev
);
2918 ret
= amd64_probe_one_instance(pdev
, mc_type
->driver_data
);
2921 debugf0("ret=%d\n", ret
);
2926 static void __devexit
amd64_remove_one_instance(struct pci_dev
*pdev
)
2928 struct mem_ctl_info
*mci
;
2929 struct amd64_pvt
*pvt
;
2931 /* Remove from EDAC CORE tracking list */
2932 mci
= edac_mc_del_mc(&pdev
->dev
);
2936 pvt
= mci
->pvt_info
;
2938 amd64_restore_ecc_error_reporting(pvt
);
2940 if (boot_cpu_data
.x86
> 0xf)
2941 amd64_teardown(pvt
);
2943 amd64_free_mc_sibling_devices(pvt
);
2946 mci
->pvt_info
= NULL
;
2948 mci_lookup
[pvt
->mc_node_id
] = NULL
;
2950 /* unregister from EDAC MCE */
2951 amd_report_gart_errors(false);
2952 amd_unregister_ecc_decoder(amd64_decode_bus_error
);
2954 /* Free the EDAC CORE resources */
2959 * This table is part of the interface for loading drivers for PCI devices. The
2960 * PCI core identifies what devices are on a system during boot, and then
2961 * inquiry this table to see if this driver is for a given device found.
2963 static const struct pci_device_id amd64_pci_table
[] __devinitdata
= {
2965 .vendor
= PCI_VENDOR_ID_AMD
,
2966 .device
= PCI_DEVICE_ID_AMD_K8_NB_MEMCTL
,
2967 .subvendor
= PCI_ANY_ID
,
2968 .subdevice
= PCI_ANY_ID
,
2971 .driver_data
= K8_CPUS
2974 .vendor
= PCI_VENDOR_ID_AMD
,
2975 .device
= PCI_DEVICE_ID_AMD_10H_NB_DRAM
,
2976 .subvendor
= PCI_ANY_ID
,
2977 .subdevice
= PCI_ANY_ID
,
2980 .driver_data
= F10_CPUS
2983 .vendor
= PCI_VENDOR_ID_AMD
,
2984 .device
= PCI_DEVICE_ID_AMD_11H_NB_DRAM
,
2985 .subvendor
= PCI_ANY_ID
,
2986 .subdevice
= PCI_ANY_ID
,
2989 .driver_data
= F11_CPUS
2993 MODULE_DEVICE_TABLE(pci
, amd64_pci_table
);
2995 static struct pci_driver amd64_pci_driver
= {
2996 .name
= EDAC_MOD_STR
,
2997 .probe
= amd64_init_one_instance
,
2998 .remove
= __devexit_p(amd64_remove_one_instance
),
2999 .id_table
= amd64_pci_table
,
3002 static void amd64_setup_pci_device(void)
3004 struct mem_ctl_info
*mci
;
3005 struct amd64_pvt
*pvt
;
3010 mci
= mci_lookup
[0];
3013 pvt
= mci
->pvt_info
;
3015 edac_pci_create_generic_ctl(&pvt
->dram_f2_ctl
->dev
,
3018 if (!amd64_ctl_pci
) {
3019 pr_warning("%s(): Unable to create PCI control\n",
3022 pr_warning("%s(): PCI error report via EDAC not set\n",
3028 static int __init
amd64_edac_init(void)
3030 int nb
, err
= -ENODEV
;
3032 edac_printk(KERN_INFO
, EDAC_MOD_STR
, EDAC_AMD64_VERSION
"\n");
3036 if (cache_k8_northbridges() < 0)
3039 err
= pci_register_driver(&amd64_pci_driver
);
3044 * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd
3045 * amd64_pvt structs. These will be used in the 2nd stage init function
3046 * to finish initialization of the MC instances.
3048 for (nb
= 0; nb
< num_k8_northbridges
; nb
++) {
3049 if (!pvt_lookup
[nb
])
3052 err
= amd64_init_2nd_stage(pvt_lookup
[nb
]);
3057 amd64_setup_pci_device();
3062 debugf0("2nd stage failed\n");
3063 pci_unregister_driver(&amd64_pci_driver
);
3068 static void __exit
amd64_edac_exit(void)
3071 edac_pci_release_generic_ctl(amd64_ctl_pci
);
3073 pci_unregister_driver(&amd64_pci_driver
);
3076 module_init(amd64_edac_init
);
3077 module_exit(amd64_edac_exit
);
3079 MODULE_LICENSE("GPL");
3080 MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
3081 "Dave Peterson, Thayne Harbaugh");
3082 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
3083 EDAC_AMD64_VERSION
);
3085 module_param(edac_op_state
, int, 0444);
3086 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");