2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names
[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names
);
33 int isa_dma_bridge_buggy
;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
37 EXPORT_SYMBOL(pci_pci_problems
);
39 unsigned int pci_pm_d3_delay
;
41 static void pci_pme_list_scan(struct work_struct
*work
);
43 static LIST_HEAD(pci_pme_list
);
44 static DEFINE_MUTEX(pci_pme_list_mutex
);
45 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
47 struct pci_pme_device
{
48 struct list_head list
;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
56 unsigned int delay
= dev
->d3_delay
;
58 if (delay
< pci_pm_d3_delay
)
59 delay
= pci_pm_d3_delay
;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported
= 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
72 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
78 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
81 * The default CLS is used if arch didn't set CLS explicitly and not
82 * all pci devices agree on the same value. Arch can override either
83 * the dfl or actual value as it sees fit. Don't forget this is
84 * measured in 32-bit words, not bytes.
86 u8 pci_dfl_cache_line_size __devinitdata
= L1_CACHE_BYTES
>> 2;
87 u8 pci_cache_line_size
;
90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
91 * @bus: pointer to PCI bus structure to search
93 * Given a PCI bus, returns the highest PCI bus number present in the set
94 * including the given PCI bus and its list of child PCI buses.
96 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
98 struct list_head
*tmp
;
101 max
= bus
->subordinate
;
102 list_for_each(tmp
, &bus
->children
) {
103 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
109 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
111 #ifdef CONFIG_HAS_IOMEM
112 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
115 * Make sure the BAR is actually a memory resource, not an IO resource
117 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
121 return ioremap_nocache(pci_resource_start(pdev
, bar
),
122 pci_resource_len(pdev
, bar
));
124 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
129 * pci_max_busnr - returns maximum PCI bus number
131 * Returns the highest PCI bus number present in the system global list of
134 unsigned char __devinit
137 struct pci_bus
*bus
= NULL
;
138 unsigned char max
, n
;
141 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
142 n
= pci_bus_max_busnr(bus
);
151 #define PCI_FIND_CAP_TTL 48
153 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
154 u8 pos
, int cap
, int *ttl
)
159 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
163 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
169 pos
+= PCI_CAP_LIST_NEXT
;
174 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
177 int ttl
= PCI_FIND_CAP_TTL
;
179 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
182 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
184 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
185 pos
+ PCI_CAP_LIST_NEXT
, cap
);
187 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
189 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
190 unsigned int devfn
, u8 hdr_type
)
194 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
195 if (!(status
& PCI_STATUS_CAP_LIST
))
199 case PCI_HEADER_TYPE_NORMAL
:
200 case PCI_HEADER_TYPE_BRIDGE
:
201 return PCI_CAPABILITY_LIST
;
202 case PCI_HEADER_TYPE_CARDBUS
:
203 return PCI_CB_CAPABILITY_LIST
;
212 * pci_find_capability - query for devices' capabilities
213 * @dev: PCI device to query
214 * @cap: capability code
216 * Tell if a device supports a given PCI capability.
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it. Possible values for @cap:
221 * %PCI_CAP_ID_PM Power Management
222 * %PCI_CAP_ID_AGP Accelerated Graphics Port
223 * %PCI_CAP_ID_VPD Vital Product Data
224 * %PCI_CAP_ID_SLOTID Slot Identification
225 * %PCI_CAP_ID_MSI Message Signalled Interrupts
226 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
227 * %PCI_CAP_ID_PCIX PCI-X
228 * %PCI_CAP_ID_EXP PCI Express
230 int pci_find_capability(struct pci_dev
*dev
, int cap
)
234 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
236 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
242 * pci_bus_find_capability - query for devices' capabilities
243 * @bus: the PCI bus to query
244 * @devfn: PCI device to query
245 * @cap: capability code
247 * Like pci_find_capability() but works for pci devices that do not have a
248 * pci_dev structure set up yet.
250 * Returns the address of the requested capability structure within the
251 * device's PCI configuration space or 0 in case the device does not
254 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
259 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
261 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
263 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
269 * pci_find_ext_capability - Find an extended capability
270 * @dev: PCI device to query
271 * @cap: capability code
273 * Returns the address of the requested extended capability structure
274 * within the device's PCI configuration space or 0 if the device does
275 * not support it. Possible values for @cap:
277 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
278 * %PCI_EXT_CAP_ID_VC Virtual Channel
279 * %PCI_EXT_CAP_ID_DSN Device Serial Number
280 * %PCI_EXT_CAP_ID_PWR Power Budgeting
282 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
286 int pos
= PCI_CFG_SPACE_SIZE
;
288 /* minimum 8 bytes per capability */
289 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
291 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
294 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
298 * If we have no capabilities, this is indicated by cap ID,
299 * cap version and next pointer all being 0.
305 if (PCI_EXT_CAP_ID(header
) == cap
)
308 pos
= PCI_EXT_CAP_NEXT(header
);
309 if (pos
< PCI_CFG_SPACE_SIZE
)
312 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
318 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
321 * pci_bus_find_ext_capability - find an extended capability
322 * @bus: the PCI bus to query
323 * @devfn: PCI device to query
324 * @cap: capability code
326 * Like pci_find_ext_capability() but works for pci devices that do not have a
327 * pci_dev structure set up yet.
329 * Returns the address of the requested capability structure within the
330 * device's PCI configuration space or 0 in case the device does not
333 int pci_bus_find_ext_capability(struct pci_bus
*bus
, unsigned int devfn
,
338 int pos
= PCI_CFG_SPACE_SIZE
;
340 /* minimum 8 bytes per capability */
341 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
343 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
345 if (header
== 0xffffffff || header
== 0)
349 if (PCI_EXT_CAP_ID(header
) == cap
)
352 pos
= PCI_EXT_CAP_NEXT(header
);
353 if (pos
< PCI_CFG_SPACE_SIZE
)
356 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
363 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
365 int rc
, ttl
= PCI_FIND_CAP_TTL
;
368 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
369 mask
= HT_3BIT_CAP_MASK
;
371 mask
= HT_5BIT_CAP_MASK
;
373 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
374 PCI_CAP_ID_HT
, &ttl
);
376 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
377 if (rc
!= PCIBIOS_SUCCESSFUL
)
380 if ((cap
& mask
) == ht_cap
)
383 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
384 pos
+ PCI_CAP_LIST_NEXT
,
385 PCI_CAP_ID_HT
, &ttl
);
391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
392 * @dev: PCI device to query
393 * @pos: Position from which to continue searching
394 * @ht_cap: Hypertransport capability code
396 * To be used in conjunction with pci_find_ht_capability() to search for
397 * all capabilities matching @ht_cap. @pos should always be a value returned
398 * from pci_find_ht_capability().
400 * NB. To be 100% safe against broken PCI devices, the caller should take
401 * steps to avoid an infinite loop.
403 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
405 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
407 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
410 * pci_find_ht_capability - query a device's Hypertransport capabilities
411 * @dev: PCI device to query
412 * @ht_cap: Hypertransport capability code
414 * Tell if a device supports a given Hypertransport capability.
415 * Returns an address within the device's PCI configuration space
416 * or 0 in case the device does not support the request capability.
417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
418 * which has a Hypertransport capability matching @ht_cap.
420 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
424 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
426 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
430 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
433 * pci_find_parent_resource - return resource region of parent bus of given region
434 * @dev: PCI device structure contains resources to be searched
435 * @res: child resource record for which parent is sought
437 * For given resource region of given device, return the resource
438 * region of parent bus the given region is contained in or where
439 * it should be allocated from.
442 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
444 const struct pci_bus
*bus
= dev
->bus
;
446 struct resource
*best
= NULL
, *r
;
448 pci_bus_for_each_resource(bus
, r
, i
) {
451 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
452 continue; /* Not contained */
453 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
454 continue; /* Wrong type */
455 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
456 return r
; /* Exact match */
457 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
458 if (r
->flags
& IORESOURCE_PREFETCH
)
460 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
469 * @dev: PCI device to have its BARs restored
471 * Restore the BAR values for a given device, so as to make it
472 * accessible by its driver.
475 pci_restore_bars(struct pci_dev
*dev
)
479 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
480 pci_update_resource(dev
, i
);
483 static struct pci_platform_pm_ops
*pci_platform_pm
;
485 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
487 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
488 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
490 pci_platform_pm
= ops
;
494 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
496 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
499 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
502 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
505 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
507 return pci_platform_pm
?
508 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
511 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
513 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
516 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
518 return pci_platform_pm
?
519 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
522 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
524 return pci_platform_pm
?
525 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
531 * @dev: PCI device to handle.
532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
535 * -EINVAL if the requested state is invalid.
536 * -EIO if device does not support PCI PM or its PM capabilities register has a
537 * wrong version, or device doesn't support the requested state.
538 * 0 if device already is in the requested state.
539 * 0 if device's power state has been successfully changed.
541 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
544 bool need_restore
= false;
546 /* Check if we're already there */
547 if (dev
->current_state
== state
)
553 if (state
< PCI_D0
|| state
> PCI_D3hot
)
556 /* Validate current state:
557 * Can enter D0 from any state, but if we can only go deeper
558 * to sleep if we're already in a low power state
560 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
561 && dev
->current_state
> state
) {
562 dev_err(&dev
->dev
, "invalid power transition "
563 "(from state %d to %d)\n", dev
->current_state
, state
);
567 /* check if this device supports the desired state */
568 if ((state
== PCI_D1
&& !dev
->d1_support
)
569 || (state
== PCI_D2
&& !dev
->d2_support
))
572 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
574 /* If we're (effectively) in D3, force entire word to 0.
575 * This doesn't affect PME_Status, disables PME_En, and
576 * sets PowerState to 0.
578 switch (dev
->current_state
) {
582 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
587 case PCI_UNKNOWN
: /* Boot-up */
588 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
589 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
591 /* Fall-through: force to D0 */
597 /* enter specified state */
598 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
600 /* Mandatory power management transition delays */
601 /* see PCI PM 1.1 5.6.1 table 18 */
602 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
603 pci_dev_d3_sleep(dev
);
604 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
605 udelay(PCI_PM_D2_DELAY
);
607 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
608 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
609 if (dev
->current_state
!= state
&& printk_ratelimit())
610 dev_info(&dev
->dev
, "Refused to change power state, "
611 "currently in D%d\n", dev
->current_state
);
613 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
614 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
615 * from D3hot to D0 _may_ perform an internal reset, thereby
616 * going to "D0 Uninitialized" rather than "D0 Initialized".
617 * For example, at least some versions of the 3c905B and the
618 * 3c556B exhibit this behaviour.
620 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
621 * devices in a D3hot state at boot. Consequently, we need to
622 * restore at least the BARs so that the device will be
623 * accessible to its driver.
626 pci_restore_bars(dev
);
629 pcie_aspm_pm_state_change(dev
->bus
->self
);
635 * pci_update_current_state - Read PCI power state of given device from its
636 * PCI PM registers and cache it
637 * @dev: PCI device to handle.
638 * @state: State to cache in case the device doesn't have the PM capability
640 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
645 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
646 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
648 dev
->current_state
= state
;
653 * pci_platform_power_transition - Use platform to change device power state
654 * @dev: PCI device to handle.
655 * @state: State to put the device into.
657 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
661 if (platform_pci_power_manageable(dev
)) {
662 error
= platform_pci_set_power_state(dev
, state
);
664 pci_update_current_state(dev
, state
);
667 /* Fall back to PCI_D0 if native PM is not supported */
669 dev
->current_state
= PCI_D0
;
676 * __pci_start_power_transition - Start power transition of a PCI device
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
680 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
683 pci_platform_power_transition(dev
, PCI_D0
);
687 * __pci_complete_power_transition - Complete power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
691 * This function should not be called directly by device drivers.
693 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
695 return state
>= PCI_D0
?
696 pci_platform_power_transition(dev
, state
) : -EINVAL
;
698 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
701 * pci_set_power_state - Set the power state of a PCI device
702 * @dev: PCI device to handle.
703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
705 * Transition a device to a new power state, using the platform firmware and/or
706 * the device's PCI PM registers.
709 * -EINVAL if the requested state is invalid.
710 * -EIO if device does not support PCI PM or its PM capabilities register has a
711 * wrong version, or device doesn't support the requested state.
712 * 0 if device already is in the requested state.
713 * 0 if device's power state has been successfully changed.
715 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
719 /* bound the state we're entering */
720 if (state
> PCI_D3hot
)
722 else if (state
< PCI_D0
)
724 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
726 * If the device or the parent bridge do not support PCI PM,
727 * ignore the request if we're doing anything other than putting
728 * it into D0 (which would only happen on boot).
732 __pci_start_power_transition(dev
, state
);
734 /* This device is quirked not to be put into D3, so
735 don't put it in D3 */
736 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
739 error
= pci_raw_set_power_state(dev
, state
);
741 if (!__pci_complete_power_transition(dev
, state
))
748 * pci_choose_state - Choose the power state of a PCI device
749 * @dev: PCI device to be suspended
750 * @state: target sleep state for the whole system. This is the value
751 * that is passed to suspend() function.
753 * Returns PCI power state suitable for given device and given system
757 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
761 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
764 ret
= platform_pci_choose_state(dev
);
765 if (ret
!= PCI_POWER_ERROR
)
768 switch (state
.event
) {
771 case PM_EVENT_FREEZE
:
772 case PM_EVENT_PRETHAW
:
773 /* REVISIT both freeze and pre-thaw "should" use D0 */
774 case PM_EVENT_SUSPEND
:
775 case PM_EVENT_HIBERNATE
:
778 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
785 EXPORT_SYMBOL(pci_choose_state
);
787 #define PCI_EXP_SAVE_REGS 7
789 #define pcie_cap_has_devctl(type, flags) 1
790 #define pcie_cap_has_lnkctl(type, flags) \
791 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
792 (type == PCI_EXP_TYPE_ROOT_PORT || \
793 type == PCI_EXP_TYPE_ENDPOINT || \
794 type == PCI_EXP_TYPE_LEG_END))
795 #define pcie_cap_has_sltctl(type, flags) \
796 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
797 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
798 (type == PCI_EXP_TYPE_DOWNSTREAM && \
799 (flags & PCI_EXP_FLAGS_SLOT))))
800 #define pcie_cap_has_rtctl(type, flags) \
801 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
802 (type == PCI_EXP_TYPE_ROOT_PORT || \
803 type == PCI_EXP_TYPE_RC_EC))
804 #define pcie_cap_has_devctl2(type, flags) \
805 ((flags & PCI_EXP_FLAGS_VERS) > 1)
806 #define pcie_cap_has_lnkctl2(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1)
808 #define pcie_cap_has_sltctl2(type, flags) \
809 ((flags & PCI_EXP_FLAGS_VERS) > 1)
811 static int pci_save_pcie_state(struct pci_dev
*dev
)
814 struct pci_cap_saved_state
*save_state
;
818 pos
= pci_pcie_cap(dev
);
822 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
824 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
827 cap
= (u16
*)&save_state
->data
[0];
829 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
831 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
832 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
833 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
834 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
835 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
836 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
837 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
838 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
839 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
840 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
841 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
842 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
843 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
844 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
849 static void pci_restore_pcie_state(struct pci_dev
*dev
)
852 struct pci_cap_saved_state
*save_state
;
856 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
857 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
858 if (!save_state
|| pos
<= 0)
860 cap
= (u16
*)&save_state
->data
[0];
862 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
864 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
865 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
866 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
867 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
868 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
869 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
870 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
871 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
872 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
873 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
874 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
875 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
876 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
877 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
881 static int pci_save_pcix_state(struct pci_dev
*dev
)
884 struct pci_cap_saved_state
*save_state
;
886 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
890 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
892 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
896 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
901 static void pci_restore_pcix_state(struct pci_dev
*dev
)
904 struct pci_cap_saved_state
*save_state
;
907 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
908 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
909 if (!save_state
|| pos
<= 0)
911 cap
= (u16
*)&save_state
->data
[0];
913 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
918 * pci_save_state - save the PCI configuration space of a device before suspending
919 * @dev: - PCI device that we're dealing with
922 pci_save_state(struct pci_dev
*dev
)
925 /* XXX: 100% dword access ok here? */
926 for (i
= 0; i
< 16; i
++)
927 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
928 dev
->state_saved
= true;
929 if ((i
= pci_save_pcie_state(dev
)) != 0)
931 if ((i
= pci_save_pcix_state(dev
)) != 0)
937 * pci_restore_state - Restore the saved state of a PCI device
938 * @dev: - PCI device that we're dealing with
941 pci_restore_state(struct pci_dev
*dev
)
946 if (!dev
->state_saved
)
949 /* PCI Express register must be restored first */
950 pci_restore_pcie_state(dev
);
953 * The Base Address register should be programmed before the command
956 for (i
= 15; i
>= 0; i
--) {
957 pci_read_config_dword(dev
, i
* 4, &val
);
958 if (val
!= dev
->saved_config_space
[i
]) {
959 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
960 "space at offset %#x (was %#x, writing %#x)\n",
961 i
, val
, (int)dev
->saved_config_space
[i
]);
962 pci_write_config_dword(dev
,i
* 4,
963 dev
->saved_config_space
[i
]);
966 pci_restore_pcix_state(dev
);
967 pci_restore_msi_state(dev
);
968 pci_restore_iov_state(dev
);
970 dev
->state_saved
= false;
975 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
979 err
= pci_set_power_state(dev
, PCI_D0
);
980 if (err
< 0 && err
!= -EIO
)
982 err
= pcibios_enable_device(dev
, bars
);
985 pci_fixup_device(pci_fixup_enable
, dev
);
991 * pci_reenable_device - Resume abandoned device
992 * @dev: PCI device to be resumed
994 * Note this function is a backend of pci_default_resume and is not supposed
995 * to be called by normal code, write proper resume handler and use it instead.
997 int pci_reenable_device(struct pci_dev
*dev
)
999 if (pci_is_enabled(dev
))
1000 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1004 static int __pci_enable_device_flags(struct pci_dev
*dev
,
1005 resource_size_t flags
)
1011 * Power state could be unknown at this point, either due to a fresh
1012 * boot or a device removal call. So get the current power state
1013 * so that things like MSI message writing will behave as expected
1014 * (e.g. if the device really is in D0 at enable time).
1018 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1019 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1022 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
1023 return 0; /* already enabled */
1025 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1026 if (dev
->resource
[i
].flags
& flags
)
1029 err
= do_pci_enable_device(dev
, bars
);
1031 atomic_dec(&dev
->enable_cnt
);
1036 * pci_enable_device_io - Initialize a device for use with IO space
1037 * @dev: PCI device to be initialized
1039 * Initialize device before it's used by a driver. Ask low-level code
1040 * to enable I/O resources. Wake up the device if it was suspended.
1041 * Beware, this function can fail.
1043 int pci_enable_device_io(struct pci_dev
*dev
)
1045 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
1049 * pci_enable_device_mem - Initialize a device for use with Memory space
1050 * @dev: PCI device to be initialized
1052 * Initialize device before it's used by a driver. Ask low-level code
1053 * to enable Memory resources. Wake up the device if it was suspended.
1054 * Beware, this function can fail.
1056 int pci_enable_device_mem(struct pci_dev
*dev
)
1058 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1062 * pci_enable_device - Initialize device before it's used by a driver.
1063 * @dev: PCI device to be initialized
1065 * Initialize device before it's used by a driver. Ask low-level code
1066 * to enable I/O and memory. Wake up the device if it was suspended.
1067 * Beware, this function can fail.
1069 * Note we don't actually enable the device many times if we call
1070 * this function repeatedly (we just increment the count).
1072 int pci_enable_device(struct pci_dev
*dev
)
1074 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1078 * Managed PCI resources. This manages device on/off, intx/msi/msix
1079 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1080 * there's no need to track it separately. pci_devres is initialized
1081 * when a device is enabled using managed PCI device enable interface.
1084 unsigned int enabled
:1;
1085 unsigned int pinned
:1;
1086 unsigned int orig_intx
:1;
1087 unsigned int restore_intx
:1;
1091 static void pcim_release(struct device
*gendev
, void *res
)
1093 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1094 struct pci_devres
*this = res
;
1097 if (dev
->msi_enabled
)
1098 pci_disable_msi(dev
);
1099 if (dev
->msix_enabled
)
1100 pci_disable_msix(dev
);
1102 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1103 if (this->region_mask
& (1 << i
))
1104 pci_release_region(dev
, i
);
1106 if (this->restore_intx
)
1107 pci_intx(dev
, this->orig_intx
);
1109 if (this->enabled
&& !this->pinned
)
1110 pci_disable_device(dev
);
1113 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1115 struct pci_devres
*dr
, *new_dr
;
1117 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1121 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1124 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1127 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1129 if (pci_is_managed(pdev
))
1130 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1135 * pcim_enable_device - Managed pci_enable_device()
1136 * @pdev: PCI device to be initialized
1138 * Managed pci_enable_device().
1140 int pcim_enable_device(struct pci_dev
*pdev
)
1142 struct pci_devres
*dr
;
1145 dr
= get_pci_dr(pdev
);
1151 rc
= pci_enable_device(pdev
);
1153 pdev
->is_managed
= 1;
1160 * pcim_pin_device - Pin managed PCI device
1161 * @pdev: PCI device to pin
1163 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1164 * driver detach. @pdev must have been enabled with
1165 * pcim_enable_device().
1167 void pcim_pin_device(struct pci_dev
*pdev
)
1169 struct pci_devres
*dr
;
1171 dr
= find_pci_dr(pdev
);
1172 WARN_ON(!dr
|| !dr
->enabled
);
1178 * pcibios_disable_device - disable arch specific PCI resources for device dev
1179 * @dev: the PCI device to disable
1181 * Disables architecture specific PCI resources for the device. This
1182 * is the default implementation. Architecture implementations can
1185 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1187 static void do_pci_disable_device(struct pci_dev
*dev
)
1191 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1192 if (pci_command
& PCI_COMMAND_MASTER
) {
1193 pci_command
&= ~PCI_COMMAND_MASTER
;
1194 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1197 pcibios_disable_device(dev
);
1201 * pci_disable_enabled_device - Disable device without updating enable_cnt
1202 * @dev: PCI device to disable
1204 * NOTE: This function is a backend of PCI power management routines and is
1205 * not supposed to be called drivers.
1207 void pci_disable_enabled_device(struct pci_dev
*dev
)
1209 if (pci_is_enabled(dev
))
1210 do_pci_disable_device(dev
);
1214 * pci_disable_device - Disable PCI device after use
1215 * @dev: PCI device to be disabled
1217 * Signal to the system that the PCI device is not in use by the system
1218 * anymore. This only involves disabling PCI bus-mastering, if active.
1220 * Note we don't actually disable the device until all callers of
1221 * pci_enable_device() have called pci_disable_device().
1224 pci_disable_device(struct pci_dev
*dev
)
1226 struct pci_devres
*dr
;
1228 dr
= find_pci_dr(dev
);
1232 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1235 do_pci_disable_device(dev
);
1237 dev
->is_busmaster
= 0;
1241 * pcibios_set_pcie_reset_state - set reset state for device dev
1242 * @dev: the PCIe device reset
1243 * @state: Reset state to enter into
1246 * Sets the PCIe reset state for the device. This is the default
1247 * implementation. Architecture implementations can override this.
1249 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1250 enum pcie_reset_state state
)
1256 * pci_set_pcie_reset_state - set reset state for device dev
1257 * @dev: the PCIe device reset
1258 * @state: Reset state to enter into
1261 * Sets the PCI reset state for the device.
1263 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1265 return pcibios_set_pcie_reset_state(dev
, state
);
1269 * pci_check_pme_status - Check if given device has generated PME.
1270 * @dev: Device to check.
1272 * Check the PME status of the device and if set, clear it and clear PME enable
1273 * (if set). Return 'true' if PME status and PME enable were both set or
1274 * 'false' otherwise.
1276 bool pci_check_pme_status(struct pci_dev
*dev
)
1285 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1286 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1287 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1290 /* Clear PME status. */
1291 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1292 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1293 /* Disable PME to avoid interrupt flood. */
1294 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1298 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1304 * Time to wait before the system can be put into a sleep state after reporting
1305 * a wakeup event signaled by a PCI device.
1307 #define PCI_WAKEUP_COOLDOWN 100
1310 * pci_wakeup_event - Report a wakeup event related to a given PCI device.
1311 * @dev: Device to report the wakeup event for.
1313 void pci_wakeup_event(struct pci_dev
*dev
)
1315 if (device_may_wakeup(&dev
->dev
))
1316 pm_wakeup_event(&dev
->dev
, PCI_WAKEUP_COOLDOWN
);
1320 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1321 * @dev: Device to handle.
1324 * Check if @dev has generated PME and queue a resume request for it in that
1327 static int pci_pme_wakeup(struct pci_dev
*dev
, void *ign
)
1329 if (pci_check_pme_status(dev
)) {
1330 pm_request_resume(&dev
->dev
);
1331 pci_wakeup_event(dev
);
1337 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1338 * @bus: Top bus of the subtree to walk.
1340 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1343 pci_walk_bus(bus
, pci_pme_wakeup
, NULL
);
1347 * pci_pme_capable - check the capability of PCI device to generate PME#
1348 * @dev: PCI device to handle.
1349 * @state: PCI state from which device will issue PME#.
1351 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1356 return !!(dev
->pme_support
& (1 << state
));
1359 static void pci_pme_list_scan(struct work_struct
*work
)
1361 struct pci_pme_device
*pme_dev
;
1363 mutex_lock(&pci_pme_list_mutex
);
1364 if (!list_empty(&pci_pme_list
)) {
1365 list_for_each_entry(pme_dev
, &pci_pme_list
, list
)
1366 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1367 schedule_delayed_work(&pci_pme_work
, msecs_to_jiffies(PME_TIMEOUT
));
1369 mutex_unlock(&pci_pme_list_mutex
);
1373 * pci_external_pme - is a device an external PCI PME source?
1374 * @dev: PCI device to check
1378 static bool pci_external_pme(struct pci_dev
*dev
)
1380 if (pci_is_pcie(dev
) || dev
->bus
->number
== 0)
1386 * pci_pme_active - enable or disable PCI device's PME# function
1387 * @dev: PCI device to handle.
1388 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1390 * The caller must verify that the device is capable of generating PME# before
1391 * calling this function with @enable equal to 'true'.
1393 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1400 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1401 /* Clear PME_Status by writing 1 to it and enable PME# */
1402 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1404 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1406 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1408 /* PCI (as opposed to PCIe) PME requires that the device have
1409 its PME# line hooked up correctly. Not all hardware vendors
1410 do this, so the PME never gets delivered and the device
1411 remains asleep. The easiest way around this is to
1412 periodically walk the list of suspended devices and check
1413 whether any have their PME flag set. The assumption is that
1414 we'll wake up often enough anyway that this won't be a huge
1415 hit, and the power savings from the devices will still be a
1418 if (pci_external_pme(dev
)) {
1419 struct pci_pme_device
*pme_dev
;
1421 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1426 mutex_lock(&pci_pme_list_mutex
);
1427 list_add(&pme_dev
->list
, &pci_pme_list
);
1428 if (list_is_singular(&pci_pme_list
))
1429 schedule_delayed_work(&pci_pme_work
,
1430 msecs_to_jiffies(PME_TIMEOUT
));
1431 mutex_unlock(&pci_pme_list_mutex
);
1433 mutex_lock(&pci_pme_list_mutex
);
1434 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1435 if (pme_dev
->dev
== dev
) {
1436 list_del(&pme_dev
->list
);
1441 mutex_unlock(&pci_pme_list_mutex
);
1446 dev_printk(KERN_DEBUG
, &dev
->dev
, "PME# %s\n",
1447 enable
? "enabled" : "disabled");
1451 * __pci_enable_wake - enable PCI device as wakeup event source
1452 * @dev: PCI device affected
1453 * @state: PCI state from which device will issue wakeup events
1454 * @runtime: True if the events are to be generated at run time
1455 * @enable: True to enable event generation; false to disable
1457 * This enables the device as a wakeup event source, or disables it.
1458 * When such events involves platform-specific hooks, those hooks are
1459 * called automatically by this routine.
1461 * Devices with legacy power management (no standard PCI PM capabilities)
1462 * always require such platform hooks.
1465 * 0 is returned on success
1466 * -EINVAL is returned if device is not supposed to wake up the system
1467 * Error code depending on the platform is returned if both the platform and
1468 * the native mechanism fail to enable the generation of wake-up events
1470 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1471 bool runtime
, bool enable
)
1475 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1478 /* Don't do the same thing twice in a row for one device. */
1479 if (!!enable
== !!dev
->wakeup_prepared
)
1483 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1484 * Anderson we should be doing PME# wake enable followed by ACPI wake
1485 * enable. To disable wake-up we call the platform first, for symmetry.
1491 if (pci_pme_capable(dev
, state
))
1492 pci_pme_active(dev
, true);
1495 error
= runtime
? platform_pci_run_wake(dev
, true) :
1496 platform_pci_sleep_wake(dev
, true);
1500 dev
->wakeup_prepared
= true;
1503 platform_pci_run_wake(dev
, false);
1505 platform_pci_sleep_wake(dev
, false);
1506 pci_pme_active(dev
, false);
1507 dev
->wakeup_prepared
= false;
1512 EXPORT_SYMBOL(__pci_enable_wake
);
1515 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1516 * @dev: PCI device to prepare
1517 * @enable: True to enable wake-up event generation; false to disable
1519 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1520 * and this function allows them to set that up cleanly - pci_enable_wake()
1521 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1522 * ordering constraints.
1524 * This function only returns error code if the device is not capable of
1525 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1526 * enable wake-up power for it.
1528 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1530 return pci_pme_capable(dev
, PCI_D3cold
) ?
1531 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1532 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1536 * pci_target_state - find an appropriate low power state for a given PCI dev
1539 * Use underlying platform code to find a supported low power state for @dev.
1540 * If the platform can't manage @dev, return the deepest state from which it
1541 * can generate wake events, based on any available PME info.
1543 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1545 pci_power_t target_state
= PCI_D3hot
;
1547 if (platform_pci_power_manageable(dev
)) {
1549 * Call the platform to choose the target state of the device
1550 * and enable wake-up from this state if supported.
1552 pci_power_t state
= platform_pci_choose_state(dev
);
1555 case PCI_POWER_ERROR
:
1560 if (pci_no_d1d2(dev
))
1563 target_state
= state
;
1565 } else if (!dev
->pm_cap
) {
1566 target_state
= PCI_D0
;
1567 } else if (device_may_wakeup(&dev
->dev
)) {
1569 * Find the deepest state from which the device can generate
1570 * wake-up events, make it the target state and enable device
1573 if (dev
->pme_support
) {
1575 && !(dev
->pme_support
& (1 << target_state
)))
1580 return target_state
;
1584 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1585 * @dev: Device to handle.
1587 * Choose the power state appropriate for the device depending on whether
1588 * it can wake up the system and/or is power manageable by the platform
1589 * (PCI_D3hot is the default) and put the device into that state.
1591 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1593 pci_power_t target_state
= pci_target_state(dev
);
1596 if (target_state
== PCI_POWER_ERROR
)
1599 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1601 error
= pci_set_power_state(dev
, target_state
);
1604 pci_enable_wake(dev
, target_state
, false);
1610 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1611 * @dev: Device to handle.
1613 * Disable device's system wake-up capability and put it into D0.
1615 int pci_back_from_sleep(struct pci_dev
*dev
)
1617 pci_enable_wake(dev
, PCI_D0
, false);
1618 return pci_set_power_state(dev
, PCI_D0
);
1622 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1623 * @dev: PCI device being suspended.
1625 * Prepare @dev to generate wake-up events at run time and put it into a low
1628 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1630 pci_power_t target_state
= pci_target_state(dev
);
1633 if (target_state
== PCI_POWER_ERROR
)
1636 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1638 error
= pci_set_power_state(dev
, target_state
);
1641 __pci_enable_wake(dev
, target_state
, true, false);
1647 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1648 * @dev: Device to check.
1650 * Return true if the device itself is cabable of generating wake-up events
1651 * (through the platform or using the native PCIe PME) or if the device supports
1652 * PME and one of its upstream bridges can generate wake-up events.
1654 bool pci_dev_run_wake(struct pci_dev
*dev
)
1656 struct pci_bus
*bus
= dev
->bus
;
1658 if (device_run_wake(&dev
->dev
))
1661 if (!dev
->pme_support
)
1664 while (bus
->parent
) {
1665 struct pci_dev
*bridge
= bus
->self
;
1667 if (device_run_wake(&bridge
->dev
))
1673 /* We have reached the root bus. */
1675 return device_run_wake(bus
->bridge
);
1679 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
1682 * pci_pm_init - Initialize PM functions of given PCI device
1683 * @dev: PCI device to handle.
1685 void pci_pm_init(struct pci_dev
*dev
)
1690 pm_runtime_forbid(&dev
->dev
);
1691 device_enable_async_suspend(&dev
->dev
);
1692 dev
->wakeup_prepared
= false;
1696 /* find PCI PM capability in list */
1697 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1700 /* Check device's ability to generate PME# */
1701 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1703 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1704 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1705 pmc
& PCI_PM_CAP_VER_MASK
);
1710 dev
->d3_delay
= PCI_PM_D3_WAIT
;
1712 dev
->d1_support
= false;
1713 dev
->d2_support
= false;
1714 if (!pci_no_d1d2(dev
)) {
1715 if (pmc
& PCI_PM_CAP_D1
)
1716 dev
->d1_support
= true;
1717 if (pmc
& PCI_PM_CAP_D2
)
1718 dev
->d2_support
= true;
1720 if (dev
->d1_support
|| dev
->d2_support
)
1721 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1722 dev
->d1_support
? " D1" : "",
1723 dev
->d2_support
? " D2" : "");
1726 pmc
&= PCI_PM_CAP_PME_MASK
;
1728 dev_printk(KERN_DEBUG
, &dev
->dev
,
1729 "PME# supported from%s%s%s%s%s\n",
1730 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1731 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1732 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1733 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1734 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1735 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1737 * Make device's PM flags reflect the wake-up capability, but
1738 * let the user space enable it to wake up the system as needed.
1740 device_set_wakeup_capable(&dev
->dev
, true);
1741 /* Disable the PME# generation functionality */
1742 pci_pme_active(dev
, false);
1744 dev
->pme_support
= 0;
1749 * platform_pci_wakeup_init - init platform wakeup if present
1752 * Some devices don't have PCI PM caps but can still generate wakeup
1753 * events through platform methods (like ACPI events). If @dev supports
1754 * platform wakeup events, set the device flag to indicate as much. This
1755 * may be redundant if the device also supports PCI PM caps, but double
1756 * initialization should be safe in that case.
1758 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1760 if (!platform_pci_can_wakeup(dev
))
1763 device_set_wakeup_capable(&dev
->dev
, true);
1764 platform_pci_sleep_wake(dev
, false);
1768 * pci_add_save_buffer - allocate buffer for saving given capability registers
1769 * @dev: the PCI device
1770 * @cap: the capability to allocate the buffer for
1771 * @size: requested size of the buffer
1773 static int pci_add_cap_save_buffer(
1774 struct pci_dev
*dev
, char cap
, unsigned int size
)
1777 struct pci_cap_saved_state
*save_state
;
1779 pos
= pci_find_capability(dev
, cap
);
1783 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1787 save_state
->cap_nr
= cap
;
1788 pci_add_saved_cap(dev
, save_state
);
1794 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1795 * @dev: the PCI device
1797 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1801 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1802 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1805 "unable to preallocate PCI Express save buffer\n");
1807 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1810 "unable to preallocate PCI-X save buffer\n");
1814 * pci_enable_ari - enable ARI forwarding if hardware support it
1815 * @dev: the PCI device
1817 void pci_enable_ari(struct pci_dev
*dev
)
1822 struct pci_dev
*bridge
;
1824 if (!pci_is_pcie(dev
) || dev
->devfn
)
1827 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1831 bridge
= dev
->bus
->self
;
1832 if (!bridge
|| !pci_is_pcie(bridge
))
1835 pos
= pci_pcie_cap(bridge
);
1839 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1840 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1843 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1844 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1845 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1847 bridge
->ari_enabled
= 1;
1850 static int pci_acs_enable
;
1853 * pci_request_acs - ask for ACS to be enabled if supported
1855 void pci_request_acs(void)
1861 * pci_enable_acs - enable ACS if hardware support it
1862 * @dev: the PCI device
1864 void pci_enable_acs(struct pci_dev
*dev
)
1870 if (!pci_acs_enable
)
1873 if (!pci_is_pcie(dev
))
1876 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
1880 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
1881 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
1883 /* Source Validation */
1884 ctrl
|= (cap
& PCI_ACS_SV
);
1886 /* P2P Request Redirect */
1887 ctrl
|= (cap
& PCI_ACS_RR
);
1889 /* P2P Completion Redirect */
1890 ctrl
|= (cap
& PCI_ACS_CR
);
1892 /* Upstream Forwarding */
1893 ctrl
|= (cap
& PCI_ACS_UF
);
1895 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
1899 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1900 * @dev: the PCI device
1901 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1903 * Perform INTx swizzling for a device behind one level of bridge. This is
1904 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1905 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1906 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1907 * the PCI Express Base Specification, Revision 2.1)
1909 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1913 if (pci_ari_enabled(dev
->bus
))
1916 slot
= PCI_SLOT(dev
->devfn
);
1918 return (((pin
- 1) + slot
) % 4) + 1;
1922 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1930 while (!pci_is_root_bus(dev
->bus
)) {
1931 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1932 dev
= dev
->bus
->self
;
1939 * pci_common_swizzle - swizzle INTx all the way to root bridge
1940 * @dev: the PCI device
1941 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1943 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1944 * bridges all the way up to a PCI root bus.
1946 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1950 while (!pci_is_root_bus(dev
->bus
)) {
1951 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1952 dev
= dev
->bus
->self
;
1955 return PCI_SLOT(dev
->devfn
);
1959 * pci_release_region - Release a PCI bar
1960 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1961 * @bar: BAR to release
1963 * Releases the PCI I/O and memory resources previously reserved by a
1964 * successful call to pci_request_region. Call this function only
1965 * after all use of the PCI regions has ceased.
1967 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1969 struct pci_devres
*dr
;
1971 if (pci_resource_len(pdev
, bar
) == 0)
1973 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1974 release_region(pci_resource_start(pdev
, bar
),
1975 pci_resource_len(pdev
, bar
));
1976 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1977 release_mem_region(pci_resource_start(pdev
, bar
),
1978 pci_resource_len(pdev
, bar
));
1980 dr
= find_pci_dr(pdev
);
1982 dr
->region_mask
&= ~(1 << bar
);
1986 * __pci_request_region - Reserved PCI I/O and memory resource
1987 * @pdev: PCI device whose resources are to be reserved
1988 * @bar: BAR to be reserved
1989 * @res_name: Name to be associated with resource.
1990 * @exclusive: whether the region access is exclusive or not
1992 * Mark the PCI region associated with PCI device @pdev BR @bar as
1993 * being reserved by owner @res_name. Do not access any
1994 * address inside the PCI regions unless this call returns
1997 * If @exclusive is set, then the region is marked so that userspace
1998 * is explicitly not allowed to map the resource via /dev/mem or
1999 * sysfs MMIO access.
2001 * Returns 0 on success, or %EBUSY on error. A warning
2002 * message is also printed on failure.
2004 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
2007 struct pci_devres
*dr
;
2009 if (pci_resource_len(pdev
, bar
) == 0)
2012 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2013 if (!request_region(pci_resource_start(pdev
, bar
),
2014 pci_resource_len(pdev
, bar
), res_name
))
2017 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2018 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2019 pci_resource_len(pdev
, bar
), res_name
,
2024 dr
= find_pci_dr(pdev
);
2026 dr
->region_mask
|= 1 << bar
;
2031 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2032 &pdev
->resource
[bar
]);
2037 * pci_request_region - Reserve PCI I/O and memory resource
2038 * @pdev: PCI device whose resources are to be reserved
2039 * @bar: BAR to be reserved
2040 * @res_name: Name to be associated with resource
2042 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2043 * being reserved by owner @res_name. Do not access any
2044 * address inside the PCI regions unless this call returns
2047 * Returns 0 on success, or %EBUSY on error. A warning
2048 * message is also printed on failure.
2050 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2052 return __pci_request_region(pdev
, bar
, res_name
, 0);
2056 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2057 * @pdev: PCI device whose resources are to be reserved
2058 * @bar: BAR to be reserved
2059 * @res_name: Name to be associated with resource.
2061 * Mark the PCI region associated with PCI device @pdev BR @bar as
2062 * being reserved by owner @res_name. Do not access any
2063 * address inside the PCI regions unless this call returns
2066 * Returns 0 on success, or %EBUSY on error. A warning
2067 * message is also printed on failure.
2069 * The key difference that _exclusive makes it that userspace is
2070 * explicitly not allowed to map the resource via /dev/mem or
2073 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2075 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2078 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2079 * @pdev: PCI device whose resources were previously reserved
2080 * @bars: Bitmask of BARs to be released
2082 * Release selected PCI I/O and memory resources previously reserved.
2083 * Call this function only after all use of the PCI regions has ceased.
2085 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2089 for (i
= 0; i
< 6; i
++)
2090 if (bars
& (1 << i
))
2091 pci_release_region(pdev
, i
);
2094 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2095 const char *res_name
, int excl
)
2099 for (i
= 0; i
< 6; i
++)
2100 if (bars
& (1 << i
))
2101 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2107 if (bars
& (1 << i
))
2108 pci_release_region(pdev
, i
);
2115 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2116 * @pdev: PCI device whose resources are to be reserved
2117 * @bars: Bitmask of BARs to be requested
2118 * @res_name: Name to be associated with resource
2120 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2121 const char *res_name
)
2123 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2126 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
2127 int bars
, const char *res_name
)
2129 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2130 IORESOURCE_EXCLUSIVE
);
2134 * pci_release_regions - Release reserved PCI I/O and memory resources
2135 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2137 * Releases all PCI I/O and memory resources previously reserved by a
2138 * successful call to pci_request_regions. Call this function only
2139 * after all use of the PCI regions has ceased.
2142 void pci_release_regions(struct pci_dev
*pdev
)
2144 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2148 * pci_request_regions - Reserved PCI I/O and memory resources
2149 * @pdev: PCI device whose resources are to be reserved
2150 * @res_name: Name to be associated with resource.
2152 * Mark all PCI regions associated with PCI device @pdev as
2153 * being reserved by owner @res_name. Do not access any
2154 * address inside the PCI regions unless this call returns
2157 * Returns 0 on success, or %EBUSY on error. A warning
2158 * message is also printed on failure.
2160 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2162 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2166 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2167 * @pdev: PCI device whose resources are to be reserved
2168 * @res_name: Name to be associated with resource.
2170 * Mark all PCI regions associated with PCI device @pdev as
2171 * being reserved by owner @res_name. Do not access any
2172 * address inside the PCI regions unless this call returns
2175 * pci_request_regions_exclusive() will mark the region so that
2176 * /dev/mem and the sysfs MMIO access will not be allowed.
2178 * Returns 0 on success, or %EBUSY on error. A warning
2179 * message is also printed on failure.
2181 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2183 return pci_request_selected_regions_exclusive(pdev
,
2184 ((1 << 6) - 1), res_name
);
2187 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2191 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2193 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2195 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2196 if (cmd
!= old_cmd
) {
2197 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2198 enable
? "enabling" : "disabling");
2199 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2201 dev
->is_busmaster
= enable
;
2205 * pci_set_master - enables bus-mastering for device dev
2206 * @dev: the PCI device to enable
2208 * Enables bus-mastering on the device and calls pcibios_set_master()
2209 * to do the needed arch specific settings.
2211 void pci_set_master(struct pci_dev
*dev
)
2213 __pci_set_master(dev
, true);
2214 pcibios_set_master(dev
);
2218 * pci_clear_master - disables bus-mastering for device dev
2219 * @dev: the PCI device to disable
2221 void pci_clear_master(struct pci_dev
*dev
)
2223 __pci_set_master(dev
, false);
2227 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2228 * @dev: the PCI device for which MWI is to be enabled
2230 * Helper function for pci_set_mwi.
2231 * Originally copied from drivers/net/acenic.c.
2232 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2234 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2236 int pci_set_cacheline_size(struct pci_dev
*dev
)
2240 if (!pci_cache_line_size
)
2243 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2244 equal to or multiple of the right value. */
2245 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2246 if (cacheline_size
>= pci_cache_line_size
&&
2247 (cacheline_size
% pci_cache_line_size
) == 0)
2250 /* Write the correct value. */
2251 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2253 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2254 if (cacheline_size
== pci_cache_line_size
)
2257 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
2258 "supported\n", pci_cache_line_size
<< 2);
2262 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2264 #ifdef PCI_DISABLE_MWI
2265 int pci_set_mwi(struct pci_dev
*dev
)
2270 int pci_try_set_mwi(struct pci_dev
*dev
)
2275 void pci_clear_mwi(struct pci_dev
*dev
)
2282 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2283 * @dev: the PCI device for which MWI is enabled
2285 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2287 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2290 pci_set_mwi(struct pci_dev
*dev
)
2295 rc
= pci_set_cacheline_size(dev
);
2299 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2300 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
2301 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2302 cmd
|= PCI_COMMAND_INVALIDATE
;
2303 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2310 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2311 * @dev: the PCI device for which MWI is enabled
2313 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2314 * Callers are not required to check the return value.
2316 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2318 int pci_try_set_mwi(struct pci_dev
*dev
)
2320 int rc
= pci_set_mwi(dev
);
2325 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2326 * @dev: the PCI device to disable
2328 * Disables PCI Memory-Write-Invalidate transaction on the device
2331 pci_clear_mwi(struct pci_dev
*dev
)
2335 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2336 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2337 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2338 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2341 #endif /* ! PCI_DISABLE_MWI */
2344 * pci_intx - enables/disables PCI INTx for device dev
2345 * @pdev: the PCI device to operate on
2346 * @enable: boolean: whether to enable or disable PCI INTx
2348 * Enables/disables PCI INTx for device dev
2351 pci_intx(struct pci_dev
*pdev
, int enable
)
2353 u16 pci_command
, new;
2355 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2358 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2360 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2363 if (new != pci_command
) {
2364 struct pci_devres
*dr
;
2366 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2368 dr
= find_pci_dr(pdev
);
2369 if (dr
&& !dr
->restore_intx
) {
2370 dr
->restore_intx
= 1;
2371 dr
->orig_intx
= !enable
;
2377 * pci_msi_off - disables any msi or msix capabilities
2378 * @dev: the PCI device to operate on
2380 * If you want to use msi see pci_enable_msi and friends.
2381 * This is a lower level primitive that allows us to disable
2382 * msi operation at the device level.
2384 void pci_msi_off(struct pci_dev
*dev
)
2389 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2391 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2392 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2393 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2395 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2397 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2398 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2399 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2402 EXPORT_SYMBOL_GPL(pci_msi_off
);
2404 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2406 return dma_set_max_seg_size(&dev
->dev
, size
);
2408 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2410 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2412 return dma_set_seg_boundary(&dev
->dev
, mask
);
2414 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2416 static int pcie_flr(struct pci_dev
*dev
, int probe
)
2421 u16 status
, control
;
2423 pos
= pci_pcie_cap(dev
);
2427 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
2428 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2434 /* Wait for Transaction Pending bit clean */
2435 for (i
= 0; i
< 4; i
++) {
2437 msleep((1 << (i
- 1)) * 100);
2439 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
2440 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2444 dev_err(&dev
->dev
, "transaction is not cleared; "
2445 "proceeding with reset anyway\n");
2448 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &control
);
2449 control
|= PCI_EXP_DEVCTL_BCR_FLR
;
2450 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, control
);
2457 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
2464 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2468 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
2469 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2475 /* Wait for Transaction Pending bit clean */
2476 for (i
= 0; i
< 4; i
++) {
2478 msleep((1 << (i
- 1)) * 100);
2480 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
2481 if (!(status
& PCI_AF_STATUS_TP
))
2485 dev_err(&dev
->dev
, "transaction is not cleared; "
2486 "proceeding with reset anyway\n");
2489 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2495 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
2502 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
2503 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
2509 if (dev
->current_state
!= PCI_D0
)
2512 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2514 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2515 pci_dev_d3_sleep(dev
);
2517 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2519 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2520 pci_dev_d3_sleep(dev
);
2525 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
2528 struct pci_dev
*pdev
;
2530 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
2533 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
2540 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
2541 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
2542 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2545 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
2546 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2552 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
2559 pci_block_user_cfg_access(dev
);
2560 /* block PM suspend, driver probe, etc. */
2561 device_lock(&dev
->dev
);
2564 rc
= pci_dev_specific_reset(dev
, probe
);
2568 rc
= pcie_flr(dev
, probe
);
2572 rc
= pci_af_flr(dev
, probe
);
2576 rc
= pci_pm_reset(dev
, probe
);
2580 rc
= pci_parent_bus_reset(dev
, probe
);
2583 device_unlock(&dev
->dev
);
2584 pci_unblock_user_cfg_access(dev
);
2591 * __pci_reset_function - reset a PCI device function
2592 * @dev: PCI device to reset
2594 * Some devices allow an individual function to be reset without affecting
2595 * other functions in the same device. The PCI device must be responsive
2596 * to PCI config space in order to use this function.
2598 * The device function is presumed to be unused when this function is called.
2599 * Resetting the device will make the contents of PCI configuration space
2600 * random, so any caller of this must be prepared to reinitialise the
2601 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2604 * Returns 0 if the device function was successfully reset or negative if the
2605 * device doesn't support resetting a single function.
2607 int __pci_reset_function(struct pci_dev
*dev
)
2609 return pci_dev_reset(dev
, 0);
2611 EXPORT_SYMBOL_GPL(__pci_reset_function
);
2614 * pci_probe_reset_function - check whether the device can be safely reset
2615 * @dev: PCI device to reset
2617 * Some devices allow an individual function to be reset without affecting
2618 * other functions in the same device. The PCI device must be responsive
2619 * to PCI config space in order to use this function.
2621 * Returns 0 if the device function can be reset or negative if the
2622 * device doesn't support resetting a single function.
2624 int pci_probe_reset_function(struct pci_dev
*dev
)
2626 return pci_dev_reset(dev
, 1);
2630 * pci_reset_function - quiesce and reset a PCI device function
2631 * @dev: PCI device to reset
2633 * Some devices allow an individual function to be reset without affecting
2634 * other functions in the same device. The PCI device must be responsive
2635 * to PCI config space in order to use this function.
2637 * This function does not just reset the PCI portion of a device, but
2638 * clears all the state associated with the device. This function differs
2639 * from __pci_reset_function in that it saves and restores device state
2642 * Returns 0 if the device function was successfully reset or negative if the
2643 * device doesn't support resetting a single function.
2645 int pci_reset_function(struct pci_dev
*dev
)
2649 rc
= pci_dev_reset(dev
, 1);
2653 pci_save_state(dev
);
2656 * both INTx and MSI are disabled after the Interrupt Disable bit
2657 * is set and the Bus Master bit is cleared.
2659 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2661 rc
= pci_dev_reset(dev
, 0);
2663 pci_restore_state(dev
);
2667 EXPORT_SYMBOL_GPL(pci_reset_function
);
2670 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2671 * @dev: PCI device to query
2673 * Returns mmrbc: maximum designed memory read count in bytes
2674 * or appropriate error value.
2676 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2681 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2685 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
2688 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
2690 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2693 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2694 * @dev: PCI device to query
2696 * Returns mmrbc: maximum memory read count in bytes
2697 * or appropriate error value.
2699 int pcix_get_mmrbc(struct pci_dev
*dev
)
2704 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2708 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
2711 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2713 EXPORT_SYMBOL(pcix_get_mmrbc
);
2716 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2717 * @dev: PCI device to query
2718 * @mmrbc: maximum memory read count in bytes
2719 * valid values are 512, 1024, 2048, 4096
2721 * If possible sets maximum memory read byte count, some bridges have erratas
2722 * that prevent this.
2724 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2730 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2733 v
= ffs(mmrbc
) - 10;
2735 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2739 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
2742 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2745 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
2748 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2750 if (v
> o
&& dev
->bus
&&
2751 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2754 cmd
&= ~PCI_X_CMD_MAX_READ
;
2756 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
2761 EXPORT_SYMBOL(pcix_set_mmrbc
);
2764 * pcie_get_readrq - get PCI Express read request size
2765 * @dev: PCI device to query
2767 * Returns maximum memory read request in bytes
2768 * or appropriate error value.
2770 int pcie_get_readrq(struct pci_dev
*dev
)
2775 cap
= pci_pcie_cap(dev
);
2779 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2781 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2785 EXPORT_SYMBOL(pcie_get_readrq
);
2788 * pcie_set_readrq - set PCI Express maximum memory read request
2789 * @dev: PCI device to query
2790 * @rq: maximum memory read count in bytes
2791 * valid values are 128, 256, 512, 1024, 2048, 4096
2793 * If possible sets maximum read byte count
2795 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2797 int cap
, err
= -EINVAL
;
2800 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2803 v
= (ffs(rq
) - 8) << 12;
2805 cap
= pci_pcie_cap(dev
);
2809 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2813 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2814 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2816 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2822 EXPORT_SYMBOL(pcie_set_readrq
);
2825 * pci_select_bars - Make BAR mask from the type of resource
2826 * @dev: the PCI device for which BAR mask is made
2827 * @flags: resource type mask to be selected
2829 * This helper routine makes bar mask from the type of resource.
2831 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2834 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2835 if (pci_resource_flags(dev
, i
) & flags
)
2841 * pci_resource_bar - get position of the BAR associated with a resource
2842 * @dev: the PCI device
2843 * @resno: the resource number
2844 * @type: the BAR type to be filled in
2846 * Returns BAR position in config space, or 0 if the BAR is invalid.
2848 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2852 if (resno
< PCI_ROM_RESOURCE
) {
2853 *type
= pci_bar_unknown
;
2854 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2855 } else if (resno
== PCI_ROM_RESOURCE
) {
2856 *type
= pci_bar_mem32
;
2857 return dev
->rom_base_reg
;
2858 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
2859 /* device specific resource */
2860 reg
= pci_iov_resource_bar(dev
, resno
, type
);
2865 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
2869 /* Some architectures require additional programming to enable VGA */
2870 static arch_set_vga_state_t arch_set_vga_state
;
2872 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
2874 arch_set_vga_state
= func
; /* NULL disables */
2877 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
2878 unsigned int command_bits
, bool change_bridge
)
2880 if (arch_set_vga_state
)
2881 return arch_set_vga_state(dev
, decode
, command_bits
,
2887 * pci_set_vga_state - set VGA decode state on device and parents if requested
2888 * @dev: the PCI device
2889 * @decode: true = enable decoding, false = disable decoding
2890 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2891 * @change_bridge: traverse ancestors and change bridges
2893 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
2894 unsigned int command_bits
, bool change_bridge
)
2896 struct pci_bus
*bus
;
2897 struct pci_dev
*bridge
;
2901 WARN_ON(command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
));
2903 /* ARCH specific VGA enables */
2904 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, change_bridge
);
2908 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2910 cmd
|= command_bits
;
2912 cmd
&= ~command_bits
;
2913 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2915 if (change_bridge
== false)
2922 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
2925 cmd
|= PCI_BRIDGE_CTL_VGA
;
2927 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
2928 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
2936 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2937 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2938 static DEFINE_SPINLOCK(resource_alignment_lock
);
2941 * pci_specified_resource_alignment - get resource alignment specified by user.
2942 * @dev: the PCI device to get
2944 * RETURNS: Resource alignment if it is specified.
2945 * Zero if it is not specified.
2947 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2949 int seg
, bus
, slot
, func
, align_order
, count
;
2950 resource_size_t align
= 0;
2953 spin_lock(&resource_alignment_lock
);
2954 p
= resource_alignment_param
;
2957 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2963 if (sscanf(p
, "%x:%x:%x.%x%n",
2964 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2966 if (sscanf(p
, "%x:%x.%x%n",
2967 &bus
, &slot
, &func
, &count
) != 3) {
2968 /* Invalid format */
2969 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2975 if (seg
== pci_domain_nr(dev
->bus
) &&
2976 bus
== dev
->bus
->number
&&
2977 slot
== PCI_SLOT(dev
->devfn
) &&
2978 func
== PCI_FUNC(dev
->devfn
)) {
2979 if (align_order
== -1) {
2982 align
= 1 << align_order
;
2987 if (*p
!= ';' && *p
!= ',') {
2988 /* End of param or invalid format */
2993 spin_unlock(&resource_alignment_lock
);
2998 * pci_is_reassigndev - check if specified PCI is target device to reassign
2999 * @dev: the PCI device to check
3001 * RETURNS: non-zero for PCI device is a target device to reassign,
3004 int pci_is_reassigndev(struct pci_dev
*dev
)
3006 return (pci_specified_resource_alignment(dev
) != 0);
3009 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
3011 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
3012 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
3013 spin_lock(&resource_alignment_lock
);
3014 strncpy(resource_alignment_param
, buf
, count
);
3015 resource_alignment_param
[count
] = '\0';
3016 spin_unlock(&resource_alignment_lock
);
3020 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
3023 spin_lock(&resource_alignment_lock
);
3024 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
3025 spin_unlock(&resource_alignment_lock
);
3029 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
3031 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
3034 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
3035 const char *buf
, size_t count
)
3037 return pci_set_resource_alignment_param(buf
, count
);
3040 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
3041 pci_resource_alignment_store
);
3043 static int __init
pci_resource_alignment_sysfs_init(void)
3045 return bus_create_file(&pci_bus_type
,
3046 &bus_attr_resource_alignment
);
3049 late_initcall(pci_resource_alignment_sysfs_init
);
3051 static void __devinit
pci_no_domains(void)
3053 #ifdef CONFIG_PCI_DOMAINS
3054 pci_domains_supported
= 0;
3059 * pci_ext_cfg_enabled - can we access extended PCI config space?
3060 * @dev: The PCI device of the root bridge.
3062 * Returns 1 if we can access PCI extended config space (offsets
3063 * greater than 0xff). This is the default implementation. Architecture
3064 * implementations can override this.
3066 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
3071 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
3074 EXPORT_SYMBOL(pci_fixup_cardbus
);
3076 static int __init
pci_setup(char *str
)
3079 char *k
= strchr(str
, ',');
3082 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
3083 if (!strcmp(str
, "nomsi")) {
3085 } else if (!strcmp(str
, "noaer")) {
3087 } else if (!strcmp(str
, "nodomains")) {
3089 } else if (!strncmp(str
, "cbiosize=", 9)) {
3090 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
3091 } else if (!strncmp(str
, "cbmemsize=", 10)) {
3092 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
3093 } else if (!strncmp(str
, "resource_alignment=", 19)) {
3094 pci_set_resource_alignment_param(str
+ 19,
3096 } else if (!strncmp(str
, "ecrc=", 5)) {
3097 pcie_ecrc_get_policy(str
+ 5);
3098 } else if (!strncmp(str
, "hpiosize=", 9)) {
3099 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
3100 } else if (!strncmp(str
, "hpmemsize=", 10)) {
3101 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
3103 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
3111 early_param("pci", pci_setup
);
3113 EXPORT_SYMBOL(pci_reenable_device
);
3114 EXPORT_SYMBOL(pci_enable_device_io
);
3115 EXPORT_SYMBOL(pci_enable_device_mem
);
3116 EXPORT_SYMBOL(pci_enable_device
);
3117 EXPORT_SYMBOL(pcim_enable_device
);
3118 EXPORT_SYMBOL(pcim_pin_device
);
3119 EXPORT_SYMBOL(pci_disable_device
);
3120 EXPORT_SYMBOL(pci_find_capability
);
3121 EXPORT_SYMBOL(pci_bus_find_capability
);
3122 EXPORT_SYMBOL(pci_release_regions
);
3123 EXPORT_SYMBOL(pci_request_regions
);
3124 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3125 EXPORT_SYMBOL(pci_release_region
);
3126 EXPORT_SYMBOL(pci_request_region
);
3127 EXPORT_SYMBOL(pci_request_region_exclusive
);
3128 EXPORT_SYMBOL(pci_release_selected_regions
);
3129 EXPORT_SYMBOL(pci_request_selected_regions
);
3130 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3131 EXPORT_SYMBOL(pci_set_master
);
3132 EXPORT_SYMBOL(pci_clear_master
);
3133 EXPORT_SYMBOL(pci_set_mwi
);
3134 EXPORT_SYMBOL(pci_try_set_mwi
);
3135 EXPORT_SYMBOL(pci_clear_mwi
);
3136 EXPORT_SYMBOL_GPL(pci_intx
);
3137 EXPORT_SYMBOL(pci_assign_resource
);
3138 EXPORT_SYMBOL(pci_find_parent_resource
);
3139 EXPORT_SYMBOL(pci_select_bars
);
3141 EXPORT_SYMBOL(pci_set_power_state
);
3142 EXPORT_SYMBOL(pci_save_state
);
3143 EXPORT_SYMBOL(pci_restore_state
);
3144 EXPORT_SYMBOL(pci_pme_capable
);
3145 EXPORT_SYMBOL(pci_pme_active
);
3146 EXPORT_SYMBOL(pci_wake_from_d3
);
3147 EXPORT_SYMBOL(pci_target_state
);
3148 EXPORT_SYMBOL(pci_prepare_to_sleep
);
3149 EXPORT_SYMBOL(pci_back_from_sleep
);
3150 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);