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OMAP3xxx: hwmod data: Add USBOTG
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blobcce09fdb904195f79b6d2f50f3ee5181d1c4c623
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l4_3xxx.h>
22 #include <plat/i2c.h>
23 #include <plat/gpio.h>
24 #include <plat/smartreflex.h>
25
26 #include "omap_hwmod_common_data.h"
27
28 #include "prm-regbits-34xx.h"
29 #include "cm-regbits-34xx.h"
30 #include "wd_timer.h"
31
32 /*
33 * OMAP3xxx hardware module integration data
34 *
35 * ALl of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs
38 * elsewhere.
39 */
40
41 static struct omap_hwmod omap3xxx_mpu_hwmod;
42 static struct omap_hwmod omap3xxx_iva_hwmod;
43 static struct omap_hwmod omap3xxx_l3_main_hwmod;
44 static struct omap_hwmod omap3xxx_l4_core_hwmod;
45 static struct omap_hwmod omap3xxx_l4_per_hwmod;
46 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
47 static struct omap_hwmod omap3xxx_i2c1_hwmod;
48 static struct omap_hwmod omap3xxx_i2c2_hwmod;
49 static struct omap_hwmod omap3xxx_i2c3_hwmod;
50 static struct omap_hwmod omap3xxx_gpio1_hwmod;
51 static struct omap_hwmod omap3xxx_gpio2_hwmod;
52 static struct omap_hwmod omap3xxx_gpio3_hwmod;
53 static struct omap_hwmod omap3xxx_gpio4_hwmod;
54 static struct omap_hwmod omap3xxx_gpio5_hwmod;
55 static struct omap_hwmod omap3xxx_gpio6_hwmod;
56 static struct omap_hwmod omap34xx_sr1_hwmod;
57 static struct omap_hwmod omap34xx_sr2_hwmod;
58
59 static struct omap_hwmod omap3xxx_dma_system_hwmod;
60
61 /* L3 -> L4_CORE interface */
62 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
63 .master = &omap3xxx_l3_main_hwmod,
64 .slave = &omap3xxx_l4_core_hwmod,
65 .user = OCP_USER_MPU | OCP_USER_SDMA,
66 };
67
68 /* L3 -> L4_PER interface */
69 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
70 .master = &omap3xxx_l3_main_hwmod,
71 .slave = &omap3xxx_l4_per_hwmod,
72 .user = OCP_USER_MPU | OCP_USER_SDMA,
73 };
74
75 /* MPU -> L3 interface */
76 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
77 .master = &omap3xxx_mpu_hwmod,
78 .slave = &omap3xxx_l3_main_hwmod,
79 .user = OCP_USER_MPU,
80 };
81
82 /* Slave interfaces on the L3 interconnect */
83 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
84 &omap3xxx_mpu__l3_main,
85 };
86
87 /* Master interfaces on the L3 interconnect */
88 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
89 &omap3xxx_l3_main__l4_core,
90 &omap3xxx_l3_main__l4_per,
91 };
92
93 /* L3 */
94 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
95 .name = "l3_main",
96 .class = &l3_hwmod_class,
97 .masters = omap3xxx_l3_main_masters,
98 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
99 .slaves = omap3xxx_l3_main_slaves,
100 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
102 .flags = HWMOD_NO_IDLEST,
103 };
104
105 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
106 static struct omap_hwmod omap3xxx_uart1_hwmod;
107 static struct omap_hwmod omap3xxx_uart2_hwmod;
108 static struct omap_hwmod omap3xxx_uart3_hwmod;
109 static struct omap_hwmod omap3xxx_uart4_hwmod;
110 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
111
112 /* l3_core -> usbhsotg interface */
113 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
114 .master = &omap3xxx_usbhsotg_hwmod,
115 .slave = &omap3xxx_l3_main_hwmod,
116 .clk = "core_l3_ick",
117 .user = OCP_USER_MPU,
118 };
119
120 /* L4_CORE -> L4_WKUP interface */
121 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
122 .master = &omap3xxx_l4_core_hwmod,
123 .slave = &omap3xxx_l4_wkup_hwmod,
124 .user = OCP_USER_MPU | OCP_USER_SDMA,
125 };
126
127 /* L4 CORE -> UART1 interface */
128 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
129 {
130 .pa_start = OMAP3_UART1_BASE,
131 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
132 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
133 },
134 };
135
136 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
137 .master = &omap3xxx_l4_core_hwmod,
138 .slave = &omap3xxx_uart1_hwmod,
139 .clk = "uart1_ick",
140 .addr = omap3xxx_uart1_addr_space,
141 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
142 .user = OCP_USER_MPU | OCP_USER_SDMA,
143 };
144
145 /* L4 CORE -> UART2 interface */
146 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
147 {
148 .pa_start = OMAP3_UART2_BASE,
149 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
150 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
151 },
152 };
153
154 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
155 .master = &omap3xxx_l4_core_hwmod,
156 .slave = &omap3xxx_uart2_hwmod,
157 .clk = "uart2_ick",
158 .addr = omap3xxx_uart2_addr_space,
159 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
160 .user = OCP_USER_MPU | OCP_USER_SDMA,
161 };
162
163 /* L4 PER -> UART3 interface */
164 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
165 {
166 .pa_start = OMAP3_UART3_BASE,
167 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
168 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
169 },
170 };
171
172 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
173 .master = &omap3xxx_l4_per_hwmod,
174 .slave = &omap3xxx_uart3_hwmod,
175 .clk = "uart3_ick",
176 .addr = omap3xxx_uart3_addr_space,
177 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
178 .user = OCP_USER_MPU | OCP_USER_SDMA,
179 };
180
181 /* L4 PER -> UART4 interface */
182 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
183 {
184 .pa_start = OMAP3_UART4_BASE,
185 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
186 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
187 },
188 };
189
190 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
191 .master = &omap3xxx_l4_per_hwmod,
192 .slave = &omap3xxx_uart4_hwmod,
193 .clk = "uart4_ick",
194 .addr = omap3xxx_uart4_addr_space,
195 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
196 .user = OCP_USER_MPU | OCP_USER_SDMA,
197 };
198
199 /* I2C IP block address space length (in bytes) */
200 #define OMAP2_I2C_AS_LEN 128
201
202 /* L4 CORE -> I2C1 interface */
203 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
204 {
205 .pa_start = 0x48070000,
206 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
207 .flags = ADDR_TYPE_RT,
208 },
209 };
210
211 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
212 .master = &omap3xxx_l4_core_hwmod,
213 .slave = &omap3xxx_i2c1_hwmod,
214 .clk = "i2c1_ick",
215 .addr = omap3xxx_i2c1_addr_space,
216 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
217 .fw = {
218 .omap2 = {
219 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
220 .l4_prot_group = 7,
221 .flags = OMAP_FIREWALL_L4,
222 }
223 },
224 .user = OCP_USER_MPU | OCP_USER_SDMA,
225 };
226
227 /* L4 CORE -> I2C2 interface */
228 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
229 {
230 .pa_start = 0x48072000,
231 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
232 .flags = ADDR_TYPE_RT,
233 },
234 };
235
236 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
237 .master = &omap3xxx_l4_core_hwmod,
238 .slave = &omap3xxx_i2c2_hwmod,
239 .clk = "i2c2_ick",
240 .addr = omap3xxx_i2c2_addr_space,
241 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
242 .fw = {
243 .omap2 = {
244 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
245 .l4_prot_group = 7,
246 .flags = OMAP_FIREWALL_L4,
247 }
248 },
249 .user = OCP_USER_MPU | OCP_USER_SDMA,
250 };
251
252 /* L4 CORE -> I2C3 interface */
253 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
254 {
255 .pa_start = 0x48060000,
256 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
257 .flags = ADDR_TYPE_RT,
258 },
259 };
260
261 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
262 .master = &omap3xxx_l4_core_hwmod,
263 .slave = &omap3xxx_i2c3_hwmod,
264 .clk = "i2c3_ick",
265 .addr = omap3xxx_i2c3_addr_space,
266 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
267 .fw = {
268 .omap2 = {
269 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
270 .l4_prot_group = 7,
271 .flags = OMAP_FIREWALL_L4,
272 }
273 },
274 .user = OCP_USER_MPU | OCP_USER_SDMA,
275 };
276
277 /* L4 CORE -> SR1 interface */
278 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
279 {
280 .pa_start = OMAP34XX_SR1_BASE,
281 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
282 .flags = ADDR_TYPE_RT,
283 },
284 };
285
286 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
287 .master = &omap3xxx_l4_core_hwmod,
288 .slave = &omap34xx_sr1_hwmod,
289 .clk = "sr_l4_ick",
290 .addr = omap3_sr1_addr_space,
291 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
292 .user = OCP_USER_MPU,
293 };
294
295 /* L4 CORE -> SR1 interface */
296 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
297 {
298 .pa_start = OMAP34XX_SR2_BASE,
299 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
300 .flags = ADDR_TYPE_RT,
301 },
302 };
303
304 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
305 .master = &omap3xxx_l4_core_hwmod,
306 .slave = &omap34xx_sr2_hwmod,
307 .clk = "sr_l4_ick",
308 .addr = omap3_sr2_addr_space,
309 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
310 .user = OCP_USER_MPU,
311 };
312
313 /*
314 * usbhsotg interface data
315 */
316
317 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
318 {
319 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
320 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
321 .flags = ADDR_TYPE_RT
322 },
323 };
324
325 /* l4_core -> usbhsotg */
326 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
327 .master = &omap3xxx_l4_core_hwmod,
328 .slave = &omap3xxx_usbhsotg_hwmod,
329 .clk = "l4_ick",
330 .addr = omap3xxx_usbhsotg_addrs,
331 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
332 .user = OCP_USER_MPU,
333 };
334
335 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
336 &omap3xxx_usbhsotg__l3,
337 };
338
339 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
340 &omap3xxx_l4_core__usbhsotg,
341 };
342
343 /* Slave interfaces on the L4_CORE interconnect */
344 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
345 &omap3xxx_l3_main__l4_core,
346 &omap3_l4_core__sr1,
347 &omap3_l4_core__sr2,
348 };
349
350 /* Master interfaces on the L4_CORE interconnect */
351 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
352 &omap3xxx_l4_core__l4_wkup,
353 &omap3_l4_core__uart1,
354 &omap3_l4_core__uart2,
355 &omap3_l4_core__i2c1,
356 &omap3_l4_core__i2c2,
357 &omap3_l4_core__i2c3,
358 };
359
360 /* L4 CORE */
361 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
362 .name = "l4_core",
363 .class = &l4_hwmod_class,
364 .masters = omap3xxx_l4_core_masters,
365 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
366 .slaves = omap3xxx_l4_core_slaves,
367 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
368 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
369 .flags = HWMOD_NO_IDLEST,
370 };
371
372 /* Slave interfaces on the L4_PER interconnect */
373 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
374 &omap3xxx_l3_main__l4_per,
375 };
376
377 /* Master interfaces on the L4_PER interconnect */
378 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
379 &omap3_l4_per__uart3,
380 &omap3_l4_per__uart4,
381 };
382
383 /* L4 PER */
384 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
385 .name = "l4_per",
386 .class = &l4_hwmod_class,
387 .masters = omap3xxx_l4_per_masters,
388 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
389 .slaves = omap3xxx_l4_per_slaves,
390 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
391 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
392 .flags = HWMOD_NO_IDLEST,
393 };
394
395 /* Slave interfaces on the L4_WKUP interconnect */
396 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
397 &omap3xxx_l4_core__l4_wkup,
398 };
399
400 /* Master interfaces on the L4_WKUP interconnect */
401 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
402 };
403
404 /* L4 WKUP */
405 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
406 .name = "l4_wkup",
407 .class = &l4_hwmod_class,
408 .masters = omap3xxx_l4_wkup_masters,
409 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
410 .slaves = omap3xxx_l4_wkup_slaves,
411 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
413 .flags = HWMOD_NO_IDLEST,
414 };
415
416 /* Master interfaces on the MPU device */
417 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
418 &omap3xxx_mpu__l3_main,
419 };
420
421 /* MPU */
422 static struct omap_hwmod omap3xxx_mpu_hwmod = {
423 .name = "mpu",
424 .class = &mpu_hwmod_class,
425 .main_clk = "arm_fck",
426 .masters = omap3xxx_mpu_masters,
427 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
428 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
429 };
430
431 /*
432 * IVA2_2 interface data
433 */
434
435 /* IVA2 <- L3 interface */
436 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
437 .master = &omap3xxx_l3_main_hwmod,
438 .slave = &omap3xxx_iva_hwmod,
439 .clk = "iva2_ck",
440 .user = OCP_USER_MPU | OCP_USER_SDMA,
441 };
442
443 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
444 &omap3xxx_l3__iva,
445 };
446
447 /*
448 * IVA2 (IVA2)
449 */
450
451 static struct omap_hwmod omap3xxx_iva_hwmod = {
452 .name = "iva",
453 .class = &iva_hwmod_class,
454 .masters = omap3xxx_iva_masters,
455 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
457 };
458
459 /* l4_wkup -> wd_timer2 */
460 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
461 {
462 .pa_start = 0x48314000,
463 .pa_end = 0x4831407f,
464 .flags = ADDR_TYPE_RT
465 },
466 };
467
468 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
469 .master = &omap3xxx_l4_wkup_hwmod,
470 .slave = &omap3xxx_wd_timer2_hwmod,
471 .clk = "wdt2_ick",
472 .addr = omap3xxx_wd_timer2_addrs,
473 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
474 .user = OCP_USER_MPU | OCP_USER_SDMA,
475 };
476
477 /*
478 * 'wd_timer' class
479 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
480 * overflow condition
481 */
482
483 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
484 .rev_offs = 0x0000,
485 .sysc_offs = 0x0010,
486 .syss_offs = 0x0014,
487 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
488 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
489 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
490 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
491 .sysc_fields = &omap_hwmod_sysc_type1,
492 };
493
494 /* I2C common */
495 static struct omap_hwmod_class_sysconfig i2c_sysc = {
496 .rev_offs = 0x00,
497 .sysc_offs = 0x20,
498 .syss_offs = 0x10,
499 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
500 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
501 SYSC_HAS_AUTOIDLE),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
503 .sysc_fields = &omap_hwmod_sysc_type1,
504 };
505
506 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
507 .name = "wd_timer",
508 .sysc = &omap3xxx_wd_timer_sysc,
509 .pre_shutdown = &omap2_wd_timer_disable
510 };
511
512 /* wd_timer2 */
513 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
514 &omap3xxx_l4_wkup__wd_timer2,
515 };
516
517 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
518 .name = "wd_timer2",
519 .class = &omap3xxx_wd_timer_hwmod_class,
520 .main_clk = "wdt2_fck",
521 .prcm = {
522 .omap2 = {
523 .prcm_reg_id = 1,
524 .module_bit = OMAP3430_EN_WDT2_SHIFT,
525 .module_offs = WKUP_MOD,
526 .idlest_reg_id = 1,
527 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
528 },
529 },
530 .slaves = omap3xxx_wd_timer2_slaves,
531 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
533 };
534
535 /* UART common */
536
537 static struct omap_hwmod_class_sysconfig uart_sysc = {
538 .rev_offs = 0x50,
539 .sysc_offs = 0x54,
540 .syss_offs = 0x58,
541 .sysc_flags = (SYSC_HAS_SIDLEMODE |
542 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
543 SYSC_HAS_AUTOIDLE),
544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
545 .sysc_fields = &omap_hwmod_sysc_type1,
546 };
547
548 static struct omap_hwmod_class uart_class = {
549 .name = "uart",
550 .sysc = &uart_sysc,
551 };
552
553 /* UART1 */
554
555 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
556 { .irq = INT_24XX_UART1_IRQ, },
557 };
558
559 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
560 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
561 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
562 };
563
564 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
565 &omap3_l4_core__uart1,
566 };
567
568 static struct omap_hwmod omap3xxx_uart1_hwmod = {
569 .name = "uart1",
570 .mpu_irqs = uart1_mpu_irqs,
571 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
572 .sdma_reqs = uart1_sdma_reqs,
573 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
574 .main_clk = "uart1_fck",
575 .prcm = {
576 .omap2 = {
577 .module_offs = CORE_MOD,
578 .prcm_reg_id = 1,
579 .module_bit = OMAP3430_EN_UART1_SHIFT,
580 .idlest_reg_id = 1,
581 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
582 },
583 },
584 .slaves = omap3xxx_uart1_slaves,
585 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
586 .class = &uart_class,
587 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
588 };
589
590 /* UART2 */
591
592 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
593 { .irq = INT_24XX_UART2_IRQ, },
594 };
595
596 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
597 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
598 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
599 };
600
601 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
602 &omap3_l4_core__uart2,
603 };
604
605 static struct omap_hwmod omap3xxx_uart2_hwmod = {
606 .name = "uart2",
607 .mpu_irqs = uart2_mpu_irqs,
608 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
609 .sdma_reqs = uart2_sdma_reqs,
610 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
611 .main_clk = "uart2_fck",
612 .prcm = {
613 .omap2 = {
614 .module_offs = CORE_MOD,
615 .prcm_reg_id = 1,
616 .module_bit = OMAP3430_EN_UART2_SHIFT,
617 .idlest_reg_id = 1,
618 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
619 },
620 },
621 .slaves = omap3xxx_uart2_slaves,
622 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
623 .class = &uart_class,
624 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
625 };
626
627 /* UART3 */
628
629 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
630 { .irq = INT_24XX_UART3_IRQ, },
631 };
632
633 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
634 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
635 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
636 };
637
638 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
639 &omap3_l4_per__uart3,
640 };
641
642 static struct omap_hwmod omap3xxx_uart3_hwmod = {
643 .name = "uart3",
644 .mpu_irqs = uart3_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
646 .sdma_reqs = uart3_sdma_reqs,
647 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
648 .main_clk = "uart3_fck",
649 .prcm = {
650 .omap2 = {
651 .module_offs = OMAP3430_PER_MOD,
652 .prcm_reg_id = 1,
653 .module_bit = OMAP3430_EN_UART3_SHIFT,
654 .idlest_reg_id = 1,
655 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
656 },
657 },
658 .slaves = omap3xxx_uart3_slaves,
659 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
660 .class = &uart_class,
661 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
662 };
663
664 /* UART4 */
665
666 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
667 { .irq = INT_36XX_UART4_IRQ, },
668 };
669
670 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
671 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
672 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
673 };
674
675 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
676 &omap3_l4_per__uart4,
677 };
678
679 static struct omap_hwmod omap3xxx_uart4_hwmod = {
680 .name = "uart4",
681 .mpu_irqs = uart4_mpu_irqs,
682 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
683 .sdma_reqs = uart4_sdma_reqs,
684 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
685 .main_clk = "uart4_fck",
686 .prcm = {
687 .omap2 = {
688 .module_offs = OMAP3430_PER_MOD,
689 .prcm_reg_id = 1,
690 .module_bit = OMAP3630_EN_UART4_SHIFT,
691 .idlest_reg_id = 1,
692 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
693 },
694 },
695 .slaves = omap3xxx_uart4_slaves,
696 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
697 .class = &uart_class,
698 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
699 };
700
701 static struct omap_hwmod_class i2c_class = {
702 .name = "i2c",
703 .sysc = &i2c_sysc,
704 };
705
706 /* I2C1 */
707
708 static struct omap_i2c_dev_attr i2c1_dev_attr = {
709 .fifo_depth = 8, /* bytes */
710 };
711
712 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
713 { .irq = INT_24XX_I2C1_IRQ, },
714 };
715
716 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
717 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
718 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
719 };
720
721 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
722 &omap3_l4_core__i2c1,
723 };
724
725 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
726 .name = "i2c1",
727 .mpu_irqs = i2c1_mpu_irqs,
728 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
729 .sdma_reqs = i2c1_sdma_reqs,
730 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
731 .main_clk = "i2c1_fck",
732 .prcm = {
733 .omap2 = {
734 .module_offs = CORE_MOD,
735 .prcm_reg_id = 1,
736 .module_bit = OMAP3430_EN_I2C1_SHIFT,
737 .idlest_reg_id = 1,
738 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
739 },
740 },
741 .slaves = omap3xxx_i2c1_slaves,
742 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
743 .class = &i2c_class,
744 .dev_attr = &i2c1_dev_attr,
745 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
746 };
747
748 /* I2C2 */
749
750 static struct omap_i2c_dev_attr i2c2_dev_attr = {
751 .fifo_depth = 8, /* bytes */
752 };
753
754 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
755 { .irq = INT_24XX_I2C2_IRQ, },
756 };
757
758 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
759 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
760 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
761 };
762
763 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
764 &omap3_l4_core__i2c2,
765 };
766
767 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
768 .name = "i2c2",
769 .mpu_irqs = i2c2_mpu_irqs,
770 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
771 .sdma_reqs = i2c2_sdma_reqs,
772 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
773 .main_clk = "i2c2_fck",
774 .prcm = {
775 .omap2 = {
776 .module_offs = CORE_MOD,
777 .prcm_reg_id = 1,
778 .module_bit = OMAP3430_EN_I2C2_SHIFT,
779 .idlest_reg_id = 1,
780 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
781 },
782 },
783 .slaves = omap3xxx_i2c2_slaves,
784 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
785 .class = &i2c_class,
786 .dev_attr = &i2c2_dev_attr,
787 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
788 };
789
790 /* I2C3 */
791
792 static struct omap_i2c_dev_attr i2c3_dev_attr = {
793 .fifo_depth = 64, /* bytes */
794 };
795
796 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
797 { .irq = INT_34XX_I2C3_IRQ, },
798 };
799
800 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
801 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
802 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
803 };
804
805 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
806 &omap3_l4_core__i2c3,
807 };
808
809 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
810 .name = "i2c3",
811 .mpu_irqs = i2c3_mpu_irqs,
812 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
813 .sdma_reqs = i2c3_sdma_reqs,
814 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
815 .main_clk = "i2c3_fck",
816 .prcm = {
817 .omap2 = {
818 .module_offs = CORE_MOD,
819 .prcm_reg_id = 1,
820 .module_bit = OMAP3430_EN_I2C3_SHIFT,
821 .idlest_reg_id = 1,
822 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
823 },
824 },
825 .slaves = omap3xxx_i2c3_slaves,
826 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
827 .class = &i2c_class,
828 .dev_attr = &i2c3_dev_attr,
829 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
830 };
831
832 /* l4_wkup -> gpio1 */
833 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
834 {
835 .pa_start = 0x48310000,
836 .pa_end = 0x483101ff,
837 .flags = ADDR_TYPE_RT
838 },
839 };
840
841 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
842 .master = &omap3xxx_l4_wkup_hwmod,
843 .slave = &omap3xxx_gpio1_hwmod,
844 .addr = omap3xxx_gpio1_addrs,
845 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
846 .user = OCP_USER_MPU | OCP_USER_SDMA,
847 };
848
849 /* l4_per -> gpio2 */
850 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
851 {
852 .pa_start = 0x49050000,
853 .pa_end = 0x490501ff,
854 .flags = ADDR_TYPE_RT
855 },
856 };
857
858 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
859 .master = &omap3xxx_l4_per_hwmod,
860 .slave = &omap3xxx_gpio2_hwmod,
861 .addr = omap3xxx_gpio2_addrs,
862 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
863 .user = OCP_USER_MPU | OCP_USER_SDMA,
864 };
865
866 /* l4_per -> gpio3 */
867 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
868 {
869 .pa_start = 0x49052000,
870 .pa_end = 0x490521ff,
871 .flags = ADDR_TYPE_RT
872 },
873 };
874
875 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
876 .master = &omap3xxx_l4_per_hwmod,
877 .slave = &omap3xxx_gpio3_hwmod,
878 .addr = omap3xxx_gpio3_addrs,
879 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
880 .user = OCP_USER_MPU | OCP_USER_SDMA,
881 };
882
883 /* l4_per -> gpio4 */
884 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
885 {
886 .pa_start = 0x49054000,
887 .pa_end = 0x490541ff,
888 .flags = ADDR_TYPE_RT
889 },
890 };
891
892 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
893 .master = &omap3xxx_l4_per_hwmod,
894 .slave = &omap3xxx_gpio4_hwmod,
895 .addr = omap3xxx_gpio4_addrs,
896 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
897 .user = OCP_USER_MPU | OCP_USER_SDMA,
898 };
899
900 /* l4_per -> gpio5 */
901 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
902 {
903 .pa_start = 0x49056000,
904 .pa_end = 0x490561ff,
905 .flags = ADDR_TYPE_RT
906 },
907 };
908
909 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
910 .master = &omap3xxx_l4_per_hwmod,
911 .slave = &omap3xxx_gpio5_hwmod,
912 .addr = omap3xxx_gpio5_addrs,
913 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
914 .user = OCP_USER_MPU | OCP_USER_SDMA,
915 };
916
917 /* l4_per -> gpio6 */
918 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
919 {
920 .pa_start = 0x49058000,
921 .pa_end = 0x490581ff,
922 .flags = ADDR_TYPE_RT
923 },
924 };
925
926 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
927 .master = &omap3xxx_l4_per_hwmod,
928 .slave = &omap3xxx_gpio6_hwmod,
929 .addr = omap3xxx_gpio6_addrs,
930 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
931 .user = OCP_USER_MPU | OCP_USER_SDMA,
932 };
933
934 /*
935 * 'gpio' class
936 * general purpose io module
937 */
938
939 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
940 .rev_offs = 0x0000,
941 .sysc_offs = 0x0010,
942 .syss_offs = 0x0014,
943 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
944 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
945 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
946 .sysc_fields = &omap_hwmod_sysc_type1,
947 };
948
949 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
950 .name = "gpio",
951 .sysc = &omap3xxx_gpio_sysc,
952 .rev = 1,
953 };
954
955 /* gpio_dev_attr*/
956 static struct omap_gpio_dev_attr gpio_dev_attr = {
957 .bank_width = 32,
958 .dbck_flag = true,
959 };
960
961 /* gpio1 */
962 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
963 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
964 };
965
966 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
967 { .role = "dbclk", .clk = "gpio1_dbck", },
968 };
969
970 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
971 &omap3xxx_l4_wkup__gpio1,
972 };
973
974 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
975 .name = "gpio1",
976 .mpu_irqs = omap3xxx_gpio1_irqs,
977 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
978 .main_clk = "gpio1_ick",
979 .opt_clks = gpio1_opt_clks,
980 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
981 .prcm = {
982 .omap2 = {
983 .prcm_reg_id = 1,
984 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
985 .module_offs = WKUP_MOD,
986 .idlest_reg_id = 1,
987 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
988 },
989 },
990 .slaves = omap3xxx_gpio1_slaves,
991 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
992 .class = &omap3xxx_gpio_hwmod_class,
993 .dev_attr = &gpio_dev_attr,
994 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
995 };
996
997 /* gpio2 */
998 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
999 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
1000 };
1001
1002 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1003 { .role = "dbclk", .clk = "gpio2_dbck", },
1004 };
1005
1006 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1007 &omap3xxx_l4_per__gpio2,
1008 };
1009
1010 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1011 .name = "gpio2",
1012 .mpu_irqs = omap3xxx_gpio2_irqs,
1013 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
1014 .main_clk = "gpio2_ick",
1015 .opt_clks = gpio2_opt_clks,
1016 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1017 .prcm = {
1018 .omap2 = {
1019 .prcm_reg_id = 1,
1020 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1021 .module_offs = OMAP3430_PER_MOD,
1022 .idlest_reg_id = 1,
1023 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1024 },
1025 },
1026 .slaves = omap3xxx_gpio2_slaves,
1027 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1028 .class = &omap3xxx_gpio_hwmod_class,
1029 .dev_attr = &gpio_dev_attr,
1030 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1031 };
1032
1033 /* gpio3 */
1034 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
1035 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
1036 };
1037
1038 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1039 { .role = "dbclk", .clk = "gpio3_dbck", },
1040 };
1041
1042 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1043 &omap3xxx_l4_per__gpio3,
1044 };
1045
1046 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1047 .name = "gpio3",
1048 .mpu_irqs = omap3xxx_gpio3_irqs,
1049 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
1050 .main_clk = "gpio3_ick",
1051 .opt_clks = gpio3_opt_clks,
1052 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1053 .prcm = {
1054 .omap2 = {
1055 .prcm_reg_id = 1,
1056 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1057 .module_offs = OMAP3430_PER_MOD,
1058 .idlest_reg_id = 1,
1059 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1060 },
1061 },
1062 .slaves = omap3xxx_gpio3_slaves,
1063 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1064 .class = &omap3xxx_gpio_hwmod_class,
1065 .dev_attr = &gpio_dev_attr,
1066 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1067 };
1068
1069 /* gpio4 */
1070 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
1071 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
1072 };
1073
1074 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1075 { .role = "dbclk", .clk = "gpio4_dbck", },
1076 };
1077
1078 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1079 &omap3xxx_l4_per__gpio4,
1080 };
1081
1082 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1083 .name = "gpio4",
1084 .mpu_irqs = omap3xxx_gpio4_irqs,
1085 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1086 .main_clk = "gpio4_ick",
1087 .opt_clks = gpio4_opt_clks,
1088 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1089 .prcm = {
1090 .omap2 = {
1091 .prcm_reg_id = 1,
1092 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1093 .module_offs = OMAP3430_PER_MOD,
1094 .idlest_reg_id = 1,
1095 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1096 },
1097 },
1098 .slaves = omap3xxx_gpio4_slaves,
1099 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1100 .class = &omap3xxx_gpio_hwmod_class,
1101 .dev_attr = &gpio_dev_attr,
1102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1103 };
1104
1105 /* gpio5 */
1106 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1107 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1108 };
1109
1110 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1111 { .role = "dbclk", .clk = "gpio5_dbck", },
1112 };
1113
1114 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1115 &omap3xxx_l4_per__gpio5,
1116 };
1117
1118 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1119 .name = "gpio5",
1120 .mpu_irqs = omap3xxx_gpio5_irqs,
1121 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1122 .main_clk = "gpio5_ick",
1123 .opt_clks = gpio5_opt_clks,
1124 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1125 .prcm = {
1126 .omap2 = {
1127 .prcm_reg_id = 1,
1128 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1129 .module_offs = OMAP3430_PER_MOD,
1130 .idlest_reg_id = 1,
1131 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1132 },
1133 },
1134 .slaves = omap3xxx_gpio5_slaves,
1135 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1136 .class = &omap3xxx_gpio_hwmod_class,
1137 .dev_attr = &gpio_dev_attr,
1138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1139 };
1140
1141 /* gpio6 */
1142 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1143 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1144 };
1145
1146 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1147 { .role = "dbclk", .clk = "gpio6_dbck", },
1148 };
1149
1150 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1151 &omap3xxx_l4_per__gpio6,
1152 };
1153
1154 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1155 .name = "gpio6",
1156 .mpu_irqs = omap3xxx_gpio6_irqs,
1157 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1158 .main_clk = "gpio6_ick",
1159 .opt_clks = gpio6_opt_clks,
1160 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1161 .prcm = {
1162 .omap2 = {
1163 .prcm_reg_id = 1,
1164 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1165 .module_offs = OMAP3430_PER_MOD,
1166 .idlest_reg_id = 1,
1167 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1168 },
1169 },
1170 .slaves = omap3xxx_gpio6_slaves,
1171 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1172 .class = &omap3xxx_gpio_hwmod_class,
1173 .dev_attr = &gpio_dev_attr,
1174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1175 };
1176
1177 /* dma_system -> L3 */
1178 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1179 .master = &omap3xxx_dma_system_hwmod,
1180 .slave = &omap3xxx_l3_main_hwmod,
1181 .clk = "core_l3_ick",
1182 .user = OCP_USER_MPU | OCP_USER_SDMA,
1183 };
1184
1185 /* dma attributes */
1186 static struct omap_dma_dev_attr dma_dev_attr = {
1187 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1188 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1189 .lch_count = 32,
1190 };
1191
1192 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1193 .rev_offs = 0x0000,
1194 .sysc_offs = 0x002c,
1195 .syss_offs = 0x0028,
1196 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1197 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1198 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
1199 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1200 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1201 .sysc_fields = &omap_hwmod_sysc_type1,
1202 };
1203
1204 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1205 .name = "dma",
1206 .sysc = &omap3xxx_dma_sysc,
1207 };
1208
1209 /* dma_system */
1210 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
1211 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1212 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1213 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1214 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1215 };
1216
1217 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1218 {
1219 .pa_start = 0x48056000,
1220 .pa_end = 0x4a0560ff,
1221 .flags = ADDR_TYPE_RT
1222 },
1223 };
1224
1225 /* dma_system master ports */
1226 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
1227 &omap3xxx_dma_system__l3,
1228 };
1229
1230 /* l4_cfg -> dma_system */
1231 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1232 .master = &omap3xxx_l4_core_hwmod,
1233 .slave = &omap3xxx_dma_system_hwmod,
1234 .clk = "core_l4_ick",
1235 .addr = omap3xxx_dma_system_addrs,
1236 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
1237 .user = OCP_USER_MPU | OCP_USER_SDMA,
1238 };
1239
1240 /* dma_system slave ports */
1241 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
1242 &omap3xxx_l4_core__dma_system,
1243 };
1244
1245 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1246 .name = "dma",
1247 .class = &omap3xxx_dma_hwmod_class,
1248 .mpu_irqs = omap3xxx_dma_system_irqs,
1249 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
1250 .main_clk = "core_l3_ick",
1251 .prcm = {
1252 .omap2 = {
1253 .module_offs = CORE_MOD,
1254 .prcm_reg_id = 1,
1255 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1256 .idlest_reg_id = 1,
1257 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1258 },
1259 },
1260 .slaves = omap3xxx_dma_system_slaves,
1261 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
1262 .masters = omap3xxx_dma_system_masters,
1263 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
1264 .dev_attr = &dma_dev_attr,
1265 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1266 .flags = HWMOD_NO_IDLEST,
1267 };
1268
1269 /* SR common */
1270 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1271 .clkact_shift = 20,
1272 };
1273
1274 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1275 .sysc_offs = 0x24,
1276 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1277 .clockact = CLOCKACT_TEST_ICLK,
1278 .sysc_fields = &omap34xx_sr_sysc_fields,
1279 };
1280
1281 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1282 .name = "smartreflex",
1283 .sysc = &omap34xx_sr_sysc,
1284 .rev = 1,
1285 };
1286
1287 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1288 .sidle_shift = 24,
1289 .enwkup_shift = 26
1290 };
1291
1292 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1293 .sysc_offs = 0x38,
1294 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1295 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1296 SYSC_NO_CACHE),
1297 .sysc_fields = &omap36xx_sr_sysc_fields,
1298 };
1299
1300 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1301 .name = "smartreflex",
1302 .sysc = &omap36xx_sr_sysc,
1303 .rev = 2,
1304 };
1305
1306 /* SR1 */
1307 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
1308 &omap3_l4_core__sr1,
1309 };
1310
1311 static struct omap_hwmod omap34xx_sr1_hwmod = {
1312 .name = "sr1_hwmod",
1313 .class = &omap34xx_smartreflex_hwmod_class,
1314 .main_clk = "sr1_fck",
1315 .vdd_name = "mpu",
1316 .prcm = {
1317 .omap2 = {
1318 .prcm_reg_id = 1,
1319 .module_bit = OMAP3430_EN_SR1_SHIFT,
1320 .module_offs = WKUP_MOD,
1321 .idlest_reg_id = 1,
1322 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1323 },
1324 },
1325 .slaves = omap3_sr1_slaves,
1326 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
1327 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1328 CHIP_IS_OMAP3430ES3_0 |
1329 CHIP_IS_OMAP3430ES3_1),
1330 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1331 };
1332
1333 static struct omap_hwmod omap36xx_sr1_hwmod = {
1334 .name = "sr1_hwmod",
1335 .class = &omap36xx_smartreflex_hwmod_class,
1336 .main_clk = "sr1_fck",
1337 .vdd_name = "mpu",
1338 .prcm = {
1339 .omap2 = {
1340 .prcm_reg_id = 1,
1341 .module_bit = OMAP3430_EN_SR1_SHIFT,
1342 .module_offs = WKUP_MOD,
1343 .idlest_reg_id = 1,
1344 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1345 },
1346 },
1347 .slaves = omap3_sr1_slaves,
1348 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
1349 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1350 };
1351
1352 /* SR2 */
1353 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
1354 &omap3_l4_core__sr2,
1355 };
1356
1357 static struct omap_hwmod omap34xx_sr2_hwmod = {
1358 .name = "sr2_hwmod",
1359 .class = &omap34xx_smartreflex_hwmod_class,
1360 .main_clk = "sr2_fck",
1361 .vdd_name = "core",
1362 .prcm = {
1363 .omap2 = {
1364 .prcm_reg_id = 1,
1365 .module_bit = OMAP3430_EN_SR2_SHIFT,
1366 .module_offs = WKUP_MOD,
1367 .idlest_reg_id = 1,
1368 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1369 },
1370 },
1371 .slaves = omap3_sr2_slaves,
1372 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
1373 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1374 CHIP_IS_OMAP3430ES3_0 |
1375 CHIP_IS_OMAP3430ES3_1),
1376 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1377 };
1378
1379 static struct omap_hwmod omap36xx_sr2_hwmod = {
1380 .name = "sr2_hwmod",
1381 .class = &omap36xx_smartreflex_hwmod_class,
1382 .main_clk = "sr2_fck",
1383 .vdd_name = "core",
1384 .prcm = {
1385 .omap2 = {
1386 .prcm_reg_id = 1,
1387 .module_bit = OMAP3430_EN_SR2_SHIFT,
1388 .module_offs = WKUP_MOD,
1389 .idlest_reg_id = 1,
1390 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1391 },
1392 },
1393 .slaves = omap3_sr2_slaves,
1394 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
1395 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1396 };
1397
1398 /*
1399 * usbhsotg
1400 */
1401 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1402 .rev_offs = 0x0400,
1403 .sysc_offs = 0x0404,
1404 .syss_offs = 0x0408,
1405 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1406 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1407 SYSC_HAS_AUTOIDLE),
1408 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1409 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1410 .sysc_fields = &omap_hwmod_sysc_type1,
1411 };
1412
1413 static struct omap_hwmod_class usbotg_class = {
1414 .name = "usbotg",
1415 .sysc = &omap3xxx_usbhsotg_sysc,
1416 };
1417
1418 /* usb_otg_hs */
1419 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1420
1421 { .name = "mc", .irq = 92 },
1422 { .name = "dma", .irq = 93 },
1423 };
1424
1425 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1426 .name = "usb_otg_hs",
1427 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1428 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
1429 .main_clk = "hsotgusb_ick",
1430 .prcm = {
1431 .omap2 = {
1432 .prcm_reg_id = 1,
1433 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1434 .module_offs = CORE_MOD,
1435 .idlest_reg_id = 1,
1436 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1437 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1438 },
1439 },
1440 .masters = omap3xxx_usbhsotg_masters,
1441 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
1442 .slaves = omap3xxx_usbhsotg_slaves,
1443 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
1444 .class = &usbotg_class,
1445
1446 /*
1447 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1448 * broken when autoidle is enabled
1449 * workaround is to disable the autoidle bit at module level.
1450 */
1451 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1452 | HWMOD_SWSUP_MSTANDBY,
1453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1454 };
1455
1456 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1457 &omap3xxx_l3_main_hwmod,
1458 &omap3xxx_l4_core_hwmod,
1459 &omap3xxx_l4_per_hwmod,
1460 &omap3xxx_l4_wkup_hwmod,
1461 &omap3xxx_mpu_hwmod,
1462 &omap3xxx_iva_hwmod,
1463 &omap3xxx_wd_timer2_hwmod,
1464 &omap3xxx_uart1_hwmod,
1465 &omap3xxx_uart2_hwmod,
1466 &omap3xxx_uart3_hwmod,
1467 &omap3xxx_uart4_hwmod,
1468 &omap3xxx_i2c1_hwmod,
1469 &omap3xxx_i2c2_hwmod,
1470 &omap3xxx_i2c3_hwmod,
1471 &omap34xx_sr1_hwmod,
1472 &omap34xx_sr2_hwmod,
1473 &omap36xx_sr1_hwmod,
1474 &omap36xx_sr2_hwmod,
1475
1476
1477 /* gpio class */
1478 &omap3xxx_gpio1_hwmod,
1479 &omap3xxx_gpio2_hwmod,
1480 &omap3xxx_gpio3_hwmod,
1481 &omap3xxx_gpio4_hwmod,
1482 &omap3xxx_gpio5_hwmod,
1483 &omap3xxx_gpio6_hwmod,
1484
1485 /* dma_system class*/
1486 &omap3xxx_dma_system_hwmod,
1487
1488 /* usbotg class */
1489 &omap3xxx_usbhsotg_hwmod,
1490
1491 NULL,
1492 };
1493
1494 int __init omap3xxx_hwmod_init(void)
1495 {
1496 return omap_hwmod_init(omap3xxx_hwmods);
1497 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree