drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25
  26 #include "xhci.h"
  27
  28 /* Device for a quirk */
  29 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  30 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  31
  32 #define PCI_VENDOR_ID_ETRON             0x1b6f
  33 #define PCI_DEVICE_ID_ASROCK_P67        0x7023
  34
  35 static const char hcd_name[] = "xhci_hcd";
  36
  37 /* called after powerup, by probe or system-pm "wakeup" */
  38 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  39 {
  40         /*
  41          * TODO: Implement finding debug ports later.
  42          * TODO: see if there are any quirks that need to be added to handle
  43          * new extended capabilities.
  44          */
  45
  46         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  47         if (!pci_set_mwi(pdev))
  48                 xhci_dbg(xhci, "MWI active\n");
  49
  50         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  51         return 0;
  52 }
  53
  54 /* called during probe() after chip reset completes */
  55 static int xhci_pci_setup(struct usb_hcd *hcd)
  56 {
  57         struct xhci_hcd         *xhci;
  58         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  59         int                     retval;
  60         u32                     temp;
  61
  62         hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
  63
  64         if (usb_hcd_is_primary_hcd(hcd)) {
  65                 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
  66                 if (!xhci)
  67                         return -ENOMEM;
  68                 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
  69                 xhci->main_hcd = hcd;
  70                 /* Mark the first roothub as being USB 2.0.
  71                  * The xHCI driver will register the USB 3.0 roothub.
  72                  */
  73                 hcd->speed = HCD_USB2;
  74                 hcd->self.root_hub->speed = USB_SPEED_HIGH;
  75                 /*
  76                  * USB 2.0 roothub under xHCI has an integrated TT,
  77                  * (rate matching hub) as opposed to having an OHCI/UHCI
  78                  * companion controller.
  79                  */
  80                 hcd->has_tt = 1;
  81         } else {
  82                 /* xHCI private pointer was set in xhci_pci_probe for the second
  83                  * registered roothub.
  84                  */
  85                 xhci = hcd_to_xhci(hcd);
  86                 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  87                 if (HCC_64BIT_ADDR(temp)) {
  88                         xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  89                         dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
  90                 } else {
  91                         dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
  92                 }
  93                 return 0;
  94         }
  95
  96         xhci->cap_regs = hcd->regs;
  97         xhci->op_regs = hcd->regs +
  98                 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
  99         xhci->run_regs = hcd->regs +
 100                 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
 101         /* Cache read-only capability registers */
 102         xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
 103         xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
 104         xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
 105         xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
 106         xhci->hci_version = HC_VERSION(xhci->hcc_params);
 107         xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 108         xhci_print_registers(xhci);
 109
 110         /* Look for vendor-specific quirks */
 111         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 112                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
 113                 if (pdev->revision == 0x0) {
 114                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 115                         xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
 116                                         " endpoint cmd after reset endpoint\n");
 117                 }
 118                 /* Fresco Logic confirms: all revisions of this chip do not
 119                  * support MSI, even though some of them claim to in their PCI
 120                  * capabilities.
 121                  */
 122                 xhci->quirks |= XHCI_BROKEN_MSI;
 123                 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
 124                                 "has broken MSI implementation\n",
 125                                 pdev->revision);
 126         }
 127
 128         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 129                 xhci->quirks |= XHCI_NEC_HOST;
 130
 131         /* AMD PLL quirk */
 132         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 133                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 134         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 135                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 136                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 137                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 138                 xhci->limit_active_eps = 64;
 139                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 140         }
 141         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 142                         pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
 143                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 144                 xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
 145         }
 146
 147         /* Make sure the HC is halted. */
 148         retval = xhci_halt(xhci);
 149         if (retval)
 150                 goto error;
 151
 152         xhci_dbg(xhci, "Resetting HCD\n");
 153         /* Reset the internal HC memory state and registers. */
 154         retval = xhci_reset(xhci);
 155         if (retval)
 156                 goto error;
 157         xhci_dbg(xhci, "Reset complete\n");
 158
 159         temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 160         if (HCC_64BIT_ADDR(temp)) {
 161                 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
 162                 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
 163         } else {
 164                 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
 165         }
 166
 167         xhci_dbg(xhci, "Calling HCD init\n");
 168         /* Initialize HCD and host controller data structures. */
 169         retval = xhci_init(hcd);
 170         if (retval)
 171                 goto error;
 172         xhci_dbg(xhci, "Called HCD init\n");
 173
 174         pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 175         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 176
 177         /* Find any debug ports */
 178         retval = xhci_pci_reinit(xhci, pdev);
 179         if (!retval)
 180                 return retval;
 181
 182 error:
 183         kfree(xhci);
 184         return retval;
 185 }
 186
 187 /*
 188  * We need to register our own PCI probe function (instead of the USB core's
 189  * function) in order to create a second roothub under xHCI.
 190  */
 191 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 192 {
 193         int retval;
 194         struct xhci_hcd *xhci;
 195         struct hc_driver *driver;
 196         struct usb_hcd *hcd;
 197
 198         driver = (struct hc_driver *)id->driver_data;
 199         /* Register the USB 2.0 roothub.
 200          * FIXME: USB core must know to register the USB 2.0 roothub first.
 201          * This is sort of silly, because we could just set the HCD driver flags
 202          * to say USB 2.0, but I'm not sure what the implications would be in
 203          * the other parts of the HCD code.
 204          */
 205         retval = usb_hcd_pci_probe(dev, id);
 206
 207         if (retval)
 208                 return retval;
 209
 210         /* USB 2.0 roothub is stored in the PCI device now. */
 211         hcd = dev_get_drvdata(&dev->dev);
 212         xhci = hcd_to_xhci(hcd);
 213         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 214                                 pci_name(dev), hcd);
 215         if (!xhci->shared_hcd) {
 216                 retval = -ENOMEM;
 217                 goto dealloc_usb2_hcd;
 218         }
 219
 220         /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
 221          * is called by usb_add_hcd().
 222          */
 223         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
 224
 225         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 226                         IRQF_DISABLED | IRQF_SHARED);
 227         if (retval)
 228                 goto put_usb3_hcd;
 229         /* Roothub already marked as USB 3.0 speed */
 230         return 0;
 231
 232 put_usb3_hcd:
 233         usb_put_hcd(xhci->shared_hcd);
 234 dealloc_usb2_hcd:
 235         usb_hcd_pci_remove(dev);
 236         return retval;
 237 }
 238
 239 static void xhci_pci_remove(struct pci_dev *dev)
 240 {
 241         struct xhci_hcd *xhci;
 242
 243         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 244         if (xhci->shared_hcd) {
 245                 usb_remove_hcd(xhci->shared_hcd);
 246                 usb_put_hcd(xhci->shared_hcd);
 247         }
 248         usb_hcd_pci_remove(dev);
 249         kfree(xhci);
 250 }
 251
 252 #ifdef CONFIG_PM
 253 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 254 {
 255         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 256         int     retval = 0;
 257
 258         if (hcd->state != HC_STATE_SUSPENDED ||
 259                         xhci->shared_hcd->state != HC_STATE_SUSPENDED)
 260                 return -EINVAL;
 261
 262         retval = xhci_suspend(xhci);
 263
 264         return retval;
 265 }
 266
 267 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 268 {
 269         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 270         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 271         int                     retval = 0;
 272
 273         /* The BIOS on systems with the Intel Panther Point chipset may or may
 274          * not support xHCI natively.  That means that during system resume, it
 275          * may switch the ports back to EHCI so that users can use their
 276          * keyboard to select a kernel from GRUB after resume from hibernate.
 277          *
 278          * The BIOS is supposed to remember whether the OS had xHCI ports
 279          * enabled before resume, and switch the ports back to xHCI when the
 280          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 281          * writers.
 282          *
 283          * Unconditionally switch the ports back to xHCI after a system resume.
 284          * We can't tell whether the EHCI or xHCI controller will be resumed
 285          * first, so we have to do the port switchover in both drivers.  Writing
 286          * a '1' to the port switchover registers should have no effect if the
 287          * port was already switched over.
 288          */
 289         if (usb_is_intel_switchable_xhci(pdev))
 290                 usb_enable_xhci_ports(pdev);
 291
 292         retval = xhci_resume(xhci, hibernated);
 293         return retval;
 294 }
 295 #endif /* CONFIG_PM */
 296
 297 static const struct hc_driver xhci_pci_hc_driver = {
 298         .description =          hcd_name,
 299         .product_desc =         "xHCI Host Controller",
 300         .hcd_priv_size =        sizeof(struct xhci_hcd *),
 301
 302         /*
 303          * generic hardware linkage
 304          */
 305         .irq =                  xhci_irq,
 306         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
 307
 308         /*
 309          * basic lifecycle operations
 310          */
 311         .reset =                xhci_pci_setup,
 312         .start =                xhci_run,
 313 #ifdef CONFIG_PM
 314         .pci_suspend =          xhci_pci_suspend,
 315         .pci_resume =           xhci_pci_resume,
 316 #endif
 317         .stop =                 xhci_stop,
 318         .shutdown =             xhci_shutdown,
 319
 320         /*
 321          * managing i/o requests and associated device resources
 322          */
 323         .urb_enqueue =          xhci_urb_enqueue,
 324         .urb_dequeue =          xhci_urb_dequeue,
 325         .alloc_dev =            xhci_alloc_dev,
 326         .free_dev =             xhci_free_dev,
 327         .alloc_streams =        xhci_alloc_streams,
 328         .free_streams =         xhci_free_streams,
 329         .add_endpoint =         xhci_add_endpoint,
 330         .drop_endpoint =        xhci_drop_endpoint,
 331         .endpoint_reset =       xhci_endpoint_reset,
 332         .check_bandwidth =      xhci_check_bandwidth,
 333         .reset_bandwidth =      xhci_reset_bandwidth,
 334         .address_device =       xhci_address_device,
 335         .update_hub_device =    xhci_update_hub_device,
 336         .reset_device =         xhci_discover_or_reset_device,
 337
 338         /*
 339          * scheduling support
 340          */
 341         .get_frame_number =     xhci_get_frame,
 342
 343         /* Root hub support */
 344         .hub_control =          xhci_hub_control,
 345         .hub_status_data =      xhci_hub_status_data,
 346         .bus_suspend =          xhci_bus_suspend,
 347         .bus_resume =           xhci_bus_resume,
 348 };
 349
 350 /*-------------------------------------------------------------------------*/
 351
 352 /* PCI driver selection metadata; PCI hotplugging uses this */
 353 static const struct pci_device_id pci_ids[] = { {
 354         /* handle any USB 3.0 xHCI controller */
 355         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 356         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 357         },
 358         { /* end: all zeroes */ }
 359 };
 360 MODULE_DEVICE_TABLE(pci, pci_ids);
 361
 362 /* pci driver glue; this is a "new style" PCI driver module */
 363 static struct pci_driver xhci_pci_driver = {
 364         .name =         (char *) hcd_name,
 365         .id_table =     pci_ids,
 366
 367         .probe =        xhci_pci_probe,
 368         .remove =       xhci_pci_remove,
 369         /* suspend and resume implemented later */
 370
 371         .shutdown =     usb_hcd_pci_shutdown,
 372 #ifdef CONFIG_PM_SLEEP
 373         .driver = {
 374                 .pm = &usb_hcd_pci_pm_ops
 375         },
 376 #endif
 377 };
 378
 379 int xhci_register_pci(void)
 380 {
 381         return pci_register_driver(&xhci_pci_driver);
 382 }
 383
 384 void xhci_unregister_pci(void)
 385 {
 386         pci_unregister_driver(&xhci_pci_driver);
 387 }