arch/powerpc/sysdev/uic.c

   1 /*
   2  * arch/powerpc/sysdev/uic.c
   3  *
   4  * IBM PowerPC 4xx Universal Interrupt Controller
   5  *
   6  * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/slab.h>
  18 #include <linux/stddef.h>
  19 #include <linux/sched.h>
  20 #include <linux/signal.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/device.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/irq.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel_stat.h>
  28 #include <asm/irq.h>
  29 #include <asm/io.h>
  30 #include <asm/prom.h>
  31 #include <asm/dcr.h>
  32
  33 #define NR_UIC_INTS     32
  34
  35 #define UIC_SR          0x0
  36 #define UIC_ER          0x2
  37 #define UIC_CR          0x3
  38 #define UIC_PR          0x4
  39 #define UIC_TR          0x5
  40 #define UIC_MSR         0x6
  41 #define UIC_VR          0x7
  42 #define UIC_VCR         0x8
  43
  44 #define uic_irq_to_hw(virq)     (irq_map[virq].hwirq)
  45
  46 struct uic *primary_uic;
  47
  48 struct uic {
  49         int index;
  50         int dcrbase;
  51
  52         spinlock_t lock;
  53
  54         /* The remapper for this UIC */
  55         struct irq_host *irqhost;
  56
  57         /* For secondary UICs, the cascade interrupt's irqaction */
  58         struct irqaction cascade;
  59
  60         /* The device node of the interrupt controller */
  61         struct device_node *of_node;
  62 };
  63
  64 static void uic_unmask_irq(unsigned int virq)
  65 {
  66         struct uic *uic = get_irq_chip_data(virq);
  67         unsigned int src = uic_irq_to_hw(virq);
  68         unsigned long flags;
  69         u32 er;
  70
  71         spin_lock_irqsave(&uic->lock, flags);
  72         er = mfdcr(uic->dcrbase + UIC_ER);
  73         er |= 1 << (31 - src);
  74         mtdcr(uic->dcrbase + UIC_ER, er);
  75         spin_unlock_irqrestore(&uic->lock, flags);
  76 }
  77
  78 static void uic_mask_irq(unsigned int virq)
  79 {
  80         struct uic *uic = get_irq_chip_data(virq);
  81         unsigned int src = uic_irq_to_hw(virq);
  82         unsigned long flags;
  83         u32 er;
  84
  85         spin_lock_irqsave(&uic->lock, flags);
  86         er = mfdcr(uic->dcrbase + UIC_ER);
  87         er &= ~(1 << (31 - src));
  88         mtdcr(uic->dcrbase + UIC_ER, er);
  89         spin_unlock_irqrestore(&uic->lock, flags);
  90 }
  91
  92 static void uic_ack_irq(unsigned int virq)
  93 {
  94         struct uic *uic = get_irq_chip_data(virq);
  95         unsigned int src = uic_irq_to_hw(virq);
  96         unsigned long flags;
  97
  98         spin_lock_irqsave(&uic->lock, flags);
  99         mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
 100         spin_unlock_irqrestore(&uic->lock, flags);
 101 }
 102
 103 static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
 104 {
 105         struct uic *uic = get_irq_chip_data(virq);
 106         unsigned int src = uic_irq_to_hw(virq);
 107         struct irq_desc *desc = get_irq_desc(virq);
 108         unsigned long flags;
 109         int trigger, polarity;
 110         u32 tr, pr, mask;
 111
 112         switch (flow_type & IRQ_TYPE_SENSE_MASK) {
 113         case IRQ_TYPE_NONE:
 114                 uic_mask_irq(virq);
 115                 return 0;
 116
 117         case IRQ_TYPE_EDGE_RISING:
 118                 trigger = 1; polarity = 1;
 119                 break;
 120         case IRQ_TYPE_EDGE_FALLING:
 121                 trigger = 1; polarity = 0;
 122                 break;
 123         case IRQ_TYPE_LEVEL_HIGH:
 124                 trigger = 0; polarity = 1;
 125                 break;
 126         case IRQ_TYPE_LEVEL_LOW:
 127                 trigger = 0; polarity = 0;
 128                 break;
 129         default:
 130                 return -EINVAL;
 131         }
 132
 133         mask = ~(1 << (31 - src));
 134
 135         spin_lock_irqsave(&uic->lock, flags);
 136         tr = mfdcr(uic->dcrbase + UIC_TR);
 137         pr = mfdcr(uic->dcrbase + UIC_PR);
 138         tr = (tr & mask) | (trigger << (31-src));
 139         pr = (pr & mask) | (polarity << (31-src));
 140
 141         mtdcr(uic->dcrbase + UIC_PR, pr);
 142         mtdcr(uic->dcrbase + UIC_TR, tr);
 143
 144         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 145         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 146         if (!trigger)
 147                 desc->status |= IRQ_LEVEL;
 148
 149         spin_unlock_irqrestore(&uic->lock, flags);
 150
 151         return 0;
 152 }
 153
 154 static struct irq_chip uic_irq_chip = {
 155         .typename       = " UIC  ",
 156         .unmask         = uic_unmask_irq,
 157         .mask           = uic_mask_irq,
 158 /*      .mask_ack       = uic_mask_irq_and_ack, */
 159         .ack            = uic_ack_irq,
 160         .set_type       = uic_set_irq_type,
 161 };
 162
 163 /**
 164  *      handle_uic_irq - irq flow handler for UIC
 165  *      @irq:   the interrupt number
 166  *      @desc:  the interrupt description structure for this irq
 167  *
 168  * This is modified version of the generic handle_level_irq() suitable
 169  * for the UIC.  On the UIC, acking (i.e. clearing the SR bit) a level
 170  * irq will have no effect if the interrupt is still asserted by the
 171  * device, even if the interrupt is already masked.  Therefore, unlike
 172  * the standard handle_level_irq(), we must ack the interrupt *after*
 173  * invoking the ISR (which should have de-asserted the interrupt in
 174  * the external source).  For edge interrupts we ack at the beginning
 175  * instead of the end, to keep the window in which we can miss an
 176  * interrupt as small as possible.
 177  */
 178 void fastcall handle_uic_irq(unsigned int irq, struct irq_desc *desc)
 179 {
 180         unsigned int cpu = smp_processor_id();
 181         struct irqaction *action;
 182         irqreturn_t action_ret;
 183
 184         spin_lock(&desc->lock);
 185         if (desc->status & IRQ_LEVEL)
 186                 desc->chip->mask(irq);
 187         else
 188                 desc->chip->mask_ack(irq);
 189
 190         if (unlikely(desc->status & IRQ_INPROGRESS))
 191                 goto out_unlock;
 192         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
 193         kstat_cpu(cpu).irqs[irq]++;
 194
 195         /*
 196          * If its disabled or no action available
 197          * keep it masked and get out of here
 198          */
 199         action = desc->action;
 200         if (unlikely(!action || (desc->status & IRQ_DISABLED))) {
 201                 desc->status |= IRQ_PENDING;
 202                 goto out_unlock;
 203         }
 204
 205         desc->status |= IRQ_INPROGRESS;
 206         desc->status &= ~IRQ_PENDING;
 207         spin_unlock(&desc->lock);
 208
 209         action_ret = handle_IRQ_event(irq, action);
 210
 211         spin_lock(&desc->lock);
 212         desc->status &= ~IRQ_INPROGRESS;
 213         if (desc->status & IRQ_LEVEL)
 214                 desc->chip->ack(irq);
 215         if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
 216                 desc->chip->unmask(irq);
 217 out_unlock:
 218         spin_unlock(&desc->lock);
 219 }
 220
 221 static int uic_host_match(struct irq_host *h, struct device_node *node)
 222 {
 223         struct uic *uic = h->host_data;
 224         return uic->of_node == node;
 225 }
 226
 227 static int uic_host_map(struct irq_host *h, unsigned int virq,
 228                         irq_hw_number_t hw)
 229 {
 230         struct uic *uic = h->host_data;
 231
 232         set_irq_chip_data(virq, uic);
 233         /* Despite the name, handle_level_irq() works for both level
 234          * and edge irqs on UIC.  FIXME: check this is correct */
 235         set_irq_chip_and_handler(virq, &uic_irq_chip, handle_uic_irq);
 236
 237         /* Set default irq type */
 238         set_irq_type(virq, IRQ_TYPE_NONE);
 239
 240         return 0;
 241 }
 242
 243 static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
 244                           u32 *intspec, unsigned int intsize,
 245                           irq_hw_number_t *out_hwirq, unsigned int *out_type)
 246
 247 {
 248         /* UIC intspecs must have 2 cells */
 249         BUG_ON(intsize != 2);
 250         *out_hwirq = intspec[0];
 251         *out_type = intspec[1];
 252         return 0;
 253 }
 254
 255 static struct irq_host_ops uic_host_ops = {
 256         .match  = uic_host_match,
 257         .map    = uic_host_map,
 258         .xlate  = uic_host_xlate,
 259 };
 260
 261 irqreturn_t uic_cascade(int virq, void *data)
 262 {
 263         struct uic *uic = data;
 264         u32 msr;
 265         int src;
 266         int subvirq;
 267
 268         msr = mfdcr(uic->dcrbase + UIC_MSR);
 269         src = 32 - ffs(msr);
 270
 271         subvirq = irq_linear_revmap(uic->irqhost, src);
 272         generic_handle_irq(subvirq);
 273
 274         return IRQ_HANDLED;
 275 }
 276
 277 static struct uic * __init uic_init_one(struct device_node *node)
 278 {
 279         struct uic *uic;
 280         const u32 *indexp, *dcrreg;
 281         int len;
 282
 283         BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
 284
 285         uic = alloc_bootmem(sizeof(*uic));
 286         if (! uic)
 287                 return NULL; /* FIXME: panic? */
 288
 289         memset(uic, 0, sizeof(*uic));
 290         spin_lock_init(&uic->lock);
 291         uic->of_node = of_node_get(node);
 292         indexp = of_get_property(node, "cell-index", &len);
 293         if (!indexp || (len != sizeof(u32))) {
 294                 printk(KERN_ERR "uic: Device node %s has missing or invalid "
 295                        "cell-index property\n", node->full_name);
 296                 return NULL;
 297         }
 298         uic->index = *indexp;
 299
 300         dcrreg = of_get_property(node, "dcr-reg", &len);
 301         if (!dcrreg || (len != 2*sizeof(u32))) {
 302                 printk(KERN_ERR "uic: Device node %s has missing or invalid "
 303                        "dcr-reg property\n", node->full_name);
 304                 return NULL;
 305         }
 306         uic->dcrbase = *dcrreg;
 307
 308         uic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_UIC_INTS,
 309                                       &uic_host_ops, -1);
 310         if (! uic->irqhost) {
 311                 of_node_put(node);
 312                 return NULL; /* FIXME: panic? */
 313         }
 314
 315         uic->irqhost->host_data = uic;
 316
 317         /* Start with all interrupts disabled, level and non-critical */
 318         mtdcr(uic->dcrbase + UIC_ER, 0);
 319         mtdcr(uic->dcrbase + UIC_CR, 0);
 320         mtdcr(uic->dcrbase + UIC_TR, 0);
 321         /* Clear any pending interrupts, in case the firmware left some */
 322         mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
 323
 324         printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
 325                 NR_UIC_INTS, uic->dcrbase);
 326
 327         return uic;
 328 }
 329
 330 void __init uic_init_tree(void)
 331 {
 332         struct device_node *np;
 333         struct uic *uic;
 334         const u32 *interrupts;
 335
 336         /* First locate and initialize the top-level UIC */
 337
 338         np = of_find_compatible_node(NULL, NULL, "ibm,uic");
 339         while (np) {
 340                 interrupts = of_get_property(np, "interrupts", NULL);
 341                 if (! interrupts)
 342                         break;
 343
 344                 np = of_find_compatible_node(np, NULL, "ibm,uic");
 345         }
 346
 347         BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
 348                       * top-level interrupt controller */
 349         primary_uic = uic_init_one(np);
 350         if (! primary_uic)
 351                 panic("Unable to initialize primary UIC %s\n", np->full_name);
 352
 353         irq_set_default_host(primary_uic->irqhost);
 354         of_node_put(np);
 355
 356         /* The scan again for cascaded UICs */
 357         np = of_find_compatible_node(NULL, NULL, "ibm,uic");
 358         while (np) {
 359                 interrupts = of_get_property(np, "interrupts", NULL);
 360                 if (interrupts) {
 361                         /* Secondary UIC */
 362                         int cascade_virq;
 363                         int ret;
 364
 365                         uic = uic_init_one(np);
 366                         if (! uic)
 367                                 panic("Unable to initialize a secondary UIC %s\n",
 368                                       np->full_name);
 369
 370                         cascade_virq = irq_of_parse_and_map(np, 0);
 371
 372                         uic->cascade.handler = uic_cascade;
 373                         uic->cascade.name = "UIC cascade";
 374                         uic->cascade.dev_id = uic;
 375
 376                         ret = setup_irq(cascade_virq, &uic->cascade);
 377                         if (ret)
 378                                 printk(KERN_ERR "Failed to setup_irq(%d) for "
 379                                        "UIC%d cascade\n", cascade_virq,
 380                                        uic->index);
 381
 382                         /* FIXME: setup critical cascade?? */
 383                 }
 384
 385                 np = of_find_compatible_node(np, NULL, "ibm,uic");
 386         }
 387 }
 388
 389 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 390 unsigned int uic_get_irq(void)
 391 {
 392         u32 msr;
 393         int src;
 394
 395         BUG_ON(! primary_uic);
 396
 397         msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
 398         src = 32 - ffs(msr);
 399
 400         return irq_linear_revmap(primary_uic->irqhost, src);
 401 }