2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
41 * Various Linux-internal data structures created from the
44 int apic_version
[MAX_APICS
];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
48 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
49 int mp_bus_id_to_pci_bus
[MAX_MP_BUSSES
] = { [0 ... MAX_MP_BUSSES
-1] = -1 };
50 static int mp_current_pci_id
;
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
58 /* MP IRQ source entries */
64 unsigned long mp_lapic_addr
;
66 unsigned int def_to_bigsmp
= 0;
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid
= -1U;
70 /* Internal processor count */
71 unsigned int num_processors
;
73 unsigned disabled_cpus __cpuinitdata
;
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map
;
79 DEFINE_PER_CPU(u16
, x86_bios_cpu_apicid
) = BAD_APICID
;
83 * Intel MP BIOS table parsing routines:
88 * Checksum an MP configuration block.
91 static int __init
mpf_checksum(unsigned char *mp
, int len
)
101 #ifdef CONFIG_X86_NUMAQ
103 * Have to match translation table entries to main table entries by counter
104 * hence the mpc_record variable .... can't see a less disgusting way of
108 static int mpc_record
;
109 static struct mpc_config_translation
*translation_table
[MAX_MPC_ENTRY
] __cpuinitdata
;
112 static void __cpuinit
MP_processor_info (struct mpc_config_processor
*m
)
114 int ver
, apicid
, cpu
;
116 physid_mask_t phys_cpu
;
118 if (!(m
->mpc_cpuflag
& CPU_ENABLED
)) {
123 #ifdef CONFIG_X86_NUMAQ
124 apicid
= mpc_apic_id(m
, translation_table
[mpc_record
]);
126 Dprintk("Processor #%d %u:%u APIC version %d\n",
128 (m
->mpc_cpufeature
& CPU_FAMILY_MASK
) >> 8,
129 (m
->mpc_cpufeature
& CPU_MODEL_MASK
) >> 4,
131 apicid
= m
->mpc_apicid
;
134 if (m
->mpc_featureflag
&(1<<0))
135 Dprintk(" Floating point unit present.\n");
136 if (m
->mpc_featureflag
&(1<<7))
137 Dprintk(" Machine Exception supported.\n");
138 if (m
->mpc_featureflag
&(1<<8))
139 Dprintk(" 64 bit compare & exchange supported.\n");
140 if (m
->mpc_featureflag
&(1<<9))
141 Dprintk(" Internal APIC present.\n");
142 if (m
->mpc_featureflag
&(1<<11))
143 Dprintk(" SEP present.\n");
144 if (m
->mpc_featureflag
&(1<<12))
145 Dprintk(" MTRR present.\n");
146 if (m
->mpc_featureflag
&(1<<13))
147 Dprintk(" PGE present.\n");
148 if (m
->mpc_featureflag
&(1<<14))
149 Dprintk(" MCA present.\n");
150 if (m
->mpc_featureflag
&(1<<15))
151 Dprintk(" CMOV present.\n");
152 if (m
->mpc_featureflag
&(1<<16))
153 Dprintk(" PAT present.\n");
154 if (m
->mpc_featureflag
&(1<<17))
155 Dprintk(" PSE present.\n");
156 if (m
->mpc_featureflag
&(1<<18))
157 Dprintk(" PSN present.\n");
158 if (m
->mpc_featureflag
&(1<<19))
159 Dprintk(" Cache Line Flush Instruction present.\n");
161 if (m
->mpc_featureflag
&(1<<21))
162 Dprintk(" Debug Trace and EMON Store present.\n");
163 if (m
->mpc_featureflag
&(1<<22))
164 Dprintk(" ACPI Thermal Throttle Registers present.\n");
165 if (m
->mpc_featureflag
&(1<<23))
166 Dprintk(" MMX present.\n");
167 if (m
->mpc_featureflag
&(1<<24))
168 Dprintk(" FXSR present.\n");
169 if (m
->mpc_featureflag
&(1<<25))
170 Dprintk(" XMM present.\n");
171 if (m
->mpc_featureflag
&(1<<26))
172 Dprintk(" Willamette New Instructions present.\n");
173 if (m
->mpc_featureflag
&(1<<27))
174 Dprintk(" Self Snoop present.\n");
175 if (m
->mpc_featureflag
&(1<<28))
176 Dprintk(" HT present.\n");
177 if (m
->mpc_featureflag
&(1<<29))
178 Dprintk(" Thermal Monitor present.\n");
179 /* 30, 31 Reserved */
182 if (m
->mpc_cpuflag
& CPU_BOOTPROCESSOR
) {
183 Dprintk(" Bootup CPU\n");
184 boot_cpu_physical_apicid
= m
->mpc_apicid
;
187 ver
= m
->mpc_apicver
;
193 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
194 "fixing up to 0x10. (tell your hw vendor)\n",
198 apic_version
[m
->mpc_apicid
] = ver
;
200 phys_cpu
= apicid_to_cpu_present(apicid
);
201 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, phys_cpu
);
203 if (num_processors
>= NR_CPUS
) {
204 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
205 " Processor ignored.\n", NR_CPUS
);
209 if (num_processors
>= maxcpus
) {
210 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
211 " Processor ignored.\n", maxcpus
);
215 cpu_set(num_processors
, cpu_possible_map
);
217 cpus_complement(tmp_map
, cpu_present_map
);
218 cpu
= first_cpu(tmp_map
);
220 if (m
->mpc_cpuflag
& CPU_BOOTPROCESSOR
)
222 * x86_bios_cpu_apicid is required to have processors listed
223 * in same order as logical cpu numbers. Hence the first
224 * entry is BSP, and so on.
229 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
230 * but we need to work other dependencies like SMP_SUSPEND etc
231 * before this can be done without some confusion.
232 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
233 * - Ashok Raj <ashok.raj@intel.com>
235 if (num_processors
> 8) {
236 switch (boot_cpu_data
.x86_vendor
) {
237 case X86_VENDOR_INTEL
:
238 if (!APIC_XAPIC(ver
)) {
242 /* If P4 and above fall through */
248 /* are we being called early in kernel startup? */
249 if (x86_cpu_to_apicid_early_ptr
) {
250 u16
*cpu_to_apicid
= x86_cpu_to_apicid_early_ptr
;
251 u16
*bios_cpu_apicid
= x86_bios_cpu_apicid_early_ptr
;
253 cpu_to_apicid
[cpu
] = m
->mpc_apicid
;
254 bios_cpu_apicid
[num_processors
- 1] = m
->mpc_apicid
;
256 per_cpu(x86_cpu_to_apicid
, cpu
) = m
->mpc_apicid
;
257 per_cpu(x86_bios_cpu_apicid
, cpu
) = m
->mpc_apicid
;
260 cpu_set(cpu
, cpu_present_map
);
263 static void __init
MP_bus_info (struct mpc_config_bus
*m
)
267 memcpy(str
, m
->mpc_bustype
, 6);
270 #ifdef CONFIG_X86_NUMAQ
271 mpc_oem_bus_info(m
, str
, translation_table
[mpc_record
]);
273 Dprintk("Bus #%d is %s\n", m
->mpc_busid
, str
);
276 #if MAX_MP_BUSSES < 256
277 if (m
->mpc_busid
>= MAX_MP_BUSSES
) {
278 printk(KERN_WARNING
"MP table busid value (%d) for bustype %s "
279 " is too large, max. supported is %d\n",
280 m
->mpc_busid
, str
, MAX_MP_BUSSES
- 1);
285 set_bit(m
->mpc_busid
, mp_bus_not_pci
);
286 if (strncmp(str
, BUSTYPE_PCI
, sizeof(BUSTYPE_PCI
)-1) == 0) {
287 #ifdef CONFIG_X86_NUMAQ
288 mpc_oem_pci_bus(m
, translation_table
[mpc_record
]);
290 clear_bit(m
->mpc_busid
, mp_bus_not_pci
);
291 mp_bus_id_to_pci_bus
[m
->mpc_busid
] = mp_current_pci_id
;
293 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
294 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_PCI
;
295 } else if (strncmp(str
, BUSTYPE_ISA
, sizeof(BUSTYPE_ISA
)-1) == 0) {
296 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_ISA
;
297 } else if (strncmp(str
, BUSTYPE_EISA
, sizeof(BUSTYPE_EISA
)-1) == 0) {
298 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_EISA
;
299 } else if (strncmp(str
, BUSTYPE_MCA
, sizeof(BUSTYPE_MCA
)-1) == 0) {
300 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_MCA
;
302 printk(KERN_WARNING
"Unknown bustype %s - ignoring\n", str
);
307 static int bad_ioapic(unsigned long address
)
309 if (nr_ioapics
>= MAX_IO_APICS
) {
310 printk(KERN_ERR
"ERROR: Max # of I/O APICs (%d) exceeded "
311 "(found %d)\n", MAX_IO_APICS
, nr_ioapics
);
312 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
315 printk(KERN_ERR
"WARNING: Bogus (zero) I/O APIC address"
316 " found in table, skipping!\n");
322 static void __init
MP_ioapic_info (struct mpc_config_ioapic
*m
)
324 if (!(m
->mpc_flags
& MPC_APIC_USABLE
))
327 printk(KERN_INFO
"I/O APIC #%d Version %d at 0x%X.\n",
328 m
->mpc_apicid
, m
->mpc_apicver
, m
->mpc_apicaddr
);
330 if (bad_ioapic(m
->mpc_apicaddr
))
333 mp_ioapics
[nr_ioapics
] = *m
;
337 static void __init
MP_intsrc_info (struct mpc_config_intsrc
*m
)
339 mp_irqs
[mp_irq_entries
] = *m
;
340 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
341 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
342 m
->mpc_irqtype
, m
->mpc_irqflag
& 3,
343 (m
->mpc_irqflag
>> 2) & 3, m
->mpc_srcbus
,
344 m
->mpc_srcbusirq
, m
->mpc_dstapic
, m
->mpc_dstirq
);
345 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
346 panic("Max # of irq sources exceeded!!\n");
349 static void __init
MP_lintsrc_info (struct mpc_config_lintsrc
*m
)
351 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
352 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
353 m
->mpc_irqtype
, m
->mpc_irqflag
& 3,
354 (m
->mpc_irqflag
>> 2) &3, m
->mpc_srcbusid
,
355 m
->mpc_srcbusirq
, m
->mpc_destapic
, m
->mpc_destapiclint
);
358 #ifdef CONFIG_X86_NUMAQ
359 static void __init
MP_translation_info (struct mpc_config_translation
*m
)
361 printk(KERN_INFO
"Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record
, m
->trans_type
, m
->trans_quad
, m
->trans_global
, m
->trans_local
);
363 if (mpc_record
>= MAX_MPC_ENTRY
)
364 printk(KERN_ERR
"MAX_MPC_ENTRY exceeded!\n");
366 translation_table
[mpc_record
] = m
; /* stash this for later */
367 if (m
->trans_quad
< MAX_NUMNODES
&& !node_online(m
->trans_quad
))
368 node_set_online(m
->trans_quad
);
372 * Read/parse the MPC oem tables
375 static void __init
smp_read_mpc_oem(struct mp_config_oemtable
*oemtable
, \
376 unsigned short oemsize
)
378 int count
= sizeof (*oemtable
); /* the header size */
379 unsigned char *oemptr
= ((unsigned char *)oemtable
)+count
;
382 printk(KERN_INFO
"Found an OEM MPC table at %8p - parsing it ... \n", oemtable
);
383 if (memcmp(oemtable
->oem_signature
,MPC_OEM_SIGNATURE
,4))
385 printk(KERN_WARNING
"SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
386 oemtable
->oem_signature
[0],
387 oemtable
->oem_signature
[1],
388 oemtable
->oem_signature
[2],
389 oemtable
->oem_signature
[3]);
392 if (mpf_checksum((unsigned char *)oemtable
,oemtable
->oem_length
))
394 printk(KERN_WARNING
"SMP oem mptable: checksum error!\n");
397 while (count
< oemtable
->oem_length
) {
401 struct mpc_config_translation
*m
=
402 (struct mpc_config_translation
*)oemptr
;
403 MP_translation_info(m
);
404 oemptr
+= sizeof(*m
);
411 printk(KERN_WARNING
"Unrecognised OEM table entry type! - %d\n", (int) *oemptr
);
418 static inline void mps_oem_check(struct mp_config_table
*mpc
, char *oem
,
421 if (strncmp(oem
, "IBM NUMA", 8))
422 printk("Warning! May not be a NUMA-Q system!\n");
424 smp_read_mpc_oem((struct mp_config_oemtable
*) mpc
->mpc_oemptr
,
427 #endif /* CONFIG_X86_NUMAQ */
433 static int __init
smp_read_mpc(struct mp_config_table
*mpc
)
437 int count
=sizeof(*mpc
);
438 unsigned char *mpt
=((unsigned char *)mpc
)+count
;
440 if (memcmp(mpc
->mpc_signature
,MPC_SIGNATURE
,4)) {
441 printk(KERN_ERR
"SMP mptable: bad signature [0x%x]!\n",
442 *(u32
*)mpc
->mpc_signature
);
445 if (mpf_checksum((unsigned char *)mpc
,mpc
->mpc_length
)) {
446 printk(KERN_ERR
"SMP mptable: checksum error!\n");
449 if (mpc
->mpc_spec
!=0x01 && mpc
->mpc_spec
!=0x04) {
450 printk(KERN_ERR
"SMP mptable: bad table version (%d)!!\n",
454 if (!mpc
->mpc_lapic
) {
455 printk(KERN_ERR
"SMP mptable: null local APIC address!\n");
458 memcpy(oem
,mpc
->mpc_oem
,8);
460 printk(KERN_INFO
"OEM ID: %s ",oem
);
462 memcpy(str
,mpc
->mpc_productid
,12);
464 printk("Product ID: %s ",str
);
466 mps_oem_check(mpc
, oem
, str
);
468 printk("APIC at: 0x%X\n", mpc
->mpc_lapic
);
471 * Save the local APIC address (it might be non-default) -- but only
472 * if we're not using ACPI.
475 mp_lapic_addr
= mpc
->mpc_lapic
;
478 * Now process the configuration blocks.
480 #ifdef CONFIG_X86_NUMAQ
483 while (count
< mpc
->mpc_length
) {
487 struct mpc_config_processor
*m
=
488 (struct mpc_config_processor
*)mpt
;
489 /* ACPI may have already provided this data */
491 MP_processor_info(m
);
498 struct mpc_config_bus
*m
=
499 (struct mpc_config_bus
*)mpt
;
507 struct mpc_config_ioapic
*m
=
508 (struct mpc_config_ioapic
*)mpt
;
516 struct mpc_config_intsrc
*m
=
517 (struct mpc_config_intsrc
*)mpt
;
526 struct mpc_config_lintsrc
*m
=
527 (struct mpc_config_lintsrc
*)mpt
;
535 count
= mpc
->mpc_length
;
539 #ifdef CONFIG_X86_NUMAQ
543 setup_apic_routing();
545 printk(KERN_ERR
"SMP mptable: no processors registered!\n");
546 return num_processors
;
549 static int __init
ELCR_trigger(unsigned int irq
)
553 port
= 0x4d0 + (irq
>> 3);
554 return (inb(port
) >> (irq
& 7)) & 1;
557 static void __init
construct_default_ioirq_mptable(int mpc_default_type
)
559 struct mpc_config_intsrc intsrc
;
561 int ELCR_fallback
= 0;
563 intsrc
.mpc_type
= MP_INTSRC
;
564 intsrc
.mpc_irqflag
= 0; /* conforming */
565 intsrc
.mpc_srcbus
= 0;
566 intsrc
.mpc_dstapic
= mp_ioapics
[0].mpc_apicid
;
568 intsrc
.mpc_irqtype
= mp_INT
;
571 * If true, we have an ISA/PCI system with no IRQ entries
572 * in the MP table. To prevent the PCI interrupts from being set up
573 * incorrectly, we try to use the ELCR. The sanity check to see if
574 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
575 * never be level sensitive, so we simply see if the ELCR agrees.
576 * If it does, we assume it's valid.
578 if (mpc_default_type
== 5) {
579 printk(KERN_INFO
"ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
581 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
582 printk(KERN_WARNING
"ELCR contains invalid data... not using ELCR\n");
584 printk(KERN_INFO
"Using ELCR to identify PCI interrupts\n");
589 for (i
= 0; i
< 16; i
++) {
590 switch (mpc_default_type
) {
592 if (i
== 0 || i
== 13)
593 continue; /* IRQ0 & IRQ13 not connected */
597 continue; /* IRQ2 is never connected */
602 * If the ELCR indicates a level-sensitive interrupt, we
603 * copy that information over to the MP table in the
604 * irqflag field (level sensitive, active high polarity).
607 intsrc
.mpc_irqflag
= 13;
609 intsrc
.mpc_irqflag
= 0;
612 intsrc
.mpc_srcbusirq
= i
;
613 intsrc
.mpc_dstirq
= i
? i
: 2; /* IRQ0 to INTIN2 */
614 MP_intsrc_info(&intsrc
);
617 intsrc
.mpc_irqtype
= mp_ExtINT
;
618 intsrc
.mpc_srcbusirq
= 0;
619 intsrc
.mpc_dstirq
= 0; /* 8259A to INTIN0 */
620 MP_intsrc_info(&intsrc
);
623 static inline void __init
construct_default_ISA_mptable(int mpc_default_type
)
625 struct mpc_config_processor processor
;
626 struct mpc_config_bus bus
;
627 struct mpc_config_ioapic ioapic
;
628 struct mpc_config_lintsrc lintsrc
;
629 int linttypes
[2] = { mp_ExtINT
, mp_NMI
};
633 * local APIC has default address
635 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
638 * 2 CPUs, numbered 0 & 1.
640 processor
.mpc_type
= MP_PROCESSOR
;
641 /* Either an integrated APIC or a discrete 82489DX. */
642 processor
.mpc_apicver
= mpc_default_type
> 4 ? 0x10 : 0x01;
643 processor
.mpc_cpuflag
= CPU_ENABLED
;
644 processor
.mpc_cpufeature
= (boot_cpu_data
.x86
<< 8) |
645 (boot_cpu_data
.x86_model
<< 4) |
646 boot_cpu_data
.x86_mask
;
647 processor
.mpc_featureflag
= boot_cpu_data
.x86_capability
[0];
648 processor
.mpc_reserved
[0] = 0;
649 processor
.mpc_reserved
[1] = 0;
650 for (i
= 0; i
< 2; i
++) {
651 processor
.mpc_apicid
= i
;
652 MP_processor_info(&processor
);
655 bus
.mpc_type
= MP_BUS
;
657 switch (mpc_default_type
) {
660 printk(KERN_ERR
"Unknown standard configuration %d\n",
665 memcpy(bus
.mpc_bustype
, "ISA ", 6);
670 memcpy(bus
.mpc_bustype
, "EISA ", 6);
674 memcpy(bus
.mpc_bustype
, "MCA ", 6);
677 if (mpc_default_type
> 4) {
679 memcpy(bus
.mpc_bustype
, "PCI ", 6);
683 ioapic
.mpc_type
= MP_IOAPIC
;
684 ioapic
.mpc_apicid
= 2;
685 ioapic
.mpc_apicver
= mpc_default_type
> 4 ? 0x10 : 0x01;
686 ioapic
.mpc_flags
= MPC_APIC_USABLE
;
687 ioapic
.mpc_apicaddr
= 0xFEC00000;
688 MP_ioapic_info(&ioapic
);
691 * We set up most of the low 16 IO-APIC pins according to MPS rules.
693 construct_default_ioirq_mptable(mpc_default_type
);
695 lintsrc
.mpc_type
= MP_LINTSRC
;
696 lintsrc
.mpc_irqflag
= 0; /* conforming */
697 lintsrc
.mpc_srcbusid
= 0;
698 lintsrc
.mpc_srcbusirq
= 0;
699 lintsrc
.mpc_destapic
= MP_APIC_ALL
;
700 for (i
= 0; i
< 2; i
++) {
701 lintsrc
.mpc_irqtype
= linttypes
[i
];
702 lintsrc
.mpc_destapiclint
= i
;
703 MP_lintsrc_info(&lintsrc
);
707 static struct intel_mp_floating
*mpf_found
;
710 * Scan the memory blocks for an SMP configuration block.
712 void __init
get_smp_config (void)
714 struct intel_mp_floating
*mpf
= mpf_found
;
717 * ACPI supports both logical (e.g. Hyper-Threading) and physical
718 * processors, where MPS only supports physical.
720 if (acpi_lapic
&& acpi_ioapic
) {
721 printk(KERN_INFO
"Using ACPI (MADT) for SMP configuration information\n");
725 printk(KERN_INFO
"Using ACPI for processor (LAPIC) configuration information\n");
727 printk(KERN_INFO
"Intel MultiProcessor Specification v1.%d\n", mpf
->mpf_specification
);
728 if (mpf
->mpf_feature2
& (1<<7)) {
729 printk(KERN_INFO
" IMCR and PIC compatibility mode.\n");
732 printk(KERN_INFO
" Virtual Wire compatibility mode.\n");
737 * Now see if we need to read further.
739 if (mpf
->mpf_feature1
!= 0) {
741 printk(KERN_INFO
"Default MP configuration #%d\n", mpf
->mpf_feature1
);
742 construct_default_ISA_mptable(mpf
->mpf_feature1
);
744 } else if (mpf
->mpf_physptr
) {
747 * Read the physical hardware table. Anything here will
748 * override the defaults.
750 if (!smp_read_mpc(phys_to_virt(mpf
->mpf_physptr
))) {
751 smp_found_config
= 0;
752 printk(KERN_ERR
"BIOS bug, MP table errors detected!...\n");
753 printk(KERN_ERR
"... disabling SMP support. (tell your hw vendor)\n");
757 * If there are no explicit MP IRQ entries, then we are
758 * broken. We set up most of the low 16 IO-APIC pins to
759 * ISA defaults and hope it will work.
761 if (!mp_irq_entries
) {
762 struct mpc_config_bus bus
;
764 printk(KERN_ERR
"BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
766 bus
.mpc_type
= MP_BUS
;
768 memcpy(bus
.mpc_bustype
, "ISA ", 6);
771 construct_default_ioirq_mptable(0);
777 printk(KERN_INFO
"Processors: %d\n", num_processors
);
779 * Only use the first configuration found.
783 static int __init
smp_scan_config (unsigned long base
, unsigned long length
)
785 unsigned long *bp
= phys_to_virt(base
);
786 struct intel_mp_floating
*mpf
;
788 printk(KERN_INFO
"Scan SMP from %p for %ld bytes.\n", bp
,length
);
789 if (sizeof(*mpf
) != 16)
790 printk("Error: MPF size\n");
793 mpf
= (struct intel_mp_floating
*)bp
;
794 if ((*bp
== SMP_MAGIC_IDENT
) &&
795 (mpf
->mpf_length
== 1) &&
796 !mpf_checksum((unsigned char *)bp
, 16) &&
797 ((mpf
->mpf_specification
== 1)
798 || (mpf
->mpf_specification
== 4)) ) {
800 smp_found_config
= 1;
801 printk(KERN_INFO
"found SMP MP-table at [%p] %08lx\n",
802 mpf
, virt_to_phys(mpf
));
803 reserve_bootmem(virt_to_phys(mpf
), PAGE_SIZE
,
805 if (mpf
->mpf_physptr
) {
807 * We cannot access to MPC table to compute
808 * table size yet, as only few megabytes from
809 * the bottom is mapped now.
810 * PC-9800's MPC table places on the very last
811 * of physical memory; so that simply reserving
812 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
813 * in reserve_bootmem.
815 unsigned long size
= PAGE_SIZE
;
816 unsigned long end
= max_low_pfn
* PAGE_SIZE
;
817 if (mpf
->mpf_physptr
+ size
> end
)
818 size
= end
- mpf
->mpf_physptr
;
819 reserve_bootmem(mpf
->mpf_physptr
, size
,
832 void __init
find_smp_config (void)
834 unsigned int address
;
837 * FIXME: Linux assumes you have 640K of base ram..
838 * this continues the error...
840 * 1) Scan the bottom 1K for a signature
841 * 2) Scan the top 1K of base RAM
842 * 3) Scan the 64K of bios
844 if (smp_scan_config(0x0,0x400) ||
845 smp_scan_config(639*0x400,0x400) ||
846 smp_scan_config(0xF0000,0x10000))
849 * If it is an SMP machine we should know now, unless the
850 * configuration is in an EISA/MCA bus machine with an
851 * extended bios data area.
853 * there is a real-mode segmented pointer pointing to the
854 * 4K EBDA area at 0x40E, calculate and scan it here.
856 * NOTE! There are Linux loaders that will corrupt the EBDA
857 * area, and as such this kind of SMP config may be less
858 * trustworthy, simply because the SMP table may have been
859 * stomped on during early boot. These loaders are buggy and
862 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
865 address
= get_bios_ebda();
867 smp_scan_config(address
, 0x400);
872 /* --------------------------------------------------------------------------
873 ACPI-based MP Configuration
874 -------------------------------------------------------------------------- */
878 void __init
mp_register_lapic_address(u64 address
)
880 mp_lapic_addr
= (unsigned long) address
;
882 set_fixmap_nocache(FIX_APIC_BASE
, mp_lapic_addr
);
884 if (boot_cpu_physical_apicid
== -1U)
885 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
887 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid
);
890 void __cpuinit
mp_register_lapic (u8 id
, u8 enabled
)
892 struct mpc_config_processor processor
;
895 if (MAX_APICS
- id
<= 0) {
896 printk(KERN_WARNING
"Processor #%d invalid (max %d)\n",
901 if (id
== boot_cpu_physical_apicid
)
904 processor
.mpc_type
= MP_PROCESSOR
;
905 processor
.mpc_apicid
= id
;
906 processor
.mpc_apicver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
907 processor
.mpc_cpuflag
= (enabled
? CPU_ENABLED
: 0);
908 processor
.mpc_cpuflag
|= (boot_cpu
? CPU_BOOTPROCESSOR
: 0);
909 processor
.mpc_cpufeature
= (boot_cpu_data
.x86
<< 8) |
910 (boot_cpu_data
.x86_model
<< 4) | boot_cpu_data
.x86_mask
;
911 processor
.mpc_featureflag
= boot_cpu_data
.x86_capability
[0];
912 processor
.mpc_reserved
[0] = 0;
913 processor
.mpc_reserved
[1] = 0;
915 MP_processor_info(&processor
);
918 #ifdef CONFIG_X86_IO_APIC
921 #define MP_MAX_IOAPIC_PIN 127
923 static struct mp_ioapic_routing
{
927 u32 pin_programmed
[4];
928 } mp_ioapic_routing
[MAX_IO_APICS
];
930 static int mp_find_ioapic (int gsi
)
934 /* Find the IOAPIC that manages this GSI. */
935 for (i
= 0; i
< nr_ioapics
; i
++) {
936 if ((gsi
>= mp_ioapic_routing
[i
].gsi_base
)
937 && (gsi
<= mp_ioapic_routing
[i
].gsi_end
))
941 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
946 static u8
uniq_ioapic_id(u8 id
)
948 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
949 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
950 return io_apic_get_unique_id(nr_ioapics
, id
);
955 void __init
mp_register_ioapic(u8 id
, u32 address
, u32 gsi_base
)
959 if (bad_ioapic(address
))
964 mp_ioapics
[idx
].mpc_type
= MP_IOAPIC
;
965 mp_ioapics
[idx
].mpc_flags
= MPC_APIC_USABLE
;
966 mp_ioapics
[idx
].mpc_apicaddr
= address
;
968 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
969 mp_ioapics
[idx
].mpc_apicid
= uniq_ioapic_id(id
);
970 mp_ioapics
[idx
].mpc_apicver
= io_apic_get_version(idx
);
973 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
974 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
976 mp_ioapic_routing
[idx
].apic_id
= mp_ioapics
[idx
].mpc_apicid
;
977 mp_ioapic_routing
[idx
].gsi_base
= gsi_base
;
978 mp_ioapic_routing
[idx
].gsi_end
= gsi_base
+
979 io_apic_get_redir_entries(idx
);
981 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
982 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].mpc_apicid
,
983 mp_ioapics
[idx
].mpc_apicver
,
984 mp_ioapics
[idx
].mpc_apicaddr
,
985 mp_ioapic_routing
[idx
].gsi_base
,
986 mp_ioapic_routing
[idx
].gsi_end
);
992 mp_override_legacy_irq(u8 bus_irq
, u8 polarity
, u8 trigger
, u32 gsi
)
994 struct mpc_config_intsrc intsrc
;
999 * Convert 'gsi' to 'ioapic.pin'.
1001 ioapic
= mp_find_ioapic(gsi
);
1004 pin
= gsi
- mp_ioapic_routing
[ioapic
].gsi_base
;
1007 * TBD: This check is for faulty timer entries, where the override
1008 * erroneously sets the trigger to level, resulting in a HUGE
1009 * increase of timer interrupts!
1011 if ((bus_irq
== 0) && (trigger
== 3))
1014 intsrc
.mpc_type
= MP_INTSRC
;
1015 intsrc
.mpc_irqtype
= mp_INT
;
1016 intsrc
.mpc_irqflag
= (trigger
<< 2) | polarity
;
1017 intsrc
.mpc_srcbus
= MP_ISA_BUS
;
1018 intsrc
.mpc_srcbusirq
= bus_irq
; /* IRQ */
1019 intsrc
.mpc_dstapic
= mp_ioapics
[ioapic
].mpc_apicid
; /* APIC ID */
1020 intsrc
.mpc_dstirq
= pin
; /* INTIN# */
1022 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1023 intsrc
.mpc_irqtype
, intsrc
.mpc_irqflag
& 3,
1024 (intsrc
.mpc_irqflag
>> 2) & 3, intsrc
.mpc_srcbus
,
1025 intsrc
.mpc_srcbusirq
, intsrc
.mpc_dstapic
, intsrc
.mpc_dstirq
);
1027 mp_irqs
[mp_irq_entries
] = intsrc
;
1028 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
1029 panic("Max # of irq sources exceeded!\n");
1032 void __init
mp_config_acpi_legacy_irqs (void)
1034 struct mpc_config_intsrc intsrc
;
1038 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1040 * Fabricate the legacy ISA bus (bus #31).
1042 mp_bus_id_to_type
[MP_ISA_BUS
] = MP_BUS_ISA
;
1044 set_bit(MP_ISA_BUS
, mp_bus_not_pci
);
1045 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS
);
1048 * Older generations of ES7000 have no legacy identity mappings
1050 if (es7000_plat
== 1)
1054 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1056 ioapic
= mp_find_ioapic(0);
1060 intsrc
.mpc_type
= MP_INTSRC
;
1061 intsrc
.mpc_irqflag
= 0; /* Conforming */
1062 intsrc
.mpc_srcbus
= MP_ISA_BUS
;
1063 intsrc
.mpc_dstapic
= mp_ioapics
[ioapic
].mpc_apicid
;
1066 * Use the default configuration for the IRQs 0-15. Unless
1067 * overridden by (MADT) interrupt source override entries.
1069 for (i
= 0; i
< 16; i
++) {
1072 for (idx
= 0; idx
< mp_irq_entries
; idx
++) {
1073 struct mpc_config_intsrc
*irq
= mp_irqs
+ idx
;
1075 /* Do we already have a mapping for this ISA IRQ? */
1076 if (irq
->mpc_srcbus
== MP_ISA_BUS
&& irq
->mpc_srcbusirq
== i
)
1079 /* Do we already have a mapping for this IOAPIC pin */
1080 if ((irq
->mpc_dstapic
== intsrc
.mpc_dstapic
) &&
1081 (irq
->mpc_dstirq
== i
))
1085 if (idx
!= mp_irq_entries
) {
1086 printk(KERN_DEBUG
"ACPI: IRQ%d used by override.\n", i
);
1087 continue; /* IRQ already used */
1090 intsrc
.mpc_irqtype
= mp_INT
;
1091 intsrc
.mpc_srcbusirq
= i
; /* Identity mapped */
1092 intsrc
.mpc_dstirq
= i
;
1094 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1095 "%d-%d\n", intsrc
.mpc_irqtype
, intsrc
.mpc_irqflag
& 3,
1096 (intsrc
.mpc_irqflag
>> 2) & 3, intsrc
.mpc_srcbus
,
1097 intsrc
.mpc_srcbusirq
, intsrc
.mpc_dstapic
,
1100 mp_irqs
[mp_irq_entries
] = intsrc
;
1101 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
1102 panic("Max # of irq sources exceeded!\n");
1106 #define MAX_GSI_NUM 4096
1107 #define IRQ_COMPRESSION_START 64
1109 int mp_register_gsi(u32 gsi
, int triggering
, int polarity
)
1114 static int pci_irq
= IRQ_COMPRESSION_START
;
1116 * Mapping between Global System Interrupts, which
1117 * represent all possible interrupts, and IRQs
1118 * assigned to actual devices.
1120 static int gsi_to_irq
[MAX_GSI_NUM
];
1122 /* Don't set up the ACPI SCI because it's already set up */
1123 if (acpi_gbl_FADT
.sci_interrupt
== gsi
)
1126 ioapic
= mp_find_ioapic(gsi
);
1128 printk(KERN_WARNING
"No IOAPIC for GSI %u\n", gsi
);
1132 ioapic_pin
= gsi
- mp_ioapic_routing
[ioapic
].gsi_base
;
1134 if (ioapic_renumber_irq
)
1135 gsi
= ioapic_renumber_irq(ioapic
, gsi
);
1138 * Avoid pin reprogramming. PRTs typically include entries
1139 * with redundant pin->gsi mappings (but unique PCI devices);
1140 * we only program the IOAPIC on the first.
1142 bit
= ioapic_pin
% 32;
1143 idx
= (ioapic_pin
< 32) ? 0 : (ioapic_pin
/ 32);
1145 printk(KERN_ERR
"Invalid reference to IOAPIC pin "
1146 "%d-%d\n", mp_ioapic_routing
[ioapic
].apic_id
,
1150 if ((1<<bit
) & mp_ioapic_routing
[ioapic
].pin_programmed
[idx
]) {
1151 Dprintk(KERN_DEBUG
"Pin %d-%d already programmed\n",
1152 mp_ioapic_routing
[ioapic
].apic_id
, ioapic_pin
);
1153 return (gsi
< IRQ_COMPRESSION_START
? gsi
: gsi_to_irq
[gsi
]);
1156 mp_ioapic_routing
[ioapic
].pin_programmed
[idx
] |= (1<<bit
);
1159 * For GSI >= 64, use IRQ compression
1161 if ((gsi
>= IRQ_COMPRESSION_START
)
1162 && (triggering
== ACPI_LEVEL_SENSITIVE
)) {
1164 * For PCI devices assign IRQs in order, avoiding gaps
1165 * due to unused I/O APIC pins.
1168 if (gsi
< MAX_GSI_NUM
) {
1170 * Retain the VIA chipset work-around (gsi > 15), but
1171 * avoid a problem where the 8254 timer (IRQ0) is setup
1172 * via an override (so it's not on pin 0 of the ioapic),
1173 * and at the same time, the pin 0 interrupt is a PCI
1174 * type. The gsi > 15 test could cause these two pins
1175 * to be shared as IRQ0, and they are not shareable.
1176 * So test for this condition, and if necessary, avoid
1177 * the pin collision.
1179 if (gsi
> 15 || (gsi
== 0 && !timer_uses_ioapic_pin_0
))
1182 * Don't assign IRQ used by ACPI SCI
1184 if (gsi
== acpi_gbl_FADT
.sci_interrupt
)
1186 gsi_to_irq
[irq
] = gsi
;
1188 printk(KERN_ERR
"GSI %u is too high\n", gsi
);
1193 io_apic_set_pci_routing(ioapic
, ioapic_pin
, gsi
,
1194 triggering
== ACPI_EDGE_SENSITIVE
? 0 : 1,
1195 polarity
== ACPI_ACTIVE_HIGH
? 0 : 1);
1199 #endif /* CONFIG_X86_IO_APIC */
1200 #endif /* CONFIG_ACPI */